http://ltwiki.org/api.php?action=feedcontributions&user=Analogspiceman&feedformat=atomLTwiki-Wiki for LTspice - User contributions [en]2020-05-30T09:05:30ZUser contributionsMediaWiki 1.31.7http://ltwiki.org/index.php?title=Undocumented_LTspice&diff=2124Undocumented LTspice2019-11-24T18:03:07Z<p>Analogspiceman: /* Circuit Element Area Multiplier */ clarity</p>
<hr />
<div>== Introduction ==<br />
'''Please submit your requests for additions or changes to ''Undocumented LTspice'' on the "discussion" page (second tab above).'''<br />
<br />
LTspice/SwitcherCAD III is a complete and fully functional SPICE program (electronic circuit simulator) that is available free of charge from the Linear Technology Corporation (LTC).&nbsp; Because of its superior performance, excellent community support and ease of file sharing, it is rapidly replacing all other SPICE programs, regardless of price, as the simulator of choice for hobbyists, students and professionals alike.<br />
<br />
The purpose of this topic is to explore and explain '''''some''''' of the many useful or quirky features that have never appeared in the standard documentation whether due to simple oversight, the feature being considered not important enough, not polished enough or functionally obsolete – or even due to the feature being considered proprietary to another brand of SPICE or to LTspice itself.&nbsp; LTC considers some of these undocumented features as fair game for open discussion in public forums such as the LTspice Yahoo users group, whereas for others, it considers any such open discussions as a violation of its License Agreement.<br />
<br />
"''Fair game''" is any feature that is or has ever been part of the normal distribution, i.e., appears or ever has appeared in the Help file, as plain text in any of the included sample or example files, in any program menu available during normal use of the program, or in any of the materials, presentation files or handouts from any LTspice seminar presentation.&nbsp; Such items are all considered as having been officially "''documented''" and are specifically allowed as discussion topics in public forums such as the LTspice Yahoo users group.&nbsp; However, be advised that any items that have been dropped from the documentation, even if still functional, should generally be considered obsolete and in risk of being purged from the program code at any time (fortunately, such items are quite rare).<br />
<br />
As to the classification of anything not covered above, you must make your own common sense judgment or ask the advice of the users group moderator or the program author via private email.&nbsp; Clearly any standard, generic SPICE feature that works in LTspice would be okay for general use and discussion regardless of its state of documentation in LTspice.&nbsp; A lot of the standard devices have undocumented parameters (e.g., tempcos) or syntax (e.g., Pspice specific compatibility) that would fall into this category.&nbsp; Just as clearly, any undocumented A-device that is specific to LTC’s encrypted, high performance SMPS IC models would likely be considered proprietary knowledge to be protected with due diligence from release to the public domain, lest LTC’s competitors gain the de facto permission to freely copy them in their own circuit simulator offerings (however, it is difficult to see how LTC could legitimately prevent private individuals from making use of such undocumented features in their own simulations or discussing them via private communications).&nbsp; For these reasons, this last category of undocumented features will not be directly discussed here.<br />
<br />
== Numerical Accuracy/Dynamic Range ==<br />
<br />
LTspice generally represents numbers using 64 bit double precision arithmetic with the following data structure:<br />
<br />
[[File:IEEE_754_Double_Floating_Point_Format.png|frameless|700px|<b>Sign: 1 bit, exponent: 11 bits, fraction: 52 bits.</b>]]<br />
<br />
For general component values LTspice will accept numbers that range in magnitude from as large as &plusmn;&thinsp;1.798 x 10<sup>+308</sup> down to as small as &plusmn;&thinsp;2.225 x 10<sup>&minus;308</sup>.&ensp; Values exceeding this range are interpreted as &plusmn; infinity or as zero.&nbsp; However, because of the 52 bit precision of the fractional part of the significand, the practical numerical dynamic range will be circuit dependent.&nbsp; A 53 bit binary significand gives LTspice about 16 significant figures for internal math computations.&nbsp; Thus, if impedances vary by more than 16 orders of magnitude, numerical difficulties may ensue, depending on the topology of the circuit (this is because matrix solving frequently involves differencing two very similar numbers &ndash; for example, the next larger number than one is 1.0000000000000002 &ndash; anything closer is not resolvable).&nbsp; LTspice's proprietary alternate solver extends this precision by about another 3 orders of magnitude at a cost of a modest speed penalty.<br />
<br />
<br />
== A-Devices ==<br />
<br />
A-devices are Linear Technology Corporation's proprietary special function/mixed mode circuit simulation elements.&nbsp; According to LTspice’s Help file, the behavior of a number of these is undocumented because they frequently change with each new set of models available for LTspice (such changes actually are quite rare and this reason is most likely offered as both as a credible reason for keeping them hidden and to discourage anyone from bothering to attempt to explore and/or use them).<br />
<br />
The Help file lists A-device syntax as:<br />
Annn n001 n002 n003 n004 n005 n006 n007 n008 <model> [instance parameters]<br />
Note that all A-devices have up to 8 possible active device connections, up to 5 inputs (terminals 1 through 5) usually 2 outputs (terminals 6 and 7), and with terminal 8 always as the device common.&nbsp; A-devices are always netlisted with the full eight connections.&nbsp; The netlister connects any unused inputs and outputs to terminal 8.&nbsp; The A-device compiler recognizes this condition as a flag that that terminal is not used and removes it from the simulation matrix.&nbsp; Current is sourced or sunk from the outputs (typically the Q or main output on terminal 7 and the Q&#773; or complementary output on terminal 6) and is returned through device common, terminal 8.<br />
<br />
A-devices are implemented this way to allow a single device type to act as any combination of a 1 to 5 input, 1 to 2 output device, but with no simulation speed penalty for unused terminals.&nbsp; Refer to the program Help file for more details about LTspice’s documented A-devices.<br />
<br />
Here is a listing of all known LTspice A-devices.<br />
<br />
<u>Documented directly in Help:</u><br />
* '''Buf''' (aka Buf1 Inv)<br />
* '''AND'''<br />
* '''OR'''<br />
* '''XOR''' – when more than two inputs are present, uses the correct definition of ''true if one and only one input is true'', rather than the more common <u>incorrect</u> definition of ''true if an odd number of inputs are true'' (which should be called an '''ODD/NODD''' gate rather than an '''XOR/XNOR''' gate).<br />
* '''Schmitt''' (aka SchmittBuf SchmittInv DifSchmitt DiffSchmittBuf DiffSchmittInv)<br />
* '''Dflop''' (CLR takes precedence over PRE, also a start up state may be set – see '''SRflop''')<br />
* '''Varistor'''<br />
* '''Modulator''' (aka Modulate Modulate2)<br />
<u>Not documented in Help but available via the schematic Component Selector:</u><br />
* '''SRflop''' – located in Digital<br />
* '''PhaseDet''' (aka PhiDet) – located in Digital<br />
* '''Counter''' – located in Digital and documented in the users group (has been officially approved for public use)<br />
* '''SampleHold''' (aka Sample) – located in Special Functions<br />
<u>Documented in sample schematics included with the program distribution:</u><br />
* '''PhaseDet''' (aka PhiDet) – located in examples/Educational/PLL2.asc<br />
* '''SampleHold''' (aka Sample) – located in examples/Educational/S&H.asc<br />
* '''OTA''' – used in UniversalOpamp plaintext subcircuits (in lib/sub), but users group posts (some long standing) containing information about additional aspects of this have been censored<br />
<u>Not documented anywhere by LTC:</u><br />
* '''XxxxxxXxxx''' – prior long standing users group posts about this digital toggle type device have now been censored<br />
* '''XxXxxXXX''' – DAC type device never discussed in the users group<br />
* '''XXXXX''' – DAC type device never discussed in the users group<br />
* '''XXXX''' – DAC type device never discussed in the users group<br />
* '''Xxx''' – amplifier type device never discussed in the users group<br />
<u>Not documented anywhere by LTC</u>, but the first two of these devices were extensively documented in the users group.&nbsp; All three devices were eliminated /protected in June 2006 (approximately at release 2.17u ) and all users group posts (some long standing) about these devices have been censored /deleted from the users group archive:<br />
* '''XXXxxxx''' – PWM current mode control comparator and latch<br />
* '''XxxXxx''' – used for making PWM IC External Oscillators<br />
* '''Xxxxx''' – used for making PWM IC oscillators<br />
<u>Obsolete devices that have been deleted from the LTspice executable:</u><br />
* '''JKflop'''<br />
* '''PGateDrive'''<br />
* '''invPGateDrive'''<br />
* '''invGateDrive'''<br />
The three DACs, XxXxxXXX, XxxXXX, XXXX, are specialized A-devices that probably are of little general interest (although their functions and pinouts could likely be easily guessed by examining the data sheets of the few specialized LTC ICs making use of them).<br />
<br />
The XXXX seems to be the only straightforward, generic DAC, but very spice-efficient DACs are quite easy to make using standard, approved devices.<br />
<br />
<br />
----<br />
=== SRflop ===<br />
The Set/Reset Flip-Flop symbol is located in the ''Digital'' symbol folder.<br />
* The '''R''' (reset) input takes precedence over the '''S''' (set) input.<br />
* The start up state of the flip-flop (initial condition) may be specified by adding an "'''ic='''" attribute.<br />
** An "'''ic'''" value > '''Ref''' interprets to a high, e.g., "'''ic=1'''" sets the '''Q''' output high and "'''ic=0'''" sets it low.&nbsp; (Note: the logic threshold '''Ref''' parameter defaults to 0.5 and its use is documented in '''Help'''.)<br />
<br />
<br />
----<br />
=== PhaseDet (aka PhiDet) ===<br />
The Phase Detector symbol is located in the ''Digital'' symbol folder.<br />
<br />
The Examples folder contains a schematic with some documentation: ''Examples/Educational/PLL2.asc''<br />
<br />
<br />
----<br />
=== SampleHold (aka Sample) ===<br />
<br />
The Sample & Hold symbol is located in the ''Special Functions'' symbol folder.<br />
<br />
An example schematic, ''S&H.asc'', is located in the ''Examples/Educational'' schematic folder.<br />
<br />
The behavioral a-device Sample and Hold has two modes of operation.&nbsp; The output may follow the input whenever the '''S/H''' input is true or the output may latch to the input when the '''CLK''' input goes true.&nbsp; Note that ''one and only one'' of these two inputs must be connected.<br />
<br />
Parameters unique to the Sample and Hold a-device are as follows:<br />
*'''Rout''' defaults to 1kΩ (instead of the standard a-device 1Ω).<br />
*'''Vhigh''' defaults to 10V and Vlow defaults to -10V (note: these are output voltage saturation levels).<br />
<br />
<br />
----<br />
=== OTA ===<br />
<br />
The OTA (Operational Transconductance Amplifier) is used in the various UniversalOpamp plaintext subcircuits (located in a standard LTspice program installation in ''lib/sub'').<br />
<br />
The default transfer function is a hyperbolic tangent (tanh), which closely approximates the transfer function of a bipolar transistor differential amplifier (this limit can be disabled by adding the flag parameter, '''Linear''').&nbsp; Two differential input pairs are available on pins 1 and 2 ( &minus; + ) and on pins 3 and 4 ( + &minus; ).&nbsp; The transconductance current source output appears on pin 7.&nbsp; As usual, pin 8, if connected, becomes the device's floating "gnd" reference.&nbsp; For reference, a dc "rail" voltage, which represents the maximum possible output (calculated from combining both voltage and current saturation limits), appears on pin 6.&nbsp; This voltage reflects the negative limit only and has an output impedance identical to that of the main output.<br />
<br />
<br />
'''<u>Parameters:</u>''' (* indicates an undocumented parameter)&nbsp; Note all OTA parameters were undocumented until November 2019.<br />
* '''Ref''' (default = 0V) is the input offset voltage<br />
* '''G''' (default = 1u-mho) is the raw input "gain" (transconductance), where Vdiff = ( '''Ref''' – V(1,2) ) * V(3,4)&nbsp; and Iraw = '''G''' * Vdiff<br />
* '''Iout''' (default = 10uA) is the output saturation current, which may be superseded by one or both of<br />
** '''Isrc''' (or '''Isource''', default = '''Iout''') is the output sourcing saturation current<br />
** '''Isink''' (a negative number, default = &minus;'''Iout''') is the output sinking saturation current<br />
*** '''Asym''' is a flag parameter that, if present, enables independent asymmetrical limits for '''Isrc/Isource''' and '''Isink'''<br />
*** '''Linear''' is a flag parameter that, if present, disables output limiting<br />
* *'''Ioffset''' (default = 0A) is the output offset current<br />
* *'''PowerUp''' (default = true) is a Boolean parameter that if < 0.5 disables all pin 7 output current<br />
* '''EAclk''' (default = none) is the reference designator of the gate indicating a clock period for steady state detection (net zero current out of the OTA integreated over this period is deemed steady state)<br />
* '''Ibuck''' (default = 0A) is the expression of current that is presumed to not be involved in slewing the voltage of the compensation capacitor<br />
* '''Rout''' (default = 1/Gmin) is the internal output resistance<br />
* '''Cout''' (default = 0F) is the capacitance in parallel with '''Rout'''<br />
* '''Vhigh''' (default = 2V) is the positive output "rail" voltage (set to 1e308 to disable limit)<br />
* '''Vlow''' (default = 0V) is the negative output "rail" voltage (set to &minus;1e308 to disable limit)<br />
* '''Rclamp''' (default = 1Ω) is the clamping resistance to the voltage rails<br />
* '''Epsilon''' (default = 0V) is the voltage range to gradually switch in '''Rclamp''' impedance<br />
* '''EN''' (default = 0V/√Hz) is the voltage noise density<br />
* '''ENk''' (default = 0Hz) is the voltage noise knee frequency<br />
* '''IN''' (default = 0A/√Hz) is the current noise density<br />
* '''INk''' (default = 0Hz) is the current noise knee frequency<br />
* '''INcm''' (default = 0A/√Hz) is the common mode current noise density<br />
* '''INcmk''' (default = 0Hz) is the common mode current noise knee frequency<br />
<br />
<br />
'''<u>Output Current Limit:</u>'''<br />
* With no flag parameter: Io = tanh ( Iraw / Isat ) * Isat + Idc + '''Ioffset'''&nbsp; (note that one limit's action/shape is affected by the opposing limit's magnitude)<br /> ''where'' Vdiff = ( '''Ref''' – V(1,2) ) * V(3,4) , Iraw = '''G''' * Vdiff , Isat = ( '''Isink''' – '''Isrc''' ) / 2&nbsp; and Idc = ( '''Isink''' + '''Isrc''' ) / 2 ; ('''Isink''' is a ''negative number'' )<br />
* With the '''Asym''' flag parameter: Io = if ( Vdiff , tanh ( Iraw / '''Isrc''' ) * '''Isrc''' , tanh ( Iraw / '''Isink''' ) * '''Isink''' ) + '''Ioffset''' <br /> ''note that'' the "if ( <polarity test>, <then action>, <else action> )" conditional statement completely separates the positive and negative limits<br />
* With the '''Linear''' flag parameter: Io = Iraw + '''Ioffset''' (output current does not saturate)<br />
* Note that in all cases the final value of Io is multiplied by buf&thinsp;( '''PowerUp''' )<br />
<br />
<br />
'''<u>Output Voltage Limit:</u>'''<br />
* Clamps through a resistance of '''Rclamp''' to "rails" of '''Vhigh''' and &minus;'''Vlow'''<br />
<br />
<br />
'''<u>Noise Voltage Density:</u>'''<br />
* Vnoise = ('''EN''' + '''IN''' * Rin_equivalent) * '''G''' * '''Rout'''<br />
<br />
<br />
----<br />
<br />
=== Counter (divide by n): ===<br />
<br />
The Counter symbol is located in the ''Digital'' symbol folder (added October 2013).<br />
<br />
This device divides the input pulse stream on the '''CLK''' input (terminal 1) by the parameter '''cycles''' (required) with the divided output pulse stream appearing on the '''Phi1''' main '''Q''' output (terminal 7) and the '''Phi2''' complementary '''Q&#773;''' output (terminal 6).&nbsp; Counting occurs at the rising edge of the pulse stream and duty cycle may be specified.&nbsp; A reset input is available on terminal 2, but this terminal is not present on the standard symbol.&nbsp; Initially and after a reset, the Counter starts high, then goes high again on every Nth edge after that, where N= round('''cycles''').&nbsp; Note that output behavior is inverted compared to a standard ripple counter.<br />
<br />
Parameters unique to the Counter a-device are as follows:<br />
*'''Cycles''' divides the rising edge input pulse stream by round(<exp>) where <exp> is the expression assigned to this mandatory parameter.<br />
*'''Duty''' specifies the output pulse width = round('''cycles'''*'''duty'''). Duty cycle defaults to 0.5 if '''duty''' is omitted.<br />
Most of the usual digital a-device parameters may also be optionally applied, e.g., '''Trise''', '''Vhigh''', '''Vlow''', '''Ref''', etc. with the exception of '''Td''', which is ignored (the Counter accepts no delay).<br />
<br />
The '''cycles''' expression accepts b-source syntax and thus may be a simple constant or may be a complex expression containing constants, parameters, functions, the keyword '''time''', node voltages and branch currents.&nbsp; The Counter output will go to zero whenever the value of '''cycles''' falls below 1.5.&nbsp; If the Counter is clocked when the value of '''cycles''' is below 1.5, the Counter is reset.<br />
<br />
To use this symbol a '''cycles''' parameter must be specified after placing the symbol on a schematic (right-click on the symbol to open the "Component Attribute Editor" window and, in the '''Value''' attribute field, enter a '''cycles''' parameter, e.g. "cycles=2" for a divide by two counter).<br />
<br />
A symbol including the reset input and test circuit is available in the online Yahoo LTspice users group: ''Files/Tut/Digital A-Devices''.&nbsp; Alternately, LTspice's standard S/R flip-flop symbol may be used to stand in for the Counter with reset by editing its '''SpiceModel''' attribute from "SRFLOP" to "Counter" after it has been placed on the schematic ('''S''' becomes the clock input, '''R''' becomes the reset input and '''Q''' and '''Q&#773;''' become the two outputs).<br />
<br />
<br />
== B-Sources ==<br />
<br />
While many b-source features were not documented until relatively recently (~2007), most are now at least touched upon in Help and the few that are not are covered in the [[B sources (complete reference)]] in this wiki.<br />
* '''Cpar'''&nbsp; In addition to the parameter '''Rpar''' (which is documented in Help), current source type behavioral sources (i.e., "I=" "R=" and "P=") now accept the '''Cpar''' parameter to specify a parallel capacitance.&nbsp; Current derived b-sources driving one ohm in parallel with a small capacitance (e.g., Rpar=1 Cpar=1n) are much more convergence friendly than stiff voltage sources and should be used whenever possible.&nbsp; Nortonizing voltage sources to current sources in parallel with one ohm requires no conversion calculation, but the Nortonized parallel impedance may be set as low as desired if the current source gain is up scaled to compensate.<br />
* '''Bn P=f(...)'''&nbsp; Arbitrary Power Sink/source where '''f''' is a constant or is an arbitrary function of any valid node voltage, branch current, etc. as with standard b-sources (note: power is sourced when '''f''' is negative).&nbsp; In order to avoid large currents at voltages near zero, the arbitrary power sink/sources foldbacks to resistive behavior when the absolute value of voltage across the device falls below a default value of 1 volt.&nbsp; The foldback point may be modified by specifying a '''VprXover''' parameter for the device, e.g. '''VprXover=50mV'''. <br />
* '''Bn R=f(...)'''&nbsp; Arbitrary Resistor where '''f''' is an arbitrary function of '''x''' (which has the special meaning of the voltage across '''R''' in this context) and/or any valid node voltage, branch current, etc. as with standard b-sources.<br />
* '''[[units] Freq=<valuelist> [delay=<value>]]'''&nbsp; (Pspice compatible format)<br /> The transfer function of the Freq circuit element is specified by an ordered list of points of freq(Hz), mag(dB) and phase(deg) as follows: <(f1,m1,p1)[(f2,m2,p2)...]> where f1<f2<f3, etc.&nbsp; The following units specifiers may optionally precede the Freq keyword: “rad”=radians, “mag”=non dB, (“dB” and “deg” return the defaults), “r_i”=real and imaginary in place of magnitude and phase.&nbsp; If a delay value is called out, the phases of the table values are modified to reflect the delay (delay is automatically adjusted to maintain causality in any case). <br />
* '''NoJacob'''&nbsp; The optional '''NoJacob''' flag parameter unburdens a device from carrying the mathematical overhead of a Jacobian.&nbsp; For linear or certain well behaved b-source expressions, this small reduction in computational burden can reduce run times slightly.&nbsp; Use with extreme caution, as this greatly increases the risk of creating convergence problems or other errors if misapplied. <br />
* '''~'''&nbsp; Boolean operator: convert succeeding expression to Boolean then invert<br />
* '''=='''&nbsp; Boolean operator: true if preceding expression is equal to succeeding expression, otherwise false<br />
* '''boltz'''&nbsp; Boltzmann constant = 1.38062 e-23<br />
* '''planck'''&nbsp; Planck's constant = 6.62620 e-34<br />
* '''echarge'''&nbsp; Charge of an electron = 1.6021765 e-19<br />
* '''kelvin'''&nbsp; Absolute Zero in degrees C = -273.150<br />
* '''Gmin'''&nbsp; Minimum conductance = 1e-12 (or as set in the '''Control Panel''' or via an .option statement)<br />
** '''Gmin''' is added to every PN junction to aid convergence and is the default off-conductance for current or voltage controlled switches and LTspice's idealized diode model.<br />
* '''square(x)'''&nbsp; Function = x**2<br />
* '''tbl'''&nbsp; Alternate function name, aka '''table''' (look-up table)<br />
* '''stp(x)'''&nbsp; Alternate function name, aka '''u(x)''' (unit step)<br />
* '''fra(x)'''&nbsp; Function, very similar to '''white(x)''', but = 0 if not SMPS in steady state condition<br />
* '''UpLim(x, pos, z)'''&nbsp; Function, similar to '''Min(x, y)''', but "'''z'''" defines a zone with quadratic soft limiting (note: "'''x'''" and "'''pos'''" are ''not'' strictly interchangeable and "'''z'''" must be the end argument)<br />
.func '''UpLim'''(x, y, z) if(y-x < z, y - z*exp((y-x-z)/z), x) ; this is '''UpLim's''' equivalent mathematical function<br />
* '''DnLim(x, neg, z)'''&nbsp; Function, similar to '''Max(x, y)''', but "'''z'''" defines a zone with quadratic soft limiting (note: "'''x'''" and "'''neg'''" are ''not'' strictly interchangeable and "'''z'''" must be the end argument)<br />
.func '''DnLim'''(x, y, z) if(x-y < z, y + z*exp((x-y-z)/z), x) ; this is '''DnLim's''' equivalent mathematical function<br />
* '''UpLim(DnLim(x, neg, z_dn), pos, z_up)'''&nbsp; Composite function, similar to '''Limit(x, neg, pos)''', but with up and down soft limit zones (note: arguments are ''not'' commutative)<br />
.func '''RndLim'''(x, neg, pos, z)= '''UpLim'''('''DnLim'''(x, neg, z), pos, z)<br />
* As with the hard limit functions, any or all arguments may be constants or functions of time, node voltages, branch currents, etc.: '''''UpLim'''(13, V(1,2)*I(Vs), Min(time**2, 5))''.<br />
* When their soft limits are greater than zero, these functions have continuous derivatives for superior dc convergence over '''Min()''', '''Max()''' and '''Limit()'''.<br />
* Outside their soft limit zones these functions are perfectly linear which may make them superior to '''tanh()''' as a smooth limit function in amplifier macro-modeling applications.<br />
<br />
Note that LTspice can execute behavioral sources in either 2G6, PSpice, or Berkeley SPICE syntax in addition to its own enlarged set of behavioral language.<br />
<br />
<br />
== G-Sources ==<br />
<br />
G-Sources have two additional parameters, Vto (threshold) and dir (direction)<br />
<br />
Here is the equivalent function:<br />
<br />
.func Gsq(x, gain, Vto, dir)=<br />
+ gain*if(dir==0, x, sgn(dir)*uramp(sgn(dir)*(x-Vto))**2)<br />
<br />
where x=V(nc+,nc-), the control voltage per the usual G syntax notation from Help:<br />
<br />
Gxxx n+ n- nc+ nc- <gain><br />
<br />
Here is a component where this feature is used, along with conventional G-Sources [http://ltwiki.org/files/LTC6268.zip LTC6268]<br><br />
<br />
<br />
== Standard Sources ==<br />
<br />
Add documentation for data file input and triggered sources and the Pspice compatible behavioral forms for E and G sources (at some point, perhaps ~2007, these were added to Help).<br />
<br />
<br />
=== Piecewise Linear Sources (PWL) ===<br />
<br />
LTspice supports many more forms of the PWL statement than given in the documentation.&nbsp; LTspice is largely compatible with other SPICE versions, providing similar or identical PWL features.<br />
<br />
The non-documented PWL statements can be added on a schematic by first adding a normal source from the Component library, and using the Advanced setting of the source to set the function of the source to one of the two available PWL functions.&nbsp; Once the source is placed on the schematic a right-click on the PWL statement allows to edit it.&nbsp; Once the PWL statement has been changed to a non-documented PWL statement it can also be edited by right-clicking on the component symbol.&nbsp; The right-click will then no longer bring up the special window for changing a source function, but the generic component attribute editor.&nbsp; The PWL statement goes into the value field.<br />
<br />
The principle form of the PLW statement is<br />
<br />
PWL [VALUE_SCALE_FACTOR=<vsf>]<br />
[TIME_SCALE_FACTOR=<tsf>]<br />
<data specification><br />
[TRIGGER <trigger expression>]<br />
<br />
The functions of the scale factors are obvious.&nbsp; When given, each value or time in the <data specification> is multiplied by them.&nbsp; The default for each factor is 1.<br />
<br />
The <data specification> is very flexible.&nbsp; Data can either be provided directly in the statement, or by referring to a file (these are documented features).&nbsp; Further, data can be specified so it is repeated a number of times, or forever (both undocumented).&nbsp; Also, data can be specified in a relative way (undocumented).&nbsp; And finally, specifications can be combined to a certain extent (undocumented).<br />
<br />
The simplest form of a <data specification> is a list of one or more data points.&nbsp; Each point is a pair of a time <t''x''> and a value <v''x''> values.&nbsp; A pair can, but need not be, grouped together by brackets.&nbsp; Using brackets simplifies the reading of longer lists.&nbsp; Also, commas can be used to separate and group data points. <br />
<br />
PWL <t1> <v1> <...> <tn> <vn><br />
PWL (<t1> <v1> <...> <tn> <vn>)<br />
PWL (<t1> <v1>) <...> (<tn> <vn>)<br />
PWL <t1>, <v1> <...> <tn>, <vn><br />
<br />
The usual suffixes, like ''m'' for milli or 'k' for kilo can be used both for times and values, e.g.:<br />
<br />
PWL (0m 1 1m 2 1m 3 4m 2)<br />
<br />
A value <v''x''> can also be an expression in curly brackets.&nbsp; However, while function names like ''sin()'' are recognized, the keyword ''time'' is not.&nbsp; This makes it difficult, probably impossible, to generate time-dependent data, like ''{sin(time)}'' or ''{rand(time)}'' (to generate random noise)<ref>Other SPICE versions have no such problem with ''time''</ref>.<br />
<br />
PWL (0 {sin(1)}) (1 {sin(2)})<br />
<br />
Time values <t''x''> can be specified as relative to the previous time value, by prefixing the value with a ''+'' sign, e.g. specifying values at 0, 1, 2, and 7 seconds:<br />
<br />
PWL (0 1 +1 2 +1 3 +5 2)<br />
<br />
Instead of placing the values directly into the PWL statement they can also be placed in a file, and the file referred in the PWL statement<br />
<br />
PWL file=<name of the file><br />
<br />
A list of data points or a file reference can be repeated a fixed amount of times <n>, or forever<br />
<br />
PWL REPEAT FOR <n> (<data list>|<file spec>) ENDREPEAT<br />
PWL REPEAT FOREVER (<data list>|<file spec>) ENDREPEAT<br />
<br />
E.g. to repeat a sequence of values for five times<br />
<br />
PWL REPEAT FOR 5 ( 0 1 1 1 2 2 3 1 ) ENDREPEAT<br />
PWL REPEAT FOR 5 ( file=<name of file> ) ENDREPEAT<br />
<br />
Data specifications can be combined, e.g:<br />
<br />
PWL (0 0 1 1 2 1 3 0) REPEAT FOR 5 (file=<name of file>) ENDREPEAT<br />
PWL REPEAT FOR 7 (file=pwl_data.txt) ENDREPEAT REPEAT FOR 6 (file=pwl_data2.txt) ENDREPEAT<br />
<br />
Repeat statements can be nested, e.g.:<br />
<br />
PWL REPEAT FOREVER (0 1 1 2) REPEAT FOR 3 (2 3 3 1) ENDREPEAT ENDREPEAT<br />
<br />
The <trigger expression> turns the source's output on as long as the expression is true.&nbsp; For example, if there is a node n001 in the circuit, the following will turn the output on as long as the node's voltage is greater 1.5V.&nbsp; A source that is turned off is 'stuck' at the first value given in its specification.&nbsp; In the following example the first pair is (0 0), i.e. a value of 0 at time 0.&nbsp; Therefore, when turned off, the source will be stuck at 0.<br />
<br />
PWL ( 0 0 1 1 2 1 3 0) TRIGGER V(n001)>1.5<br />
<br />
<br />
== Standard Devices ==<br />
<br />
=== Diodes: Sidewall Parameters ===<br />
<br />
LTspice (04/05/10) now supports the following diode sidewall parameters:<br />
* '''perim''': Sidewall perimeter (periphery) ; default value = 0m.<br />
* '''Isw''': Sidewall saturation current ; default value = 0A.<br />
* '''Ns''': Sidewall junction emission coefficient ; default value = N (I when Level=11)?<br />
* '''Rsw''': Sidewall series resistance ; default value = 0 ohm.<br />
* '''Cjsw''': Sidewall zero-bias capacitance ; default value = 0.9F * perim?<br />
* '''Vjsw''': Sidewall junction potential ; default value = Vj (1 when Level=11)?<br />
* '''Mjsw''': Sidewall grating coefficient ; default value = 0.33.<br />
* '''Fcs''': Sidewall forward-bias depletion capacitance coefficient ; default value = 0.5 (Fc when Level = 11)?<br />
<br />
<br />
----<br />
=== BJTs: Additional Gummel-Poon Parameters ===<br />
<br />
Bipolar CB avalanche breakdown is modeled in the LTspice Gummel-Poon device:<br />
* '''BVcbo''': C-B breakdown voltage.<br />
* '''nBVcbo''': breakdown emission coefficient ; default value = 1?<br />
* '''TBVcbo1''': linear temperature coefficient of breakdown voltage.<br />
* '''TBVcbo2''': quadratic temperature coefficient of breakdown voltage.<br />
<br />
Bipolar BE breakdown is also in the LTspice Gummel-Poon device:<br />
* '''BVbe''': B-E breakdown voltage.<br />
* '''IBVbe''': breakdown current at breakdown voltage.<br />
* '''nBVbe''': breakdown emission coefficient.<br />
<br />
<br />
----<br />
=== VDMOS: Breakdown, Sub-threshold Enhancements ===<br />
<br />
LTspice now contains a number of otherwise undocumented parameters to enhance its proprietary VDMOS model.&nbsp; These allow for body diode breakdown, subthreshold conduction with independent fits to the saturation and linear regions of the output characteristics and mobility reduction due to large Vgs.&nbsp; Most of these have recently become documented in the Help file (** denotes still undocumented).<br />
<br />
* '''BV''': breakdown voltage.<br />
* '''IBV''': breakdown current at breakdown voltage.<br />
* '''nBV''': breakdown emission coefficient.<br />
* '''Mtriode''': A conductance multiplier for the triode region.&nbsp; It allows independent matching of the saturation and linear regions of the MOSFET.<br />
* '''subthres''': The current (per volt Vds) at which the square-law drain current verses Vgs switches over to exponential.<br />
* '''theta''': ** mobility reduction due to large Vgs (limits drain current to direct gate voltage dependence instead of square law).<br />
<br />
<br />
<u>'''VDMOS Capacitance (Cgd Curve Fit Equation)'''</u><br />
<br />
LTspice Help outlines how LTspice generates the VDMOS nonlinear gate-drain capacitance, presenting the general form of the equations used, but it does not reveal the details of the parameters used by the fit equations.&nbsp; Help states that the capacitance expression fit uses two expressions, one for negative gate-drain voltages and another for positive.&nbsp; These expressions meet at zero voltage and it may be assumed that at this point, they must be identical in value and slope.&nbsp; This reduces the system to two equations in two unknowns, allowing a solution for the remaining fit parameters to be obtained.&nbsp; For the following equations, "'''s'''" is the slope at the zero point, "'''y'''" is the offset and "'''x'''" is the gate-drain voltage (''not'' the drain-source voltage).<br />
<br />
* Positive gate-drain voltage region: '''Cgd = s * tanh(a*x) + y''' (inversion region - switch is on)<br />
* Negative gate-drain voltage region: '''Cgd = s * atan(a*x) + y''' (Vds large - switch is off or turning off)<br />
<br />
Where '''s = (Cgdmax - Cgdmin)/(1 + Pi/2)''' and '''y = Cgdmax - s''' and "'''a'''", '''Cgdmax''' and '''Cgdmin''' are existing VDMOS model parameters.<br />
<br />
Note that in Help the unspecified parameters are given as '''A''', '''B''', '''C''', and '''D'''. These parameters are equivalent to '''s''' and '''y''' as follows: '''A = C = s''' and '''B = D = y'''.<br />
<br />
<br />
----<br />
=== Capacitors ===<br />
<br />
==== Capacitor Multipliers ====<br />
Capacitors allow an alternate form for the device multiplier m=<value> (number of units in parallel - see [[C_Capacitor|Capacitors in Help]]).&nbsp; In place of "m=<number>", "x<number>" may be used, i.e.: x2, x 2, x0.5, x3.14159.&nbsp; Note that whitespace may optionally separate the leading x and the following number.<br />
<br />
<br />
----<br />
=== Inductors ===<br />
<br />
==== Maximum Coupling Factor ====<br />
In LTspice, it is not really possible to set the winding coupling factor (K) exactly to unity.&nbsp; A little experimentation reveals this number to be 1-1n=.999999999.&nbsp; For 1-1n < k <=1, LTspice sets k=1-1n, never informing the user, not even in the error log where the netlist has been flattened and abstract expressions have been converted to numerics.<br />
<br />
If k is set to greater than one, LTspice issues a warning that k has been reduced to one (which actually is 1-1n).&nbsp; However this action is not reflected in the netlist nor in the error log's digested netlist.<br />
<br />
<br />
----<br />
=== Resistors ===<br />
<br />
==== Behavioral Resistors ====<br />
<br />
Create a behavioral resistor by right-mouse-button clicking on its Value field and edit its value to read: R=<expression>.&nbsp; This feature is undocumented, but is considered permissible to use.&nbsp; The expression syntax is the same as for a general behavioral source (see [[B_Arbitrary_behavioral_voltage_or_current_sources|B-sources in Help]]).<br />
<br />
The resistance must not go to zero and negative values can lead to convergence problems, so it is advisable to restrict its values to within a meaningful range as per the following Value example:<br />
<br />
R = limit(1,100k,V(1,2)*I(V1)) ; R stays between 1 ohm and 100k<br />
<br />
To plot an I-V curve, start by using the differential cursor to plot the voltage across the resistor.&nbsp; First click and hold down the left-mouse-button (red probe icon) on one side of the resistor and then drag and drop the black probe icon on the other side.&nbsp; Finish by dragging the mouse pointer over the x-axis (a ruler icon will appear) and the click the left mouse button to bring up the Horizontal Axis menu.&nbsp; Change the Quantity Plotted from "time" to "I(R1)" (assuming R1 is your behavioral resistor).<br />
<br />
<br />
==== Behavioral Resistor & Power Sink/Source ====<br />
<br />
Arbitrary Power Sink or Source where the function '''P=f()''' for power '''f''' is a constant or is an arbitrary function of any valid node voltage, branch current, etc. as with standard b-sources (note: power is sourced when '''f''' is negative).&nbsp; In order to avoid large currents at voltages near zero, the arbitrary power sink/sources foldbacks to resistive behavior when the absolute value of voltage across the device falls below a default value of 1 volt.&nbsp; The foldback point may be modified by specifying a '''VprXover''' parameter for the device, e.g. '''VprXover=50mV'''.<br />
<br />
Bxxx n1 n2 P=<expression> [VprXover=<value>] ; example: B1 1 0 P=500W VprXover=5V (R=50mΩ below 5V)<br />
<br />
<br />
==== Dual Value Resistors (for ac analysis) ====<br />
<br />
LTspice is like Hspice in that it allows resistors to have different dc and ac values.&nbsp; If ''ac=<value>'' is specified as a resistor parameter (either immediately after the normal dc value or in the '''Value2''' field), the operating point is calculated using the dc value of resistance, but the ac resistance value is used in the ac analysis.&nbsp; This may be useful when analyzing operational amplifiers, since the operating point computation can be performed on the unity gain configuration using a low value for the feedback resistance and the ac analysis may then be performed on a nearly open loop configuration by specifying a very large value for the ac resistance.<br />
<br />
<br />
==== Resistor (and Capacitor) Model Statements ====<br />
<br />
It's not in the .model section of the Help file, but LTspice seems to recognize standard model statements for resistors (RES) and capacitors (CAP), but not inductors (IND).<br />
<br />
As in many other SPICE simulators, "RES" and "CAP" are allowed as model keywords.&nbsp; For example, with the following line of spicetext<br />
<br />
.model X7R cap (T_measured=20 Tc1=0 Tc2=-19u)<br />
<br />
on a schematic, if a capacitor then has "X7R" entered into its "SpiceModel" field (via ctrl-right mouse click) its base value will be multiplied by the following temperature factor, TF<br />
<br />
TF = 1 + Tc1*(T-Tmeasured) + Tc2*(T-Tmeasured)**2<br />
where T = the global temperature TEMP or the local instance if specified.<br />
<br />
I haven't checked if higher order factors are accepted or if voltage or current factors can be used (they work for some other SPICEs).<br />
<br />
The Help file specifies the optional instance of [temp=<value>] syntax for resistors, capacitors and inductors, but only for capacitors does it define this as "instance temperature (for tempcos in a corresponding .model statement)," although nothing further about the model syntax is mentioned.<br />
<br />
The help file does not document the "noiseless" control parameter which applies to the resistance in many LTspice circuit elements with resistive elements (resistors, switches, RC lines, others).&nbsp; As its name suggests, this parameter blocks its applicable element's contribution to noise calculations.<br />
<br />
<br />
----<br />
=== Lossy Transmission Lines ===<br />
<br />
There are two undocumented lossy transmission line models implemented in LTspice.&nbsp; One is CPL model (P device), and the other is TXL model (Y device).<br />
<br />
The undocumented CPL is a K-Spice-like element, which in theory should be similar to the RLGC model, but without frequency dependent loss (neither skin effect and nor frequency dependent dielectric loss).&nbsp; It also has at least one bug causing an incorrect output voltage offset (a workaround is to only use signals with no dc offset). <br />
<br />
Below are example netlists from K-Spice, which have been translated as required (very little) into LTspice syntax.<br />
<pre><br />
****** test circuit for CPL transmission line simulation *******<br />
*<br />
M1 0 268 299 0 MN0P9 w=18u l=1u<br />
M2 299 267 748 0 MN0P9 w=18u l=1u<br />
M3 0 168 648 0 MN0P9 w=18u l=0u9<br />
M4 1 268 748 1 MP1P0 w=36u l=1u<br />
M5 1 267 748 1 MP1P0 w=36u l=1u<br />
M6 1 168 648 1 MP1P0 w=36u l=1u<br />
*<br />
CN648 648 0 25f4<br />
CN651 651 0 7f4<br />
CN748 748 0 25f4<br />
CN751 751 0 9f4<br />
CN299 299 0 5f4<br />
*<br />
P1 648 748 0 651 751 0 Pline<br />
*<br />
vdd 1 0 DC 5<br />
Vk 267 0 DC 5<br />
*<br />
*Vs 168 0 PWL (4 15n9 0 16n1 5 31n9 5 32n1 0)<br />
*Vs 268 0 PWL (4 15n9 0 16n1 5 31n9 5 32n1 0)<br />
*<br />
Vs1 168 0 Pulse (0 5 15n9 0n2 0n2 15n8 60n)<br />
Vs2 268 0 Pulse (0 5 15n9 0n2 0n2 15n8 60n)<br />
*<br />
.tran 0n2 47n9 0 1n<br />
.model Pline CPL<br />
+ R=0.2 0 0.2<br />
+ L=9n13 3n3 9n13<br />
+ G=0 0 0<br />
+ C=365f -90f 365f<br />
+ Length=24<br />
********************** MODEL SPECIFICATION **********************<br />
.model MN0P9 NMOS Vto=0.8 Kp=48u Gamma=0.30 Phi=0.55 Lambda=0<br />
+ Cgso=0 Cgdo=0 Cj=0 Cjsw=0 Tox=18u Ld=0<br />
.model MP1P0 PMOS Vto=-0.8 Kp=21u Gamma=0.45 Phi=0.61 Lambda=0<br />
+ Cgso=0 Cgdo=0 Cj=0 Cjsw=0 Tox=18u Ld=0<br />
.end<br />
<br />
******* test circuit for TXL transmission line simulation *******<br />
M5 0 168 2 0 MN0P9 w=18u l=0u9<br />
M6 1 168 2 1 MP1P0 w=36u l=1u<br />
Cn2 2 0 25f4<br />
Cn3 3 0 7f4<br />
Y1 2 0 3 0 Ymod<br />
Vdd 1 0 dc 5.0<br />
Vs 168 0 Pulse (0 5 15n9 0n2 0n2 15n8 32n)<br />
*Vs 168 0 PWL(15n9 0 16n1 5 31n9 5 32n1 0)<br />
.tran 0n2 47n 0 0n1<br />
.model MN0P9 NMOS Vto=0.8 Kp=48u Gamma=0.3 Phi=0.55 Lambda=0<br />
+ Cgso=0 Cgdo=0 Cj=0 Cjsw=0 Tox=18u Ld=0<br />
.model MP1P0 PMOS Vto=-0.8 Kp=21u Gamma=0.45 Phi=0.61 Lambda=0<br />
+ Cgso=0 Cgdo=0 Cj=0 Cjsw=0 Tox=18u Ld=0<br />
.model Ymod Txl R=12.45 L=9u G=0 C=0p47 Length=16<br />
.end<br />
</pre><br />
<br />
<br />
----<br />
=== Voltage Controlled Switches ===<br />
<br />
LTspice has a cleaner syntax for voltage controlled switches, but has no problem with any PSpice voltage controlled switch syntax.<br />
<br />
<br />
== Dot Commands ==<br />
=== .Ac (ac analysis) ===<br />
<br />
In an ac analysis, it seems that the maximum number of points that may calculated is limited to about 65k.&nbsp; If more are requested, LTspice will reduce the point count to this maximum, but without generating an error or warning.&nbsp; This limitation may become significant when attempting to simulate very high Q circuits over too broad a frequency range (e.g., crystal oscillators showing overtones).<br />
<br />
<br />
----<br />
=== .Options ===<br />
<br />
Note: ".opt" is accepted as shorthand notation for ".options" (options are added as text onto the schematic as a [[SPICE Directive]]).<br />
<br />
There are a whole lot of .option parameters and other control parameters (mostly legacy from SPICE 2 and Pspice) that should be documented (a few probably actually could be useful).&nbsp; Many of these are listed in the LTspice Yahoo group message [http://tech.groups.yahoo.com/group/LTspice/message/20174 #20174].<br />
<br />
<br />
==== .options List ====<br />
<br />
This flag parameter causes a dump of the flatened netlist (after expanding subcircuits) to appear in the '''SPICE Error Log''' file (sticky and causes the corresponding '''Generate Expanded Listing''' option check box in '''Operation''' tab of the [[Control Panel]] to become checked).<br />
<br />
.opt List ; selects "Generate Expanded Listing" in the Control Panel<br />
<br />
<br />
==== .options DampInductors=<''value''> ====<br />
<br />
This has the same effect as unchecking (value=0) or checking (value=1) the '''Rpar''' inductor option on the '''Hacks''' tab of the '''Control Panel''', overriding whatever is set there (the default value in LTspice is 1 or ''ON'', which is opposite the standard SPICE convention).&nbsp; The default value for the parallel damping resistance equals 1e12 times the inductance value (1T x L) and is only applied in the case of a transient analysis.<br />
<br />
.opt DampInductors=0 ; turn off LTspice's default parallel damping resistance<br />
<br />
<br />
==== .options Thev_Induc=<''value''> ====<br />
<br />
This has the same effect as unchecking (value=0) or checking (value=1) the '''Rser''' inductor option on the '''Hacks''' tab of the '''Control Panel''', overriding whatever is set there (the default value in LTspice is 0 or ''ON'', which is opposite the standard SPICE convention).&nbsp; The default value for the series damping resistance equals 1 milliohm and is applied to all analyses.<br />
<br />
.opt Thev_Induc=1 ; turn off LTspice's default 1 milliohm series damping resistance (R = 0)<br />
<br />
Notes:<br />
* Using the standard SPICE convention settings for these two inductor options causes the circuit matrix to be bigger, run slower and be more prone to convergence errors.<br />
* I have yet to discover how to alter the global default enabled values for Rpar and Rser (changing Gmin has no effect on the parallel damping resistance for inductors). <br />
<br />
<br />
==== .options Gfarad=<''value''> ====<br />
<br />
Added at LTspice version 4.14h (per public posting by Yahoo LTspice group moderator, Helmut Sennewald, 04/13/12).<br />
<br />
This option allows the user to set the global value for a capacitor's default parallel conductance factor (1/'''Rpar''' = Gpar = '''Gfarad'''*C).<br />
<br />
.opt Gfarad=1e-12 ; has no effect because this is the existing default conductance factor<br />
.opt Gfarad=0 ; sets the global conductance factor to zero (removes the hidden default parallel resistance for all capacitors)<br />
<br />
Notes:<br />
* As a convergence aid, capacitors in LTspice include a hidden default parallel resistance of '''Rpar''' = 1e12/C.&nbsp; Specifying any value for '''Equiv. Parallel Resistance''' ('''Rpar''') in a capacitor's '''Component Editor''' window will override this default.&nbsp; Specifying a value of zero ('''Rpar'''=0) removes the default resistance (sets the conductance to zero).<br />
* The arbitrary capacitor (specified via a behavioral charge equation - refer to the topic in '''Help''') has no parallel conductance and is not affected by '''Gfarad'''.<br />
<br />
<br />
==== .options Gfloat=<''value''> ====<br />
<br />
This option allows the user to set the global value for the shunt conductance from floating nodes to ground.<br />
<br />
.opt Gfloat=1e-12 ; has no effect because this is the existing default conductance factor (which is Gshunt)<br />
.opt Gfloat=0 ; sets the global conductance factor to zero (removes the hidden default ground shunt resistance for all floating nodes)<br />
<br />
Notes:<br />
* As a convergence aid, floating nodes in LTspice include a hidden default shunt resistance to ground.&nbsp; The default value is equal to the value of '''Gshunt''' (which also may be optionally set - refer to the topic in '''Help''').&nbsp; Specifying a value for '''Gfloat''' will override this default.&nbsp; Specifying a value of zero removes the default shunt resistance (sets the conductance to zero).<br />
* Floating nodes are typically created when only connected to capacitors and/or current sources.<br />
<br />
<br />
==== .options TopologyCheck=2 ====<br />
<br />
Listed in the ChangeLog 09/14/11: "Beta Optimisations regarding dangling nodes."<br />
<br />
Setting this parameter to 2 has the same effect as checking '''Enable beta circuit matrix optimizations''' on the '''Hacks''' tab of the '''Control Panel''', overriding whatever is set there.<br />
<br />
.opt TopologyCheck=2 ; (parameter numbers 0 and 1 are documented in Help)<br />
<br />
<br />
==== .options tSeed=<''value''> ====<br />
<br />
This option lets you seed the integrator with a specific guess for the initial .tran timestep<br />
<br />
.opt tSeed=100n<br />
<br />
<br />
----<br />
=== .NodeAlias <''aliasName''> <''netName''> ===<br />
<br />
Listed in the ChangeLog 10/06/10: "Allows to give a net an alternative name." <br />
<br />
Placing the Jumper symbol (''lib/sym/Misc/jumper'') is another, documented and probably more convenient way of giving the same net two names, however, in a hierarchical design, it only functions on a top level schematic.<br />
<br />
.nodealias output drain<br />
<br />
<br />
== Miscellaneous Hints and Tricks ==<br />
<br />
... should be added here or given its own section if warranted.<br />
<br />
Here's a hint to anyone wishing to keep up-to-date with the latest additions to '''LTspice''''s great features - always read the '''''changelog.txt''''' file (located in the '''LTspiceIV''' program folder) after every web update /sync release.<br />
* From the ChangeLog on 02/21/07: "Added a check box on the Tools=>Control Panel=>Hacks! pane to allow the '''MC generator''' to be reseeded by the real time clock."<br />
<br />
<br />
'''A-Devices''' See message #19378 from the LTspice Yahoo users group.<br />
<br />
<br />
----<br />
=== Circuit Element Area Multiplier ===<br />
Only the following LTspice elements accept the device die ''Area Multiplier'' parameter, '''m'''=<value>, where '''m''' is the value by which the element model die area will be multiplied:<br />
<br />
'''C''' (Capacitors), '''D''' (Diodes), '''J*''' (JFETs), '''L''' (Inductors), '''M''' (MOSFETs), '''Q*''' (Bipolar Transistors) '''R*''' (Resistors), '''Z''' (MESFETs and IGBTs).<br />
<br />
<nowiki> </nowiki>'' '''* m'''=<value> is an undocumented or poorly documented feature of this element''<br />
<br />
Note that the Help file documentation does not mention that '''m'''=<value> works for resistors and only vaguely mentions that area scaling (not '''m''') is available for JFETs and bipolar resistors.<br />
<br />
''''M'''' is useful for scaling standard devices from LTspice's built in libraries up or down in die size to match similar, but different area device (element) models.&nbsp; '''M'''=2 is like running two identical devices in parallel.&nbsp; '''M'''=0.5 is like running with half the device die area.&nbsp; Devices are LTspice elements (MOSFET, NPN, PNP, etc.) with native models.<br />
<br />
----<br />
<br />
=== Alternate Syntax ===<br />
<br />
In many contexts, where possible, LTspice supports alternate syntaxes compatible with other simulators.<br />
* Single quotes generally may be used in place of curly braces.<br />
<br />
<br />
=== AKO Aliases (A Kind Of) ===<br />
<br />
''Suppose I wished to modify a single parameter of an existing model but don't want to copy the full model out as a duplicate and adjust it.&nbsp; I want to pick up all of the specified and default parameter values for the given model name (and if it specifies yet another, to pick up those, as well) and simply modify one parameter or two in a new model.''<br />
<br />
''A reason I may wish to do this is that I may, at some later time, decide to modify the underlying model and I'd like all of the dependent models to pick up the underlying changes, automatically.&nbsp; I just don't know if there is syntax for it.&nbsp; Do you know?''<br />
<br />
Yes.&nbsp; Try something like this:<br />
<br />
.model 2N2222mod ako: 2N2222 bf=5 ; same except lower beta<br />
<br />
<br />
----<br />
> It appears that parameters must ultimately resolve to numbers instead of text.<br />
<br />
You are correct in your supposition - parameters must be numbers.<br />
<br />
> Is there a way to pass text to a subcircuit to do what I want?<br />
<br />
Yes.&nbsp; Models can take numeric alias using the AKO ("A Kind Of") function.<br />
These numeric aliases will work with parameter passing:<br />
<br />
.model 1 ako:2N3904 ;the existing 2N3904 model now also known as "1"<br />
.model 2 ako:2N2222 ;the existing 2N2222 model now also known as "2"<br />
<br />
This topic has been discussed many times in this forum before, but it may be difficult to search for because the name of the AKO function doesn't really correspond to "Also Known As" (it stands for "A Kind Of").<br />
<br />
You can find many examples using AKO in the Group archive here:<br />
<br />
Files -> Tut -> Stepping to the max<br />
<br />
<br />
=== Stepping a Model ===<br />
<br />
Sometimes it might be of interest to try out several different types of some component in a circuit, instead of just stepping a single parameter of a component.&nbsp; This can be done by giving the models that should be tried number-only names.&nbsp; For example, using the above discussed AKO feature, NPN transistors can be named as follows:<br />
<br />
.model 3904 ako:2N3904<br />
.model 2222 ako:2N2222<br />
.model 547 ako:BC547<br />
<br />
It is also possible to define a model with a number-only name from scratch:<br />
<br />
.model 4 NPN<br />
<br />
The next step is to add a spice directive to define a parameter, ''STM'' in the example below, which is stepped through the model names.&nbsp; Since the ''.step'' command can only step numeric values it is vital that the models have been given number-only names, as shown above. <br />
<br />
.step param STM list 3904 2222 547 4<br />
<br />
The last step is then to use the parameter in place of a model ''Value''.&nbsp; To make sure the parameter is evaluated, it needs to be placed in brakes.&nbsp; For example, the above defined parameter ''STM'' would be given in the form of ''{STM}'' as the ''Value'' of an NPN transistor symbol.<br />
<br />
<br />
=== Schematic Editor ===<br />
<br />
====Key Combination====<br />
* '''Shift-Ctrl-Alt-R''': Permanently renumbers all reference designators within the schematic.<br />
* '''Shift-Ctrl-Alt-H''': Temporarily highlights all hidden text within the schematic.<br />
* Hold down '''Ctrl''' when placing wires to route at any angle.<br />
* Hold down '''Ctrl''' when drawing lines to draw off grid.<br />
* Hold down '''Ctrl''' or '''Shift''' for more movement with '''arrow keys'''.<br />
* Hold down '''Ctrl''' ''and'' '''Shift''' for ''most'' movement with '''arrow keys'''.<br />
* Text preceeded with an underscore ("_") character will be displayed as overbarred (for active LOW digital signals).<br />
* '''Cross Probing''': Clicking '''Alt-Left''' on a label in the plot pane highlights the corresponding node in the schematic (since end of October 2012 release).&nbsp; E.g. clicking '''Alt-Left''' on a label like ''V(n001)'' in the plot pane highlights the ''n001'' node.&nbsp; Clicking '''Alt-Left''' on a label like ''I(R1)'' highlights ''R1'' in the schematic.<br />
<br />
<br />
====Operating Point Data Labels (visible numeric dc bias values)====<br />
<br />
LTspice has the ability to display dc operating point voltages, currents and expressions (e.g., power, energy, efficiency, etc.) directly within the schematic.&nbsp; Normally, labels are placed upon wires (nodes) much like '''Net Labels'''. <br />
<br />
<br />
===== Preparation =====<br />
<br />
To be able to place/show operating point data labels right-click on an empty area of the schematic and select "'''View'''" from the drop down menu list. <br />
* Checking "'''Show .op Data Flags'''" shows all operating point numerical information on the schematic.<br />
Further, in the main menu<br />
* Checking "'''Mark Unconn. Pins'''" (main menu -> View) shows anchor boxes on the schematic when a label is moved.<br />
<br />
<br />
===== Creating a Label when doing a .op Simulation =====<br />
<br />
When doing a DC operating point simulation (.op) an operating point data label can be created as follows<br />
<br />
* Run the .op simulation<br />
* Left-Click on a net (a wire).&nbsp; This creates a new label that can be placed with the cursor.<br />
<br />
<br />
===== Creating a Label when doing another Simulations =====<br />
<br />
When doing other kinds of simulations than a DC operating point simulation (.op) operating point data labels can be created by right-clicking on an empty area of the schematic, then selecting '''View->Place .op Data Label''' on the drop down menu.&nbsp; The new label can be attached to a net with the cursor.<br />
<br />
<br />
===== Format and Layout =====<br />
<br />
Once placed, an operating point data label may be freely moved or copied and then edited to be completely unrelated to the original node.&nbsp; It is of course possible to decorate a label by using the normal drawing functions.&nbsp; For example painting a rectangle around it (main menu Edit->Draw->Rectangle) or by placing some text nearby (main menu Edit->Text).<br />
<br />
Operating point data labels default to the display of the voltage of the node to which they are attached (signified by the dollar sign character "$"), but this may be edited to be any valid expression, including currents, powers or even the voltage of a specific node.&nbsp; Right-clicking on a operating point data label brings up a popup window for selecting the data to display or enter an expression.<br />
<br />
With fractional values, all available non-zero digits will be displayed, often resulting in unwanted numerical clutter.&nbsp; The number of visible digits may be aesthetically limited by appropriately editing the expression to be displayed.&nbsp; Examples of rounding expressions used for formating:<br />
<br />
round($*1k)/1k ; display no more than 3 digits (typically automatically expressed in engineering format).<br />
round(I(R1)*1k)/1k ; same display format as above, but expression is of the current through R1.<br />
round(V(1,2)*1k)/1k ; same format, but expression is of the voltage difference between nodes 1 & 2.<br />
<br />
<br />
====Bussing of Connections and Components (BUS shorthand notation)====<br />
<br />
LTspice has an undocumented feature to draw busses (groups of nets) on the schematic.&nbsp; This feature is erratic.&nbsp; It is recommended to double check the resulting circuit by studying the netlist (main menu View->SPICE Netlist), because it is possible to attach wires to busses without exactly knowing which signal (net) from the bus the wire should actually represent.&nbsp; Busses are purely cosmetic on the schematic, they have no special SPICE function.&nbsp; All bussing notation is resolved (flattened to normal net notation) by the schematic editor prior to the creation of the SPICE netlist (the netlister does not understand bus notation, i.e. it it not possible to use a SPICE deck with bus notation in LTspice).<br />
<br />
An alternative to busses is to use individual net labels to connect distant nets.<br />
<br />
A net (wire) becomes a bus whenever any one of the following three conditions are met:<br />
<br />
# The wire is labeled with a netname with an array suffix.&nbsp; An array suffix consists of two numbers separated by a colon and enclosed in brackets.&nbsp; For example ''Data[0:7]'' means the bus consists of the eight nets ''Data[0]'', ''Data[1]'', up to ''Data[7]''. <br />
# The wire is connected to the wide end of a BUS tap (main menu Edit->Place BUS tap). <br />A net connected to the other end, the pointed end of a tap, is called a tap net, and is an individual net from the nets represented by the bus.&nbsp; Tap nets must be labeled with an individual array element suffix (a single number without colon enclosed in brackets).&nbsp; For example ''Data[3]'' would be the label of a tap net out of the ''Data[0:7]'' bus.<br />
# The net is connected to a bus pin of a component that has an array type name.<br />
<br />
Once a wire is becoming a bus it is automatically drawn with extra thick lines.<br />
<br />
A bus may be automatically connected (netlisted) to a corresponding array of components.&nbsp; An array of components is created by appending a bracketed array specifier to the instance name (reference designator) of a bus-connected single component.&nbsp; For example, instead of naming a transistor ''Q1'' naming it ''Q[1:4]'' would result in the single symbol representing four identical transistors.&nbsp; The base, collector and emitter pins of these component array all need to be connected to busses.&nbsp; For example to busses called ''Base[1:4]'', ''Collector[1:4]'', and ''Emitter[1:4]''.&nbsp; The resulting netlist is arbitrary if the pins of a component array are not properly connected to busses, but e.g. accidentally to single nets only.<br />
<br />
Note that recursive connections are possible around a single device or device group through the use of appropriate net labeling.&nbsp; For example', a single digital DFLOP device may be annotated to represent a 64 shift-register string by:<br />
<br />
# adding a 64 element array suffix to its instance name, e.g. ''A1'' would become ''A1[0:63]'',<br />
# placing on its D input a corresponding array net label, e.g., ''Data[0:63]'' (the particular name is unimportant), and<br />
# placing on its Q output an appropriately displaced array net label, e.g., ''Data[1:64]''.<br />
<br />
The result would be that the D inputs of A1[1] to A1[63] are connected to the Q outputs of A1[0] to A1[62].&nbsp; The D input of A1[0] (''Data[0]'') and Q output of A1[63] (''Data[64]'') need to be tapped off individually from the bus, and would represent the input and output of the resulting 64 bit shift register.<br />
<br />
; Example Notes<nowiki>:</nowiki><br />
: As usual for any flip-flop, a delay parameter must be specified in the Value field, e.g., ''td=10ns''.<br />
: The D input to the first gate may be individually accessed by its appropriate array index, e.g., ''Data[0]''<br />
<br />
<br />
====Title Block====<br />
<br />
The schematic editor can display a special symbol as a title block.&nbsp; This is a combined feature of the schematic editor and the symbol editor.&nbsp; The feature is purely cosmetic.&nbsp; It allows to decorate a schematic so it looks more like a traditional drawing (depending on what is actually in the title block symbol). <br />
<br />
The title block needs to be created in the form of a symbol (.asy file), and be of symbol type MASTER.&nbsp; However, the LTspice symbol editor does not allow the creation of a symbol with such a type, while editing such a symbol is possible.&nbsp; Therefore, it is initially necessary to created an empty MASTER symbol with a text editor.&nbsp; Once initially created it can be opened and edited in LTspice.<br />
<br />
To start it is enough to create a .asy file with the following two lines in a text editor<br />
<br />
Version 4<br />
SymbolType MASTER<br />
<br />
Once saved from the text editor the file can then be opened in LTspice and the drawing commands can be used to design the title block, e.g. a frame, and several text fields.&nbsp; Pins must not be added to a title block symbol.&nbsp; Once saved in a project's directory, the title block can be added to a schematic just like any other symbol. <br />
<br />
Since it is difficult to edit a schematic while a title block is visible (attempting to select a component results in the selection of the title block instead), the title block may be turned on and off via the following option.<br />
<br />
View->Control Panel->Drafting Options->Show Title Blocks<br />
<br />
Before printing a page with a title block it is advisable to adjust the zooming of the schematic in the schematic editor, so the schematic with the title block exactly fits the screen.&nbsp; This can be done either via the toolbar button "Zoom full extents" or the menu item View->Zoom to fit.&nbsp; This assumes every symbol has been drawn within the boundaries of the title block.<br />
<br />
Here is an example of a simple title block symbol [[File:Title-block.asy]].<br />
<br />
<br />
=== Symbol Editor ===<br />
<br />
====Placing the ''Linear Technology'' or ''Analog Devices'' logos[[File:Logos.gif|100x24px]] within a Symbol====<br />
<br />
The text '''''LT''''' or '''''ADI''''' (must be all uppercase) in a symbol (menu Draw->Text) is replaced with the corresponding company logo when the symbol is used on a schematic.<br />
<br />
====Cut & Paste Between Symbols====<br />
<br />
Unfortunately this has yet to be implemented.&nbsp; Two workarounds are possible, but they are both cumbersome.<br />
<br />
# Open the symbol you wish to copy, then immediately save it with a new name.&nbsp; Modifying first before saving is dangerous because this requires always remembering to change the name after a distracting editing process.&nbsp; However, if the original ''is'' inadvertently overwritten, as long as the file is not closed the original may be recovered by repeatedly pressing the Undo key and then resaving.<br />
# Use a text editor to open both symbol files and copy the ASCII drawing command sequences from one file to the other.&nbsp; The commands are not difficult to read for selective editing, but the entire sequence also may be copied over and then subsequently graphically cleaned up from within LTspice's symbol editor.<br />
<br />
<br />
=== Plotting ===<br />
<br />
==== Cross Probing Key Combination ====<br />
<br />
* Clicking '''Alt-Left''' on a label in the plot pane highlights the corresponding node in the schematic (since end of October 2012 release).&nbsp; E.g. clicking '''Alt-Left''' on a label like ''V(n001)'' in the plot pane highlights the ''n001'' node.&nbsp; Clicking '''Alt-Left''' on a label like''I(R1)'' highlights ''R1'' in the schematic.<br />
<br />
<br />
==== Eye Diagram ====<br />
<br />
LTspice can plot eye diagrams - a feature which is only semi-documented.&nbsp; The following two "Plot Settings" menu items related to eye diagrams<br />
<br />
[select a plot pane (.raw)]<br />
Plot Settings->Eye Diagram->Enable<br />
Plot Settings->Eye Diagram->Properties<br />
<br />
They are usually disabled.&nbsp; LTspice enables them when adding the insufficiently documented, baudrate-option <br />
<br />
.option baudrate=<rate><br />
<br />
to a schematic.&nbsp; Instead of <rate> the nominal symbol rate of the signal should be given.&nbsp; <rate> defines at what intervals the signal should be triggered.<br />
<br />
Once enabled the <br />
<br />
Plot Settings->Eye Diagram->Properties<br />
<br />
menu item allows to set two more eye diagram properties.&nbsp; An initial delay, which effectively specifies where the eye(s) should be plotted on the horizontal axis.&nbsp; And the number of eyes, which is equivalent how many trigger intervals should be displayed.<br />
<br />
The following schematics both contain a baudrate option, but it is commented out. <br />
<br />
examples/Education/PLL.asc<br />
examples/Education/PLL2.asc<br />
<br />
Uncommenting the option, running the simulation, enabling the eye diagram in the Plot Settings, and then probing the signal net (not the out net) gives a typical eye diagram.<br />
<br />
<br />
=== Probing Subcircuit Waveforms (signal naming conventions) ===<br />
<br />
To be able to display subcircuit waveforms, you must first ensure that the ''Save Subcircuit Node Voltages'' and the ''Save Subcircuit Device Currents'' options are enabled in the '''Save Defaults''' tab of the [[Control Panel]].&nbsp; Then, if your simulation was created as a hierarchical design using LTspice's '''Schematic Capture''' window, you may simply use the probe tool to select an active subcircuit schematic's nodes as required.&nbsp; But if the SPICE netlist was imported from an external source then the probe statement format is as follows:<br />
<br />
* a top level node:<br />
.probe v(node)<br />
<br />
* a subcircuit node:<br />
.probe v(subckt_name:node)<br />
.probe v(subckt_name:subsubckt_name:node)<br />
<br />
* a subcircuit MOSFET drain current:<br />
.probe id(subckt_name:mp1)<br />
<br />
<br />
=== Netlists ===<br />
<br />
A netlist line starting with "'''*!LTspice:''' " is now treated as a SPICE directive for LTspice (but a comment in other SPICE programs). - 09/05/06<br />
<br />
= References & Footnotes =<br />
<br />
<references/><br />
<br />
<br />
{{#widget:DISQUS<br />
|id=ltwiki<br />
|uniqid={{PAGENAME}}<br />
|url={{fullurl:{{PAGENAME}}}}<br />
}}</div>Analogspicemanhttp://ltwiki.org/index.php?title=Undocumented_LTspice&diff=2123Undocumented LTspice2019-11-24T05:42:36Z<p>Analogspiceman: /* Circuit Element Area Multiplier */</p>
<hr />
<div>== Introduction ==<br />
'''Please submit your requests for additions or changes to ''Undocumented LTspice'' on the "discussion" page (second tab above).'''<br />
<br />
LTspice/SwitcherCAD III is a complete and fully functional SPICE program (electronic circuit simulator) that is available free of charge from the Linear Technology Corporation (LTC).&nbsp; Because of its superior performance, excellent community support and ease of file sharing, it is rapidly replacing all other SPICE programs, regardless of price, as the simulator of choice for hobbyists, students and professionals alike.<br />
<br />
The purpose of this topic is to explore and explain '''''some''''' of the many useful or quirky features that have never appeared in the standard documentation whether due to simple oversight, the feature being considered not important enough, not polished enough or functionally obsolete – or even due to the feature being considered proprietary to another brand of SPICE or to LTspice itself.&nbsp; LTC considers some of these undocumented features as fair game for open discussion in public forums such as the LTspice Yahoo users group, whereas for others, it considers any such open discussions as a violation of its License Agreement.<br />
<br />
"''Fair game''" is any feature that is or has ever been part of the normal distribution, i.e., appears or ever has appeared in the Help file, as plain text in any of the included sample or example files, in any program menu available during normal use of the program, or in any of the materials, presentation files or handouts from any LTspice seminar presentation.&nbsp; Such items are all considered as having been officially "''documented''" and are specifically allowed as discussion topics in public forums such as the LTspice Yahoo users group.&nbsp; However, be advised that any items that have been dropped from the documentation, even if still functional, should generally be considered obsolete and in risk of being purged from the program code at any time (fortunately, such items are quite rare).<br />
<br />
As to the classification of anything not covered above, you must make your own common sense judgment or ask the advice of the users group moderator or the program author via private email.&nbsp; Clearly any standard, generic SPICE feature that works in LTspice would be okay for general use and discussion regardless of its state of documentation in LTspice.&nbsp; A lot of the standard devices have undocumented parameters (e.g., tempcos) or syntax (e.g., Pspice specific compatibility) that would fall into this category.&nbsp; Just as clearly, any undocumented A-device that is specific to LTC’s encrypted, high performance SMPS IC models would likely be considered proprietary knowledge to be protected with due diligence from release to the public domain, lest LTC’s competitors gain the de facto permission to freely copy them in their own circuit simulator offerings (however, it is difficult to see how LTC could legitimately prevent private individuals from making use of such undocumented features in their own simulations or discussing them via private communications).&nbsp; For these reasons, this last category of undocumented features will not be directly discussed here.<br />
<br />
== Numerical Accuracy/Dynamic Range ==<br />
<br />
LTspice generally represents numbers using 64 bit double precision arithmetic with the following data structure:<br />
<br />
[[File:IEEE_754_Double_Floating_Point_Format.png|frameless|700px|<b>Sign: 1 bit, exponent: 11 bits, fraction: 52 bits.</b>]]<br />
<br />
For general component values LTspice will accept numbers that range in magnitude from as large as &plusmn;&thinsp;1.798 x 10<sup>+308</sup> down to as small as &plusmn;&thinsp;2.225 x 10<sup>&minus;308</sup>.&ensp; Values exceeding this range are interpreted as &plusmn; infinity or as zero.&nbsp; However, because of the 52 bit precision of the fractional part of the significand, the practical numerical dynamic range will be circuit dependent.&nbsp; A 53 bit binary significand gives LTspice about 16 significant figures for internal math computations.&nbsp; Thus, if impedances vary by more than 16 orders of magnitude, numerical difficulties may ensue, depending on the topology of the circuit (this is because matrix solving frequently involves differencing two very similar numbers &ndash; for example, the next larger number than one is 1.0000000000000002 &ndash; anything closer is not resolvable).&nbsp; LTspice's proprietary alternate solver extends this precision by about another 3 orders of magnitude at a cost of a modest speed penalty.<br />
<br />
<br />
== A-Devices ==<br />
<br />
A-devices are Linear Technology Corporation's proprietary special function/mixed mode circuit simulation elements.&nbsp; According to LTspice’s Help file, the behavior of a number of these is undocumented because they frequently change with each new set of models available for LTspice (such changes actually are quite rare and this reason is most likely offered as both as a credible reason for keeping them hidden and to discourage anyone from bothering to attempt to explore and/or use them).<br />
<br />
The Help file lists A-device syntax as:<br />
Annn n001 n002 n003 n004 n005 n006 n007 n008 <model> [instance parameters]<br />
Note that all A-devices have up to 8 possible active device connections, up to 5 inputs (terminals 1 through 5) usually 2 outputs (terminals 6 and 7), and with terminal 8 always as the device common.&nbsp; A-devices are always netlisted with the full eight connections.&nbsp; The netlister connects any unused inputs and outputs to terminal 8.&nbsp; The A-device compiler recognizes this condition as a flag that that terminal is not used and removes it from the simulation matrix.&nbsp; Current is sourced or sunk from the outputs (typically the Q or main output on terminal 7 and the Q&#773; or complementary output on terminal 6) and is returned through device common, terminal 8.<br />
<br />
A-devices are implemented this way to allow a single device type to act as any combination of a 1 to 5 input, 1 to 2 output device, but with no simulation speed penalty for unused terminals.&nbsp; Refer to the program Help file for more details about LTspice’s documented A-devices.<br />
<br />
Here is a listing of all known LTspice A-devices.<br />
<br />
<u>Documented directly in Help:</u><br />
* '''Buf''' (aka Buf1 Inv)<br />
* '''AND'''<br />
* '''OR'''<br />
* '''XOR''' – when more than two inputs are present, uses the correct definition of ''true if one and only one input is true'', rather than the more common <u>incorrect</u> definition of ''true if an odd number of inputs are true'' (which should be called an '''ODD/NODD''' gate rather than an '''XOR/XNOR''' gate).<br />
* '''Schmitt''' (aka SchmittBuf SchmittInv DifSchmitt DiffSchmittBuf DiffSchmittInv)<br />
* '''Dflop''' (CLR takes precedence over PRE, also a start up state may be set – see '''SRflop''')<br />
* '''Varistor'''<br />
* '''Modulator''' (aka Modulate Modulate2)<br />
<u>Not documented in Help but available via the schematic Component Selector:</u><br />
* '''SRflop''' – located in Digital<br />
* '''PhaseDet''' (aka PhiDet) – located in Digital<br />
* '''Counter''' – located in Digital and documented in the users group (has been officially approved for public use)<br />
* '''SampleHold''' (aka Sample) – located in Special Functions<br />
<u>Documented in sample schematics included with the program distribution:</u><br />
* '''PhaseDet''' (aka PhiDet) – located in examples/Educational/PLL2.asc<br />
* '''SampleHold''' (aka Sample) – located in examples/Educational/S&H.asc<br />
* '''OTA''' – used in UniversalOpamp plaintext subcircuits (in lib/sub), but users group posts (some long standing) containing information about additional aspects of this have been censored<br />
<u>Not documented anywhere by LTC:</u><br />
* '''XxxxxxXxxx''' – prior long standing users group posts about this digital toggle type device have now been censored<br />
* '''XxXxxXXX''' – DAC type device never discussed in the users group<br />
* '''XXXXX''' – DAC type device never discussed in the users group<br />
* '''XXXX''' – DAC type device never discussed in the users group<br />
* '''Xxx''' – amplifier type device never discussed in the users group<br />
<u>Not documented anywhere by LTC</u>, but the first two of these devices were extensively documented in the users group.&nbsp; All three devices were eliminated /protected in June 2006 (approximately at release 2.17u ) and all users group posts (some long standing) about these devices have been censored /deleted from the users group archive:<br />
* '''XXXxxxx''' – PWM current mode control comparator and latch<br />
* '''XxxXxx''' – used for making PWM IC External Oscillators<br />
* '''Xxxxx''' – used for making PWM IC oscillators<br />
<u>Obsolete devices that have been deleted from the LTspice executable:</u><br />
* '''JKflop'''<br />
* '''PGateDrive'''<br />
* '''invPGateDrive'''<br />
* '''invGateDrive'''<br />
The three DACs, XxXxxXXX, XxxXXX, XXXX, are specialized A-devices that probably are of little general interest (although their functions and pinouts could likely be easily guessed by examining the data sheets of the few specialized LTC ICs making use of them).<br />
<br />
The XXXX seems to be the only straightforward, generic DAC, but very spice-efficient DACs are quite easy to make using standard, approved devices.<br />
<br />
<br />
----<br />
=== SRflop ===<br />
The Set/Reset Flip-Flop symbol is located in the ''Digital'' symbol folder.<br />
* The '''R''' (reset) input takes precedence over the '''S''' (set) input.<br />
* The start up state of the flip-flop (initial condition) may be specified by adding an "'''ic='''" attribute.<br />
** An "'''ic'''" value > '''Ref''' interprets to a high, e.g., "'''ic=1'''" sets the '''Q''' output high and "'''ic=0'''" sets it low.&nbsp; (Note: the logic threshold '''Ref''' parameter defaults to 0.5 and its use is documented in '''Help'''.)<br />
<br />
<br />
----<br />
=== PhaseDet (aka PhiDet) ===<br />
The Phase Detector symbol is located in the ''Digital'' symbol folder.<br />
<br />
The Examples folder contains a schematic with some documentation: ''Examples/Educational/PLL2.asc''<br />
<br />
<br />
----<br />
=== SampleHold (aka Sample) ===<br />
<br />
The Sample & Hold symbol is located in the ''Special Functions'' symbol folder.<br />
<br />
An example schematic, ''S&H.asc'', is located in the ''Examples/Educational'' schematic folder.<br />
<br />
The behavioral a-device Sample and Hold has two modes of operation.&nbsp; The output may follow the input whenever the '''S/H''' input is true or the output may latch to the input when the '''CLK''' input goes true.&nbsp; Note that ''one and only one'' of these two inputs must be connected.<br />
<br />
Parameters unique to the Sample and Hold a-device are as follows:<br />
*'''Rout''' defaults to 1kΩ (instead of the standard a-device 1Ω).<br />
*'''Vhigh''' defaults to 10V and Vlow defaults to -10V (note: these are output voltage saturation levels).<br />
<br />
<br />
----<br />
=== OTA ===<br />
<br />
The OTA (Operational Transconductance Amplifier) is used in the various UniversalOpamp plaintext subcircuits (located in a standard LTspice program installation in ''lib/sub'').<br />
<br />
The default transfer function is a hyperbolic tangent (tanh), which closely approximates the transfer function of a bipolar transistor differential amplifier (this limit can be disabled by adding the flag parameter, '''Linear''').&nbsp; Two differential input pairs are available on pins 1 and 2 ( &minus; + ) and on pins 3 and 4 ( + &minus; ).&nbsp; The transconductance current source output appears on pin 7.&nbsp; As usual, pin 8, if connected, becomes the device's floating "gnd" reference.&nbsp; For reference, a dc "rail" voltage, which represents the maximum possible output (calculated from combining both voltage and current saturation limits), appears on pin 6.&nbsp; This voltage reflects the negative limit only and has an output impedance identical to that of the main output.<br />
<br />
<br />
'''<u>Parameters:</u>''' (* indicates an undocumented parameter)&nbsp; Note all OTA parameters were undocumented until November 2019.<br />
* '''Ref''' (default = 0V) is the input offset voltage<br />
* '''G''' (default = 1u-mho) is the raw input "gain" (transconductance), where Vdiff = ( '''Ref''' – V(1,2) ) * V(3,4)&nbsp; and Iraw = '''G''' * Vdiff<br />
* '''Iout''' (default = 10uA) is the output saturation current, which may be superseded by one or both of<br />
** '''Isrc''' (or '''Isource''', default = '''Iout''') is the output sourcing saturation current<br />
** '''Isink''' (a negative number, default = &minus;'''Iout''') is the output sinking saturation current<br />
*** '''Asym''' is a flag parameter that, if present, enables independent asymmetrical limits for '''Isrc/Isource''' and '''Isink'''<br />
*** '''Linear''' is a flag parameter that, if present, disables output limiting<br />
* *'''Ioffset''' (default = 0A) is the output offset current<br />
* *'''PowerUp''' (default = true) is a Boolean parameter that if < 0.5 disables all pin 7 output current<br />
* '''EAclk''' (default = none) is the reference designator of the gate indicating a clock period for steady state detection (net zero current out of the OTA integreated over this period is deemed steady state)<br />
* '''Ibuck''' (default = 0A) is the expression of current that is presumed to not be involved in slewing the voltage of the compensation capacitor<br />
* '''Rout''' (default = 1/Gmin) is the internal output resistance<br />
* '''Cout''' (default = 0F) is the capacitance in parallel with '''Rout'''<br />
* '''Vhigh''' (default = 2V) is the positive output "rail" voltage (set to 1e308 to disable limit)<br />
* '''Vlow''' (default = 0V) is the negative output "rail" voltage (set to &minus;1e308 to disable limit)<br />
* '''Rclamp''' (default = 1Ω) is the clamping resistance to the voltage rails<br />
* '''Epsilon''' (default = 0V) is the voltage range to gradually switch in '''Rclamp''' impedance<br />
* '''EN''' (default = 0V/√Hz) is the voltage noise density<br />
* '''ENk''' (default = 0Hz) is the voltage noise knee frequency<br />
* '''IN''' (default = 0A/√Hz) is the current noise density<br />
* '''INk''' (default = 0Hz) is the current noise knee frequency<br />
* '''INcm''' (default = 0A/√Hz) is the common mode current noise density<br />
* '''INcmk''' (default = 0Hz) is the common mode current noise knee frequency<br />
<br />
<br />
'''<u>Output Current Limit:</u>'''<br />
* With no flag parameter: Io = tanh ( Iraw / Isat ) * Isat + Idc + '''Ioffset'''&nbsp; (note that one limit's action/shape is affected by the opposing limit's magnitude)<br /> ''where'' Vdiff = ( '''Ref''' – V(1,2) ) * V(3,4) , Iraw = '''G''' * Vdiff , Isat = ( '''Isink''' – '''Isrc''' ) / 2&nbsp; and Idc = ( '''Isink''' + '''Isrc''' ) / 2 ; ('''Isink''' is a ''negative number'' )<br />
* With the '''Asym''' flag parameter: Io = if ( Vdiff , tanh ( Iraw / '''Isrc''' ) * '''Isrc''' , tanh ( Iraw / '''Isink''' ) * '''Isink''' ) + '''Ioffset''' <br /> ''note that'' the "if ( <polarity test>, <then action>, <else action> )" conditional statement completely separates the positive and negative limits<br />
* With the '''Linear''' flag parameter: Io = Iraw + '''Ioffset''' (output current does not saturate)<br />
* Note that in all cases the final value of Io is multiplied by buf&thinsp;( '''PowerUp''' )<br />
<br />
<br />
'''<u>Output Voltage Limit:</u>'''<br />
* Clamps through a resistance of '''Rclamp''' to "rails" of '''Vhigh''' and &minus;'''Vlow'''<br />
<br />
<br />
'''<u>Noise Voltage Density:</u>'''<br />
* Vnoise = ('''EN''' + '''IN''' * Rin_equivalent) * '''G''' * '''Rout'''<br />
<br />
<br />
----<br />
<br />
=== Counter (divide by n): ===<br />
<br />
The Counter symbol is located in the ''Digital'' symbol folder (added October 2013).<br />
<br />
This device divides the input pulse stream on the '''CLK''' input (terminal 1) by the parameter '''cycles''' (required) with the divided output pulse stream appearing on the '''Phi1''' main '''Q''' output (terminal 7) and the '''Phi2''' complementary '''Q&#773;''' output (terminal 6).&nbsp; Counting occurs at the rising edge of the pulse stream and duty cycle may be specified.&nbsp; A reset input is available on terminal 2, but this terminal is not present on the standard symbol.&nbsp; Initially and after a reset, the Counter starts high, then goes high again on every Nth edge after that, where N= round('''cycles''').&nbsp; Note that output behavior is inverted compared to a standard ripple counter.<br />
<br />
Parameters unique to the Counter a-device are as follows:<br />
*'''Cycles''' divides the rising edge input pulse stream by round(<exp>) where <exp> is the expression assigned to this mandatory parameter.<br />
*'''Duty''' specifies the output pulse width = round('''cycles'''*'''duty'''). Duty cycle defaults to 0.5 if '''duty''' is omitted.<br />
Most of the usual digital a-device parameters may also be optionally applied, e.g., '''Trise''', '''Vhigh''', '''Vlow''', '''Ref''', etc. with the exception of '''Td''', which is ignored (the Counter accepts no delay).<br />
<br />
The '''cycles''' expression accepts b-source syntax and thus may be a simple constant or may be a complex expression containing constants, parameters, functions, the keyword '''time''', node voltages and branch currents.&nbsp; The Counter output will go to zero whenever the value of '''cycles''' falls below 1.5.&nbsp; If the Counter is clocked when the value of '''cycles''' is below 1.5, the Counter is reset.<br />
<br />
To use this symbol a '''cycles''' parameter must be specified after placing the symbol on a schematic (right-click on the symbol to open the "Component Attribute Editor" window and, in the '''Value''' attribute field, enter a '''cycles''' parameter, e.g. "cycles=2" for a divide by two counter).<br />
<br />
A symbol including the reset input and test circuit is available in the online Yahoo LTspice users group: ''Files/Tut/Digital A-Devices''.&nbsp; Alternately, LTspice's standard S/R flip-flop symbol may be used to stand in for the Counter with reset by editing its '''SpiceModel''' attribute from "SRFLOP" to "Counter" after it has been placed on the schematic ('''S''' becomes the clock input, '''R''' becomes the reset input and '''Q''' and '''Q&#773;''' become the two outputs).<br />
<br />
<br />
== B-Sources ==<br />
<br />
While many b-source features were not documented until relatively recently (~2007), most are now at least touched upon in Help and the few that are not are covered in the [[B sources (complete reference)]] in this wiki.<br />
* '''Cpar'''&nbsp; In addition to the parameter '''Rpar''' (which is documented in Help), current source type behavioral sources (i.e., "I=" "R=" and "P=") now accept the '''Cpar''' parameter to specify a parallel capacitance.&nbsp; Current derived b-sources driving one ohm in parallel with a small capacitance (e.g., Rpar=1 Cpar=1n) are much more convergence friendly than stiff voltage sources and should be used whenever possible.&nbsp; Nortonizing voltage sources to current sources in parallel with one ohm requires no conversion calculation, but the Nortonized parallel impedance may be set as low as desired if the current source gain is up scaled to compensate.<br />
* '''Bn P=f(...)'''&nbsp; Arbitrary Power Sink/source where '''f''' is a constant or is an arbitrary function of any valid node voltage, branch current, etc. as with standard b-sources (note: power is sourced when '''f''' is negative).&nbsp; In order to avoid large currents at voltages near zero, the arbitrary power sink/sources foldbacks to resistive behavior when the absolute value of voltage across the device falls below a default value of 1 volt.&nbsp; The foldback point may be modified by specifying a '''VprXover''' parameter for the device, e.g. '''VprXover=50mV'''. <br />
* '''Bn R=f(...)'''&nbsp; Arbitrary Resistor where '''f''' is an arbitrary function of '''x''' (which has the special meaning of the voltage across '''R''' in this context) and/or any valid node voltage, branch current, etc. as with standard b-sources.<br />
* '''[[units] Freq=<valuelist> [delay=<value>]]'''&nbsp; (Pspice compatible format)<br /> The transfer function of the Freq circuit element is specified by an ordered list of points of freq(Hz), mag(dB) and phase(deg) as follows: <(f1,m1,p1)[(f2,m2,p2)...]> where f1<f2<f3, etc.&nbsp; The following units specifiers may optionally precede the Freq keyword: “rad”=radians, “mag”=non dB, (“dB” and “deg” return the defaults), “r_i”=real and imaginary in place of magnitude and phase.&nbsp; If a delay value is called out, the phases of the table values are modified to reflect the delay (delay is automatically adjusted to maintain causality in any case). <br />
* '''NoJacob'''&nbsp; The optional '''NoJacob''' flag parameter unburdens a device from carrying the mathematical overhead of a Jacobian.&nbsp; For linear or certain well behaved b-source expressions, this small reduction in computational burden can reduce run times slightly.&nbsp; Use with extreme caution, as this greatly increases the risk of creating convergence problems or other errors if misapplied. <br />
* '''~'''&nbsp; Boolean operator: convert succeeding expression to Boolean then invert<br />
* '''=='''&nbsp; Boolean operator: true if preceding expression is equal to succeeding expression, otherwise false<br />
* '''boltz'''&nbsp; Boltzmann constant = 1.38062 e-23<br />
* '''planck'''&nbsp; Planck's constant = 6.62620 e-34<br />
* '''echarge'''&nbsp; Charge of an electron = 1.6021765 e-19<br />
* '''kelvin'''&nbsp; Absolute Zero in degrees C = -273.150<br />
* '''Gmin'''&nbsp; Minimum conductance = 1e-12 (or as set in the '''Control Panel''' or via an .option statement)<br />
** '''Gmin''' is added to every PN junction to aid convergence and is the default off-conductance for current or voltage controlled switches and LTspice's idealized diode model.<br />
* '''square(x)'''&nbsp; Function = x**2<br />
* '''tbl'''&nbsp; Alternate function name, aka '''table''' (look-up table)<br />
* '''stp(x)'''&nbsp; Alternate function name, aka '''u(x)''' (unit step)<br />
* '''fra(x)'''&nbsp; Function, very similar to '''white(x)''', but = 0 if not SMPS in steady state condition<br />
* '''UpLim(x, pos, z)'''&nbsp; Function, similar to '''Min(x, y)''', but "'''z'''" defines a zone with quadratic soft limiting (note: "'''x'''" and "'''pos'''" are ''not'' strictly interchangeable and "'''z'''" must be the end argument)<br />
.func '''UpLim'''(x, y, z) if(y-x < z, y - z*exp((y-x-z)/z), x) ; this is '''UpLim's''' equivalent mathematical function<br />
* '''DnLim(x, neg, z)'''&nbsp; Function, similar to '''Max(x, y)''', but "'''z'''" defines a zone with quadratic soft limiting (note: "'''x'''" and "'''neg'''" are ''not'' strictly interchangeable and "'''z'''" must be the end argument)<br />
.func '''DnLim'''(x, y, z) if(x-y < z, y + z*exp((x-y-z)/z), x) ; this is '''DnLim's''' equivalent mathematical function<br />
* '''UpLim(DnLim(x, neg, z_dn), pos, z_up)'''&nbsp; Composite function, similar to '''Limit(x, neg, pos)''', but with up and down soft limit zones (note: arguments are ''not'' commutative)<br />
.func '''RndLim'''(x, neg, pos, z)= '''UpLim'''('''DnLim'''(x, neg, z), pos, z)<br />
* As with the hard limit functions, any or all arguments may be constants or functions of time, node voltages, branch currents, etc.: '''''UpLim'''(13, V(1,2)*I(Vs), Min(time**2, 5))''.<br />
* When their soft limits are greater than zero, these functions have continuous derivatives for superior dc convergence over '''Min()''', '''Max()''' and '''Limit()'''.<br />
* Outside their soft limit zones these functions are perfectly linear which may make them superior to '''tanh()''' as a smooth limit function in amplifier macro-modeling applications.<br />
<br />
Note that LTspice can execute behavioral sources in either 2G6, PSpice, or Berkeley SPICE syntax in addition to its own enlarged set of behavioral language.<br />
<br />
<br />
== G-Sources ==<br />
<br />
G-Sources have two additional parameters, Vto (threshold) and dir (direction)<br />
<br />
Here is the equivalent function:<br />
<br />
.func Gsq(x, gain, Vto, dir)=<br />
+ gain*if(dir==0, x, sgn(dir)*uramp(sgn(dir)*(x-Vto))**2)<br />
<br />
where x=V(nc+,nc-), the control voltage per the usual G syntax notation from Help:<br />
<br />
Gxxx n+ n- nc+ nc- <gain><br />
<br />
Here is a component where this feature is used, along with conventional G-Sources [http://ltwiki.org/files/LTC6268.zip LTC6268]<br><br />
<br />
<br />
== Standard Sources ==<br />
<br />
Add documentation for data file input and triggered sources and the Pspice compatible behavioral forms for E and G sources (at some point, perhaps ~2007, these were added to Help).<br />
<br />
<br />
=== Piecewise Linear Sources (PWL) ===<br />
<br />
LTspice supports many more forms of the PWL statement than given in the documentation.&nbsp; LTspice is largely compatible with other SPICE versions, providing similar or identical PWL features.<br />
<br />
The non-documented PWL statements can be added on a schematic by first adding a normal source from the Component library, and using the Advanced setting of the source to set the function of the source to one of the two available PWL functions.&nbsp; Once the source is placed on the schematic a right-click on the PWL statement allows to edit it.&nbsp; Once the PWL statement has been changed to a non-documented PWL statement it can also be edited by right-clicking on the component symbol.&nbsp; The right-click will then no longer bring up the special window for changing a source function, but the generic component attribute editor.&nbsp; The PWL statement goes into the value field.<br />
<br />
The principle form of the PLW statement is<br />
<br />
PWL [VALUE_SCALE_FACTOR=<vsf>]<br />
[TIME_SCALE_FACTOR=<tsf>]<br />
<data specification><br />
[TRIGGER <trigger expression>]<br />
<br />
The functions of the scale factors are obvious.&nbsp; When given, each value or time in the <data specification> is multiplied by them.&nbsp; The default for each factor is 1.<br />
<br />
The <data specification> is very flexible.&nbsp; Data can either be provided directly in the statement, or by referring to a file (these are documented features).&nbsp; Further, data can be specified so it is repeated a number of times, or forever (both undocumented).&nbsp; Also, data can be specified in a relative way (undocumented).&nbsp; And finally, specifications can be combined to a certain extent (undocumented).<br />
<br />
The simplest form of a <data specification> is a list of one or more data points.&nbsp; Each point is a pair of a time <t''x''> and a value <v''x''> values.&nbsp; A pair can, but need not be, grouped together by brackets.&nbsp; Using brackets simplifies the reading of longer lists.&nbsp; Also, commas can be used to separate and group data points. <br />
<br />
PWL <t1> <v1> <...> <tn> <vn><br />
PWL (<t1> <v1> <...> <tn> <vn>)<br />
PWL (<t1> <v1>) <...> (<tn> <vn>)<br />
PWL <t1>, <v1> <...> <tn>, <vn><br />
<br />
The usual suffixes, like ''m'' for milli or 'k' for kilo can be used both for times and values, e.g.:<br />
<br />
PWL (0m 1 1m 2 1m 3 4m 2)<br />
<br />
A value <v''x''> can also be an expression in curly brackets.&nbsp; However, while function names like ''sin()'' are recognized, the keyword ''time'' is not.&nbsp; This makes it difficult, probably impossible, to generate time-dependent data, like ''{sin(time)}'' or ''{rand(time)}'' (to generate random noise)<ref>Other SPICE versions have no such problem with ''time''</ref>.<br />
<br />
PWL (0 {sin(1)}) (1 {sin(2)})<br />
<br />
Time values <t''x''> can be specified as relative to the previous time value, by prefixing the value with a ''+'' sign, e.g. specifying values at 0, 1, 2, and 7 seconds:<br />
<br />
PWL (0 1 +1 2 +1 3 +5 2)<br />
<br />
Instead of placing the values directly into the PWL statement they can also be placed in a file, and the file referred in the PWL statement<br />
<br />
PWL file=<name of the file><br />
<br />
A list of data points or a file reference can be repeated a fixed amount of times <n>, or forever<br />
<br />
PWL REPEAT FOR <n> (<data list>|<file spec>) ENDREPEAT<br />
PWL REPEAT FOREVER (<data list>|<file spec>) ENDREPEAT<br />
<br />
E.g. to repeat a sequence of values for five times<br />
<br />
PWL REPEAT FOR 5 ( 0 1 1 1 2 2 3 1 ) ENDREPEAT<br />
PWL REPEAT FOR 5 ( file=<name of file> ) ENDREPEAT<br />
<br />
Data specifications can be combined, e.g:<br />
<br />
PWL (0 0 1 1 2 1 3 0) REPEAT FOR 5 (file=<name of file>) ENDREPEAT<br />
PWL REPEAT FOR 7 (file=pwl_data.txt) ENDREPEAT REPEAT FOR 6 (file=pwl_data2.txt) ENDREPEAT<br />
<br />
Repeat statements can be nested, e.g.:<br />
<br />
PWL REPEAT FOREVER (0 1 1 2) REPEAT FOR 3 (2 3 3 1) ENDREPEAT ENDREPEAT<br />
<br />
The <trigger expression> turns the source's output on as long as the expression is true.&nbsp; For example, if there is a node n001 in the circuit, the following will turn the output on as long as the node's voltage is greater 1.5V.&nbsp; A source that is turned off is 'stuck' at the first value given in its specification.&nbsp; In the following example the first pair is (0 0), i.e. a value of 0 at time 0.&nbsp; Therefore, when turned off, the source will be stuck at 0.<br />
<br />
PWL ( 0 0 1 1 2 1 3 0) TRIGGER V(n001)>1.5<br />
<br />
<br />
== Standard Devices ==<br />
<br />
=== Diodes: Sidewall Parameters ===<br />
<br />
LTspice (04/05/10) now supports the following diode sidewall parameters:<br />
* '''perim''': Sidewall perimeter (periphery) ; default value = 0m.<br />
* '''Isw''': Sidewall saturation current ; default value = 0A.<br />
* '''Ns''': Sidewall junction emission coefficient ; default value = N (I when Level=11)?<br />
* '''Rsw''': Sidewall series resistance ; default value = 0 ohm.<br />
* '''Cjsw''': Sidewall zero-bias capacitance ; default value = 0.9F * perim?<br />
* '''Vjsw''': Sidewall junction potential ; default value = Vj (1 when Level=11)?<br />
* '''Mjsw''': Sidewall grating coefficient ; default value = 0.33.<br />
* '''Fcs''': Sidewall forward-bias depletion capacitance coefficient ; default value = 0.5 (Fc when Level = 11)?<br />
<br />
<br />
----<br />
=== BJTs: Additional Gummel-Poon Parameters ===<br />
<br />
Bipolar CB avalanche breakdown is modeled in the LTspice Gummel-Poon device:<br />
* '''BVcbo''': C-B breakdown voltage.<br />
* '''nBVcbo''': breakdown emission coefficient ; default value = 1?<br />
* '''TBVcbo1''': linear temperature coefficient of breakdown voltage.<br />
* '''TBVcbo2''': quadratic temperature coefficient of breakdown voltage.<br />
<br />
Bipolar BE breakdown is also in the LTspice Gummel-Poon device:<br />
* '''BVbe''': B-E breakdown voltage.<br />
* '''IBVbe''': breakdown current at breakdown voltage.<br />
* '''nBVbe''': breakdown emission coefficient.<br />
<br />
<br />
----<br />
=== VDMOS: Breakdown, Sub-threshold Enhancements ===<br />
<br />
LTspice now contains a number of otherwise undocumented parameters to enhance its proprietary VDMOS model.&nbsp; These allow for body diode breakdown, subthreshold conduction with independent fits to the saturation and linear regions of the output characteristics and mobility reduction due to large Vgs.&nbsp; Most of these have recently become documented in the Help file (** denotes still undocumented).<br />
<br />
* '''BV''': breakdown voltage.<br />
* '''IBV''': breakdown current at breakdown voltage.<br />
* '''nBV''': breakdown emission coefficient.<br />
* '''Mtriode''': A conductance multiplier for the triode region.&nbsp; It allows independent matching of the saturation and linear regions of the MOSFET.<br />
* '''subthres''': The current (per volt Vds) at which the square-law drain current verses Vgs switches over to exponential.<br />
* '''theta''': ** mobility reduction due to large Vgs (limits drain current to direct gate voltage dependence instead of square law).<br />
<br />
<br />
<u>'''VDMOS Capacitance (Cgd Curve Fit Equation)'''</u><br />
<br />
LTspice Help outlines how LTspice generates the VDMOS nonlinear gate-drain capacitance, presenting the general form of the equations used, but it does not reveal the details of the parameters used by the fit equations.&nbsp; Help states that the capacitance expression fit uses two expressions, one for negative gate-drain voltages and another for positive.&nbsp; These expressions meet at zero voltage and it may be assumed that at this point, they must be identical in value and slope.&nbsp; This reduces the system to two equations in two unknowns, allowing a solution for the remaining fit parameters to be obtained.&nbsp; For the following equations, "'''s'''" is the slope at the zero point, "'''y'''" is the offset and "'''x'''" is the gate-drain voltage (''not'' the drain-source voltage).<br />
<br />
* Positive gate-drain voltage region: '''Cgd = s * tanh(a*x) + y''' (inversion region - switch is on)<br />
* Negative gate-drain voltage region: '''Cgd = s * atan(a*x) + y''' (Vds large - switch is off or turning off)<br />
<br />
Where '''s = (Cgdmax - Cgdmin)/(1 + Pi/2)''' and '''y = Cgdmax - s''' and "'''a'''", '''Cgdmax''' and '''Cgdmin''' are existing VDMOS model parameters.<br />
<br />
Note that in Help the unspecified parameters are given as '''A''', '''B''', '''C''', and '''D'''. These parameters are equivalent to '''s''' and '''y''' as follows: '''A = C = s''' and '''B = D = y'''.<br />
<br />
<br />
----<br />
=== Capacitors ===<br />
<br />
==== Capacitor Multipliers ====<br />
Capacitors allow an alternate form for the device multiplier m=<value> (number of units in parallel - see [[C_Capacitor|Capacitors in Help]]).&nbsp; In place of "m=<number>", "x<number>" may be used, i.e.: x2, x 2, x0.5, x3.14159.&nbsp; Note that whitespace may optionally separate the leading x and the following number.<br />
<br />
<br />
----<br />
=== Inductors ===<br />
<br />
==== Maximum Coupling Factor ====<br />
In LTspice, it is not really possible to set the winding coupling factor (K) exactly to unity.&nbsp; A little experimentation reveals this number to be 1-1n=.999999999.&nbsp; For 1-1n < k <=1, LTspice sets k=1-1n, never informing the user, not even in the error log where the netlist has been flattened and abstract expressions have been converted to numerics.<br />
<br />
If k is set to greater than one, LTspice issues a warning that k has been reduced to one (which actually is 1-1n).&nbsp; However this action is not reflected in the netlist nor in the error log's digested netlist.<br />
<br />
<br />
----<br />
=== Resistors ===<br />
<br />
==== Behavioral Resistors ====<br />
<br />
Create a behavioral resistor by right-mouse-button clicking on its Value field and edit its value to read: R=<expression>.&nbsp; This feature is undocumented, but is considered permissible to use.&nbsp; The expression syntax is the same as for a general behavioral source (see [[B_Arbitrary_behavioral_voltage_or_current_sources|B-sources in Help]]).<br />
<br />
The resistance must not go to zero and negative values can lead to convergence problems, so it is advisable to restrict its values to within a meaningful range as per the following Value example:<br />
<br />
R = limit(1,100k,V(1,2)*I(V1)) ; R stays between 1 ohm and 100k<br />
<br />
To plot an I-V curve, start by using the differential cursor to plot the voltage across the resistor.&nbsp; First click and hold down the left-mouse-button (red probe icon) on one side of the resistor and then drag and drop the black probe icon on the other side.&nbsp; Finish by dragging the mouse pointer over the x-axis (a ruler icon will appear) and the click the left mouse button to bring up the Horizontal Axis menu.&nbsp; Change the Quantity Plotted from "time" to "I(R1)" (assuming R1 is your behavioral resistor).<br />
<br />
<br />
==== Behavioral Resistor & Power Sink/Source ====<br />
<br />
Arbitrary Power Sink or Source where the function '''P=f()''' for power '''f''' is a constant or is an arbitrary function of any valid node voltage, branch current, etc. as with standard b-sources (note: power is sourced when '''f''' is negative).&nbsp; In order to avoid large currents at voltages near zero, the arbitrary power sink/sources foldbacks to resistive behavior when the absolute value of voltage across the device falls below a default value of 1 volt.&nbsp; The foldback point may be modified by specifying a '''VprXover''' parameter for the device, e.g. '''VprXover=50mV'''.<br />
<br />
Bxxx n1 n2 P=<expression> [VprXover=<value>] ; example: B1 1 0 P=500W VprXover=5V (R=50mΩ below 5V)<br />
<br />
<br />
==== Dual Value Resistors (for ac analysis) ====<br />
<br />
LTspice is like Hspice in that it allows resistors to have different dc and ac values.&nbsp; If ''ac=<value>'' is specified as a resistor parameter (either immediately after the normal dc value or in the '''Value2''' field), the operating point is calculated using the dc value of resistance, but the ac resistance value is used in the ac analysis.&nbsp; This may be useful when analyzing operational amplifiers, since the operating point computation can be performed on the unity gain configuration using a low value for the feedback resistance and the ac analysis may then be performed on a nearly open loop configuration by specifying a very large value for the ac resistance.<br />
<br />
<br />
==== Resistor (and Capacitor) Model Statements ====<br />
<br />
It's not in the .model section of the Help file, but LTspice seems to recognize standard model statements for resistors (RES) and capacitors (CAP), but not inductors (IND).<br />
<br />
As in many other SPICE simulators, "RES" and "CAP" are allowed as model keywords.&nbsp; For example, with the following line of spicetext<br />
<br />
.model X7R cap (T_measured=20 Tc1=0 Tc2=-19u)<br />
<br />
on a schematic, if a capacitor then has "X7R" entered into its "SpiceModel" field (via ctrl-right mouse click) its base value will be multiplied by the following temperature factor, TF<br />
<br />
TF = 1 + Tc1*(T-Tmeasured) + Tc2*(T-Tmeasured)**2<br />
where T = the global temperature TEMP or the local instance if specified.<br />
<br />
I haven't checked if higher order factors are accepted or if voltage or current factors can be used (they work for some other SPICEs).<br />
<br />
The Help file specifies the optional instance of [temp=<value>] syntax for resistors, capacitors and inductors, but only for capacitors does it define this as "instance temperature (for tempcos in a corresponding .model statement)," although nothing further about the model syntax is mentioned.<br />
<br />
The help file does not document the "noiseless" control parameter which applies to the resistance in many LTspice circuit elements with resistive elements (resistors, switches, RC lines, others).&nbsp; As its name suggests, this parameter blocks its applicable element's contribution to noise calculations.<br />
<br />
<br />
----<br />
=== Lossy Transmission Lines ===<br />
<br />
There are two undocumented lossy transmission line models implemented in LTspice.&nbsp; One is CPL model (P device), and the other is TXL model (Y device).<br />
<br />
The undocumented CPL is a K-Spice-like element, which in theory should be similar to the RLGC model, but without frequency dependent loss (neither skin effect and nor frequency dependent dielectric loss).&nbsp; It also has at least one bug causing an incorrect output voltage offset (a workaround is to only use signals with no dc offset). <br />
<br />
Below are example netlists from K-Spice, which have been translated as required (very little) into LTspice syntax.<br />
<pre><br />
****** test circuit for CPL transmission line simulation *******<br />
*<br />
M1 0 268 299 0 MN0P9 w=18u l=1u<br />
M2 299 267 748 0 MN0P9 w=18u l=1u<br />
M3 0 168 648 0 MN0P9 w=18u l=0u9<br />
M4 1 268 748 1 MP1P0 w=36u l=1u<br />
M5 1 267 748 1 MP1P0 w=36u l=1u<br />
M6 1 168 648 1 MP1P0 w=36u l=1u<br />
*<br />
CN648 648 0 25f4<br />
CN651 651 0 7f4<br />
CN748 748 0 25f4<br />
CN751 751 0 9f4<br />
CN299 299 0 5f4<br />
*<br />
P1 648 748 0 651 751 0 Pline<br />
*<br />
vdd 1 0 DC 5<br />
Vk 267 0 DC 5<br />
*<br />
*Vs 168 0 PWL (4 15n9 0 16n1 5 31n9 5 32n1 0)<br />
*Vs 268 0 PWL (4 15n9 0 16n1 5 31n9 5 32n1 0)<br />
*<br />
Vs1 168 0 Pulse (0 5 15n9 0n2 0n2 15n8 60n)<br />
Vs2 268 0 Pulse (0 5 15n9 0n2 0n2 15n8 60n)<br />
*<br />
.tran 0n2 47n9 0 1n<br />
.model Pline CPL<br />
+ R=0.2 0 0.2<br />
+ L=9n13 3n3 9n13<br />
+ G=0 0 0<br />
+ C=365f -90f 365f<br />
+ Length=24<br />
********************** MODEL SPECIFICATION **********************<br />
.model MN0P9 NMOS Vto=0.8 Kp=48u Gamma=0.30 Phi=0.55 Lambda=0<br />
+ Cgso=0 Cgdo=0 Cj=0 Cjsw=0 Tox=18u Ld=0<br />
.model MP1P0 PMOS Vto=-0.8 Kp=21u Gamma=0.45 Phi=0.61 Lambda=0<br />
+ Cgso=0 Cgdo=0 Cj=0 Cjsw=0 Tox=18u Ld=0<br />
.end<br />
<br />
******* test circuit for TXL transmission line simulation *******<br />
M5 0 168 2 0 MN0P9 w=18u l=0u9<br />
M6 1 168 2 1 MP1P0 w=36u l=1u<br />
Cn2 2 0 25f4<br />
Cn3 3 0 7f4<br />
Y1 2 0 3 0 Ymod<br />
Vdd 1 0 dc 5.0<br />
Vs 168 0 Pulse (0 5 15n9 0n2 0n2 15n8 32n)<br />
*Vs 168 0 PWL(15n9 0 16n1 5 31n9 5 32n1 0)<br />
.tran 0n2 47n 0 0n1<br />
.model MN0P9 NMOS Vto=0.8 Kp=48u Gamma=0.3 Phi=0.55 Lambda=0<br />
+ Cgso=0 Cgdo=0 Cj=0 Cjsw=0 Tox=18u Ld=0<br />
.model MP1P0 PMOS Vto=-0.8 Kp=21u Gamma=0.45 Phi=0.61 Lambda=0<br />
+ Cgso=0 Cgdo=0 Cj=0 Cjsw=0 Tox=18u Ld=0<br />
.model Ymod Txl R=12.45 L=9u G=0 C=0p47 Length=16<br />
.end<br />
</pre><br />
<br />
<br />
----<br />
=== Voltage Controlled Switches ===<br />
<br />
LTspice has a cleaner syntax for voltage controlled switches, but has no problem with any PSpice voltage controlled switch syntax.<br />
<br />
<br />
== Dot Commands ==<br />
=== .Ac (ac analysis) ===<br />
<br />
In an ac analysis, it seems that the maximum number of points that may calculated is limited to about 65k.&nbsp; If more are requested, LTspice will reduce the point count to this maximum, but without generating an error or warning.&nbsp; This limitation may become significant when attempting to simulate very high Q circuits over too broad a frequency range (e.g., crystal oscillators showing overtones).<br />
<br />
<br />
----<br />
=== .Options ===<br />
<br />
Note: ".opt" is accepted as shorthand notation for ".options" (options are added as text onto the schematic as a [[SPICE Directive]]).<br />
<br />
There are a whole lot of .option parameters and other control parameters (mostly legacy from SPICE 2 and Pspice) that should be documented (a few probably actually could be useful).&nbsp; Many of these are listed in the LTspice Yahoo group message [http://tech.groups.yahoo.com/group/LTspice/message/20174 #20174].<br />
<br />
<br />
==== .options List ====<br />
<br />
This flag parameter causes a dump of the flatened netlist (after expanding subcircuits) to appear in the '''SPICE Error Log''' file (sticky and causes the corresponding '''Generate Expanded Listing''' option check box in '''Operation''' tab of the [[Control Panel]] to become checked).<br />
<br />
.opt List ; selects "Generate Expanded Listing" in the Control Panel<br />
<br />
<br />
==== .options DampInductors=<''value''> ====<br />
<br />
This has the same effect as unchecking (value=0) or checking (value=1) the '''Rpar''' inductor option on the '''Hacks''' tab of the '''Control Panel''', overriding whatever is set there (the default value in LTspice is 1 or ''ON'', which is opposite the standard SPICE convention).&nbsp; The default value for the parallel damping resistance equals 1e12 times the inductance value (1T x L) and is only applied in the case of a transient analysis.<br />
<br />
.opt DampInductors=0 ; turn off LTspice's default parallel damping resistance<br />
<br />
<br />
==== .options Thev_Induc=<''value''> ====<br />
<br />
This has the same effect as unchecking (value=0) or checking (value=1) the '''Rser''' inductor option on the '''Hacks''' tab of the '''Control Panel''', overriding whatever is set there (the default value in LTspice is 0 or ''ON'', which is opposite the standard SPICE convention).&nbsp; The default value for the series damping resistance equals 1 milliohm and is applied to all analyses.<br />
<br />
.opt Thev_Induc=1 ; turn off LTspice's default 1 milliohm series damping resistance (R = 0)<br />
<br />
Notes:<br />
* Using the standard SPICE convention settings for these two inductor options causes the circuit matrix to be bigger, run slower and be more prone to convergence errors.<br />
* I have yet to discover how to alter the global default enabled values for Rpar and Rser (changing Gmin has no effect on the parallel damping resistance for inductors). <br />
<br />
<br />
==== .options Gfarad=<''value''> ====<br />
<br />
Added at LTspice version 4.14h (per public posting by Yahoo LTspice group moderator, Helmut Sennewald, 04/13/12).<br />
<br />
This option allows the user to set the global value for a capacitor's default parallel conductance factor (1/'''Rpar''' = Gpar = '''Gfarad'''*C).<br />
<br />
.opt Gfarad=1e-12 ; has no effect because this is the existing default conductance factor<br />
.opt Gfarad=0 ; sets the global conductance factor to zero (removes the hidden default parallel resistance for all capacitors)<br />
<br />
Notes:<br />
* As a convergence aid, capacitors in LTspice include a hidden default parallel resistance of '''Rpar''' = 1e12/C.&nbsp; Specifying any value for '''Equiv. Parallel Resistance''' ('''Rpar''') in a capacitor's '''Component Editor''' window will override this default.&nbsp; Specifying a value of zero ('''Rpar'''=0) removes the default resistance (sets the conductance to zero).<br />
* The arbitrary capacitor (specified via a behavioral charge equation - refer to the topic in '''Help''') has no parallel conductance and is not affected by '''Gfarad'''.<br />
<br />
<br />
==== .options Gfloat=<''value''> ====<br />
<br />
This option allows the user to set the global value for the shunt conductance from floating nodes to ground.<br />
<br />
.opt Gfloat=1e-12 ; has no effect because this is the existing default conductance factor (which is Gshunt)<br />
.opt Gfloat=0 ; sets the global conductance factor to zero (removes the hidden default ground shunt resistance for all floating nodes)<br />
<br />
Notes:<br />
* As a convergence aid, floating nodes in LTspice include a hidden default shunt resistance to ground.&nbsp; The default value is equal to the value of '''Gshunt''' (which also may be optionally set - refer to the topic in '''Help''').&nbsp; Specifying a value for '''Gfloat''' will override this default.&nbsp; Specifying a value of zero removes the default shunt resistance (sets the conductance to zero).<br />
* Floating nodes are typically created when only connected to capacitors and/or current sources.<br />
<br />
<br />
==== .options TopologyCheck=2 ====<br />
<br />
Listed in the ChangeLog 09/14/11: "Beta Optimisations regarding dangling nodes."<br />
<br />
Setting this parameter to 2 has the same effect as checking '''Enable beta circuit matrix optimizations''' on the '''Hacks''' tab of the '''Control Panel''', overriding whatever is set there.<br />
<br />
.opt TopologyCheck=2 ; (parameter numbers 0 and 1 are documented in Help)<br />
<br />
<br />
==== .options tSeed=<''value''> ====<br />
<br />
This option lets you seed the integrator with a specific guess for the initial .tran timestep<br />
<br />
.opt tSeed=100n<br />
<br />
<br />
----<br />
=== .NodeAlias <''aliasName''> <''netName''> ===<br />
<br />
Listed in the ChangeLog 10/06/10: "Allows to give a net an alternative name." <br />
<br />
Placing the Jumper symbol (''lib/sym/Misc/jumper'') is another, documented and probably more convenient way of giving the same net two names, however, in a hierarchical design, it only functions on a top level schematic.<br />
<br />
.nodealias output drain<br />
<br />
<br />
== Miscellaneous Hints and Tricks ==<br />
<br />
... should be added here or given its own section if warranted.<br />
<br />
Here's a hint to anyone wishing to keep up-to-date with the latest additions to '''LTspice''''s great features - always read the '''''changelog.txt''''' file (located in the '''LTspiceIV''' program folder) after every web update /sync release.<br />
* From the ChangeLog on 02/21/07: "Added a check box on the Tools=>Control Panel=>Hacks! pane to allow the '''MC generator''' to be reseeded by the real time clock."<br />
<br />
<br />
'''A-Devices''' See message #19378 from the LTspice Yahoo users group.<br />
<br />
<br />
----<br />
=== Circuit Element Area Multiplier ===<br />
Only the following LTspice elements accept the ''Area Multiplier'' parameter, '''m'''=<value>, where '''m''' is the value by which the element area will be multiplied:<br />
<br />
'''C''' (Capacitors), '''D''' (Diodes), '''J*''' (JFETs), '''L''' (Inductors), '''M''' (MOSFETs), '''Q*''' (Bipolar Transistors) '''R*''' (Resistors), '''Z''' (MESFETs and IGBTs).<br />
<br />
<nowiki> </nowiki>'''''* m'''=<value> is an undocumented or poorly documented feature of this element''<br />
<br />
<br />
----<br />
<br />
=== Alternate Syntax ===<br />
<br />
In many contexts, where possible, LTspice supports alternate syntaxes compatible with other simulators.<br />
* Single quotes generally may be used in place of curly braces.<br />
<br />
<br />
=== AKO Aliases (A Kind Of) ===<br />
<br />
''Suppose I wished to modify a single parameter of an existing model but don't want to copy the full model out as a duplicate and adjust it.&nbsp; I want to pick up all of the specified and default parameter values for the given model name (and if it specifies yet another, to pick up those, as well) and simply modify one parameter or two in a new model.''<br />
<br />
''A reason I may wish to do this is that I may, at some later time, decide to modify the underlying model and I'd like all of the dependent models to pick up the underlying changes, automatically.&nbsp; I just don't know if there is syntax for it.&nbsp; Do you know?''<br />
<br />
Yes.&nbsp; Try something like this:<br />
<br />
.model 2N2222mod ako: 2N2222 bf=5 ; same except lower beta<br />
<br />
<br />
----<br />
> It appears that parameters must ultimately resolve to numbers instead of text.<br />
<br />
You are correct in your supposition - parameters must be numbers.<br />
<br />
> Is there a way to pass text to a subcircuit to do what I want?<br />
<br />
Yes.&nbsp; Models can take numeric alias using the AKO ("A Kind Of") function.<br />
These numeric aliases will work with parameter passing:<br />
<br />
.model 1 ako:2N3904 ;the existing 2N3904 model now also known as "1"<br />
.model 2 ako:2N2222 ;the existing 2N2222 model now also known as "2"<br />
<br />
This topic has been discussed many times in this forum before, but it may be difficult to search for because the name of the AKO function doesn't really correspond to "Also Known As" (it stands for "A Kind Of").<br />
<br />
You can find many examples using AKO in the Group archive here:<br />
<br />
Files -> Tut -> Stepping to the max<br />
<br />
<br />
=== Stepping a Model ===<br />
<br />
Sometimes it might be of interest to try out several different types of some component in a circuit, instead of just stepping a single parameter of a component.&nbsp; This can be done by giving the models that should be tried number-only names.&nbsp; For example, using the above discussed AKO feature, NPN transistors can be named as follows:<br />
<br />
.model 3904 ako:2N3904<br />
.model 2222 ako:2N2222<br />
.model 547 ako:BC547<br />
<br />
It is also possible to define a model with a number-only name from scratch:<br />
<br />
.model 4 NPN<br />
<br />
The next step is to add a spice directive to define a parameter, ''STM'' in the example below, which is stepped through the model names.&nbsp; Since the ''.step'' command can only step numeric values it is vital that the models have been given number-only names, as shown above. <br />
<br />
.step param STM list 3904 2222 547 4<br />
<br />
The last step is then to use the parameter in place of a model ''Value''.&nbsp; To make sure the parameter is evaluated, it needs to be placed in brakes.&nbsp; For example, the above defined parameter ''STM'' would be given in the form of ''{STM}'' as the ''Value'' of an NPN transistor symbol.<br />
<br />
<br />
=== Schematic Editor ===<br />
<br />
====Key Combination====<br />
* '''Shift-Ctrl-Alt-R''': Permanently renumbers all reference designators within the schematic.<br />
* '''Shift-Ctrl-Alt-H''': Temporarily highlights all hidden text within the schematic.<br />
* Hold down '''Ctrl''' when placing wires to route at any angle.<br />
* Hold down '''Ctrl''' when drawing lines to draw off grid.<br />
* Hold down '''Ctrl''' or '''Shift''' for more movement with '''arrow keys'''.<br />
* Hold down '''Ctrl''' ''and'' '''Shift''' for ''most'' movement with '''arrow keys'''.<br />
* Text preceeded with an underscore ("_") character will be displayed as overbarred (for active LOW digital signals).<br />
* '''Cross Probing''': Clicking '''Alt-Left''' on a label in the plot pane highlights the corresponding node in the schematic (since end of October 2012 release).&nbsp; E.g. clicking '''Alt-Left''' on a label like ''V(n001)'' in the plot pane highlights the ''n001'' node.&nbsp; Clicking '''Alt-Left''' on a label like ''I(R1)'' highlights ''R1'' in the schematic.<br />
<br />
<br />
====Operating Point Data Labels (visible numeric dc bias values)====<br />
<br />
LTspice has the ability to display dc operating point voltages, currents and expressions (e.g., power, energy, efficiency, etc.) directly within the schematic.&nbsp; Normally, labels are placed upon wires (nodes) much like '''Net Labels'''. <br />
<br />
<br />
===== Preparation =====<br />
<br />
To be able to place/show operating point data labels right-click on an empty area of the schematic and select "'''View'''" from the drop down menu list. <br />
* Checking "'''Show .op Data Flags'''" shows all operating point numerical information on the schematic.<br />
Further, in the main menu<br />
* Checking "'''Mark Unconn. Pins'''" (main menu -> View) shows anchor boxes on the schematic when a label is moved.<br />
<br />
<br />
===== Creating a Label when doing a .op Simulation =====<br />
<br />
When doing a DC operating point simulation (.op) an operating point data label can be created as follows<br />
<br />
* Run the .op simulation<br />
* Left-Click on a net (a wire).&nbsp; This creates a new label that can be placed with the cursor.<br />
<br />
<br />
===== Creating a Label when doing another Simulations =====<br />
<br />
When doing other kinds of simulations than a DC operating point simulation (.op) operating point data labels can be created by right-clicking on an empty area of the schematic, then selecting '''View->Place .op Data Label''' on the drop down menu.&nbsp; The new label can be attached to a net with the cursor.<br />
<br />
<br />
===== Format and Layout =====<br />
<br />
Once placed, an operating point data label may be freely moved or copied and then edited to be completely unrelated to the original node.&nbsp; It is of course possible to decorate a label by using the normal drawing functions.&nbsp; For example painting a rectangle around it (main menu Edit->Draw->Rectangle) or by placing some text nearby (main menu Edit->Text).<br />
<br />
Operating point data labels default to the display of the voltage of the node to which they are attached (signified by the dollar sign character "$"), but this may be edited to be any valid expression, including currents, powers or even the voltage of a specific node.&nbsp; Right-clicking on a operating point data label brings up a popup window for selecting the data to display or enter an expression.<br />
<br />
With fractional values, all available non-zero digits will be displayed, often resulting in unwanted numerical clutter.&nbsp; The number of visible digits may be aesthetically limited by appropriately editing the expression to be displayed.&nbsp; Examples of rounding expressions used for formating:<br />
<br />
round($*1k)/1k ; display no more than 3 digits (typically automatically expressed in engineering format).<br />
round(I(R1)*1k)/1k ; same display format as above, but expression is of the current through R1.<br />
round(V(1,2)*1k)/1k ; same format, but expression is of the voltage difference between nodes 1 & 2.<br />
<br />
<br />
====Bussing of Connections and Components (BUS shorthand notation)====<br />
<br />
LTspice has an undocumented feature to draw busses (groups of nets) on the schematic.&nbsp; This feature is erratic.&nbsp; It is recommended to double check the resulting circuit by studying the netlist (main menu View->SPICE Netlist), because it is possible to attach wires to busses without exactly knowing which signal (net) from the bus the wire should actually represent.&nbsp; Busses are purely cosmetic on the schematic, they have no special SPICE function.&nbsp; All bussing notation is resolved (flattened to normal net notation) by the schematic editor prior to the creation of the SPICE netlist (the netlister does not understand bus notation, i.e. it it not possible to use a SPICE deck with bus notation in LTspice).<br />
<br />
An alternative to busses is to use individual net labels to connect distant nets.<br />
<br />
A net (wire) becomes a bus whenever any one of the following three conditions are met:<br />
<br />
# The wire is labeled with a netname with an array suffix.&nbsp; An array suffix consists of two numbers separated by a colon and enclosed in brackets.&nbsp; For example ''Data[0:7]'' means the bus consists of the eight nets ''Data[0]'', ''Data[1]'', up to ''Data[7]''. <br />
# The wire is connected to the wide end of a BUS tap (main menu Edit->Place BUS tap). <br />A net connected to the other end, the pointed end of a tap, is called a tap net, and is an individual net from the nets represented by the bus.&nbsp; Tap nets must be labeled with an individual array element suffix (a single number without colon enclosed in brackets).&nbsp; For example ''Data[3]'' would be the label of a tap net out of the ''Data[0:7]'' bus.<br />
# The net is connected to a bus pin of a component that has an array type name.<br />
<br />
Once a wire is becoming a bus it is automatically drawn with extra thick lines.<br />
<br />
A bus may be automatically connected (netlisted) to a corresponding array of components.&nbsp; An array of components is created by appending a bracketed array specifier to the instance name (reference designator) of a bus-connected single component.&nbsp; For example, instead of naming a transistor ''Q1'' naming it ''Q[1:4]'' would result in the single symbol representing four identical transistors.&nbsp; The base, collector and emitter pins of these component array all need to be connected to busses.&nbsp; For example to busses called ''Base[1:4]'', ''Collector[1:4]'', and ''Emitter[1:4]''.&nbsp; The resulting netlist is arbitrary if the pins of a component array are not properly connected to busses, but e.g. accidentally to single nets only.<br />
<br />
Note that recursive connections are possible around a single device or device group through the use of appropriate net labeling.&nbsp; For example', a single digital DFLOP device may be annotated to represent a 64 shift-register string by:<br />
<br />
# adding a 64 element array suffix to its instance name, e.g. ''A1'' would become ''A1[0:63]'',<br />
# placing on its D input a corresponding array net label, e.g., ''Data[0:63]'' (the particular name is unimportant), and<br />
# placing on its Q output an appropriately displaced array net label, e.g., ''Data[1:64]''.<br />
<br />
The result would be that the D inputs of A1[1] to A1[63] are connected to the Q outputs of A1[0] to A1[62].&nbsp; The D input of A1[0] (''Data[0]'') and Q output of A1[63] (''Data[64]'') need to be tapped off individually from the bus, and would represent the input and output of the resulting 64 bit shift register.<br />
<br />
; Example Notes<nowiki>:</nowiki><br />
: As usual for any flip-flop, a delay parameter must be specified in the Value field, e.g., ''td=10ns''.<br />
: The D input to the first gate may be individually accessed by its appropriate array index, e.g., ''Data[0]''<br />
<br />
<br />
====Title Block====<br />
<br />
The schematic editor can display a special symbol as a title block.&nbsp; This is a combined feature of the schematic editor and the symbol editor.&nbsp; The feature is purely cosmetic.&nbsp; It allows to decorate a schematic so it looks more like a traditional drawing (depending on what is actually in the title block symbol). <br />
<br />
The title block needs to be created in the form of a symbol (.asy file), and be of symbol type MASTER.&nbsp; However, the LTspice symbol editor does not allow the creation of a symbol with such a type, while editing such a symbol is possible.&nbsp; Therefore, it is initially necessary to created an empty MASTER symbol with a text editor.&nbsp; Once initially created it can be opened and edited in LTspice.<br />
<br />
To start it is enough to create a .asy file with the following two lines in a text editor<br />
<br />
Version 4<br />
SymbolType MASTER<br />
<br />
Once saved from the text editor the file can then be opened in LTspice and the drawing commands can be used to design the title block, e.g. a frame, and several text fields.&nbsp; Pins must not be added to a title block symbol.&nbsp; Once saved in a project's directory, the title block can be added to a schematic just like any other symbol. <br />
<br />
Since it is difficult to edit a schematic while a title block is visible (attempting to select a component results in the selection of the title block instead), the title block may be turned on and off via the following option.<br />
<br />
View->Control Panel->Drafting Options->Show Title Blocks<br />
<br />
Before printing a page with a title block it is advisable to adjust the zooming of the schematic in the schematic editor, so the schematic with the title block exactly fits the screen.&nbsp; This can be done either via the toolbar button "Zoom full extents" or the menu item View->Zoom to fit.&nbsp; This assumes every symbol has been drawn within the boundaries of the title block.<br />
<br />
Here is an example of a simple title block symbol [[File:Title-block.asy]].<br />
<br />
<br />
=== Symbol Editor ===<br />
<br />
====Placing the ''Linear Technology'' or ''Analog Devices'' logos[[File:Logos.gif|100x24px]] within a Symbol====<br />
<br />
The text '''''LT''''' or '''''ADI''''' (must be all uppercase) in a symbol (menu Draw->Text) is replaced with the corresponding company logo when the symbol is used on a schematic.<br />
<br />
====Cut & Paste Between Symbols====<br />
<br />
Unfortunately this has yet to be implemented.&nbsp; Two workarounds are possible, but they are both cumbersome.<br />
<br />
# Open the symbol you wish to copy, then immediately save it with a new name.&nbsp; Modifying first before saving is dangerous because this requires always remembering to change the name after a distracting editing process.&nbsp; However, if the original ''is'' inadvertently overwritten, as long as the file is not closed the original may be recovered by repeatedly pressing the Undo key and then resaving.<br />
# Use a text editor to open both symbol files and copy the ASCII drawing command sequences from one file to the other.&nbsp; The commands are not difficult to read for selective editing, but the entire sequence also may be copied over and then subsequently graphically cleaned up from within LTspice's symbol editor.<br />
<br />
<br />
=== Plotting ===<br />
<br />
==== Cross Probing Key Combination ====<br />
<br />
* Clicking '''Alt-Left''' on a label in the plot pane highlights the corresponding node in the schematic (since end of October 2012 release).&nbsp; E.g. clicking '''Alt-Left''' on a label like ''V(n001)'' in the plot pane highlights the ''n001'' node.&nbsp; Clicking '''Alt-Left''' on a label like''I(R1)'' highlights ''R1'' in the schematic.<br />
<br />
<br />
==== Eye Diagram ====<br />
<br />
LTspice can plot eye diagrams - a feature which is only semi-documented.&nbsp; The following two "Plot Settings" menu items related to eye diagrams<br />
<br />
[select a plot pane (.raw)]<br />
Plot Settings->Eye Diagram->Enable<br />
Plot Settings->Eye Diagram->Properties<br />
<br />
They are usually disabled.&nbsp; LTspice enables them when adding the insufficiently documented, baudrate-option <br />
<br />
.option baudrate=<rate><br />
<br />
to a schematic.&nbsp; Instead of <rate> the nominal symbol rate of the signal should be given.&nbsp; <rate> defines at what intervals the signal should be triggered.<br />
<br />
Once enabled the <br />
<br />
Plot Settings->Eye Diagram->Properties<br />
<br />
menu item allows to set two more eye diagram properties.&nbsp; An initial delay, which effectively specifies where the eye(s) should be plotted on the horizontal axis.&nbsp; And the number of eyes, which is equivalent how many trigger intervals should be displayed.<br />
<br />
The following schematics both contain a baudrate option, but it is commented out. <br />
<br />
examples/Education/PLL.asc<br />
examples/Education/PLL2.asc<br />
<br />
Uncommenting the option, running the simulation, enabling the eye diagram in the Plot Settings, and then probing the signal net (not the out net) gives a typical eye diagram.<br />
<br />
<br />
=== Probing Subcircuit Waveforms (signal naming conventions) ===<br />
<br />
To be able to display subcircuit waveforms, you must first ensure that the ''Save Subcircuit Node Voltages'' and the ''Save Subcircuit Device Currents'' options are enabled in the '''Save Defaults''' tab of the [[Control Panel]].&nbsp; Then, if your simulation was created as a hierarchical design using LTspice's '''Schematic Capture''' window, you may simply use the probe tool to select an active subcircuit schematic's nodes as required.&nbsp; But if the SPICE netlist was imported from an external source then the probe statement format is as follows:<br />
<br />
* a top level node:<br />
.probe v(node)<br />
<br />
* a subcircuit node:<br />
.probe v(subckt_name:node)<br />
.probe v(subckt_name:subsubckt_name:node)<br />
<br />
* a subcircuit MOSFET drain current:<br />
.probe id(subckt_name:mp1)<br />
<br />
<br />
=== Netlists ===<br />
<br />
A netlist line starting with "'''*!LTspice:''' " is now treated as a SPICE directive for LTspice (but a comment in other SPICE programs). - 09/05/06<br />
<br />
= References & Footnotes =<br />
<br />
<references/><br />
<br />
<br />
{{#widget:DISQUS<br />
|id=ltwiki<br />
|uniqid={{PAGENAME}}<br />
|url={{fullurl:{{PAGENAME}}}}<br />
}}</div>Analogspicemanhttp://ltwiki.org/index.php?title=Undocumented_LTspice&diff=2122Undocumented LTspice2019-11-24T05:16:57Z<p>Analogspiceman: /* Circuit Element Area Multiplier */ typo</p>
<hr />
<div>== Introduction ==<br />
'''Please submit your requests for additions or changes to ''Undocumented LTspice'' on the "discussion" page (second tab above).'''<br />
<br />
LTspice/SwitcherCAD III is a complete and fully functional SPICE program (electronic circuit simulator) that is available free of charge from the Linear Technology Corporation (LTC).&nbsp; Because of its superior performance, excellent community support and ease of file sharing, it is rapidly replacing all other SPICE programs, regardless of price, as the simulator of choice for hobbyists, students and professionals alike.<br />
<br />
The purpose of this topic is to explore and explain '''''some''''' of the many useful or quirky features that have never appeared in the standard documentation whether due to simple oversight, the feature being considered not important enough, not polished enough or functionally obsolete – or even due to the feature being considered proprietary to another brand of SPICE or to LTspice itself.&nbsp; LTC considers some of these undocumented features as fair game for open discussion in public forums such as the LTspice Yahoo users group, whereas for others, it considers any such open discussions as a violation of its License Agreement.<br />
<br />
"''Fair game''" is any feature that is or has ever been part of the normal distribution, i.e., appears or ever has appeared in the Help file, as plain text in any of the included sample or example files, in any program menu available during normal use of the program, or in any of the materials, presentation files or handouts from any LTspice seminar presentation.&nbsp; Such items are all considered as having been officially "''documented''" and are specifically allowed as discussion topics in public forums such as the LTspice Yahoo users group.&nbsp; However, be advised that any items that have been dropped from the documentation, even if still functional, should generally be considered obsolete and in risk of being purged from the program code at any time (fortunately, such items are quite rare).<br />
<br />
As to the classification of anything not covered above, you must make your own common sense judgment or ask the advice of the users group moderator or the program author via private email.&nbsp; Clearly any standard, generic SPICE feature that works in LTspice would be okay for general use and discussion regardless of its state of documentation in LTspice.&nbsp; A lot of the standard devices have undocumented parameters (e.g., tempcos) or syntax (e.g., Pspice specific compatibility) that would fall into this category.&nbsp; Just as clearly, any undocumented A-device that is specific to LTC’s encrypted, high performance SMPS IC models would likely be considered proprietary knowledge to be protected with due diligence from release to the public domain, lest LTC’s competitors gain the de facto permission to freely copy them in their own circuit simulator offerings (however, it is difficult to see how LTC could legitimately prevent private individuals from making use of such undocumented features in their own simulations or discussing them via private communications).&nbsp; For these reasons, this last category of undocumented features will not be directly discussed here.<br />
<br />
== Numerical Accuracy/Dynamic Range ==<br />
<br />
LTspice generally represents numbers using 64 bit double precision arithmetic with the following data structure:<br />
<br />
[[File:IEEE_754_Double_Floating_Point_Format.png|frameless|700px|<b>Sign: 1 bit, exponent: 11 bits, fraction: 52 bits.</b>]]<br />
<br />
For general component values LTspice will accept numbers that range in magnitude from as large as &plusmn;&thinsp;1.798 x 10<sup>+308</sup> down to as small as &plusmn;&thinsp;2.225 x 10<sup>&minus;308</sup>.&ensp; Values exceeding this range are interpreted as &plusmn; infinity or as zero.&nbsp; However, because of the 52 bit precision of the fractional part of the significand, the practical numerical dynamic range will be circuit dependent.&nbsp; A 53 bit binary significand gives LTspice about 16 significant figures for internal math computations.&nbsp; Thus, if impedances vary by more than 16 orders of magnitude, numerical difficulties may ensue, depending on the topology of the circuit (this is because matrix solving frequently involves differencing two very similar numbers &ndash; for example, the next larger number than one is 1.0000000000000002 &ndash; anything closer is not resolvable).&nbsp; LTspice's proprietary alternate solver extends this precision by about another 3 orders of magnitude at a cost of a modest speed penalty.<br />
<br />
<br />
== A-Devices ==<br />
<br />
A-devices are Linear Technology Corporation's proprietary special function/mixed mode circuit simulation elements.&nbsp; According to LTspice’s Help file, the behavior of a number of these is undocumented because they frequently change with each new set of models available for LTspice (such changes actually are quite rare and this reason is most likely offered as both as a credible reason for keeping them hidden and to discourage anyone from bothering to attempt to explore and/or use them).<br />
<br />
The Help file lists A-device syntax as:<br />
Annn n001 n002 n003 n004 n005 n006 n007 n008 <model> [instance parameters]<br />
Note that all A-devices have up to 8 possible active device connections, up to 5 inputs (terminals 1 through 5) usually 2 outputs (terminals 6 and 7), and with terminal 8 always as the device common.&nbsp; A-devices are always netlisted with the full eight connections.&nbsp; The netlister connects any unused inputs and outputs to terminal 8.&nbsp; The A-device compiler recognizes this condition as a flag that that terminal is not used and removes it from the simulation matrix.&nbsp; Current is sourced or sunk from the outputs (typically the Q or main output on terminal 7 and the Q&#773; or complementary output on terminal 6) and is returned through device common, terminal 8.<br />
<br />
A-devices are implemented this way to allow a single device type to act as any combination of a 1 to 5 input, 1 to 2 output device, but with no simulation speed penalty for unused terminals.&nbsp; Refer to the program Help file for more details about LTspice’s documented A-devices.<br />
<br />
Here is a listing of all known LTspice A-devices.<br />
<br />
<u>Documented directly in Help:</u><br />
* '''Buf''' (aka Buf1 Inv)<br />
* '''AND'''<br />
* '''OR'''<br />
* '''XOR''' – when more than two inputs are present, uses the correct definition of ''true if one and only one input is true'', rather than the more common <u>incorrect</u> definition of ''true if an odd number of inputs are true'' (which should be called an '''ODD/NODD''' gate rather than an '''XOR/XNOR''' gate).<br />
* '''Schmitt''' (aka SchmittBuf SchmittInv DifSchmitt DiffSchmittBuf DiffSchmittInv)<br />
* '''Dflop''' (CLR takes precedence over PRE, also a start up state may be set – see '''SRflop''')<br />
* '''Varistor'''<br />
* '''Modulator''' (aka Modulate Modulate2)<br />
<u>Not documented in Help but available via the schematic Component Selector:</u><br />
* '''SRflop''' – located in Digital<br />
* '''PhaseDet''' (aka PhiDet) – located in Digital<br />
* '''Counter''' – located in Digital and documented in the users group (has been officially approved for public use)<br />
* '''SampleHold''' (aka Sample) – located in Special Functions<br />
<u>Documented in sample schematics included with the program distribution:</u><br />
* '''PhaseDet''' (aka PhiDet) – located in examples/Educational/PLL2.asc<br />
* '''SampleHold''' (aka Sample) – located in examples/Educational/S&H.asc<br />
* '''OTA''' – used in UniversalOpamp plaintext subcircuits (in lib/sub), but users group posts (some long standing) containing information about additional aspects of this have been censored<br />
<u>Not documented anywhere by LTC:</u><br />
* '''XxxxxxXxxx''' – prior long standing users group posts about this digital toggle type device have now been censored<br />
* '''XxXxxXXX''' – DAC type device never discussed in the users group<br />
* '''XXXXX''' – DAC type device never discussed in the users group<br />
* '''XXXX''' – DAC type device never discussed in the users group<br />
* '''Xxx''' – amplifier type device never discussed in the users group<br />
<u>Not documented anywhere by LTC</u>, but the first two of these devices were extensively documented in the users group.&nbsp; All three devices were eliminated /protected in June 2006 (approximately at release 2.17u ) and all users group posts (some long standing) about these devices have been censored /deleted from the users group archive:<br />
* '''XXXxxxx''' – PWM current mode control comparator and latch<br />
* '''XxxXxx''' – used for making PWM IC External Oscillators<br />
* '''Xxxxx''' – used for making PWM IC oscillators<br />
<u>Obsolete devices that have been deleted from the LTspice executable:</u><br />
* '''JKflop'''<br />
* '''PGateDrive'''<br />
* '''invPGateDrive'''<br />
* '''invGateDrive'''<br />
The three DACs, XxXxxXXX, XxxXXX, XXXX, are specialized A-devices that probably are of little general interest (although their functions and pinouts could likely be easily guessed by examining the data sheets of the few specialized LTC ICs making use of them).<br />
<br />
The XXXX seems to be the only straightforward, generic DAC, but very spice-efficient DACs are quite easy to make using standard, approved devices.<br />
<br />
<br />
----<br />
=== SRflop ===<br />
The Set/Reset Flip-Flop symbol is located in the ''Digital'' symbol folder.<br />
* The '''R''' (reset) input takes precedence over the '''S''' (set) input.<br />
* The start up state of the flip-flop (initial condition) may be specified by adding an "'''ic='''" attribute.<br />
** An "'''ic'''" value > '''Ref''' interprets to a high, e.g., "'''ic=1'''" sets the '''Q''' output high and "'''ic=0'''" sets it low.&nbsp; (Note: the logic threshold '''Ref''' parameter defaults to 0.5 and its use is documented in '''Help'''.)<br />
<br />
<br />
----<br />
=== PhaseDet (aka PhiDet) ===<br />
The Phase Detector symbol is located in the ''Digital'' symbol folder.<br />
<br />
The Examples folder contains a schematic with some documentation: ''Examples/Educational/PLL2.asc''<br />
<br />
<br />
----<br />
=== SampleHold (aka Sample) ===<br />
<br />
The Sample & Hold symbol is located in the ''Special Functions'' symbol folder.<br />
<br />
An example schematic, ''S&H.asc'', is located in the ''Examples/Educational'' schematic folder.<br />
<br />
The behavioral a-device Sample and Hold has two modes of operation.&nbsp; The output may follow the input whenever the '''S/H''' input is true or the output may latch to the input when the '''CLK''' input goes true.&nbsp; Note that ''one and only one'' of these two inputs must be connected.<br />
<br />
Parameters unique to the Sample and Hold a-device are as follows:<br />
*'''Rout''' defaults to 1kΩ (instead of the standard a-device 1Ω).<br />
*'''Vhigh''' defaults to 10V and Vlow defaults to -10V (note: these are output voltage saturation levels).<br />
<br />
<br />
----<br />
=== OTA ===<br />
<br />
The OTA (Operational Transconductance Amplifier) is used in the various UniversalOpamp plaintext subcircuits (located in a standard LTspice program installation in ''lib/sub'').<br />
<br />
The default transfer function is a hyperbolic tangent (tanh), which closely approximates the transfer function of a bipolar transistor differential amplifier (this limit can be disabled by adding the flag parameter, '''Linear''').&nbsp; Two differential input pairs are available on pins 1 and 2 ( &minus; + ) and on pins 3 and 4 ( + &minus; ).&nbsp; The transconductance current source output appears on pin 7.&nbsp; As usual, pin 8, if connected, becomes the device's floating "gnd" reference.&nbsp; For reference, a dc "rail" voltage, which represents the maximum possible output (calculated from combining both voltage and current saturation limits), appears on pin 6.&nbsp; This voltage reflects the negative limit only and has an output impedance identical to that of the main output.<br />
<br />
<br />
'''<u>Parameters:</u>''' (* indicates an undocumented parameter)&nbsp; Note all OTA parameters were undocumented until November 2019.<br />
* '''Ref''' (default = 0V) is the input offset voltage<br />
* '''G''' (default = 1u-mho) is the raw input "gain" (transconductance), where Vdiff = ( '''Ref''' – V(1,2) ) * V(3,4)&nbsp; and Iraw = '''G''' * Vdiff<br />
* '''Iout''' (default = 10uA) is the output saturation current, which may be superseded by one or both of<br />
** '''Isrc''' (or '''Isource''', default = '''Iout''') is the output sourcing saturation current<br />
** '''Isink''' (a negative number, default = &minus;'''Iout''') is the output sinking saturation current<br />
*** '''Asym''' is a flag parameter that, if present, enables independent asymmetrical limits for '''Isrc/Isource''' and '''Isink'''<br />
*** '''Linear''' is a flag parameter that, if present, disables output limiting<br />
* *'''Ioffset''' (default = 0A) is the output offset current<br />
* *'''PowerUp''' (default = true) is a Boolean parameter that if < 0.5 disables all pin 7 output current<br />
* '''EAclk''' (default = none) is the reference designator of the gate indicating a clock period for steady state detection (net zero current out of the OTA integreated over this period is deemed steady state)<br />
* '''Ibuck''' (default = 0A) is the expression of current that is presumed to not be involved in slewing the voltage of the compensation capacitor<br />
* '''Rout''' (default = 1/Gmin) is the internal output resistance<br />
* '''Cout''' (default = 0F) is the capacitance in parallel with '''Rout'''<br />
* '''Vhigh''' (default = 2V) is the positive output "rail" voltage (set to 1e308 to disable limit)<br />
* '''Vlow''' (default = 0V) is the negative output "rail" voltage (set to &minus;1e308 to disable limit)<br />
* '''Rclamp''' (default = 1Ω) is the clamping resistance to the voltage rails<br />
* '''Epsilon''' (default = 0V) is the voltage range to gradually switch in '''Rclamp''' impedance<br />
* '''EN''' (default = 0V/√Hz) is the voltage noise density<br />
* '''ENk''' (default = 0Hz) is the voltage noise knee frequency<br />
* '''IN''' (default = 0A/√Hz) is the current noise density<br />
* '''INk''' (default = 0Hz) is the current noise knee frequency<br />
* '''INcm''' (default = 0A/√Hz) is the common mode current noise density<br />
* '''INcmk''' (default = 0Hz) is the common mode current noise knee frequency<br />
<br />
<br />
'''<u>Output Current Limit:</u>'''<br />
* With no flag parameter: Io = tanh ( Iraw / Isat ) * Isat + Idc + '''Ioffset'''&nbsp; (note that one limit's action/shape is affected by the opposing limit's magnitude)<br /> ''where'' Vdiff = ( '''Ref''' – V(1,2) ) * V(3,4) , Iraw = '''G''' * Vdiff , Isat = ( '''Isink''' – '''Isrc''' ) / 2&nbsp; and Idc = ( '''Isink''' + '''Isrc''' ) / 2 ; ('''Isink''' is a ''negative number'' )<br />
* With the '''Asym''' flag parameter: Io = if ( Vdiff , tanh ( Iraw / '''Isrc''' ) * '''Isrc''' , tanh ( Iraw / '''Isink''' ) * '''Isink''' ) + '''Ioffset''' <br /> ''note that'' the "if ( <polarity test>, <then action>, <else action> )" conditional statement completely separates the positive and negative limits<br />
* With the '''Linear''' flag parameter: Io = Iraw + '''Ioffset''' (output current does not saturate)<br />
* Note that in all cases the final value of Io is multiplied by buf&thinsp;( '''PowerUp''' )<br />
<br />
<br />
'''<u>Output Voltage Limit:</u>'''<br />
* Clamps through a resistance of '''Rclamp''' to "rails" of '''Vhigh''' and &minus;'''Vlow'''<br />
<br />
<br />
'''<u>Noise Voltage Density:</u>'''<br />
* Vnoise = ('''EN''' + '''IN''' * Rin_equivalent) * '''G''' * '''Rout'''<br />
<br />
<br />
----<br />
<br />
=== Counter (divide by n): ===<br />
<br />
The Counter symbol is located in the ''Digital'' symbol folder (added October 2013).<br />
<br />
This device divides the input pulse stream on the '''CLK''' input (terminal 1) by the parameter '''cycles''' (required) with the divided output pulse stream appearing on the '''Phi1''' main '''Q''' output (terminal 7) and the '''Phi2''' complementary '''Q&#773;''' output (terminal 6).&nbsp; Counting occurs at the rising edge of the pulse stream and duty cycle may be specified.&nbsp; A reset input is available on terminal 2, but this terminal is not present on the standard symbol.&nbsp; Initially and after a reset, the Counter starts high, then goes high again on every Nth edge after that, where N= round('''cycles''').&nbsp; Note that output behavior is inverted compared to a standard ripple counter.<br />
<br />
Parameters unique to the Counter a-device are as follows:<br />
*'''Cycles''' divides the rising edge input pulse stream by round(<exp>) where <exp> is the expression assigned to this mandatory parameter.<br />
*'''Duty''' specifies the output pulse width = round('''cycles'''*'''duty'''). Duty cycle defaults to 0.5 if '''duty''' is omitted.<br />
Most of the usual digital a-device parameters may also be optionally applied, e.g., '''Trise''', '''Vhigh''', '''Vlow''', '''Ref''', etc. with the exception of '''Td''', which is ignored (the Counter accepts no delay).<br />
<br />
The '''cycles''' expression accepts b-source syntax and thus may be a simple constant or may be a complex expression containing constants, parameters, functions, the keyword '''time''', node voltages and branch currents.&nbsp; The Counter output will go to zero whenever the value of '''cycles''' falls below 1.5.&nbsp; If the Counter is clocked when the value of '''cycles''' is below 1.5, the Counter is reset.<br />
<br />
To use this symbol a '''cycles''' parameter must be specified after placing the symbol on a schematic (right-click on the symbol to open the "Component Attribute Editor" window and, in the '''Value''' attribute field, enter a '''cycles''' parameter, e.g. "cycles=2" for a divide by two counter).<br />
<br />
A symbol including the reset input and test circuit is available in the online Yahoo LTspice users group: ''Files/Tut/Digital A-Devices''.&nbsp; Alternately, LTspice's standard S/R flip-flop symbol may be used to stand in for the Counter with reset by editing its '''SpiceModel''' attribute from "SRFLOP" to "Counter" after it has been placed on the schematic ('''S''' becomes the clock input, '''R''' becomes the reset input and '''Q''' and '''Q&#773;''' become the two outputs).<br />
<br />
<br />
== B-Sources ==<br />
<br />
While many b-source features were not documented until relatively recently (~2007), most are now at least touched upon in Help and the few that are not are covered in the [[B sources (complete reference)]] in this wiki.<br />
* '''Cpar'''&nbsp; In addition to the parameter '''Rpar''' (which is documented in Help), current source type behavioral sources (i.e., "I=" "R=" and "P=") now accept the '''Cpar''' parameter to specify a parallel capacitance.&nbsp; Current derived b-sources driving one ohm in parallel with a small capacitance (e.g., Rpar=1 Cpar=1n) are much more convergence friendly than stiff voltage sources and should be used whenever possible.&nbsp; Nortonizing voltage sources to current sources in parallel with one ohm requires no conversion calculation, but the Nortonized parallel impedance may be set as low as desired if the current source gain is up scaled to compensate.<br />
* '''Bn P=f(...)'''&nbsp; Arbitrary Power Sink/source where '''f''' is a constant or is an arbitrary function of any valid node voltage, branch current, etc. as with standard b-sources (note: power is sourced when '''f''' is negative).&nbsp; In order to avoid large currents at voltages near zero, the arbitrary power sink/sources foldbacks to resistive behavior when the absolute value of voltage across the device falls below a default value of 1 volt.&nbsp; The foldback point may be modified by specifying a '''VprXover''' parameter for the device, e.g. '''VprXover=50mV'''. <br />
* '''Bn R=f(...)'''&nbsp; Arbitrary Resistor where '''f''' is an arbitrary function of '''x''' (which has the special meaning of the voltage across '''R''' in this context) and/or any valid node voltage, branch current, etc. as with standard b-sources.<br />
* '''[[units] Freq=<valuelist> [delay=<value>]]'''&nbsp; (Pspice compatible format)<br /> The transfer function of the Freq circuit element is specified by an ordered list of points of freq(Hz), mag(dB) and phase(deg) as follows: <(f1,m1,p1)[(f2,m2,p2)...]> where f1<f2<f3, etc.&nbsp; The following units specifiers may optionally precede the Freq keyword: “rad”=radians, “mag”=non dB, (“dB” and “deg” return the defaults), “r_i”=real and imaginary in place of magnitude and phase.&nbsp; If a delay value is called out, the phases of the table values are modified to reflect the delay (delay is automatically adjusted to maintain causality in any case). <br />
* '''NoJacob'''&nbsp; The optional '''NoJacob''' flag parameter unburdens a device from carrying the mathematical overhead of a Jacobian.&nbsp; For linear or certain well behaved b-source expressions, this small reduction in computational burden can reduce run times slightly.&nbsp; Use with extreme caution, as this greatly increases the risk of creating convergence problems or other errors if misapplied. <br />
* '''~'''&nbsp; Boolean operator: convert succeeding expression to Boolean then invert<br />
* '''=='''&nbsp; Boolean operator: true if preceding expression is equal to succeeding expression, otherwise false<br />
* '''boltz'''&nbsp; Boltzmann constant = 1.38062 e-23<br />
* '''planck'''&nbsp; Planck's constant = 6.62620 e-34<br />
* '''echarge'''&nbsp; Charge of an electron = 1.6021765 e-19<br />
* '''kelvin'''&nbsp; Absolute Zero in degrees C = -273.150<br />
* '''Gmin'''&nbsp; Minimum conductance = 1e-12 (or as set in the '''Control Panel''' or via an .option statement)<br />
** '''Gmin''' is added to every PN junction to aid convergence and is the default off-conductance for current or voltage controlled switches and LTspice's idealized diode model.<br />
* '''square(x)'''&nbsp; Function = x**2<br />
* '''tbl'''&nbsp; Alternate function name, aka '''table''' (look-up table)<br />
* '''stp(x)'''&nbsp; Alternate function name, aka '''u(x)''' (unit step)<br />
* '''fra(x)'''&nbsp; Function, very similar to '''white(x)''', but = 0 if not SMPS in steady state condition<br />
* '''UpLim(x, pos, z)'''&nbsp; Function, similar to '''Min(x, y)''', but "'''z'''" defines a zone with quadratic soft limiting (note: "'''x'''" and "'''pos'''" are ''not'' strictly interchangeable and "'''z'''" must be the end argument)<br />
.func '''UpLim'''(x, y, z) if(y-x < z, y - z*exp((y-x-z)/z), x) ; this is '''UpLim's''' equivalent mathematical function<br />
* '''DnLim(x, neg, z)'''&nbsp; Function, similar to '''Max(x, y)''', but "'''z'''" defines a zone with quadratic soft limiting (note: "'''x'''" and "'''neg'''" are ''not'' strictly interchangeable and "'''z'''" must be the end argument)<br />
.func '''DnLim'''(x, y, z) if(x-y < z, y + z*exp((x-y-z)/z), x) ; this is '''DnLim's''' equivalent mathematical function<br />
* '''UpLim(DnLim(x, neg, z_dn), pos, z_up)'''&nbsp; Composite function, similar to '''Limit(x, neg, pos)''', but with up and down soft limit zones (note: arguments are ''not'' commutative)<br />
.func '''RndLim'''(x, neg, pos, z)= '''UpLim'''('''DnLim'''(x, neg, z), pos, z)<br />
* As with the hard limit functions, any or all arguments may be constants or functions of time, node voltages, branch currents, etc.: '''''UpLim'''(13, V(1,2)*I(Vs), Min(time**2, 5))''.<br />
* When their soft limits are greater than zero, these functions have continuous derivatives for superior dc convergence over '''Min()''', '''Max()''' and '''Limit()'''.<br />
* Outside their soft limit zones these functions are perfectly linear which may make them superior to '''tanh()''' as a smooth limit function in amplifier macro-modeling applications.<br />
<br />
Note that LTspice can execute behavioral sources in either 2G6, PSpice, or Berkeley SPICE syntax in addition to its own enlarged set of behavioral language.<br />
<br />
<br />
== G-Sources ==<br />
<br />
G-Sources have two additional parameters, Vto (threshold) and dir (direction)<br />
<br />
Here is the equivalent function:<br />
<br />
.func Gsq(x, gain, Vto, dir)=<br />
+ gain*if(dir==0, x, sgn(dir)*uramp(sgn(dir)*(x-Vto))**2)<br />
<br />
where x=V(nc+,nc-), the control voltage per the usual G syntax notation from Help:<br />
<br />
Gxxx n+ n- nc+ nc- <gain><br />
<br />
Here is a component where this feature is used, along with conventional G-Sources [http://ltwiki.org/files/LTC6268.zip LTC6268]<br><br />
<br />
<br />
== Standard Sources ==<br />
<br />
Add documentation for data file input and triggered sources and the Pspice compatible behavioral forms for E and G sources (at some point, perhaps ~2007, these were added to Help).<br />
<br />
<br />
=== Piecewise Linear Sources (PWL) ===<br />
<br />
LTspice supports many more forms of the PWL statement than given in the documentation.&nbsp; LTspice is largely compatible with other SPICE versions, providing similar or identical PWL features.<br />
<br />
The non-documented PWL statements can be added on a schematic by first adding a normal source from the Component library, and using the Advanced setting of the source to set the function of the source to one of the two available PWL functions.&nbsp; Once the source is placed on the schematic a right-click on the PWL statement allows to edit it.&nbsp; Once the PWL statement has been changed to a non-documented PWL statement it can also be edited by right-clicking on the component symbol.&nbsp; The right-click will then no longer bring up the special window for changing a source function, but the generic component attribute editor.&nbsp; The PWL statement goes into the value field.<br />
<br />
The principle form of the PLW statement is<br />
<br />
PWL [VALUE_SCALE_FACTOR=<vsf>]<br />
[TIME_SCALE_FACTOR=<tsf>]<br />
<data specification><br />
[TRIGGER <trigger expression>]<br />
<br />
The functions of the scale factors are obvious.&nbsp; When given, each value or time in the <data specification> is multiplied by them.&nbsp; The default for each factor is 1.<br />
<br />
The <data specification> is very flexible.&nbsp; Data can either be provided directly in the statement, or by referring to a file (these are documented features).&nbsp; Further, data can be specified so it is repeated a number of times, or forever (both undocumented).&nbsp; Also, data can be specified in a relative way (undocumented).&nbsp; And finally, specifications can be combined to a certain extent (undocumented).<br />
<br />
The simplest form of a <data specification> is a list of one or more data points.&nbsp; Each point is a pair of a time <t''x''> and a value <v''x''> values.&nbsp; A pair can, but need not be, grouped together by brackets.&nbsp; Using brackets simplifies the reading of longer lists.&nbsp; Also, commas can be used to separate and group data points. <br />
<br />
PWL <t1> <v1> <...> <tn> <vn><br />
PWL (<t1> <v1> <...> <tn> <vn>)<br />
PWL (<t1> <v1>) <...> (<tn> <vn>)<br />
PWL <t1>, <v1> <...> <tn>, <vn><br />
<br />
The usual suffixes, like ''m'' for milli or 'k' for kilo can be used both for times and values, e.g.:<br />
<br />
PWL (0m 1 1m 2 1m 3 4m 2)<br />
<br />
A value <v''x''> can also be an expression in curly brackets.&nbsp; However, while function names like ''sin()'' are recognized, the keyword ''time'' is not.&nbsp; This makes it difficult, probably impossible, to generate time-dependent data, like ''{sin(time)}'' or ''{rand(time)}'' (to generate random noise)<ref>Other SPICE versions have no such problem with ''time''</ref>.<br />
<br />
PWL (0 {sin(1)}) (1 {sin(2)})<br />
<br />
Time values <t''x''> can be specified as relative to the previous time value, by prefixing the value with a ''+'' sign, e.g. specifying values at 0, 1, 2, and 7 seconds:<br />
<br />
PWL (0 1 +1 2 +1 3 +5 2)<br />
<br />
Instead of placing the values directly into the PWL statement they can also be placed in a file, and the file referred in the PWL statement<br />
<br />
PWL file=<name of the file><br />
<br />
A list of data points or a file reference can be repeated a fixed amount of times <n>, or forever<br />
<br />
PWL REPEAT FOR <n> (<data list>|<file spec>) ENDREPEAT<br />
PWL REPEAT FOREVER (<data list>|<file spec>) ENDREPEAT<br />
<br />
E.g. to repeat a sequence of values for five times<br />
<br />
PWL REPEAT FOR 5 ( 0 1 1 1 2 2 3 1 ) ENDREPEAT<br />
PWL REPEAT FOR 5 ( file=<name of file> ) ENDREPEAT<br />
<br />
Data specifications can be combined, e.g:<br />
<br />
PWL (0 0 1 1 2 1 3 0) REPEAT FOR 5 (file=<name of file>) ENDREPEAT<br />
PWL REPEAT FOR 7 (file=pwl_data.txt) ENDREPEAT REPEAT FOR 6 (file=pwl_data2.txt) ENDREPEAT<br />
<br />
Repeat statements can be nested, e.g.:<br />
<br />
PWL REPEAT FOREVER (0 1 1 2) REPEAT FOR 3 (2 3 3 1) ENDREPEAT ENDREPEAT<br />
<br />
The <trigger expression> turns the source's output on as long as the expression is true.&nbsp; For example, if there is a node n001 in the circuit, the following will turn the output on as long as the node's voltage is greater 1.5V.&nbsp; A source that is turned off is 'stuck' at the first value given in its specification.&nbsp; In the following example the first pair is (0 0), i.e. a value of 0 at time 0.&nbsp; Therefore, when turned off, the source will be stuck at 0.<br />
<br />
PWL ( 0 0 1 1 2 1 3 0) TRIGGER V(n001)>1.5<br />
<br />
<br />
== Standard Devices ==<br />
<br />
=== Diodes: Sidewall Parameters ===<br />
<br />
LTspice (04/05/10) now supports the following diode sidewall parameters:<br />
* '''perim''': Sidewall perimeter (periphery) ; default value = 0m.<br />
* '''Isw''': Sidewall saturation current ; default value = 0A.<br />
* '''Ns''': Sidewall junction emission coefficient ; default value = N (I when Level=11)?<br />
* '''Rsw''': Sidewall series resistance ; default value = 0 ohm.<br />
* '''Cjsw''': Sidewall zero-bias capacitance ; default value = 0.9F * perim?<br />
* '''Vjsw''': Sidewall junction potential ; default value = Vj (1 when Level=11)?<br />
* '''Mjsw''': Sidewall grating coefficient ; default value = 0.33.<br />
* '''Fcs''': Sidewall forward-bias depletion capacitance coefficient ; default value = 0.5 (Fc when Level = 11)?<br />
<br />
<br />
----<br />
=== BJTs: Additional Gummel-Poon Parameters ===<br />
<br />
Bipolar CB avalanche breakdown is modeled in the LTspice Gummel-Poon device:<br />
* '''BVcbo''': C-B breakdown voltage.<br />
* '''nBVcbo''': breakdown emission coefficient ; default value = 1?<br />
* '''TBVcbo1''': linear temperature coefficient of breakdown voltage.<br />
* '''TBVcbo2''': quadratic temperature coefficient of breakdown voltage.<br />
<br />
Bipolar BE breakdown is also in the LTspice Gummel-Poon device:<br />
* '''BVbe''': B-E breakdown voltage.<br />
* '''IBVbe''': breakdown current at breakdown voltage.<br />
* '''nBVbe''': breakdown emission coefficient.<br />
<br />
<br />
----<br />
=== VDMOS: Breakdown, Sub-threshold Enhancements ===<br />
<br />
LTspice now contains a number of otherwise undocumented parameters to enhance its proprietary VDMOS model.&nbsp; These allow for body diode breakdown, subthreshold conduction with independent fits to the saturation and linear regions of the output characteristics and mobility reduction due to large Vgs.&nbsp; Most of these have recently become documented in the Help file (** denotes still undocumented).<br />
<br />
* '''BV''': breakdown voltage.<br />
* '''IBV''': breakdown current at breakdown voltage.<br />
* '''nBV''': breakdown emission coefficient.<br />
* '''Mtriode''': A conductance multiplier for the triode region.&nbsp; It allows independent matching of the saturation and linear regions of the MOSFET.<br />
* '''subthres''': The current (per volt Vds) at which the square-law drain current verses Vgs switches over to exponential.<br />
* '''theta''': ** mobility reduction due to large Vgs (limits drain current to direct gate voltage dependence instead of square law).<br />
<br />
<br />
<u>'''VDMOS Capacitance (Cgd Curve Fit Equation)'''</u><br />
<br />
LTspice Help outlines how LTspice generates the VDMOS nonlinear gate-drain capacitance, presenting the general form of the equations used, but it does not reveal the details of the parameters used by the fit equations.&nbsp; Help states that the capacitance expression fit uses two expressions, one for negative gate-drain voltages and another for positive.&nbsp; These expressions meet at zero voltage and it may be assumed that at this point, they must be identical in value and slope.&nbsp; This reduces the system to two equations in two unknowns, allowing a solution for the remaining fit parameters to be obtained.&nbsp; For the following equations, "'''s'''" is the slope at the zero point, "'''y'''" is the offset and "'''x'''" is the gate-drain voltage (''not'' the drain-source voltage).<br />
<br />
* Positive gate-drain voltage region: '''Cgd = s * tanh(a*x) + y''' (inversion region - switch is on)<br />
* Negative gate-drain voltage region: '''Cgd = s * atan(a*x) + y''' (Vds large - switch is off or turning off)<br />
<br />
Where '''s = (Cgdmax - Cgdmin)/(1 + Pi/2)''' and '''y = Cgdmax - s''' and "'''a'''", '''Cgdmax''' and '''Cgdmin''' are existing VDMOS model parameters.<br />
<br />
Note that in Help the unspecified parameters are given as '''A''', '''B''', '''C''', and '''D'''. These parameters are equivalent to '''s''' and '''y''' as follows: '''A = C = s''' and '''B = D = y'''.<br />
<br />
<br />
----<br />
=== Capacitors ===<br />
<br />
==== Capacitor Multipliers ====<br />
Capacitors allow an alternate form for the device multiplier m=<value> (number of units in parallel - see [[C_Capacitor|Capacitors in Help]]).&nbsp; In place of "m=<number>", "x<number>" may be used, i.e.: x2, x 2, x0.5, x3.14159.&nbsp; Note that whitespace may optionally separate the leading x and the following number.<br />
<br />
<br />
----<br />
=== Inductors ===<br />
<br />
==== Maximum Coupling Factor ====<br />
In LTspice, it is not really possible to set the winding coupling factor (K) exactly to unity.&nbsp; A little experimentation reveals this number to be 1-1n=.999999999.&nbsp; For 1-1n < k <=1, LTspice sets k=1-1n, never informing the user, not even in the error log where the netlist has been flattened and abstract expressions have been converted to numerics.<br />
<br />
If k is set to greater than one, LTspice issues a warning that k has been reduced to one (which actually is 1-1n).&nbsp; However this action is not reflected in the netlist nor in the error log's digested netlist.<br />
<br />
<br />
----<br />
=== Resistors ===<br />
<br />
==== Behavioral Resistors ====<br />
<br />
Create a behavioral resistor by right-mouse-button clicking on its Value field and edit its value to read: R=<expression>.&nbsp; This feature is undocumented, but is considered permissible to use.&nbsp; The expression syntax is the same as for a general behavioral source (see [[B_Arbitrary_behavioral_voltage_or_current_sources|B-sources in Help]]).<br />
<br />
The resistance must not go to zero and negative values can lead to convergence problems, so it is advisable to restrict its values to within a meaningful range as per the following Value example:<br />
<br />
R = limit(1,100k,V(1,2)*I(V1)) ; R stays between 1 ohm and 100k<br />
<br />
To plot an I-V curve, start by using the differential cursor to plot the voltage across the resistor.&nbsp; First click and hold down the left-mouse-button (red probe icon) on one side of the resistor and then drag and drop the black probe icon on the other side.&nbsp; Finish by dragging the mouse pointer over the x-axis (a ruler icon will appear) and the click the left mouse button to bring up the Horizontal Axis menu.&nbsp; Change the Quantity Plotted from "time" to "I(R1)" (assuming R1 is your behavioral resistor).<br />
<br />
<br />
==== Behavioral Resistor & Power Sink/Source ====<br />
<br />
Arbitrary Power Sink or Source where the function '''P=f()''' for power '''f''' is a constant or is an arbitrary function of any valid node voltage, branch current, etc. as with standard b-sources (note: power is sourced when '''f''' is negative).&nbsp; In order to avoid large currents at voltages near zero, the arbitrary power sink/sources foldbacks to resistive behavior when the absolute value of voltage across the device falls below a default value of 1 volt.&nbsp; The foldback point may be modified by specifying a '''VprXover''' parameter for the device, e.g. '''VprXover=50mV'''.<br />
<br />
Bxxx n1 n2 P=<expression> [VprXover=<value>] ; example: B1 1 0 P=500W VprXover=5V (R=50mΩ below 5V)<br />
<br />
<br />
==== Dual Value Resistors (for ac analysis) ====<br />
<br />
LTspice is like Hspice in that it allows resistors to have different dc and ac values.&nbsp; If ''ac=<value>'' is specified as a resistor parameter (either immediately after the normal dc value or in the '''Value2''' field), the operating point is calculated using the dc value of resistance, but the ac resistance value is used in the ac analysis.&nbsp; This may be useful when analyzing operational amplifiers, since the operating point computation can be performed on the unity gain configuration using a low value for the feedback resistance and the ac analysis may then be performed on a nearly open loop configuration by specifying a very large value for the ac resistance.<br />
<br />
<br />
==== Resistor (and Capacitor) Model Statements ====<br />
<br />
It's not in the .model section of the Help file, but LTspice seems to recognize standard model statements for resistors (RES) and capacitors (CAP), but not inductors (IND).<br />
<br />
As in many other SPICE simulators, "RES" and "CAP" are allowed as model keywords.&nbsp; For example, with the following line of spicetext<br />
<br />
.model X7R cap (T_measured=20 Tc1=0 Tc2=-19u)<br />
<br />
on a schematic, if a capacitor then has "X7R" entered into its "SpiceModel" field (via ctrl-right mouse click) its base value will be multiplied by the following temperature factor, TF<br />
<br />
TF = 1 + Tc1*(T-Tmeasured) + Tc2*(T-Tmeasured)**2<br />
where T = the global temperature TEMP or the local instance if specified.<br />
<br />
I haven't checked if higher order factors are accepted or if voltage or current factors can be used (they work for some other SPICEs).<br />
<br />
The Help file specifies the optional instance of [temp=<value>] syntax for resistors, capacitors and inductors, but only for capacitors does it define this as "instance temperature (for tempcos in a corresponding .model statement)," although nothing further about the model syntax is mentioned.<br />
<br />
The help file does not document the "noiseless" control parameter which applies to the resistance in many LTspice circuit elements with resistive elements (resistors, switches, RC lines, others).&nbsp; As its name suggests, this parameter blocks its applicable element's contribution to noise calculations.<br />
<br />
<br />
----<br />
=== Lossy Transmission Lines ===<br />
<br />
There are two undocumented lossy transmission line models implemented in LTspice.&nbsp; One is CPL model (P device), and the other is TXL model (Y device).<br />
<br />
The undocumented CPL is a K-Spice-like element, which in theory should be similar to the RLGC model, but without frequency dependent loss (neither skin effect and nor frequency dependent dielectric loss).&nbsp; It also has at least one bug causing an incorrect output voltage offset (a workaround is to only use signals with no dc offset). <br />
<br />
Below are example netlists from K-Spice, which have been translated as required (very little) into LTspice syntax.<br />
<pre><br />
****** test circuit for CPL transmission line simulation *******<br />
*<br />
M1 0 268 299 0 MN0P9 w=18u l=1u<br />
M2 299 267 748 0 MN0P9 w=18u l=1u<br />
M3 0 168 648 0 MN0P9 w=18u l=0u9<br />
M4 1 268 748 1 MP1P0 w=36u l=1u<br />
M5 1 267 748 1 MP1P0 w=36u l=1u<br />
M6 1 168 648 1 MP1P0 w=36u l=1u<br />
*<br />
CN648 648 0 25f4<br />
CN651 651 0 7f4<br />
CN748 748 0 25f4<br />
CN751 751 0 9f4<br />
CN299 299 0 5f4<br />
*<br />
P1 648 748 0 651 751 0 Pline<br />
*<br />
vdd 1 0 DC 5<br />
Vk 267 0 DC 5<br />
*<br />
*Vs 168 0 PWL (4 15n9 0 16n1 5 31n9 5 32n1 0)<br />
*Vs 268 0 PWL (4 15n9 0 16n1 5 31n9 5 32n1 0)<br />
*<br />
Vs1 168 0 Pulse (0 5 15n9 0n2 0n2 15n8 60n)<br />
Vs2 268 0 Pulse (0 5 15n9 0n2 0n2 15n8 60n)<br />
*<br />
.tran 0n2 47n9 0 1n<br />
.model Pline CPL<br />
+ R=0.2 0 0.2<br />
+ L=9n13 3n3 9n13<br />
+ G=0 0 0<br />
+ C=365f -90f 365f<br />
+ Length=24<br />
********************** MODEL SPECIFICATION **********************<br />
.model MN0P9 NMOS Vto=0.8 Kp=48u Gamma=0.30 Phi=0.55 Lambda=0<br />
+ Cgso=0 Cgdo=0 Cj=0 Cjsw=0 Tox=18u Ld=0<br />
.model MP1P0 PMOS Vto=-0.8 Kp=21u Gamma=0.45 Phi=0.61 Lambda=0<br />
+ Cgso=0 Cgdo=0 Cj=0 Cjsw=0 Tox=18u Ld=0<br />
.end<br />
<br />
******* test circuit for TXL transmission line simulation *******<br />
M5 0 168 2 0 MN0P9 w=18u l=0u9<br />
M6 1 168 2 1 MP1P0 w=36u l=1u<br />
Cn2 2 0 25f4<br />
Cn3 3 0 7f4<br />
Y1 2 0 3 0 Ymod<br />
Vdd 1 0 dc 5.0<br />
Vs 168 0 Pulse (0 5 15n9 0n2 0n2 15n8 32n)<br />
*Vs 168 0 PWL(15n9 0 16n1 5 31n9 5 32n1 0)<br />
.tran 0n2 47n 0 0n1<br />
.model MN0P9 NMOS Vto=0.8 Kp=48u Gamma=0.3 Phi=0.55 Lambda=0<br />
+ Cgso=0 Cgdo=0 Cj=0 Cjsw=0 Tox=18u Ld=0<br />
.model MP1P0 PMOS Vto=-0.8 Kp=21u Gamma=0.45 Phi=0.61 Lambda=0<br />
+ Cgso=0 Cgdo=0 Cj=0 Cjsw=0 Tox=18u Ld=0<br />
.model Ymod Txl R=12.45 L=9u G=0 C=0p47 Length=16<br />
.end<br />
</pre><br />
<br />
<br />
----<br />
=== Voltage Controlled Switches ===<br />
<br />
LTspice has a cleaner syntax for voltage controlled switches, but has no problem with any PSpice voltage controlled switch syntax.<br />
<br />
<br />
== Dot Commands ==<br />
=== .Ac (ac analysis) ===<br />
<br />
In an ac analysis, it seems that the maximum number of points that may calculated is limited to about 65k.&nbsp; If more are requested, LTspice will reduce the point count to this maximum, but without generating an error or warning.&nbsp; This limitation may become significant when attempting to simulate very high Q circuits over too broad a frequency range (e.g., crystal oscillators showing overtones).<br />
<br />
<br />
----<br />
=== .Options ===<br />
<br />
Note: ".opt" is accepted as shorthand notation for ".options" (options are added as text onto the schematic as a [[SPICE Directive]]).<br />
<br />
There are a whole lot of .option parameters and other control parameters (mostly legacy from SPICE 2 and Pspice) that should be documented (a few probably actually could be useful).&nbsp; Many of these are listed in the LTspice Yahoo group message [http://tech.groups.yahoo.com/group/LTspice/message/20174 #20174].<br />
<br />
<br />
==== .options List ====<br />
<br />
This flag parameter causes a dump of the flatened netlist (after expanding subcircuits) to appear in the '''SPICE Error Log''' file (sticky and causes the corresponding '''Generate Expanded Listing''' option check box in '''Operation''' tab of the [[Control Panel]] to become checked).<br />
<br />
.opt List ; selects "Generate Expanded Listing" in the Control Panel<br />
<br />
<br />
==== .options DampInductors=<''value''> ====<br />
<br />
This has the same effect as unchecking (value=0) or checking (value=1) the '''Rpar''' inductor option on the '''Hacks''' tab of the '''Control Panel''', overriding whatever is set there (the default value in LTspice is 1 or ''ON'', which is opposite the standard SPICE convention).&nbsp; The default value for the parallel damping resistance equals 1e12 times the inductance value (1T x L) and is only applied in the case of a transient analysis.<br />
<br />
.opt DampInductors=0 ; turn off LTspice's default parallel damping resistance<br />
<br />
<br />
==== .options Thev_Induc=<''value''> ====<br />
<br />
This has the same effect as unchecking (value=0) or checking (value=1) the '''Rser''' inductor option on the '''Hacks''' tab of the '''Control Panel''', overriding whatever is set there (the default value in LTspice is 0 or ''ON'', which is opposite the standard SPICE convention).&nbsp; The default value for the series damping resistance equals 1 milliohm and is applied to all analyses.<br />
<br />
.opt Thev_Induc=1 ; turn off LTspice's default 1 milliohm series damping resistance (R = 0)<br />
<br />
Notes:<br />
* Using the standard SPICE convention settings for these two inductor options causes the circuit matrix to be bigger, run slower and be more prone to convergence errors.<br />
* I have yet to discover how to alter the global default enabled values for Rpar and Rser (changing Gmin has no effect on the parallel damping resistance for inductors). <br />
<br />
<br />
==== .options Gfarad=<''value''> ====<br />
<br />
Added at LTspice version 4.14h (per public posting by Yahoo LTspice group moderator, Helmut Sennewald, 04/13/12).<br />
<br />
This option allows the user to set the global value for a capacitor's default parallel conductance factor (1/'''Rpar''' = Gpar = '''Gfarad'''*C).<br />
<br />
.opt Gfarad=1e-12 ; has no effect because this is the existing default conductance factor<br />
.opt Gfarad=0 ; sets the global conductance factor to zero (removes the hidden default parallel resistance for all capacitors)<br />
<br />
Notes:<br />
* As a convergence aid, capacitors in LTspice include a hidden default parallel resistance of '''Rpar''' = 1e12/C.&nbsp; Specifying any value for '''Equiv. Parallel Resistance''' ('''Rpar''') in a capacitor's '''Component Editor''' window will override this default.&nbsp; Specifying a value of zero ('''Rpar'''=0) removes the default resistance (sets the conductance to zero).<br />
* The arbitrary capacitor (specified via a behavioral charge equation - refer to the topic in '''Help''') has no parallel conductance and is not affected by '''Gfarad'''.<br />
<br />
<br />
==== .options Gfloat=<''value''> ====<br />
<br />
This option allows the user to set the global value for the shunt conductance from floating nodes to ground.<br />
<br />
.opt Gfloat=1e-12 ; has no effect because this is the existing default conductance factor (which is Gshunt)<br />
.opt Gfloat=0 ; sets the global conductance factor to zero (removes the hidden default ground shunt resistance for all floating nodes)<br />
<br />
Notes:<br />
* As a convergence aid, floating nodes in LTspice include a hidden default shunt resistance to ground.&nbsp; The default value is equal to the value of '''Gshunt''' (which also may be optionally set - refer to the topic in '''Help''').&nbsp; Specifying a value for '''Gfloat''' will override this default.&nbsp; Specifying a value of zero removes the default shunt resistance (sets the conductance to zero).<br />
* Floating nodes are typically created when only connected to capacitors and/or current sources.<br />
<br />
<br />
==== .options TopologyCheck=2 ====<br />
<br />
Listed in the ChangeLog 09/14/11: "Beta Optimisations regarding dangling nodes."<br />
<br />
Setting this parameter to 2 has the same effect as checking '''Enable beta circuit matrix optimizations''' on the '''Hacks''' tab of the '''Control Panel''', overriding whatever is set there.<br />
<br />
.opt TopologyCheck=2 ; (parameter numbers 0 and 1 are documented in Help)<br />
<br />
<br />
==== .options tSeed=<''value''> ====<br />
<br />
This option lets you seed the integrator with a specific guess for the initial .tran timestep<br />
<br />
.opt tSeed=100n<br />
<br />
<br />
----<br />
=== .NodeAlias <''aliasName''> <''netName''> ===<br />
<br />
Listed in the ChangeLog 10/06/10: "Allows to give a net an alternative name." <br />
<br />
Placing the Jumper symbol (''lib/sym/Misc/jumper'') is another, documented and probably more convenient way of giving the same net two names, however, in a hierarchical design, it only functions on a top level schematic.<br />
<br />
.nodealias output drain<br />
<br />
<br />
== Miscellaneous Hints and Tricks ==<br />
<br />
... should be added here or given its own section if warranted.<br />
<br />
Here's a hint to anyone wishing to keep up-to-date with the latest additions to '''LTspice''''s great features - always read the '''''changelog.txt''''' file (located in the '''LTspiceIV''' program folder) after every web update /sync release.<br />
* From the ChangeLog on 02/21/07: "Added a check box on the Tools=>Control Panel=>Hacks! pane to allow the '''MC generator''' to be reseeded by the real time clock."<br />
<br />
<br />
'''A-Devices''' See message #19378 from the LTspice Yahoo users group.<br />
<br />
<br />
----<br />
=== Circuit Element Area Multiplier ===<br />
Only the following LTspice elements accept the ''Area Multiplier'' parameter, '''m'''=<value>, where '''m''' is the value by which the element area will be multiplied:<br />
<br />
'''C''' (Capacitors), '''D''' (Diodes), '''J*''' (JFETs), '''L''' (Inductors), '''M''' (MOSFETs), '''Q*''' (Bipolar Transistors) '''R*''' (Resistors), '''Z''' (MESFETs and IGBTs).<br />
<br />
<nowiki> </nowiki>'''''* m'''=<value> is an undocumented or poorly documented feature of this element''<br />
<br />
----<br />
<br />
=== Alternate Syntax ===<br />
<br />
In many contexts, where possible, LTspice supports alternate syntaxes compatible with other simulators.<br />
* Single quotes generally may be used in place of curly braces.<br />
<br />
<br />
=== AKO Aliases (A Kind Of) ===<br />
<br />
''Suppose I wished to modify a single parameter of an existing model but don't want to copy the full model out as a duplicate and adjust it.&nbsp; I want to pick up all of the specified and default parameter values for the given model name (and if it specifies yet another, to pick up those, as well) and simply modify one parameter or two in a new model.''<br />
<br />
''A reason I may wish to do this is that I may, at some later time, decide to modify the underlying model and I'd like all of the dependent models to pick up the underlying changes, automatically.&nbsp; I just don't know if there is syntax for it.&nbsp; Do you know?''<br />
<br />
Yes.&nbsp; Try something like this:<br />
<br />
.model 2N2222mod ako: 2N2222 bf=5 ; same except lower beta<br />
<br />
<br />
----<br />
> It appears that parameters must ultimately resolve to numbers instead of text.<br />
<br />
You are correct in your supposition - parameters must be numbers.<br />
<br />
> Is there a way to pass text to a subcircuit to do what I want?<br />
<br />
Yes.&nbsp; Models can take numeric alias using the AKO ("A Kind Of") function.<br />
These numeric aliases will work with parameter passing:<br />
<br />
.model 1 ako:2N3904 ;the existing 2N3904 model now also known as "1"<br />
.model 2 ako:2N2222 ;the existing 2N2222 model now also known as "2"<br />
<br />
This topic has been discussed many times in this forum before, but it may be difficult to search for because the name of the AKO function doesn't really correspond to "Also Known As" (it stands for "A Kind Of").<br />
<br />
You can find many examples using AKO in the Group archive here:<br />
<br />
Files -> Tut -> Stepping to the max<br />
<br />
<br />
=== Stepping a Model ===<br />
<br />
Sometimes it might be of interest to try out several different types of some component in a circuit, instead of just stepping a single parameter of a component.&nbsp; This can be done by giving the models that should be tried number-only names.&nbsp; For example, using the above discussed AKO feature, NPN transistors can be named as follows:<br />
<br />
.model 3904 ako:2N3904<br />
.model 2222 ako:2N2222<br />
.model 547 ako:BC547<br />
<br />
It is also possible to define a model with a number-only name from scratch:<br />
<br />
.model 4 NPN<br />
<br />
The next step is to add a spice directive to define a parameter, ''STM'' in the example below, which is stepped through the model names.&nbsp; Since the ''.step'' command can only step numeric values it is vital that the models have been given number-only names, as shown above. <br />
<br />
.step param STM list 3904 2222 547 4<br />
<br />
The last step is then to use the parameter in place of a model ''Value''.&nbsp; To make sure the parameter is evaluated, it needs to be placed in brakes.&nbsp; For example, the above defined parameter ''STM'' would be given in the form of ''{STM}'' as the ''Value'' of an NPN transistor symbol.<br />
<br />
<br />
=== Schematic Editor ===<br />
<br />
====Key Combination====<br />
* '''Shift-Ctrl-Alt-R''': Permanently renumbers all reference designators within the schematic.<br />
* '''Shift-Ctrl-Alt-H''': Temporarily highlights all hidden text within the schematic.<br />
* Hold down '''Ctrl''' when placing wires to route at any angle.<br />
* Hold down '''Ctrl''' when drawing lines to draw off grid.<br />
* Hold down '''Ctrl''' or '''Shift''' for more movement with '''arrow keys'''.<br />
* Hold down '''Ctrl''' ''and'' '''Shift''' for ''most'' movement with '''arrow keys'''.<br />
* Text preceeded with an underscore ("_") character will be displayed as overbarred (for active LOW digital signals).<br />
* '''Cross Probing''': Clicking '''Alt-Left''' on a label in the plot pane highlights the corresponding node in the schematic (since end of October 2012 release).&nbsp; E.g. clicking '''Alt-Left''' on a label like ''V(n001)'' in the plot pane highlights the ''n001'' node.&nbsp; Clicking '''Alt-Left''' on a label like ''I(R1)'' highlights ''R1'' in the schematic.<br />
<br />
<br />
====Operating Point Data Labels (visible numeric dc bias values)====<br />
<br />
LTspice has the ability to display dc operating point voltages, currents and expressions (e.g., power, energy, efficiency, etc.) directly within the schematic.&nbsp; Normally, labels are placed upon wires (nodes) much like '''Net Labels'''. <br />
<br />
<br />
===== Preparation =====<br />
<br />
To be able to place/show operating point data labels right-click on an empty area of the schematic and select "'''View'''" from the drop down menu list. <br />
* Checking "'''Show .op Data Flags'''" shows all operating point numerical information on the schematic.<br />
Further, in the main menu<br />
* Checking "'''Mark Unconn. Pins'''" (main menu -> View) shows anchor boxes on the schematic when a label is moved.<br />
<br />
<br />
===== Creating a Label when doing a .op Simulation =====<br />
<br />
When doing a DC operating point simulation (.op) an operating point data label can be created as follows<br />
<br />
* Run the .op simulation<br />
* Left-Click on a net (a wire).&nbsp; This creates a new label that can be placed with the cursor.<br />
<br />
<br />
===== Creating a Label when doing another Simulations =====<br />
<br />
When doing other kinds of simulations than a DC operating point simulation (.op) operating point data labels can be created by right-clicking on an empty area of the schematic, then selecting '''View->Place .op Data Label''' on the drop down menu.&nbsp; The new label can be attached to a net with the cursor.<br />
<br />
<br />
===== Format and Layout =====<br />
<br />
Once placed, an operating point data label may be freely moved or copied and then edited to be completely unrelated to the original node.&nbsp; It is of course possible to decorate a label by using the normal drawing functions.&nbsp; For example painting a rectangle around it (main menu Edit->Draw->Rectangle) or by placing some text nearby (main menu Edit->Text).<br />
<br />
Operating point data labels default to the display of the voltage of the node to which they are attached (signified by the dollar sign character "$"), but this may be edited to be any valid expression, including currents, powers or even the voltage of a specific node.&nbsp; Right-clicking on a operating point data label brings up a popup window for selecting the data to display or enter an expression.<br />
<br />
With fractional values, all available non-zero digits will be displayed, often resulting in unwanted numerical clutter.&nbsp; The number of visible digits may be aesthetically limited by appropriately editing the expression to be displayed.&nbsp; Examples of rounding expressions used for formating:<br />
<br />
round($*1k)/1k ; display no more than 3 digits (typically automatically expressed in engineering format).<br />
round(I(R1)*1k)/1k ; same display format as above, but expression is of the current through R1.<br />
round(V(1,2)*1k)/1k ; same format, but expression is of the voltage difference between nodes 1 & 2.<br />
<br />
<br />
====Bussing of Connections and Components (BUS shorthand notation)====<br />
<br />
LTspice has an undocumented feature to draw busses (groups of nets) on the schematic.&nbsp; This feature is erratic.&nbsp; It is recommended to double check the resulting circuit by studying the netlist (main menu View->SPICE Netlist), because it is possible to attach wires to busses without exactly knowing which signal (net) from the bus the wire should actually represent.&nbsp; Busses are purely cosmetic on the schematic, they have no special SPICE function.&nbsp; All bussing notation is resolved (flattened to normal net notation) by the schematic editor prior to the creation of the SPICE netlist (the netlister does not understand bus notation, i.e. it it not possible to use a SPICE deck with bus notation in LTspice).<br />
<br />
An alternative to busses is to use individual net labels to connect distant nets.<br />
<br />
A net (wire) becomes a bus whenever any one of the following three conditions are met:<br />
<br />
# The wire is labeled with a netname with an array suffix.&nbsp; An array suffix consists of two numbers separated by a colon and enclosed in brackets.&nbsp; For example ''Data[0:7]'' means the bus consists of the eight nets ''Data[0]'', ''Data[1]'', up to ''Data[7]''. <br />
# The wire is connected to the wide end of a BUS tap (main menu Edit->Place BUS tap). <br />A net connected to the other end, the pointed end of a tap, is called a tap net, and is an individual net from the nets represented by the bus.&nbsp; Tap nets must be labeled with an individual array element suffix (a single number without colon enclosed in brackets).&nbsp; For example ''Data[3]'' would be the label of a tap net out of the ''Data[0:7]'' bus.<br />
# The net is connected to a bus pin of a component that has an array type name.<br />
<br />
Once a wire is becoming a bus it is automatically drawn with extra thick lines.<br />
<br />
A bus may be automatically connected (netlisted) to a corresponding array of components.&nbsp; An array of components is created by appending a bracketed array specifier to the instance name (reference designator) of a bus-connected single component.&nbsp; For example, instead of naming a transistor ''Q1'' naming it ''Q[1:4]'' would result in the single symbol representing four identical transistors.&nbsp; The base, collector and emitter pins of these component array all need to be connected to busses.&nbsp; For example to busses called ''Base[1:4]'', ''Collector[1:4]'', and ''Emitter[1:4]''.&nbsp; The resulting netlist is arbitrary if the pins of a component array are not properly connected to busses, but e.g. accidentally to single nets only.<br />
<br />
Note that recursive connections are possible around a single device or device group through the use of appropriate net labeling.&nbsp; For example', a single digital DFLOP device may be annotated to represent a 64 shift-register string by:<br />
<br />
# adding a 64 element array suffix to its instance name, e.g. ''A1'' would become ''A1[0:63]'',<br />
# placing on its D input a corresponding array net label, e.g., ''Data[0:63]'' (the particular name is unimportant), and<br />
# placing on its Q output an appropriately displaced array net label, e.g., ''Data[1:64]''.<br />
<br />
The result would be that the D inputs of A1[1] to A1[63] are connected to the Q outputs of A1[0] to A1[62].&nbsp; The D input of A1[0] (''Data[0]'') and Q output of A1[63] (''Data[64]'') need to be tapped off individually from the bus, and would represent the input and output of the resulting 64 bit shift register.<br />
<br />
; Example Notes<nowiki>:</nowiki><br />
: As usual for any flip-flop, a delay parameter must be specified in the Value field, e.g., ''td=10ns''.<br />
: The D input to the first gate may be individually accessed by its appropriate array index, e.g., ''Data[0]''<br />
<br />
<br />
====Title Block====<br />
<br />
The schematic editor can display a special symbol as a title block.&nbsp; This is a combined feature of the schematic editor and the symbol editor.&nbsp; The feature is purely cosmetic.&nbsp; It allows to decorate a schematic so it looks more like a traditional drawing (depending on what is actually in the title block symbol). <br />
<br />
The title block needs to be created in the form of a symbol (.asy file), and be of symbol type MASTER.&nbsp; However, the LTspice symbol editor does not allow the creation of a symbol with such a type, while editing such a symbol is possible.&nbsp; Therefore, it is initially necessary to created an empty MASTER symbol with a text editor.&nbsp; Once initially created it can be opened and edited in LTspice.<br />
<br />
To start it is enough to create a .asy file with the following two lines in a text editor<br />
<br />
Version 4<br />
SymbolType MASTER<br />
<br />
Once saved from the text editor the file can then be opened in LTspice and the drawing commands can be used to design the title block, e.g. a frame, and several text fields.&nbsp; Pins must not be added to a title block symbol.&nbsp; Once saved in a project's directory, the title block can be added to a schematic just like any other symbol. <br />
<br />
Since it is difficult to edit a schematic while a title block is visible (attempting to select a component results in the selection of the title block instead), the title block may be turned on and off via the following option.<br />
<br />
View->Control Panel->Drafting Options->Show Title Blocks<br />
<br />
Before printing a page with a title block it is advisable to adjust the zooming of the schematic in the schematic editor, so the schematic with the title block exactly fits the screen.&nbsp; This can be done either via the toolbar button "Zoom full extents" or the menu item View->Zoom to fit.&nbsp; This assumes every symbol has been drawn within the boundaries of the title block.<br />
<br />
Here is an example of a simple title block symbol [[File:Title-block.asy]].<br />
<br />
<br />
=== Symbol Editor ===<br />
<br />
====Placing the ''Linear Technology'' or ''Analog Devices'' logos[[File:Logos.gif|100x24px]] within a Symbol====<br />
<br />
The text '''''LT''''' or '''''ADI''''' (must be all uppercase) in a symbol (menu Draw->Text) is replaced with the corresponding company logo when the symbol is used on a schematic.<br />
<br />
====Cut & Paste Between Symbols====<br />
<br />
Unfortunately this has yet to be implemented.&nbsp; Two workarounds are possible, but they are both cumbersome.<br />
<br />
# Open the symbol you wish to copy, then immediately save it with a new name.&nbsp; Modifying first before saving is dangerous because this requires always remembering to change the name after a distracting editing process.&nbsp; However, if the original ''is'' inadvertently overwritten, as long as the file is not closed the original may be recovered by repeatedly pressing the Undo key and then resaving.<br />
# Use a text editor to open both symbol files and copy the ASCII drawing command sequences from one file to the other.&nbsp; The commands are not difficult to read for selective editing, but the entire sequence also may be copied over and then subsequently graphically cleaned up from within LTspice's symbol editor.<br />
<br />
<br />
=== Plotting ===<br />
<br />
==== Cross Probing Key Combination ====<br />
<br />
* Clicking '''Alt-Left''' on a label in the plot pane highlights the corresponding node in the schematic (since end of October 2012 release).&nbsp; E.g. clicking '''Alt-Left''' on a label like ''V(n001)'' in the plot pane highlights the ''n001'' node.&nbsp; Clicking '''Alt-Left''' on a label like''I(R1)'' highlights ''R1'' in the schematic.<br />
<br />
<br />
==== Eye Diagram ====<br />
<br />
LTspice can plot eye diagrams - a feature which is only semi-documented.&nbsp; The following two "Plot Settings" menu items related to eye diagrams<br />
<br />
[select a plot pane (.raw)]<br />
Plot Settings->Eye Diagram->Enable<br />
Plot Settings->Eye Diagram->Properties<br />
<br />
They are usually disabled.&nbsp; LTspice enables them when adding the insufficiently documented, baudrate-option <br />
<br />
.option baudrate=<rate><br />
<br />
to a schematic.&nbsp; Instead of <rate> the nominal symbol rate of the signal should be given.&nbsp; <rate> defines at what intervals the signal should be triggered.<br />
<br />
Once enabled the <br />
<br />
Plot Settings->Eye Diagram->Properties<br />
<br />
menu item allows to set two more eye diagram properties.&nbsp; An initial delay, which effectively specifies where the eye(s) should be plotted on the horizontal axis.&nbsp; And the number of eyes, which is equivalent how many trigger intervals should be displayed.<br />
<br />
The following schematics both contain a baudrate option, but it is commented out. <br />
<br />
examples/Education/PLL.asc<br />
examples/Education/PLL2.asc<br />
<br />
Uncommenting the option, running the simulation, enabling the eye diagram in the Plot Settings, and then probing the signal net (not the out net) gives a typical eye diagram.<br />
<br />
<br />
=== Probing Subcircuit Waveforms (signal naming conventions) ===<br />
<br />
To be able to display subcircuit waveforms, you must first ensure that the ''Save Subcircuit Node Voltages'' and the ''Save Subcircuit Device Currents'' options are enabled in the '''Save Defaults''' tab of the [[Control Panel]].&nbsp; Then, if your simulation was created as a hierarchical design using LTspice's '''Schematic Capture''' window, you may simply use the probe tool to select an active subcircuit schematic's nodes as required.&nbsp; But if the SPICE netlist was imported from an external source then the probe statement format is as follows:<br />
<br />
* a top level node:<br />
.probe v(node)<br />
<br />
* a subcircuit node:<br />
.probe v(subckt_name:node)<br />
.probe v(subckt_name:subsubckt_name:node)<br />
<br />
* a subcircuit MOSFET drain current:<br />
.probe id(subckt_name:mp1)<br />
<br />
<br />
=== Netlists ===<br />
<br />
A netlist line starting with "'''*!LTspice:''' " is now treated as a SPICE directive for LTspice (but a comment in other SPICE programs). - 09/05/06<br />
<br />
= References & Footnotes =<br />
<br />
<references/><br />
<br />
<br />
{{#widget:DISQUS<br />
|id=ltwiki<br />
|uniqid={{PAGENAME}}<br />
|url={{fullurl:{{PAGENAME}}}}<br />
}}</div>Analogspicemanhttp://ltwiki.org/index.php?title=Undocumented_LTspice&diff=2121Undocumented LTspice2019-11-24T04:52:26Z<p>Analogspiceman: /* Miscellaneous Hints and Tricks */ added list of LTspice elements that support the m=<value> area multiplier</p>
<hr />
<div>== Introduction ==<br />
'''Please submit your requests for additions or changes to ''Undocumented LTspice'' on the "discussion" page (second tab above).'''<br />
<br />
LTspice/SwitcherCAD III is a complete and fully functional SPICE program (electronic circuit simulator) that is available free of charge from the Linear Technology Corporation (LTC).&nbsp; Because of its superior performance, excellent community support and ease of file sharing, it is rapidly replacing all other SPICE programs, regardless of price, as the simulator of choice for hobbyists, students and professionals alike.<br />
<br />
The purpose of this topic is to explore and explain '''''some''''' of the many useful or quirky features that have never appeared in the standard documentation whether due to simple oversight, the feature being considered not important enough, not polished enough or functionally obsolete – or even due to the feature being considered proprietary to another brand of SPICE or to LTspice itself.&nbsp; LTC considers some of these undocumented features as fair game for open discussion in public forums such as the LTspice Yahoo users group, whereas for others, it considers any such open discussions as a violation of its License Agreement.<br />
<br />
"''Fair game''" is any feature that is or has ever been part of the normal distribution, i.e., appears or ever has appeared in the Help file, as plain text in any of the included sample or example files, in any program menu available during normal use of the program, or in any of the materials, presentation files or handouts from any LTspice seminar presentation.&nbsp; Such items are all considered as having been officially "''documented''" and are specifically allowed as discussion topics in public forums such as the LTspice Yahoo users group.&nbsp; However, be advised that any items that have been dropped from the documentation, even if still functional, should generally be considered obsolete and in risk of being purged from the program code at any time (fortunately, such items are quite rare).<br />
<br />
As to the classification of anything not covered above, you must make your own common sense judgment or ask the advice of the users group moderator or the program author via private email.&nbsp; Clearly any standard, generic SPICE feature that works in LTspice would be okay for general use and discussion regardless of its state of documentation in LTspice.&nbsp; A lot of the standard devices have undocumented parameters (e.g., tempcos) or syntax (e.g., Pspice specific compatibility) that would fall into this category.&nbsp; Just as clearly, any undocumented A-device that is specific to LTC’s encrypted, high performance SMPS IC models would likely be considered proprietary knowledge to be protected with due diligence from release to the public domain, lest LTC’s competitors gain the de facto permission to freely copy them in their own circuit simulator offerings (however, it is difficult to see how LTC could legitimately prevent private individuals from making use of such undocumented features in their own simulations or discussing them via private communications).&nbsp; For these reasons, this last category of undocumented features will not be directly discussed here.<br />
<br />
== Numerical Accuracy/Dynamic Range ==<br />
<br />
LTspice generally represents numbers using 64 bit double precision arithmetic with the following data structure:<br />
<br />
[[File:IEEE_754_Double_Floating_Point_Format.png|frameless|700px|<b>Sign: 1 bit, exponent: 11 bits, fraction: 52 bits.</b>]]<br />
<br />
For general component values LTspice will accept numbers that range in magnitude from as large as &plusmn;&thinsp;1.798 x 10<sup>+308</sup> down to as small as &plusmn;&thinsp;2.225 x 10<sup>&minus;308</sup>.&ensp; Values exceeding this range are interpreted as &plusmn; infinity or as zero.&nbsp; However, because of the 52 bit precision of the fractional part of the significand, the practical numerical dynamic range will be circuit dependent.&nbsp; A 53 bit binary significand gives LTspice about 16 significant figures for internal math computations.&nbsp; Thus, if impedances vary by more than 16 orders of magnitude, numerical difficulties may ensue, depending on the topology of the circuit (this is because matrix solving frequently involves differencing two very similar numbers &ndash; for example, the next larger number than one is 1.0000000000000002 &ndash; anything closer is not resolvable).&nbsp; LTspice's proprietary alternate solver extends this precision by about another 3 orders of magnitude at a cost of a modest speed penalty.<br />
<br />
<br />
== A-Devices ==<br />
<br />
A-devices are Linear Technology Corporation's proprietary special function/mixed mode circuit simulation elements.&nbsp; According to LTspice’s Help file, the behavior of a number of these is undocumented because they frequently change with each new set of models available for LTspice (such changes actually are quite rare and this reason is most likely offered as both as a credible reason for keeping them hidden and to discourage anyone from bothering to attempt to explore and/or use them).<br />
<br />
The Help file lists A-device syntax as:<br />
Annn n001 n002 n003 n004 n005 n006 n007 n008 <model> [instance parameters]<br />
Note that all A-devices have up to 8 possible active device connections, up to 5 inputs (terminals 1 through 5) usually 2 outputs (terminals 6 and 7), and with terminal 8 always as the device common.&nbsp; A-devices are always netlisted with the full eight connections.&nbsp; The netlister connects any unused inputs and outputs to terminal 8.&nbsp; The A-device compiler recognizes this condition as a flag that that terminal is not used and removes it from the simulation matrix.&nbsp; Current is sourced or sunk from the outputs (typically the Q or main output on terminal 7 and the Q&#773; or complementary output on terminal 6) and is returned through device common, terminal 8.<br />
<br />
A-devices are implemented this way to allow a single device type to act as any combination of a 1 to 5 input, 1 to 2 output device, but with no simulation speed penalty for unused terminals.&nbsp; Refer to the program Help file for more details about LTspice’s documented A-devices.<br />
<br />
Here is a listing of all known LTspice A-devices.<br />
<br />
<u>Documented directly in Help:</u><br />
* '''Buf''' (aka Buf1 Inv)<br />
* '''AND'''<br />
* '''OR'''<br />
* '''XOR''' – when more than two inputs are present, uses the correct definition of ''true if one and only one input is true'', rather than the more common <u>incorrect</u> definition of ''true if an odd number of inputs are true'' (which should be called an '''ODD/NODD''' gate rather than an '''XOR/XNOR''' gate).<br />
* '''Schmitt''' (aka SchmittBuf SchmittInv DifSchmitt DiffSchmittBuf DiffSchmittInv)<br />
* '''Dflop''' (CLR takes precedence over PRE, also a start up state may be set – see '''SRflop''')<br />
* '''Varistor'''<br />
* '''Modulator''' (aka Modulate Modulate2)<br />
<u>Not documented in Help but available via the schematic Component Selector:</u><br />
* '''SRflop''' – located in Digital<br />
* '''PhaseDet''' (aka PhiDet) – located in Digital<br />
* '''Counter''' – located in Digital and documented in the users group (has been officially approved for public use)<br />
* '''SampleHold''' (aka Sample) – located in Special Functions<br />
<u>Documented in sample schematics included with the program distribution:</u><br />
* '''PhaseDet''' (aka PhiDet) – located in examples/Educational/PLL2.asc<br />
* '''SampleHold''' (aka Sample) – located in examples/Educational/S&H.asc<br />
* '''OTA''' – used in UniversalOpamp plaintext subcircuits (in lib/sub), but users group posts (some long standing) containing information about additional aspects of this have been censored<br />
<u>Not documented anywhere by LTC:</u><br />
* '''XxxxxxXxxx''' – prior long standing users group posts about this digital toggle type device have now been censored<br />
* '''XxXxxXXX''' – DAC type device never discussed in the users group<br />
* '''XXXXX''' – DAC type device never discussed in the users group<br />
* '''XXXX''' – DAC type device never discussed in the users group<br />
* '''Xxx''' – amplifier type device never discussed in the users group<br />
<u>Not documented anywhere by LTC</u>, but the first two of these devices were extensively documented in the users group.&nbsp; All three devices were eliminated /protected in June 2006 (approximately at release 2.17u ) and all users group posts (some long standing) about these devices have been censored /deleted from the users group archive:<br />
* '''XXXxxxx''' – PWM current mode control comparator and latch<br />
* '''XxxXxx''' – used for making PWM IC External Oscillators<br />
* '''Xxxxx''' – used for making PWM IC oscillators<br />
<u>Obsolete devices that have been deleted from the LTspice executable:</u><br />
* '''JKflop'''<br />
* '''PGateDrive'''<br />
* '''invPGateDrive'''<br />
* '''invGateDrive'''<br />
The three DACs, XxXxxXXX, XxxXXX, XXXX, are specialized A-devices that probably are of little general interest (although their functions and pinouts could likely be easily guessed by examining the data sheets of the few specialized LTC ICs making use of them).<br />
<br />
The XXXX seems to be the only straightforward, generic DAC, but very spice-efficient DACs are quite easy to make using standard, approved devices.<br />
<br />
<br />
----<br />
=== SRflop ===<br />
The Set/Reset Flip-Flop symbol is located in the ''Digital'' symbol folder.<br />
* The '''R''' (reset) input takes precedence over the '''S''' (set) input.<br />
* The start up state of the flip-flop (initial condition) may be specified by adding an "'''ic='''" attribute.<br />
** An "'''ic'''" value > '''Ref''' interprets to a high, e.g., "'''ic=1'''" sets the '''Q''' output high and "'''ic=0'''" sets it low.&nbsp; (Note: the logic threshold '''Ref''' parameter defaults to 0.5 and its use is documented in '''Help'''.)<br />
<br />
<br />
----<br />
=== PhaseDet (aka PhiDet) ===<br />
The Phase Detector symbol is located in the ''Digital'' symbol folder.<br />
<br />
The Examples folder contains a schematic with some documentation: ''Examples/Educational/PLL2.asc''<br />
<br />
<br />
----<br />
=== SampleHold (aka Sample) ===<br />
<br />
The Sample & Hold symbol is located in the ''Special Functions'' symbol folder.<br />
<br />
An example schematic, ''S&H.asc'', is located in the ''Examples/Educational'' schematic folder.<br />
<br />
The behavioral a-device Sample and Hold has two modes of operation.&nbsp; The output may follow the input whenever the '''S/H''' input is true or the output may latch to the input when the '''CLK''' input goes true.&nbsp; Note that ''one and only one'' of these two inputs must be connected.<br />
<br />
Parameters unique to the Sample and Hold a-device are as follows:<br />
*'''Rout''' defaults to 1kΩ (instead of the standard a-device 1Ω).<br />
*'''Vhigh''' defaults to 10V and Vlow defaults to -10V (note: these are output voltage saturation levels).<br />
<br />
<br />
----<br />
=== OTA ===<br />
<br />
The OTA (Operational Transconductance Amplifier) is used in the various UniversalOpamp plaintext subcircuits (located in a standard LTspice program installation in ''lib/sub'').<br />
<br />
The default transfer function is a hyperbolic tangent (tanh), which closely approximates the transfer function of a bipolar transistor differential amplifier (this limit can be disabled by adding the flag parameter, '''Linear''').&nbsp; Two differential input pairs are available on pins 1 and 2 ( &minus; + ) and on pins 3 and 4 ( + &minus; ).&nbsp; The transconductance current source output appears on pin 7.&nbsp; As usual, pin 8, if connected, becomes the device's floating "gnd" reference.&nbsp; For reference, a dc "rail" voltage, which represents the maximum possible output (calculated from combining both voltage and current saturation limits), appears on pin 6.&nbsp; This voltage reflects the negative limit only and has an output impedance identical to that of the main output.<br />
<br />
<br />
'''<u>Parameters:</u>''' (* indicates an undocumented parameter)&nbsp; Note all OTA parameters were undocumented until November 2019.<br />
* '''Ref''' (default = 0V) is the input offset voltage<br />
* '''G''' (default = 1u-mho) is the raw input "gain" (transconductance), where Vdiff = ( '''Ref''' – V(1,2) ) * V(3,4)&nbsp; and Iraw = '''G''' * Vdiff<br />
* '''Iout''' (default = 10uA) is the output saturation current, which may be superseded by one or both of<br />
** '''Isrc''' (or '''Isource''', default = '''Iout''') is the output sourcing saturation current<br />
** '''Isink''' (a negative number, default = &minus;'''Iout''') is the output sinking saturation current<br />
*** '''Asym''' is a flag parameter that, if present, enables independent asymmetrical limits for '''Isrc/Isource''' and '''Isink'''<br />
*** '''Linear''' is a flag parameter that, if present, disables output limiting<br />
* *'''Ioffset''' (default = 0A) is the output offset current<br />
* *'''PowerUp''' (default = true) is a Boolean parameter that if < 0.5 disables all pin 7 output current<br />
* '''EAclk''' (default = none) is the reference designator of the gate indicating a clock period for steady state detection (net zero current out of the OTA integreated over this period is deemed steady state)<br />
* '''Ibuck''' (default = 0A) is the expression of current that is presumed to not be involved in slewing the voltage of the compensation capacitor<br />
* '''Rout''' (default = 1/Gmin) is the internal output resistance<br />
* '''Cout''' (default = 0F) is the capacitance in parallel with '''Rout'''<br />
* '''Vhigh''' (default = 2V) is the positive output "rail" voltage (set to 1e308 to disable limit)<br />
* '''Vlow''' (default = 0V) is the negative output "rail" voltage (set to &minus;1e308 to disable limit)<br />
* '''Rclamp''' (default = 1Ω) is the clamping resistance to the voltage rails<br />
* '''Epsilon''' (default = 0V) is the voltage range to gradually switch in '''Rclamp''' impedance<br />
* '''EN''' (default = 0V/√Hz) is the voltage noise density<br />
* '''ENk''' (default = 0Hz) is the voltage noise knee frequency<br />
* '''IN''' (default = 0A/√Hz) is the current noise density<br />
* '''INk''' (default = 0Hz) is the current noise knee frequency<br />
* '''INcm''' (default = 0A/√Hz) is the common mode current noise density<br />
* '''INcmk''' (default = 0Hz) is the common mode current noise knee frequency<br />
<br />
<br />
'''<u>Output Current Limit:</u>'''<br />
* With no flag parameter: Io = tanh ( Iraw / Isat ) * Isat + Idc + '''Ioffset'''&nbsp; (note that one limit's action/shape is affected by the opposing limit's magnitude)<br /> ''where'' Vdiff = ( '''Ref''' – V(1,2) ) * V(3,4) , Iraw = '''G''' * Vdiff , Isat = ( '''Isink''' – '''Isrc''' ) / 2&nbsp; and Idc = ( '''Isink''' + '''Isrc''' ) / 2 ; ('''Isink''' is a ''negative number'' )<br />
* With the '''Asym''' flag parameter: Io = if ( Vdiff , tanh ( Iraw / '''Isrc''' ) * '''Isrc''' , tanh ( Iraw / '''Isink''' ) * '''Isink''' ) + '''Ioffset''' <br /> ''note that'' the "if ( <polarity test>, <then action>, <else action> )" conditional statement completely separates the positive and negative limits<br />
* With the '''Linear''' flag parameter: Io = Iraw + '''Ioffset''' (output current does not saturate)<br />
* Note that in all cases the final value of Io is multiplied by buf&thinsp;( '''PowerUp''' )<br />
<br />
<br />
'''<u>Output Voltage Limit:</u>'''<br />
* Clamps through a resistance of '''Rclamp''' to "rails" of '''Vhigh''' and &minus;'''Vlow'''<br />
<br />
<br />
'''<u>Noise Voltage Density:</u>'''<br />
* Vnoise = ('''EN''' + '''IN''' * Rin_equivalent) * '''G''' * '''Rout'''<br />
<br />
<br />
----<br />
<br />
=== Counter (divide by n): ===<br />
<br />
The Counter symbol is located in the ''Digital'' symbol folder (added October 2013).<br />
<br />
This device divides the input pulse stream on the '''CLK''' input (terminal 1) by the parameter '''cycles''' (required) with the divided output pulse stream appearing on the '''Phi1''' main '''Q''' output (terminal 7) and the '''Phi2''' complementary '''Q&#773;''' output (terminal 6).&nbsp; Counting occurs at the rising edge of the pulse stream and duty cycle may be specified.&nbsp; A reset input is available on terminal 2, but this terminal is not present on the standard symbol.&nbsp; Initially and after a reset, the Counter starts high, then goes high again on every Nth edge after that, where N= round('''cycles''').&nbsp; Note that output behavior is inverted compared to a standard ripple counter.<br />
<br />
Parameters unique to the Counter a-device are as follows:<br />
*'''Cycles''' divides the rising edge input pulse stream by round(<exp>) where <exp> is the expression assigned to this mandatory parameter.<br />
*'''Duty''' specifies the output pulse width = round('''cycles'''*'''duty'''). Duty cycle defaults to 0.5 if '''duty''' is omitted.<br />
Most of the usual digital a-device parameters may also be optionally applied, e.g., '''Trise''', '''Vhigh''', '''Vlow''', '''Ref''', etc. with the exception of '''Td''', which is ignored (the Counter accepts no delay).<br />
<br />
The '''cycles''' expression accepts b-source syntax and thus may be a simple constant or may be a complex expression containing constants, parameters, functions, the keyword '''time''', node voltages and branch currents.&nbsp; The Counter output will go to zero whenever the value of '''cycles''' falls below 1.5.&nbsp; If the Counter is clocked when the value of '''cycles''' is below 1.5, the Counter is reset.<br />
<br />
To use this symbol a '''cycles''' parameter must be specified after placing the symbol on a schematic (right-click on the symbol to open the "Component Attribute Editor" window and, in the '''Value''' attribute field, enter a '''cycles''' parameter, e.g. "cycles=2" for a divide by two counter).<br />
<br />
A symbol including the reset input and test circuit is available in the online Yahoo LTspice users group: ''Files/Tut/Digital A-Devices''.&nbsp; Alternately, LTspice's standard S/R flip-flop symbol may be used to stand in for the Counter with reset by editing its '''SpiceModel''' attribute from "SRFLOP" to "Counter" after it has been placed on the schematic ('''S''' becomes the clock input, '''R''' becomes the reset input and '''Q''' and '''Q&#773;''' become the two outputs).<br />
<br />
<br />
== B-Sources ==<br />
<br />
While many b-source features were not documented until relatively recently (~2007), most are now at least touched upon in Help and the few that are not are covered in the [[B sources (complete reference)]] in this wiki.<br />
* '''Cpar'''&nbsp; In addition to the parameter '''Rpar''' (which is documented in Help), current source type behavioral sources (i.e., "I=" "R=" and "P=") now accept the '''Cpar''' parameter to specify a parallel capacitance.&nbsp; Current derived b-sources driving one ohm in parallel with a small capacitance (e.g., Rpar=1 Cpar=1n) are much more convergence friendly than stiff voltage sources and should be used whenever possible.&nbsp; Nortonizing voltage sources to current sources in parallel with one ohm requires no conversion calculation, but the Nortonized parallel impedance may be set as low as desired if the current source gain is up scaled to compensate.<br />
* '''Bn P=f(...)'''&nbsp; Arbitrary Power Sink/source where '''f''' is a constant or is an arbitrary function of any valid node voltage, branch current, etc. as with standard b-sources (note: power is sourced when '''f''' is negative).&nbsp; In order to avoid large currents at voltages near zero, the arbitrary power sink/sources foldbacks to resistive behavior when the absolute value of voltage across the device falls below a default value of 1 volt.&nbsp; The foldback point may be modified by specifying a '''VprXover''' parameter for the device, e.g. '''VprXover=50mV'''. <br />
* '''Bn R=f(...)'''&nbsp; Arbitrary Resistor where '''f''' is an arbitrary function of '''x''' (which has the special meaning of the voltage across '''R''' in this context) and/or any valid node voltage, branch current, etc. as with standard b-sources.<br />
* '''[[units] Freq=<valuelist> [delay=<value>]]'''&nbsp; (Pspice compatible format)<br /> The transfer function of the Freq circuit element is specified by an ordered list of points of freq(Hz), mag(dB) and phase(deg) as follows: <(f1,m1,p1)[(f2,m2,p2)...]> where f1<f2<f3, etc.&nbsp; The following units specifiers may optionally precede the Freq keyword: “rad”=radians, “mag”=non dB, (“dB” and “deg” return the defaults), “r_i”=real and imaginary in place of magnitude and phase.&nbsp; If a delay value is called out, the phases of the table values are modified to reflect the delay (delay is automatically adjusted to maintain causality in any case). <br />
* '''NoJacob'''&nbsp; The optional '''NoJacob''' flag parameter unburdens a device from carrying the mathematical overhead of a Jacobian.&nbsp; For linear or certain well behaved b-source expressions, this small reduction in computational burden can reduce run times slightly.&nbsp; Use with extreme caution, as this greatly increases the risk of creating convergence problems or other errors if misapplied. <br />
* '''~'''&nbsp; Boolean operator: convert succeeding expression to Boolean then invert<br />
* '''=='''&nbsp; Boolean operator: true if preceding expression is equal to succeeding expression, otherwise false<br />
* '''boltz'''&nbsp; Boltzmann constant = 1.38062 e-23<br />
* '''planck'''&nbsp; Planck's constant = 6.62620 e-34<br />
* '''echarge'''&nbsp; Charge of an electron = 1.6021765 e-19<br />
* '''kelvin'''&nbsp; Absolute Zero in degrees C = -273.150<br />
* '''Gmin'''&nbsp; Minimum conductance = 1e-12 (or as set in the '''Control Panel''' or via an .option statement)<br />
** '''Gmin''' is added to every PN junction to aid convergence and is the default off-conductance for current or voltage controlled switches and LTspice's idealized diode model.<br />
* '''square(x)'''&nbsp; Function = x**2<br />
* '''tbl'''&nbsp; Alternate function name, aka '''table''' (look-up table)<br />
* '''stp(x)'''&nbsp; Alternate function name, aka '''u(x)''' (unit step)<br />
* '''fra(x)'''&nbsp; Function, very similar to '''white(x)''', but = 0 if not SMPS in steady state condition<br />
* '''UpLim(x, pos, z)'''&nbsp; Function, similar to '''Min(x, y)''', but "'''z'''" defines a zone with quadratic soft limiting (note: "'''x'''" and "'''pos'''" are ''not'' strictly interchangeable and "'''z'''" must be the end argument)<br />
.func '''UpLim'''(x, y, z) if(y-x < z, y - z*exp((y-x-z)/z), x) ; this is '''UpLim's''' equivalent mathematical function<br />
* '''DnLim(x, neg, z)'''&nbsp; Function, similar to '''Max(x, y)''', but "'''z'''" defines a zone with quadratic soft limiting (note: "'''x'''" and "'''neg'''" are ''not'' strictly interchangeable and "'''z'''" must be the end argument)<br />
.func '''DnLim'''(x, y, z) if(x-y < z, y + z*exp((x-y-z)/z), x) ; this is '''DnLim's''' equivalent mathematical function<br />
* '''UpLim(DnLim(x, neg, z_dn), pos, z_up)'''&nbsp; Composite function, similar to '''Limit(x, neg, pos)''', but with up and down soft limit zones (note: arguments are ''not'' commutative)<br />
.func '''RndLim'''(x, neg, pos, z)= '''UpLim'''('''DnLim'''(x, neg, z), pos, z)<br />
* As with the hard limit functions, any or all arguments may be constants or functions of time, node voltages, branch currents, etc.: '''''UpLim'''(13, V(1,2)*I(Vs), Min(time**2, 5))''.<br />
* When their soft limits are greater than zero, these functions have continuous derivatives for superior dc convergence over '''Min()''', '''Max()''' and '''Limit()'''.<br />
* Outside their soft limit zones these functions are perfectly linear which may make them superior to '''tanh()''' as a smooth limit function in amplifier macro-modeling applications.<br />
<br />
Note that LTspice can execute behavioral sources in either 2G6, PSpice, or Berkeley SPICE syntax in addition to its own enlarged set of behavioral language.<br />
<br />
<br />
== G-Sources ==<br />
<br />
G-Sources have two additional parameters, Vto (threshold) and dir (direction)<br />
<br />
Here is the equivalent function:<br />
<br />
.func Gsq(x, gain, Vto, dir)=<br />
+ gain*if(dir==0, x, sgn(dir)*uramp(sgn(dir)*(x-Vto))**2)<br />
<br />
where x=V(nc+,nc-), the control voltage per the usual G syntax notation from Help:<br />
<br />
Gxxx n+ n- nc+ nc- <gain><br />
<br />
Here is a component where this feature is used, along with conventional G-Sources [http://ltwiki.org/files/LTC6268.zip LTC6268]<br><br />
<br />
<br />
== Standard Sources ==<br />
<br />
Add documentation for data file input and triggered sources and the Pspice compatible behavioral forms for E and G sources (at some point, perhaps ~2007, these were added to Help).<br />
<br />
<br />
=== Piecewise Linear Sources (PWL) ===<br />
<br />
LTspice supports many more forms of the PWL statement than given in the documentation.&nbsp; LTspice is largely compatible with other SPICE versions, providing similar or identical PWL features.<br />
<br />
The non-documented PWL statements can be added on a schematic by first adding a normal source from the Component library, and using the Advanced setting of the source to set the function of the source to one of the two available PWL functions.&nbsp; Once the source is placed on the schematic a right-click on the PWL statement allows to edit it.&nbsp; Once the PWL statement has been changed to a non-documented PWL statement it can also be edited by right-clicking on the component symbol.&nbsp; The right-click will then no longer bring up the special window for changing a source function, but the generic component attribute editor.&nbsp; The PWL statement goes into the value field.<br />
<br />
The principle form of the PLW statement is<br />
<br />
PWL [VALUE_SCALE_FACTOR=<vsf>]<br />
[TIME_SCALE_FACTOR=<tsf>]<br />
<data specification><br />
[TRIGGER <trigger expression>]<br />
<br />
The functions of the scale factors are obvious.&nbsp; When given, each value or time in the <data specification> is multiplied by them.&nbsp; The default for each factor is 1.<br />
<br />
The <data specification> is very flexible.&nbsp; Data can either be provided directly in the statement, or by referring to a file (these are documented features).&nbsp; Further, data can be specified so it is repeated a number of times, or forever (both undocumented).&nbsp; Also, data can be specified in a relative way (undocumented).&nbsp; And finally, specifications can be combined to a certain extent (undocumented).<br />
<br />
The simplest form of a <data specification> is a list of one or more data points.&nbsp; Each point is a pair of a time <t''x''> and a value <v''x''> values.&nbsp; A pair can, but need not be, grouped together by brackets.&nbsp; Using brackets simplifies the reading of longer lists.&nbsp; Also, commas can be used to separate and group data points. <br />
<br />
PWL <t1> <v1> <...> <tn> <vn><br />
PWL (<t1> <v1> <...> <tn> <vn>)<br />
PWL (<t1> <v1>) <...> (<tn> <vn>)<br />
PWL <t1>, <v1> <...> <tn>, <vn><br />
<br />
The usual suffixes, like ''m'' for milli or 'k' for kilo can be used both for times and values, e.g.:<br />
<br />
PWL (0m 1 1m 2 1m 3 4m 2)<br />
<br />
A value <v''x''> can also be an expression in curly brackets.&nbsp; However, while function names like ''sin()'' are recognized, the keyword ''time'' is not.&nbsp; This makes it difficult, probably impossible, to generate time-dependent data, like ''{sin(time)}'' or ''{rand(time)}'' (to generate random noise)<ref>Other SPICE versions have no such problem with ''time''</ref>.<br />
<br />
PWL (0 {sin(1)}) (1 {sin(2)})<br />
<br />
Time values <t''x''> can be specified as relative to the previous time value, by prefixing the value with a ''+'' sign, e.g. specifying values at 0, 1, 2, and 7 seconds:<br />
<br />
PWL (0 1 +1 2 +1 3 +5 2)<br />
<br />
Instead of placing the values directly into the PWL statement they can also be placed in a file, and the file referred in the PWL statement<br />
<br />
PWL file=<name of the file><br />
<br />
A list of data points or a file reference can be repeated a fixed amount of times <n>, or forever<br />
<br />
PWL REPEAT FOR <n> (<data list>|<file spec>) ENDREPEAT<br />
PWL REPEAT FOREVER (<data list>|<file spec>) ENDREPEAT<br />
<br />
E.g. to repeat a sequence of values for five times<br />
<br />
PWL REPEAT FOR 5 ( 0 1 1 1 2 2 3 1 ) ENDREPEAT<br />
PWL REPEAT FOR 5 ( file=<name of file> ) ENDREPEAT<br />
<br />
Data specifications can be combined, e.g:<br />
<br />
PWL (0 0 1 1 2 1 3 0) REPEAT FOR 5 (file=<name of file>) ENDREPEAT<br />
PWL REPEAT FOR 7 (file=pwl_data.txt) ENDREPEAT REPEAT FOR 6 (file=pwl_data2.txt) ENDREPEAT<br />
<br />
Repeat statements can be nested, e.g.:<br />
<br />
PWL REPEAT FOREVER (0 1 1 2) REPEAT FOR 3 (2 3 3 1) ENDREPEAT ENDREPEAT<br />
<br />
The <trigger expression> turns the source's output on as long as the expression is true.&nbsp; For example, if there is a node n001 in the circuit, the following will turn the output on as long as the node's voltage is greater 1.5V.&nbsp; A source that is turned off is 'stuck' at the first value given in its specification.&nbsp; In the following example the first pair is (0 0), i.e. a value of 0 at time 0.&nbsp; Therefore, when turned off, the source will be stuck at 0.<br />
<br />
PWL ( 0 0 1 1 2 1 3 0) TRIGGER V(n001)>1.5<br />
<br />
<br />
== Standard Devices ==<br />
<br />
=== Diodes: Sidewall Parameters ===<br />
<br />
LTspice (04/05/10) now supports the following diode sidewall parameters:<br />
* '''perim''': Sidewall perimeter (periphery) ; default value = 0m.<br />
* '''Isw''': Sidewall saturation current ; default value = 0A.<br />
* '''Ns''': Sidewall junction emission coefficient ; default value = N (I when Level=11)?<br />
* '''Rsw''': Sidewall series resistance ; default value = 0 ohm.<br />
* '''Cjsw''': Sidewall zero-bias capacitance ; default value = 0.9F * perim?<br />
* '''Vjsw''': Sidewall junction potential ; default value = Vj (1 when Level=11)?<br />
* '''Mjsw''': Sidewall grating coefficient ; default value = 0.33.<br />
* '''Fcs''': Sidewall forward-bias depletion capacitance coefficient ; default value = 0.5 (Fc when Level = 11)?<br />
<br />
<br />
----<br />
=== BJTs: Additional Gummel-Poon Parameters ===<br />
<br />
Bipolar CB avalanche breakdown is modeled in the LTspice Gummel-Poon device:<br />
* '''BVcbo''': C-B breakdown voltage.<br />
* '''nBVcbo''': breakdown emission coefficient ; default value = 1?<br />
* '''TBVcbo1''': linear temperature coefficient of breakdown voltage.<br />
* '''TBVcbo2''': quadratic temperature coefficient of breakdown voltage.<br />
<br />
Bipolar BE breakdown is also in the LTspice Gummel-Poon device:<br />
* '''BVbe''': B-E breakdown voltage.<br />
* '''IBVbe''': breakdown current at breakdown voltage.<br />
* '''nBVbe''': breakdown emission coefficient.<br />
<br />
<br />
----<br />
=== VDMOS: Breakdown, Sub-threshold Enhancements ===<br />
<br />
LTspice now contains a number of otherwise undocumented parameters to enhance its proprietary VDMOS model.&nbsp; These allow for body diode breakdown, subthreshold conduction with independent fits to the saturation and linear regions of the output characteristics and mobility reduction due to large Vgs.&nbsp; Most of these have recently become documented in the Help file (** denotes still undocumented).<br />
<br />
* '''BV''': breakdown voltage.<br />
* '''IBV''': breakdown current at breakdown voltage.<br />
* '''nBV''': breakdown emission coefficient.<br />
* '''Mtriode''': A conductance multiplier for the triode region.&nbsp; It allows independent matching of the saturation and linear regions of the MOSFET.<br />
* '''subthres''': The current (per volt Vds) at which the square-law drain current verses Vgs switches over to exponential.<br />
* '''theta''': ** mobility reduction due to large Vgs (limits drain current to direct gate voltage dependence instead of square law).<br />
<br />
<br />
<u>'''VDMOS Capacitance (Cgd Curve Fit Equation)'''</u><br />
<br />
LTspice Help outlines how LTspice generates the VDMOS nonlinear gate-drain capacitance, presenting the general form of the equations used, but it does not reveal the details of the parameters used by the fit equations.&nbsp; Help states that the capacitance expression fit uses two expressions, one for negative gate-drain voltages and another for positive.&nbsp; These expressions meet at zero voltage and it may be assumed that at this point, they must be identical in value and slope.&nbsp; This reduces the system to two equations in two unknowns, allowing a solution for the remaining fit parameters to be obtained.&nbsp; For the following equations, "'''s'''" is the slope at the zero point, "'''y'''" is the offset and "'''x'''" is the gate-drain voltage (''not'' the drain-source voltage).<br />
<br />
* Positive gate-drain voltage region: '''Cgd = s * tanh(a*x) + y''' (inversion region - switch is on)<br />
* Negative gate-drain voltage region: '''Cgd = s * atan(a*x) + y''' (Vds large - switch is off or turning off)<br />
<br />
Where '''s = (Cgdmax - Cgdmin)/(1 + Pi/2)''' and '''y = Cgdmax - s''' and "'''a'''", '''Cgdmax''' and '''Cgdmin''' are existing VDMOS model parameters.<br />
<br />
Note that in Help the unspecified parameters are given as '''A''', '''B''', '''C''', and '''D'''. These parameters are equivalent to '''s''' and '''y''' as follows: '''A = C = s''' and '''B = D = y'''.<br />
<br />
<br />
----<br />
=== Capacitors ===<br />
<br />
==== Capacitor Multipliers ====<br />
Capacitors allow an alternate form for the device multiplier m=<value> (number of units in parallel - see [[C_Capacitor|Capacitors in Help]]).&nbsp; In place of "m=<number>", "x<number>" may be used, i.e.: x2, x 2, x0.5, x3.14159.&nbsp; Note that whitespace may optionally separate the leading x and the following number.<br />
<br />
<br />
----<br />
=== Inductors ===<br />
<br />
==== Maximum Coupling Factor ====<br />
In LTspice, it is not really possible to set the winding coupling factor (K) exactly to unity.&nbsp; A little experimentation reveals this number to be 1-1n=.999999999.&nbsp; For 1-1n < k <=1, LTspice sets k=1-1n, never informing the user, not even in the error log where the netlist has been flattened and abstract expressions have been converted to numerics.<br />
<br />
If k is set to greater than one, LTspice issues a warning that k has been reduced to one (which actually is 1-1n).&nbsp; However this action is not reflected in the netlist nor in the error log's digested netlist.<br />
<br />
<br />
----<br />
=== Resistors ===<br />
<br />
==== Behavioral Resistors ====<br />
<br />
Create a behavioral resistor by right-mouse-button clicking on its Value field and edit its value to read: R=<expression>.&nbsp; This feature is undocumented, but is considered permissible to use.&nbsp; The expression syntax is the same as for a general behavioral source (see [[B_Arbitrary_behavioral_voltage_or_current_sources|B-sources in Help]]).<br />
<br />
The resistance must not go to zero and negative values can lead to convergence problems, so it is advisable to restrict its values to within a meaningful range as per the following Value example:<br />
<br />
R = limit(1,100k,V(1,2)*I(V1)) ; R stays between 1 ohm and 100k<br />
<br />
To plot an I-V curve, start by using the differential cursor to plot the voltage across the resistor.&nbsp; First click and hold down the left-mouse-button (red probe icon) on one side of the resistor and then drag and drop the black probe icon on the other side.&nbsp; Finish by dragging the mouse pointer over the x-axis (a ruler icon will appear) and the click the left mouse button to bring up the Horizontal Axis menu.&nbsp; Change the Quantity Plotted from "time" to "I(R1)" (assuming R1 is your behavioral resistor).<br />
<br />
<br />
==== Behavioral Resistor & Power Sink/Source ====<br />
<br />
Arbitrary Power Sink or Source where the function '''P=f()''' for power '''f''' is a constant or is an arbitrary function of any valid node voltage, branch current, etc. as with standard b-sources (note: power is sourced when '''f''' is negative).&nbsp; In order to avoid large currents at voltages near zero, the arbitrary power sink/sources foldbacks to resistive behavior when the absolute value of voltage across the device falls below a default value of 1 volt.&nbsp; The foldback point may be modified by specifying a '''VprXover''' parameter for the device, e.g. '''VprXover=50mV'''.<br />
<br />
Bxxx n1 n2 P=<expression> [VprXover=<value>] ; example: B1 1 0 P=500W VprXover=5V (R=50mΩ below 5V)<br />
<br />
<br />
==== Dual Value Resistors (for ac analysis) ====<br />
<br />
LTspice is like Hspice in that it allows resistors to have different dc and ac values.&nbsp; If ''ac=<value>'' is specified as a resistor parameter (either immediately after the normal dc value or in the '''Value2''' field), the operating point is calculated using the dc value of resistance, but the ac resistance value is used in the ac analysis.&nbsp; This may be useful when analyzing operational amplifiers, since the operating point computation can be performed on the unity gain configuration using a low value for the feedback resistance and the ac analysis may then be performed on a nearly open loop configuration by specifying a very large value for the ac resistance.<br />
<br />
<br />
==== Resistor (and Capacitor) Model Statements ====<br />
<br />
It's not in the .model section of the Help file, but LTspice seems to recognize standard model statements for resistors (RES) and capacitors (CAP), but not inductors (IND).<br />
<br />
As in many other SPICE simulators, "RES" and "CAP" are allowed as model keywords.&nbsp; For example, with the following line of spicetext<br />
<br />
.model X7R cap (T_measured=20 Tc1=0 Tc2=-19u)<br />
<br />
on a schematic, if a capacitor then has "X7R" entered into its "SpiceModel" field (via ctrl-right mouse click) its base value will be multiplied by the following temperature factor, TF<br />
<br />
TF = 1 + Tc1*(T-Tmeasured) + Tc2*(T-Tmeasured)**2<br />
where T = the global temperature TEMP or the local instance if specified.<br />
<br />
I haven't checked if higher order factors are accepted or if voltage or current factors can be used (they work for some other SPICEs).<br />
<br />
The Help file specifies the optional instance of [temp=<value>] syntax for resistors, capacitors and inductors, but only for capacitors does it define this as "instance temperature (for tempcos in a corresponding .model statement)," although nothing further about the model syntax is mentioned.<br />
<br />
The help file does not document the "noiseless" control parameter which applies to the resistance in many LTspice circuit elements with resistive elements (resistors, switches, RC lines, others).&nbsp; As its name suggests, this parameter blocks its applicable element's contribution to noise calculations.<br />
<br />
<br />
----<br />
=== Lossy Transmission Lines ===<br />
<br />
There are two undocumented lossy transmission line models implemented in LTspice.&nbsp; One is CPL model (P device), and the other is TXL model (Y device).<br />
<br />
The undocumented CPL is a K-Spice-like element, which in theory should be similar to the RLGC model, but without frequency dependent loss (neither skin effect and nor frequency dependent dielectric loss).&nbsp; It also has at least one bug causing an incorrect output voltage offset (a workaround is to only use signals with no dc offset). <br />
<br />
Below are example netlists from K-Spice, which have been translated as required (very little) into LTspice syntax.<br />
<pre><br />
****** test circuit for CPL transmission line simulation *******<br />
*<br />
M1 0 268 299 0 MN0P9 w=18u l=1u<br />
M2 299 267 748 0 MN0P9 w=18u l=1u<br />
M3 0 168 648 0 MN0P9 w=18u l=0u9<br />
M4 1 268 748 1 MP1P0 w=36u l=1u<br />
M5 1 267 748 1 MP1P0 w=36u l=1u<br />
M6 1 168 648 1 MP1P0 w=36u l=1u<br />
*<br />
CN648 648 0 25f4<br />
CN651 651 0 7f4<br />
CN748 748 0 25f4<br />
CN751 751 0 9f4<br />
CN299 299 0 5f4<br />
*<br />
P1 648 748 0 651 751 0 Pline<br />
*<br />
vdd 1 0 DC 5<br />
Vk 267 0 DC 5<br />
*<br />
*Vs 168 0 PWL (4 15n9 0 16n1 5 31n9 5 32n1 0)<br />
*Vs 268 0 PWL (4 15n9 0 16n1 5 31n9 5 32n1 0)<br />
*<br />
Vs1 168 0 Pulse (0 5 15n9 0n2 0n2 15n8 60n)<br />
Vs2 268 0 Pulse (0 5 15n9 0n2 0n2 15n8 60n)<br />
*<br />
.tran 0n2 47n9 0 1n<br />
.model Pline CPL<br />
+ R=0.2 0 0.2<br />
+ L=9n13 3n3 9n13<br />
+ G=0 0 0<br />
+ C=365f -90f 365f<br />
+ Length=24<br />
********************** MODEL SPECIFICATION **********************<br />
.model MN0P9 NMOS Vto=0.8 Kp=48u Gamma=0.30 Phi=0.55 Lambda=0<br />
+ Cgso=0 Cgdo=0 Cj=0 Cjsw=0 Tox=18u Ld=0<br />
.model MP1P0 PMOS Vto=-0.8 Kp=21u Gamma=0.45 Phi=0.61 Lambda=0<br />
+ Cgso=0 Cgdo=0 Cj=0 Cjsw=0 Tox=18u Ld=0<br />
.end<br />
<br />
******* test circuit for TXL transmission line simulation *******<br />
M5 0 168 2 0 MN0P9 w=18u l=0u9<br />
M6 1 168 2 1 MP1P0 w=36u l=1u<br />
Cn2 2 0 25f4<br />
Cn3 3 0 7f4<br />
Y1 2 0 3 0 Ymod<br />
Vdd 1 0 dc 5.0<br />
Vs 168 0 Pulse (0 5 15n9 0n2 0n2 15n8 32n)<br />
*Vs 168 0 PWL(15n9 0 16n1 5 31n9 5 32n1 0)<br />
.tran 0n2 47n 0 0n1<br />
.model MN0P9 NMOS Vto=0.8 Kp=48u Gamma=0.3 Phi=0.55 Lambda=0<br />
+ Cgso=0 Cgdo=0 Cj=0 Cjsw=0 Tox=18u Ld=0<br />
.model MP1P0 PMOS Vto=-0.8 Kp=21u Gamma=0.45 Phi=0.61 Lambda=0<br />
+ Cgso=0 Cgdo=0 Cj=0 Cjsw=0 Tox=18u Ld=0<br />
.model Ymod Txl R=12.45 L=9u G=0 C=0p47 Length=16<br />
.end<br />
</pre><br />
<br />
<br />
----<br />
=== Voltage Controlled Switches ===<br />
<br />
LTspice has a cleaner syntax for voltage controlled switches, but has no problem with any PSpice voltage controlled switch syntax.<br />
<br />
<br />
== Dot Commands ==<br />
=== .Ac (ac analysis) ===<br />
<br />
In an ac analysis, it seems that the maximum number of points that may calculated is limited to about 65k.&nbsp; If more are requested, LTspice will reduce the point count to this maximum, but without generating an error or warning.&nbsp; This limitation may become significant when attempting to simulate very high Q circuits over too broad a frequency range (e.g., crystal oscillators showing overtones).<br />
<br />
<br />
----<br />
=== .Options ===<br />
<br />
Note: ".opt" is accepted as shorthand notation for ".options" (options are added as text onto the schematic as a [[SPICE Directive]]).<br />
<br />
There are a whole lot of .option parameters and other control parameters (mostly legacy from SPICE 2 and Pspice) that should be documented (a few probably actually could be useful).&nbsp; Many of these are listed in the LTspice Yahoo group message [http://tech.groups.yahoo.com/group/LTspice/message/20174 #20174].<br />
<br />
<br />
==== .options List ====<br />
<br />
This flag parameter causes a dump of the flatened netlist (after expanding subcircuits) to appear in the '''SPICE Error Log''' file (sticky and causes the corresponding '''Generate Expanded Listing''' option check box in '''Operation''' tab of the [[Control Panel]] to become checked).<br />
<br />
.opt List ; selects "Generate Expanded Listing" in the Control Panel<br />
<br />
<br />
==== .options DampInductors=<''value''> ====<br />
<br />
This has the same effect as unchecking (value=0) or checking (value=1) the '''Rpar''' inductor option on the '''Hacks''' tab of the '''Control Panel''', overriding whatever is set there (the default value in LTspice is 1 or ''ON'', which is opposite the standard SPICE convention).&nbsp; The default value for the parallel damping resistance equals 1e12 times the inductance value (1T x L) and is only applied in the case of a transient analysis.<br />
<br />
.opt DampInductors=0 ; turn off LTspice's default parallel damping resistance<br />
<br />
<br />
==== .options Thev_Induc=<''value''> ====<br />
<br />
This has the same effect as unchecking (value=0) or checking (value=1) the '''Rser''' inductor option on the '''Hacks''' tab of the '''Control Panel''', overriding whatever is set there (the default value in LTspice is 0 or ''ON'', which is opposite the standard SPICE convention).&nbsp; The default value for the series damping resistance equals 1 milliohm and is applied to all analyses.<br />
<br />
.opt Thev_Induc=1 ; turn off LTspice's default 1 milliohm series damping resistance (R = 0)<br />
<br />
Notes:<br />
* Using the standard SPICE convention settings for these two inductor options causes the circuit matrix to be bigger, run slower and be more prone to convergence errors.<br />
* I have yet to discover how to alter the global default enabled values for Rpar and Rser (changing Gmin has no effect on the parallel damping resistance for inductors). <br />
<br />
<br />
==== .options Gfarad=<''value''> ====<br />
<br />
Added at LTspice version 4.14h (per public posting by Yahoo LTspice group moderator, Helmut Sennewald, 04/13/12).<br />
<br />
This option allows the user to set the global value for a capacitor's default parallel conductance factor (1/'''Rpar''' = Gpar = '''Gfarad'''*C).<br />
<br />
.opt Gfarad=1e-12 ; has no effect because this is the existing default conductance factor<br />
.opt Gfarad=0 ; sets the global conductance factor to zero (removes the hidden default parallel resistance for all capacitors)<br />
<br />
Notes:<br />
* As a convergence aid, capacitors in LTspice include a hidden default parallel resistance of '''Rpar''' = 1e12/C.&nbsp; Specifying any value for '''Equiv. Parallel Resistance''' ('''Rpar''') in a capacitor's '''Component Editor''' window will override this default.&nbsp; Specifying a value of zero ('''Rpar'''=0) removes the default resistance (sets the conductance to zero).<br />
* The arbitrary capacitor (specified via a behavioral charge equation - refer to the topic in '''Help''') has no parallel conductance and is not affected by '''Gfarad'''.<br />
<br />
<br />
==== .options Gfloat=<''value''> ====<br />
<br />
This option allows the user to set the global value for the shunt conductance from floating nodes to ground.<br />
<br />
.opt Gfloat=1e-12 ; has no effect because this is the existing default conductance factor (which is Gshunt)<br />
.opt Gfloat=0 ; sets the global conductance factor to zero (removes the hidden default ground shunt resistance for all floating nodes)<br />
<br />
Notes:<br />
* As a convergence aid, floating nodes in LTspice include a hidden default shunt resistance to ground.&nbsp; The default value is equal to the value of '''Gshunt''' (which also may be optionally set - refer to the topic in '''Help''').&nbsp; Specifying a value for '''Gfloat''' will override this default.&nbsp; Specifying a value of zero removes the default shunt resistance (sets the conductance to zero).<br />
* Floating nodes are typically created when only connected to capacitors and/or current sources.<br />
<br />
<br />
==== .options TopologyCheck=2 ====<br />
<br />
Listed in the ChangeLog 09/14/11: "Beta Optimisations regarding dangling nodes."<br />
<br />
Setting this parameter to 2 has the same effect as checking '''Enable beta circuit matrix optimizations''' on the '''Hacks''' tab of the '''Control Panel''', overriding whatever is set there.<br />
<br />
.opt TopologyCheck=2 ; (parameter numbers 0 and 1 are documented in Help)<br />
<br />
<br />
==== .options tSeed=<''value''> ====<br />
<br />
This option lets you seed the integrator with a specific guess for the initial .tran timestep<br />
<br />
.opt tSeed=100n<br />
<br />
<br />
----<br />
=== .NodeAlias <''aliasName''> <''netName''> ===<br />
<br />
Listed in the ChangeLog 10/06/10: "Allows to give a net an alternative name." <br />
<br />
Placing the Jumper symbol (''lib/sym/Misc/jumper'') is another, documented and probably more convenient way of giving the same net two names, however, in a hierarchical design, it only functions on a top level schematic.<br />
<br />
.nodealias output drain<br />
<br />
<br />
== Miscellaneous Hints and Tricks ==<br />
<br />
... should be added here or given its own section if warranted.<br />
<br />
Here's a hint to anyone wishing to keep up-to-date with the latest additions to '''LTspice''''s great features - always read the '''''changelog.txt''''' file (located in the '''LTspiceIV''' program folder) after every web update /sync release.<br />
* From the ChangeLog on 02/21/07: "Added a check box on the Tools=>Control Panel=>Hacks! pane to allow the '''MC generator''' to be reseeded by the real time clock."<br />
<br />
<br />
'''A-Devices''' See message #19378 from the LTspice Yahoo users group.<br />
<br />
<br />
----<br />
=== Circuit Element Area Multiplier ===<br />
<br />
The only the following LTspice elements accept the ''Area Multiplier'' parameter, '''m'''=<value>, where '''m''' is the value by which the element area will be multiplied:<br />
<br />
'''C''' (Capacitors), '''D''' (Diodes), '''J*''' (JFETs), '''L''' (Inductors), '''M''' (MOSFETs), '''Q*''' (Bipolar Transistors) '''R*''' (Resistors), '''Z''' (MESFETs and IGBTs).<br />
<br />
<nowiki> </nowiki>'''''* m'''=<value> is an undocumented or poorly documented feature of this element''<br />
<br />
----<br />
=== Alternate Syntax ===<br />
<br />
In many contexts, where possible, LTspice supports alternate syntaxes compatible with other simulators.<br />
* Single quotes generally may be used in place of curly braces.<br />
<br />
<br />
=== AKO Aliases (A Kind Of) ===<br />
<br />
''Suppose I wished to modify a single parameter of an existing model but don't want to copy the full model out as a duplicate and adjust it.&nbsp; I want to pick up all of the specified and default parameter values for the given model name (and if it specifies yet another, to pick up those, as well) and simply modify one parameter or two in a new model.''<br />
<br />
''A reason I may wish to do this is that I may, at some later time, decide to modify the underlying model and I'd like all of the dependent models to pick up the underlying changes, automatically.&nbsp; I just don't know if there is syntax for it.&nbsp; Do you know?''<br />
<br />
Yes.&nbsp; Try something like this:<br />
<br />
.model 2N2222mod ako: 2N2222 bf=5 ; same except lower beta<br />
<br />
<br />
----<br />
> It appears that parameters must ultimately resolve to numbers instead of text.<br />
<br />
You are correct in your supposition - parameters must be numbers.<br />
<br />
> Is there a way to pass text to a subcircuit to do what I want?<br />
<br />
Yes.&nbsp; Models can take numeric alias using the AKO ("A Kind Of") function.<br />
These numeric aliases will work with parameter passing:<br />
<br />
.model 1 ako:2N3904 ;the existing 2N3904 model now also known as "1"<br />
.model 2 ako:2N2222 ;the existing 2N2222 model now also known as "2"<br />
<br />
This topic has been discussed many times in this forum before, but it may be difficult to search for because the name of the AKO function doesn't really correspond to "Also Known As" (it stands for "A Kind Of").<br />
<br />
You can find many examples using AKO in the Group archive here:<br />
<br />
Files -> Tut -> Stepping to the max<br />
<br />
<br />
=== Stepping a Model ===<br />
<br />
Sometimes it might be of interest to try out several different types of some component in a circuit, instead of just stepping a single parameter of a component.&nbsp; This can be done by giving the models that should be tried number-only names.&nbsp; For example, using the above discussed AKO feature, NPN transistors can be named as follows:<br />
<br />
.model 3904 ako:2N3904<br />
.model 2222 ako:2N2222<br />
.model 547 ako:BC547<br />
<br />
It is also possible to define a model with a number-only name from scratch:<br />
<br />
.model 4 NPN<br />
<br />
The next step is to add a spice directive to define a parameter, ''STM'' in the example below, which is stepped through the model names.&nbsp; Since the ''.step'' command can only step numeric values it is vital that the models have been given number-only names, as shown above. <br />
<br />
.step param STM list 3904 2222 547 4<br />
<br />
The last step is then to use the parameter in place of a model ''Value''.&nbsp; To make sure the parameter is evaluated, it needs to be placed in brakes.&nbsp; For example, the above defined parameter ''STM'' would be given in the form of ''{STM}'' as the ''Value'' of an NPN transistor symbol.<br />
<br />
<br />
=== Schematic Editor ===<br />
<br />
====Key Combination====<br />
* '''Shift-Ctrl-Alt-R''': Permanently renumbers all reference designators within the schematic.<br />
* '''Shift-Ctrl-Alt-H''': Temporarily highlights all hidden text within the schematic.<br />
* Hold down '''Ctrl''' when placing wires to route at any angle.<br />
* Hold down '''Ctrl''' when drawing lines to draw off grid.<br />
* Hold down '''Ctrl''' or '''Shift''' for more movement with '''arrow keys'''.<br />
* Hold down '''Ctrl''' ''and'' '''Shift''' for ''most'' movement with '''arrow keys'''.<br />
* Text preceeded with an underscore ("_") character will be displayed as overbarred (for active LOW digital signals).<br />
* '''Cross Probing''': Clicking '''Alt-Left''' on a label in the plot pane highlights the corresponding node in the schematic (since end of October 2012 release).&nbsp; E.g. clicking '''Alt-Left''' on a label like ''V(n001)'' in the plot pane highlights the ''n001'' node.&nbsp; Clicking '''Alt-Left''' on a label like ''I(R1)'' highlights ''R1'' in the schematic.<br />
<br />
<br />
====Operating Point Data Labels (visible numeric dc bias values)====<br />
<br />
LTspice has the ability to display dc operating point voltages, currents and expressions (e.g., power, energy, efficiency, etc.) directly within the schematic.&nbsp; Normally, labels are placed upon wires (nodes) much like '''Net Labels'''. <br />
<br />
<br />
===== Preparation =====<br />
<br />
To be able to place/show operating point data labels right-click on an empty area of the schematic and select "'''View'''" from the drop down menu list. <br />
* Checking "'''Show .op Data Flags'''" shows all operating point numerical information on the schematic.<br />
Further, in the main menu<br />
* Checking "'''Mark Unconn. Pins'''" (main menu -> View) shows anchor boxes on the schematic when a label is moved.<br />
<br />
<br />
===== Creating a Label when doing a .op Simulation =====<br />
<br />
When doing a DC operating point simulation (.op) an operating point data label can be created as follows<br />
<br />
* Run the .op simulation<br />
* Left-Click on a net (a wire).&nbsp; This creates a new label that can be placed with the cursor.<br />
<br />
<br />
===== Creating a Label when doing another Simulations =====<br />
<br />
When doing other kinds of simulations than a DC operating point simulation (.op) operating point data labels can be created by right-clicking on an empty area of the schematic, then selecting '''View->Place .op Data Label''' on the drop down menu.&nbsp; The new label can be attached to a net with the cursor.<br />
<br />
<br />
===== Format and Layout =====<br />
<br />
Once placed, an operating point data label may be freely moved or copied and then edited to be completely unrelated to the original node.&nbsp; It is of course possible to decorate a label by using the normal drawing functions.&nbsp; For example painting a rectangle around it (main menu Edit->Draw->Rectangle) or by placing some text nearby (main menu Edit->Text).<br />
<br />
Operating point data labels default to the display of the voltage of the node to which they are attached (signified by the dollar sign character "$"), but this may be edited to be any valid expression, including currents, powers or even the voltage of a specific node.&nbsp; Right-clicking on a operating point data label brings up a popup window for selecting the data to display or enter an expression.<br />
<br />
With fractional values, all available non-zero digits will be displayed, often resulting in unwanted numerical clutter.&nbsp; The number of visible digits may be aesthetically limited by appropriately editing the expression to be displayed.&nbsp; Examples of rounding expressions used for formating:<br />
<br />
round($*1k)/1k ; display no more than 3 digits (typically automatically expressed in engineering format).<br />
round(I(R1)*1k)/1k ; same display format as above, but expression is of the current through R1.<br />
round(V(1,2)*1k)/1k ; same format, but expression is of the voltage difference between nodes 1 & 2.<br />
<br />
<br />
====Bussing of Connections and Components (BUS shorthand notation)====<br />
<br />
LTspice has an undocumented feature to draw busses (groups of nets) on the schematic.&nbsp; This feature is erratic.&nbsp; It is recommended to double check the resulting circuit by studying the netlist (main menu View->SPICE Netlist), because it is possible to attach wires to busses without exactly knowing which signal (net) from the bus the wire should actually represent.&nbsp; Busses are purely cosmetic on the schematic, they have no special SPICE function.&nbsp; All bussing notation is resolved (flattened to normal net notation) by the schematic editor prior to the creation of the SPICE netlist (the netlister does not understand bus notation, i.e. it it not possible to use a SPICE deck with bus notation in LTspice).<br />
<br />
An alternative to busses is to use individual net labels to connect distant nets.<br />
<br />
A net (wire) becomes a bus whenever any one of the following three conditions are met:<br />
<br />
# The wire is labeled with a netname with an array suffix.&nbsp; An array suffix consists of two numbers separated by a colon and enclosed in brackets.&nbsp; For example ''Data[0:7]'' means the bus consists of the eight nets ''Data[0]'', ''Data[1]'', up to ''Data[7]''. <br />
# The wire is connected to the wide end of a BUS tap (main menu Edit->Place BUS tap). <br />A net connected to the other end, the pointed end of a tap, is called a tap net, and is an individual net from the nets represented by the bus.&nbsp; Tap nets must be labeled with an individual array element suffix (a single number without colon enclosed in brackets).&nbsp; For example ''Data[3]'' would be the label of a tap net out of the ''Data[0:7]'' bus.<br />
# The net is connected to a bus pin of a component that has an array type name.<br />
<br />
Once a wire is becoming a bus it is automatically drawn with extra thick lines.<br />
<br />
A bus may be automatically connected (netlisted) to a corresponding array of components.&nbsp; An array of components is created by appending a bracketed array specifier to the instance name (reference designator) of a bus-connected single component.&nbsp; For example, instead of naming a transistor ''Q1'' naming it ''Q[1:4]'' would result in the single symbol representing four identical transistors.&nbsp; The base, collector and emitter pins of these component array all need to be connected to busses.&nbsp; For example to busses called ''Base[1:4]'', ''Collector[1:4]'', and ''Emitter[1:4]''.&nbsp; The resulting netlist is arbitrary if the pins of a component array are not properly connected to busses, but e.g. accidentally to single nets only.<br />
<br />
Note that recursive connections are possible around a single device or device group through the use of appropriate net labeling.&nbsp; For example', a single digital DFLOP device may be annotated to represent a 64 shift-register string by:<br />
<br />
# adding a 64 element array suffix to its instance name, e.g. ''A1'' would become ''A1[0:63]'',<br />
# placing on its D input a corresponding array net label, e.g., ''Data[0:63]'' (the particular name is unimportant), and<br />
# placing on its Q output an appropriately displaced array net label, e.g., ''Data[1:64]''.<br />
<br />
The result would be that the D inputs of A1[1] to A1[63] are connected to the Q outputs of A1[0] to A1[62].&nbsp; The D input of A1[0] (''Data[0]'') and Q output of A1[63] (''Data[64]'') need to be tapped off individually from the bus, and would represent the input and output of the resulting 64 bit shift register.<br />
<br />
; Example Notes<nowiki>:</nowiki><br />
: As usual for any flip-flop, a delay parameter must be specified in the Value field, e.g., ''td=10ns''.<br />
: The D input to the first gate may be individually accessed by its appropriate array index, e.g., ''Data[0]''<br />
<br />
<br />
====Title Block====<br />
<br />
The schematic editor can display a special symbol as a title block.&nbsp; This is a combined feature of the schematic editor and the symbol editor.&nbsp; The feature is purely cosmetic.&nbsp; It allows to decorate a schematic so it looks more like a traditional drawing (depending on what is actually in the title block symbol). <br />
<br />
The title block needs to be created in the form of a symbol (.asy file), and be of symbol type MASTER.&nbsp; However, the LTspice symbol editor does not allow the creation of a symbol with such a type, while editing such a symbol is possible.&nbsp; Therefore, it is initially necessary to created an empty MASTER symbol with a text editor.&nbsp; Once initially created it can be opened and edited in LTspice.<br />
<br />
To start it is enough to create a .asy file with the following two lines in a text editor<br />
<br />
Version 4<br />
SymbolType MASTER<br />
<br />
Once saved from the text editor the file can then be opened in LTspice and the drawing commands can be used to design the title block, e.g. a frame, and several text fields.&nbsp; Pins must not be added to a title block symbol.&nbsp; Once saved in a project's directory, the title block can be added to a schematic just like any other symbol. <br />
<br />
Since it is difficult to edit a schematic while a title block is visible (attempting to select a component results in the selection of the title block instead), the title block may be turned on and off via the following option.<br />
<br />
View->Control Panel->Drafting Options->Show Title Blocks<br />
<br />
Before printing a page with a title block it is advisable to adjust the zooming of the schematic in the schematic editor, so the schematic with the title block exactly fits the screen.&nbsp; This can be done either via the toolbar button "Zoom full extents" or the menu item View->Zoom to fit.&nbsp; This assumes every symbol has been drawn within the boundaries of the title block.<br />
<br />
Here is an example of a simple title block symbol [[File:Title-block.asy]].<br />
<br />
<br />
=== Symbol Editor ===<br />
<br />
====Placing the ''Linear Technology'' or ''Analog Devices'' logos[[File:Logos.gif|100x24px]] within a Symbol====<br />
<br />
The text '''''LT''''' or '''''ADI''''' (must be all uppercase) in a symbol (menu Draw->Text) is replaced with the corresponding company logo when the symbol is used on a schematic.<br />
<br />
====Cut & Paste Between Symbols====<br />
<br />
Unfortunately this has yet to be implemented.&nbsp; Two workarounds are possible, but they are both cumbersome.<br />
<br />
# Open the symbol you wish to copy, then immediately save it with a new name.&nbsp; Modifying first before saving is dangerous because this requires always remembering to change the name after a distracting editing process.&nbsp; However, if the original ''is'' inadvertently overwritten, as long as the file is not closed the original may be recovered by repeatedly pressing the Undo key and then resaving.<br />
# Use a text editor to open both symbol files and copy the ASCII drawing command sequences from one file to the other.&nbsp; The commands are not difficult to read for selective editing, but the entire sequence also may be copied over and then subsequently graphically cleaned up from within LTspice's symbol editor.<br />
<br />
<br />
=== Plotting ===<br />
<br />
==== Cross Probing Key Combination ====<br />
<br />
* Clicking '''Alt-Left''' on a label in the plot pane highlights the corresponding node in the schematic (since end of October 2012 release).&nbsp; E.g. clicking '''Alt-Left''' on a label like ''V(n001)'' in the plot pane highlights the ''n001'' node.&nbsp; Clicking '''Alt-Left''' on a label like''I(R1)'' highlights ''R1'' in the schematic.<br />
<br />
<br />
==== Eye Diagram ====<br />
<br />
LTspice can plot eye diagrams - a feature which is only semi-documented.&nbsp; The following two "Plot Settings" menu items related to eye diagrams<br />
<br />
[select a plot pane (.raw)]<br />
Plot Settings->Eye Diagram->Enable<br />
Plot Settings->Eye Diagram->Properties<br />
<br />
They are usually disabled.&nbsp; LTspice enables them when adding the insufficiently documented, baudrate-option <br />
<br />
.option baudrate=<rate><br />
<br />
to a schematic.&nbsp; Instead of <rate> the nominal symbol rate of the signal should be given.&nbsp; <rate> defines at what intervals the signal should be triggered.<br />
<br />
Once enabled the <br />
<br />
Plot Settings->Eye Diagram->Properties<br />
<br />
menu item allows to set two more eye diagram properties.&nbsp; An initial delay, which effectively specifies where the eye(s) should be plotted on the horizontal axis.&nbsp; And the number of eyes, which is equivalent how many trigger intervals should be displayed.<br />
<br />
The following schematics both contain a baudrate option, but it is commented out. <br />
<br />
examples/Education/PLL.asc<br />
examples/Education/PLL2.asc<br />
<br />
Uncommenting the option, running the simulation, enabling the eye diagram in the Plot Settings, and then probing the signal net (not the out net) gives a typical eye diagram.<br />
<br />
<br />
=== Probing Subcircuit Waveforms (signal naming conventions) ===<br />
<br />
To be able to display subcircuit waveforms, you must first ensure that the ''Save Subcircuit Node Voltages'' and the ''Save Subcircuit Device Currents'' options are enabled in the '''Save Defaults''' tab of the [[Control Panel]].&nbsp; Then, if your simulation was created as a hierarchical design using LTspice's '''Schematic Capture''' window, you may simply use the probe tool to select an active subcircuit schematic's nodes as required.&nbsp; But if the SPICE netlist was imported from an external source then the probe statement format is as follows:<br />
<br />
* a top level node:<br />
.probe v(node)<br />
<br />
* a subcircuit node:<br />
.probe v(subckt_name:node)<br />
.probe v(subckt_name:subsubckt_name:node)<br />
<br />
* a subcircuit MOSFET drain current:<br />
.probe id(subckt_name:mp1)<br />
<br />
<br />
=== Netlists ===<br />
<br />
A netlist line starting with "'''*!LTspice:''' " is now treated as a SPICE directive for LTspice (but a comment in other SPICE programs). - 09/05/06<br />
<br />
= References & Footnotes =<br />
<br />
<references/><br />
<br />
<br />
{{#widget:DISQUS<br />
|id=ltwiki<br />
|uniqid={{PAGENAME}}<br />
|url={{fullurl:{{PAGENAME}}}}<br />
}}</div>Analogspicemanhttp://ltwiki.org/index.php?title=Transformers&diff=2120Transformers2019-11-21T04:48:06Z<p>Analogspiceman: /* Now how do I plot a B-H curve to see the Chan model's hysteresis-saturation curves? */</p>
<hr />
<div>== Transformers ==<br />
<br />
=== Introduction ===<br />
<br />
Do you wish to study the behavior of transformers and inductors and explore their mysteries?&nbsp; LTspice is the ideal learning tool for this purpose. LTspice will faithfully model both ideal and real magnetic devices.&nbsp; However, caution is advised when first experimenting with unfamiliar concepts in inductors and transformers.&nbsp; Be sure to minimize simulation problems by including reasonably realistic parasitic resistances (both series and parallel) directly into each inductor, whether used individually or as part of a transformer.<br />
<br />
A good learning and reference resource is the [http://coefs.uncc.edu/mnoras/files/2013/03/Transformer-and-Inductor-Design-Handbook_Chapter_17.pdf <i>Transformer and Inductor Design Handbook</i> Chapter 17, Winding Capacitance and Leakage Inductance] 4th Edition by Colonel William. T. McLyman.&nbsp; Mike Engelhardt, the author of LTspice, explains how to make transformers in LTspice in a [https://www.analog.com/en/technical-articles/using-transformers-in-ltspice-switcher-cadiii.html 2006 LT-Magazine article].<br />
<br />
Always keep in mind that starting a simulation with a dc voltage bias on an inductor or transformer winding will cause an initial inductor current only limited by the inductor's series resistance (this would be like trying to initialize an ideal capacitor with a current source - no matter how small the source, the dc voltage will increase without bounds - or at least until the capacitor breaks down).&nbsp; In fact, if you are like most engineers, you are much more comfortable with the behavior of capacitors.&nbsp; If so, use this to your advantage by applying duality to think of what to expect when dealing with inductors.<br />
<br />
=== How do I make a transformer in LTspice? === <br />
<br />
[[File:LTspice_Transformer.gif|right|179x143px|Two lines were used to draw the core]]<br />
<br />
Although it is very possible to make a dedicated subcircuit for a specific transformer, the preferred method of making a generic transformer when drafting a simulation schematic is to simply place a separate inductor for each separate transformer winding and then couple them all together magnetically via a single ''[[Mutual Inductance]] (K) statement'' placed as a [[SPICE Directive]] on the schematic.&nbsp; Note that inductors called out in a [[Mutual Inductance]] statement will be automatically given a phasing dot if one does not already exist.<br />
<br />
K1 L1 L2 L3 1 ; causes phasing dots to automatically appear on L1-L3 inductor symbols<br />
<br />
When creating a new transformer this way, especially for use in a switched-mode power circuit, it is generally best to first specify the mutual coupling coefficient to be exactly unity.&nbsp; By starting with unity coupling there will be no leakage inductance in any winding and this will minimize the likelihood of the windings ringing at extremely high frequencies (which can slow the simulation to a crawl at each switching edge).&nbsp; However, be aware that a mutual inductance value of plus (or minus) unity ''may'' lead to simulation difficulties if ''Skip-the-initial-operating-point-solution'' (UIC) is specified for the .tran command.&nbsp; Prevent this by specifying a realistic resistance for each inductor "winding" (ctrl-right-mouse-click).&nbsp; Note that when coupled inductors are used as transformer windings, individual winding inductances rather than turns ratios must be specified (''inductance ratios should be set to be proportional to <u>the '''square''' of the turns ratios''</u>).<br />
<br />
=== I've created an ideal transformer so it should work at all frequencies, even including DC, right? ===<br />
<br />
No, but lots of users completely misunderstand or overlook this when setting up their simulation.&nbsp; This common mistake can lead to a lot of needless doubt following unexpected and puzzling simulation results produced by LTspice when presented with an ideal transformer that is inadvertently initialized with a large amount of dc voltage applied to its windings.&nbsp; This is probably the most common self-inflicted pitfall that trips up users improperly specifying ac voltage sources.<br />
<br />
When LTspice calculates initial conditions for voltage sources, it uses the values at time = 0.&nbsp; Depending on the starting phase angle and delay specified for a sine source, this can be as much as the voltage at the peak of the sine wave.&nbsp; When the simulator attempts to find the circuit's initial solution, this is the equivalent to hooking the transformer up to a large dc voltage source.&nbsp; Current will only be limited by winding resistance (which, in the ideal case, may be zero).&nbsp; Note that a real transformer will saturate at a relatively low current and would normally not store much energy (it would also probably burn up with so much dc applied), but an ideal transformer with an ideal magnetizing inductance may store a physically impossible amount of simulated "virtual" energy.<br />
<br />
Without realizing it, many users may instruct LTspice to initialize the transformer magnetizing inductance with huge starting currents.&nbsp; Since they have used an ideal inductance that does not saturate (like a real transformer would), it starts out with dc current that may take many hundreds of line (or switching) cycles to die away.&nbsp; This completely unrealistic energy source then may dominate the simulation, causing strange and unexpectedly puzzling behavior.&nbsp; In such cases, LTspice is just innocently following the instructions given it and accurately computing the unrealistic results (garbage in, garbage out).<br />
<br />
To avoid this bogus and unwanted result, you must either arrange '''''the ac source to be zero at time zero''''' or '''''instruct LTspice not to use a dc solution for the starting point (UIC).'''''<br />
<br />
=== I want to model leakage inductance - how should I do that? ===<br />
<br />
The most flexible method is to keep the windings' mutual inductance statement at unity and add a small discrete leakage inductance in series with each winding.&nbsp; This is the most straightforward way to model transformers with asymmetrical leakage inductances.&nbsp; However, if your transformer is electrically symmetrical, it may be more convenient to simply set the mutual inductance to a value less than one.&nbsp; For each winding the resulting leakage inductance will be (1-K) times that winding's inductance.&nbsp; Also, each winding's coupled inductance also will decrease to K times that winding's inductance, but for typical values of K (>>0.9) this effect will be very small.&nbsp; Note that physical transformer leakage inductance measured in the laboratory typically is close to the sum of the leakage inductance of two windings in series combination (with coupled inductance and perhaps several windings partially in parallel).<br />
<br />
'''This is how LTspice "sees" coupled inductors:'''<br />
<br />
For n inductors coupled together with a K statement, each inductor L1 through Ln is divided into two parts, a completely non-coupled "leakage" inductance equal to (1-K)*Lx (where Lx is the particular inductor in question) and a completely coupled "mutual" inductance equal to K*Lx.&nbsp; Voltage and current ratios of the coupled parts are related by the ratio of the square root of the the inductances L1 through Ln (this is the apparent "turns ratio").<br />
<br />
[[File:Loosely_Coupled_Transformer.gif|right|186px|(full: 371x322)|Coupling is only K=0.2]]<br />
<br />
* For example, given two inductors coupled by a K statement:<br />
L1 1 0 1H<br />
L2 2 0 1H<br />
K1 L1 L2 0.2<br />
<br />
[[File:Loosely_Coupled_Equivalent.gif|right|185px|(full: 370x312)|"Winding" inductance is 1H]]<br />
<br />
* In LTspice, this is the same as:<br />
L1 1 12 0.8H<br />
L12 12 0 0.2H<br />
L2 2 12 0.8H<br />
<br />
Other engineering conventions regarding the definition of K, coupling and formula for leakage inductance are irrelevant to LTspice.&nbsp; Other formula for leakage inductance are intended to find total leakage inductance from an input winding through to an output winding(s) rather than the partial leakage inductance for each individual winding.<br />
<br />
=== How about transformer saturation effects?&nbsp; Can LTspice model those? ===<br />
<br />
Yes, LTspice comes with a non-linear hysteretic core model built in!&nbsp; This is the 1991 model by John Chan et al.&nbsp; Compared to older core models, [[the Chan model]] is particularly robust, computationally efficient and compact, requiring only three parameters to define most any commonly encountered magnetic hysteresis loop.&nbsp; (LTspice also allows building an arbitrary inductance based on self flux and/or any valid function of node voltages and branch currents.&nbsp; [[The Arbitrary Inductor model|The arbitrary inductor model]] can be very efficiently used to create saturation without hysteresis.) <br />
<br />
Once the Chan core material's generic magnetic properties are set, establishing the circuit-level non-linear inductance requires specifying three more parameters to set the geometry of the specific core and specifying one additional parameter for the core winding turn-count.&nbsp; The Chan inductor <font color="green" title="(has been mentioned as a possibility for a future release)">does not currently</font> directly support [[Mutual Inductance]], so unless only a single-winding inductor is being modeled, multiple windings must be added via additional circuitry.&nbsp; The simplest way to do this is to construct an ideal, unity coupled transformer with as many windings as required and then put the Chan inductor directly in parallel with any one of the windings (taking care to set the turns to match that particular winding).&nbsp; Since the magnetic effects (including non-saturated inductance) are already modeled by the Chan inductor, the inductance of the transformer's parallel winding must be enough larger (>>10) not to significantly load the Chan inductance.&nbsp; As before, the inductances for the other windings should be scaled by the square of their individual turns ratios (with respect to the paralleled winding).<br />
<br />
=== Okay, but calculating winding inductances is tedious.&nbsp; Is there some way to just enter a turns count for all the windings? ===<br />
<br />
Yes, this can be done in any of a number of ways.&nbsp; For example, the values for each of the inductances may be directly parametrized via <font color="green"><b title="Lx node1 node2 {Lm*(Nx/Nm)**2}">curly braces</b></font> to be a function of turns ratios (squared), or a subcircuit that accepts turns as a parameter may be used to encapsulate the windings implementation details.<br />
<br />
* Use parameters to to convert input of winding turns to inductance:<br />
[[File: Parameterized_Transformer.gif|right|307px|(full: 613x236)|Turns are entered as parameters from which the inductance is calculated]]<br />
.param Lp=20m Np=200 Ns=20 ; inputs: primary inductance, primary turns, secondary turns<br />
.param Kn=Lp/Np**2 ; calculated inductance per turn squared<br />
Lp 1 0 {Np**2*Kn} ; primary inductance = 200t**2*Kn<br />
Ls 2 0 {Ns**2*Kn} ; secondary inductance = 20t**2*Kn<br />
Kx Lp Ls 1 ; core coupling factor = 1<br />
<br />
Below is a schematic of a simple LTspice subcircuit that is functionally equivalent to a winding (without a core).&nbsp; Its symbol appears just to the right of the schematic.&nbsp; LTspice's fully extended inductor parasitics are included within this model.&nbsp; Observe that the winding is presented with a voltage equal to the core's volts/turn*primary_turns and that the core is presented with a current equal to the winding's ampere-turns = winding's amps*primary_turns.&nbsp; Also note if the leakage inductance and resistances are zero, the winding is completely floating with respect to the core and that the winding performs a voltage ratio transformation (set by the turns ratio) from DC to light.<br />
<br />
* First, the basic winding: Start (dot), Finish, Core:<br />
[[File: Simple Winding Symbol & Subcircuit.gif|right|480px|(full: 959x270)|This simple subcircuit is equivalent to an inductor or transformer winding]]<br />
.subckt Winding s f c params: n=100 L=1u Rs=1m Rp=100<br />
Lw s 1 {L} Rser={Rs} Rpar={Rp} ; leakage and resistance<br />
Ew 1 f c 0 {n} ; impose core volts/turn*turns onto winding<br />
Fw 0 c Ew {n} ; impose winding amperes*turns onto core<br />
.ends Winding<br />
<br />
<br />
=== DC to DC Transformer (no magnetizing inductance - no energy storage) ===<br />
<br />
The transformer winding subcircuits are DC coupled and, when connected to a "core" (1TΩ in parallel with 1pF) that supports DC without drawing current, they combine to make a transformer that draws no magnetizing current, stores no energy and therefore is immune to errant initial conditions.&nbsp; This model may be an advantage when first experimenting with new power circuits.<br />
<br />
For better cosmetics the simple DC core may encapsulated in its own subcircuit and symbol.&nbsp;<br />
<br />
[[File: DC_to_DC_Transformer.gif|right|188px|(full: 376x288)|DC to DC (because of "core") transformer with two windings]]<br />
* Here is a DC "core" that does not draw increasing current with time:<br />
.subckt Core_DC C<br />
Cc C 0 1p Rpar=1T ; dump the "core's" ampere-turns into a small conductance<br />
.ends Core_DC<br />
<br />
[[File: DC_to_DC_Transformer_&_Core.gif|right|186px|(full: 372x266)|DC to DC transformer with DC core symbol for aesthetics]]<br />
* DC-to-DC Transformer Equivalent (Netlist Uprocessed):<br />
Xp P 0 C Winding n=1 L=1u Rs=1m Rp=100 ; primary winding of 1:1 transformer<br />
Xs S 0 C Winding n=1 L=1u Rs=1m Rp=100 ; secondary winding of 1:1 transformer<br />
Xc C CoreDC ; subcircuit consisting of 1TΩ in parallel with 1pF<br />
<br />
=== Linear Transformer (linear magnetizing inductance - potentially unlimited energy storage) ===<br />
<br />
A standard linear transformer may easily be created simply by changing the core to be a standard inductor with Rs=0.&nbsp; In this form (with a standard ''linear'' magnetizing inductance "core") the model is mostly useful as a perceptual window into the way coupled inductors work in LTspice since linear transformers are more easily and simply built with standard coupled inductors.&nbsp; Note that the magnetizing inductance "core" is the single summing point for the ''ampere-turns'' from all the windings and is the sole source of ''impressed voltage'' (=L*di/dt) reflected onto all the windings.&nbsp; Although this subcircuit is an unnecessary and overly complex representation for a transformer with a linear core inductance, it will be absolutely required if multiple windings are to be "wrapped" onto LTspice's nonlinear Chan inductance model, so take a moment to read it through (the Chan version will follow shortly).<br />
<br />
<br />
* Parametize and wrap an inductor with a subcircuit:<br />
[[File: Linear_Core.gif|right|212px|(full: 423x165)|A linear core is simply an inductor with Rser=0]]<br />
.subckt Core_Linear C params: L=20m Rp=10k Cp=10p<br />
Lc C 0 {L} Rser=0 Rpar={Rp} Cpar={Cp}<br />
.ends Core_Linear<br />
<br />
[[File: Linear_Transformer.gif|right|187px|(full: 374x270)|Transformer with linear core]]<br />
* Linear Transformer Equivalent (Netlist Unprocessed):<br />
Xp P 0 C Winding n=1 L=1u Rs=1m Rp=100 ; primary winding of 1:1 transformer<br />
Xs S 0 C Winding n=1 L=1u Rs=1m Rp=100 ; secondary winding of 1:1 transformer<br />
Xc C Core_Linear L=20m Rp=10k Cp=10p ; subcircuit consisting of an inductor with Rs=0<br />
<br />
* Linear Transformer Equivalent (Netlist Flattened):<br />
[[File: Linear_Transformer_Full.gif|right|455px|(full: 909x236)|Transformer with linear core]]<br />
Lp Ps 1 1u Rser=1m Rpar=100 ; leakage and resistance<br />
Ep 1 Pf C 0 1 ; impose core volts/turn*turns onto winding<br />
Fp 0 C Ep 1 ; impose winding ampere*turns onto core<br />
Lc C 0 20m Rpar=10k Cpar=10p ; liner inductor core (no magnetic saturation)<br />
+ Rser=0 ; Rser must equal zero<br />
Fs 0 C Es 1 ; impose winding ampere*turns onto core<br />
Es 1 Sf C 0 1 ; impose core volts/turn*turns onto winding<br />
Ls Ss 1 1u Rser=1m Rpar=100 ; leakage and resistance<br />
<br />
=== Chan Transformer (saturating magnetizing inductance with hysteresis - limited energy storage) ===<br />
<br />
Now that the windings are separate from the core, a Chan inductor may simply be substituted for the linear inductor core.&nbsp; Since the inductance of a Chan inductor is not assigned, but is determined by its magnetic material, dimensional properties and winding turns, one must adjust inductance by iteratively adjusting the gap and/or winding turns.&nbsp; Measure inductancs by comparing slopes when subjected to the same stepped DC voltage.<br />
<br />
<br />
* Parametize and wrap a Chan inductor with a subcircuit:<br />
[[File: Chan_Core.gif|right|170px|(full: 340x288)|Physical properties based core with hysteresis and saturation]]<br />
.subckt Core_Chan C params:<br />
+ Bs=0.4 Br=0.1 Hc=20 ; Core default magnetic parameters<br />
+ A=25u1 Lm=19m8 Lg=0m7 ; Core default physical parameters<br />
+ Rp=10k Cp=10p ; Core default parallel loss and capacitance<br />
Lc C 0 Rser=0 n=1 ; force Rser=0 and n=1<br />
+ Bs={Bs} Br={Br} Hc={Hc}<br />
+ A={A} Lm={Lm} Lg={Lg}<br />
+ Rpar={Rp} Cpar={Cp}<br />
.ends Core_Chan<br />
<br />
[[File: Chan_Transformer.gif|right|172px|(full: 344x276)|Physically parameterized transformer with hysteresis and saturation]]<br />
* Chan Transformer Equivalent (Netlist Unprocessed):<br />
Xp P 0 C Winding n=100 L=1u Rs=1m Rp=100 ; primary winding of 1:1 transformer<br />
Xs S 0 C Winding n=100 L=1u Rs=1m Rp=100 ; secondary winding of 1:1 transformer<br />
Xc C Core_Chan ; Chan inductor subcircuit with forced Rs=0 and n=1<br />
+ Bs=0.4 Br=0.1 Hc=20 Br=.10 ; Assigned core magnetic parameters<br />
+ A=25u1 Lm=19m8 Lg=0m7 ; Assigned core physical parameters<br />
+ Rp=10k Cp=10p ; Assigned core parallel loss and capacitance<br />
<br />
=== Now how do I plot a B-H curve to see the Chan model's hysteresis-saturation curves? ===<br />
<br />
Plotting hysteresis-saturation curves of the Chan Transformer in LTspice<br />
<br />
''Under construction.''<br />
<br />
1 ampere∙turn/meter = 4∙π/1000 Oersted(Oe)<br />
<br />
1 volt∙seconds/turn/meter² = 1 Tesla(T) = 10,000 gauss(G)<br />
<br />
<br />
{{#widget:DISQUS<br />
|id=ltwiki<br />
|uniqid={{PAGENAME}}<br />
|url={{fullurl:{{PAGENAME}}}}<br />
}}</div>Analogspicemanhttp://ltwiki.org/index.php?title=Talk:Main_Page&diff=2119Talk:Main Page2019-11-21T04:43:29Z<p>Analogspiceman: </p>
<hr />
<div>One page removed due to error in information supplied <br />
<br />
(RE suggested by Helmut ) <br />
<br />
George<br />
----<br />
<br />
Thanks for catching that, Lewis</div>Analogspicemanhttp://ltwiki.org/index.php?title=Transformers&diff=2117Transformers2019-11-20T20:29:07Z<p>Analogspiceman: /* Transformers */ corrected typos, clarified some text</p>
<hr />
<div>== Transformers ==<br />
<br />
=== Introduction ===<br />
<br />
Do you wish to study the behavior of transformers and inductors and explore their mysteries?&nbsp; LTspice is the ideal learning tool for this purpose. LTspice will faithfully model both ideal and real magnetic devices.&nbsp; However, caution is advised when first experimenting with unfamiliar concepts in inductors and transformers.&nbsp; Be sure to minimize simulation problems by including reasonably realistic parasitic resistances (both series and parallel) directly into each inductor, whether used individually or as part of a transformer.<br />
<br />
A good learning and reference resource is the [http://coefs.uncc.edu/mnoras/files/2013/03/Transformer-and-Inductor-Design-Handbook_Chapter_17.pdf <i>Transformer and Inductor Design Handbook</i> Chapter 17, Winding Capacitance and Leakage Inductance] 4th Edition by Colonel William. T. McLyman.&nbsp; Mike Engelhardt, the author of LTspice, explains how to make transformers in LTspice in a [https://www.analog.com/en/technical-articles/using-transformers-in-ltspice-switcher-cadiii.html 2006 LT-Magazine article].<br />
<br />
Always keep in mind that starting a simulation with a dc voltage bias on an inductor or transformer winding will cause an initial inductor current only limited by the inductor's series resistance (this would be like trying to initialize an ideal capacitor with a current source - no matter how small the source, the dc voltage will increase without bounds - or at least until the capacitor breaks down).&nbsp; In fact, if you are like most engineers, you are much more comfortable with the behavior of capacitors.&nbsp; If so, use this to your advantage by applying duality to think of what to expect when dealing with inductors.<br />
<br />
=== How do I make a transformer in LTspice? === <br />
<br />
[[File:LTspice_Transformer.gif|right|179x143px|Two lines were used to draw the core]]<br />
<br />
Although it is very possible to make a dedicated subcircuit for a specific transformer, the preferred method of making a generic transformer when drafting a simulation schematic is to simply place a separate inductor for each separate transformer winding and then couple them all together magnetically via a single ''[[Mutual Inductance]] (K) statement'' placed as a [[SPICE Directive]] on the schematic.&nbsp; Note that inductors called out in a [[Mutual Inductance]] statement will be automatically given a phasing dot if one does not already exist.<br />
<br />
K1 L1 L2 L3 1 ; causes phasing dots to automatically appear on L1-L3 inductor symbols<br />
<br />
When creating a new transformer this way, especially for use in a switched-mode power circuit, it is generally best to first specify the mutual coupling coefficient to be exactly unity.&nbsp; By starting with unity coupling there will be no leakage inductance in any winding and this will minimize the likelihood of the windings ringing at extremely high frequencies (which can slow the simulation to a crawl at each switching edge).&nbsp; However, be aware that a mutual inductance value of plus (or minus) unity ''may'' lead to simulation difficulties if ''Skip-the-initial-operating-point-solution'' (UIC) is specified for the .tran command.&nbsp; Prevent this by specifying a realistic resistance for each inductor "winding" (ctrl-right-mouse-click).&nbsp; Note that when coupled inductors are used as transformer windings, individual winding inductances rather than turns ratios must be specified (''inductance ratios should be set to be proportional to <u>the '''square''' of the turns ratios''</u>).<br />
<br />
=== I've created an ideal transformer so it should work at all frequencies, even including DC, right? ===<br />
<br />
No, but lots of users completely misunderstand or overlook this when setting up their simulation.&nbsp; This common mistake can lead to a lot of needless doubt following unexpected and puzzling simulation results produced by LTspice when presented with an ideal transformer that is inadvertently initialized with a large amount of dc voltage applied to its windings.&nbsp; This is probably the most common self-inflicted pitfall that trips up users improperly specifying ac voltage sources.<br />
<br />
When LTspice calculates initial conditions for voltage sources, it uses the values at time = 0.&nbsp; Depending on the starting phase angle and delay specified for a sine source, this can be as much as the voltage at the peak of the sine wave.&nbsp; When the simulator attempts to find the circuit's initial solution, this is the equivalent to hooking the transformer up to a large dc voltage source.&nbsp; Current will only be limited by winding resistance (which, in the ideal case, may be zero).&nbsp; Note that a real transformer will saturate at a relatively low current and would normally not store much energy (it would also probably burn up with so much dc applied), but an ideal transformer with an ideal magnetizing inductance may store a physically impossible amount of simulated "virtual" energy.<br />
<br />
Without realizing it, many users may instruct LTspice to initialize the transformer magnetizing inductance with huge starting currents.&nbsp; Since they have used an ideal inductance that does not saturate (like a real transformer would), it starts out with dc current that may take many hundreds of line (or switching) cycles to die away.&nbsp; This completely unrealistic energy source then may dominate the simulation, causing strange and unexpectedly puzzling behavior.&nbsp; In such cases, LTspice is just innocently following the instructions given it and accurately computing the unrealistic results (garbage in, garbage out).<br />
<br />
To avoid this bogus and unwanted result, you must either arrange '''''the ac source to be zero at time zero''''' or '''''instruct LTspice not to use a dc solution for the starting point (UIC).'''''<br />
<br />
=== I want to model leakage inductance - how should I do that? ===<br />
<br />
The most flexible method is to keep the windings' mutual inductance statement at unity and add a small discrete leakage inductance in series with each winding.&nbsp; This is the most straightforward way to model transformers with asymmetrical leakage inductances.&nbsp; However, if your transformer is electrically symmetrical, it may be more convenient to simply set the mutual inductance to a value less than one.&nbsp; For each winding the resulting leakage inductance will be (1-K) times that winding's inductance.&nbsp; Also, each winding's coupled inductance also will decrease to K times that winding's inductance, but for typical values of K (>>0.9) this effect will be very small.&nbsp; Note that physical transformer leakage inductance measured in the laboratory typically is close to the sum of the leakage inductance of two windings in series combination (with coupled inductance and perhaps several windings partially in parallel).<br />
<br />
'''This is how LTspice "sees" coupled inductors:'''<br />
<br />
For n inductors coupled together with a K statement, each inductor L1 through Ln is divided into two parts, a completely non-coupled "leakage" inductance equal to (1-K)*Lx (where Lx is the particular inductor in question) and a completely coupled "mutual" inductance equal to K*Lx.&nbsp; Voltage and current ratios of the coupled parts are related by the ratio of the square root of the the inductances L1 through Ln (this is the apparent "turns ratio").<br />
<br />
[[File:Loosely_Coupled_Transformer.gif|right|186px|(full: 371x322)|Coupling is only K=0.2]]<br />
<br />
* For example, given two inductors coupled by a K statement:<br />
L1 1 0 1H<br />
L2 2 0 1H<br />
K1 L1 L2 0.2<br />
<br />
[[File:Loosely_Coupled_Equivalent.gif|right|185px|(full: 370x312)|"Winding" inductance is 1H]]<br />
<br />
* In LTspice, this is the same as:<br />
L1 1 12 0.8H<br />
L12 12 0 0.2H<br />
L2 2 12 0.8H<br />
<br />
Other engineering conventions regarding the definition of K, coupling and formula for leakage inductance are irrelevant to LTspice.&nbsp; Other formula for leakage inductance are intended to find total leakage inductance from an input winding through to an output winding(s) rather than the partial leakage inductance for each individual winding.<br />
<br />
=== How about transformer saturation effects?&nbsp; Can LTspice model those? ===<br />
<br />
Yes, LTspice comes with a non-linear hysteretic core model built in!&nbsp; This is the 1991 model by John Chan et al.&nbsp; Compared to older core models, [[the Chan model]] is particularly robust, computationally efficient and compact, requiring only three parameters to define most any commonly encountered magnetic hysteresis loop.&nbsp; (LTspice also allows building an arbitrary inductance based on self flux and/or any valid function of node voltages and branch currents.&nbsp; [[The Arbitrary Inductor model|The arbitrary inductor model]] can be very efficiently used to create saturation without hysteresis.) <br />
<br />
Once the Chan core material's generic magnetic properties are set, establishing the circuit-level non-linear inductance requires specifying three more parameters to set the geometry of the specific core and specifying one additional parameter for the core winding turn-count.&nbsp; The Chan inductor <font color="green" title="(has been mentioned as a possibility for a future release)">does not currently</font> directly support [[Mutual Inductance]], so unless only a single-winding inductor is being modeled, multiple windings must be added via additional circuitry.&nbsp; The simplest way to do this is to construct an ideal, unity coupled transformer with as many windings as required and then put the Chan inductor directly in parallel with any one of the windings (taking care to set the turns to match that particular winding).&nbsp; Since the magnetic effects (including non-saturated inductance) are already modeled by the Chan inductor, the inductance of the transformer's parallel winding must be enough larger (>>10) not to significantly load the Chan inductance.&nbsp; As before, the inductances for the other windings should be scaled by the square of their individual turns ratios (with respect to the paralleled winding).<br />
<br />
=== Okay, but calculating winding inductances is tedious.&nbsp; Is there some way to just enter a turns count for all the windings? ===<br />
<br />
Yes, this can be done in any of a number of ways.&nbsp; For example, the values for each of the inductances may be directly parametrized via <font color="green"><b title="Lx node1 node2 {Lm*(Nx/Nm)**2}">curly braces</b></font> to be a function of turns ratios (squared), or a subcircuit that accepts turns as a parameter may be used to encapsulate the windings implementation details.<br />
<br />
* Use parameters to to convert input of winding turns to inductance:<br />
[[File: Parameterized_Transformer.gif|right|307px|(full: 613x236)|Turns are entered as parameters from which the inductance is calculated]]<br />
.param Lp=20m Np=200 Ns=20 ; inputs: primary inductance, primary turns, secondary turns<br />
.param Kn=Lp/Np**2 ; calculated inductance per turn squared<br />
Lp 1 0 {Np**2*Kn} ; primary inductance = 200t**2*Kn<br />
Ls 2 0 {Ns**2*Kn} ; secondary inductance = 20t**2*Kn<br />
Kx Lp Ls 1 ; core coupling factor = 1<br />
<br />
Below is a schematic of a simple LTspice subcircuit that is functionally equivalent to a winding (without a core).&nbsp; Its symbol appears just to the right of the schematic.&nbsp; LTspice's fully extended inductor parasitics are included within this model.&nbsp; Observe that the winding is presented with a voltage equal to the core's volts/turn*primary_turns and that the core is presented with a current equal to the winding's ampere-turns = winding's amps*primary_turns.&nbsp; Also note if the leakage inductance and resistances are zero, the winding is completely floating with respect to the core and that the winding performs a voltage ratio transformation (set by the turns ratio) from DC to light.<br />
<br />
* First, the basic winding: Start (dot), Finish, Core:<br />
[[File: Simple Winding Symbol & Subcircuit.gif|right|480px|(full: 959x270)|This simple subcircuit is equivalent to an inductor or transformer winding]]<br />
.subckt Winding s f c params: n=100 L=1u Rs=1m Rp=100<br />
Lw s 1 {L} Rser={Rs} Rpar={Rp} ; leakage and resistance<br />
Ew 1 f c 0 {n} ; impose core volts/turn*turns onto winding<br />
Fw 0 c Ew {n} ; impose winding amperes*turns onto core<br />
.ends Winding<br />
<br />
<br />
=== DC to DC Transformer (no magnetizing inductance - no energy storage) ===<br />
<br />
The transformer winding subcircuits are DC coupled and, when connected to a "core" (1TΩ in parallel with 1pF) that supports DC without drawing current, they combine to make a transformer that draws no magnetizing current, stores no energy and therefore is immune to errant initial conditions.&nbsp; This model may be an advantage when first experimenting with new power circuits.<br />
<br />
For better cosmetics the simple DC core may encapsulated in its own subcircuit and symbol.&nbsp;<br />
<br />
[[File: DC_to_DC_Transformer.gif|right|188px|(full: 376x288)|DC to DC (because of "core") transformer with two windings]]<br />
* Here is a DC "core" that does not draw increasing current with time:<br />
.subckt Core_DC C<br />
Cc C 0 1p Rpar=1T ; dump the "core's" ampere-turns into a small conductance<br />
.ends Core_DC<br />
<br />
[[File: DC_to_DC_Transformer_&_Core.gif|right|186px|(full: 372x266)|DC to DC transformer with DC core symbol for aesthetics]]<br />
* DC-to-DC Transformer Equivalent (Netlist Uprocessed):<br />
Xp P 0 C Winding n=1 L=1u Rs=1m Rp=100 ; primary winding of 1:1 transformer<br />
Xs S 0 C Winding n=1 L=1u Rs=1m Rp=100 ; secondary winding of 1:1 transformer<br />
Xc C CoreDC ; subcircuit consisting of 1TΩ in parallel with 1pF<br />
<br />
=== Linear Transformer (linear magnetizing inductance - potentially unlimited energy storage) ===<br />
<br />
A standard linear transformer may easily be created simply by changing the core to be a standard inductor with Rs=0.&nbsp; In this form (with a standard ''linear'' magnetizing inductance "core") the model is mostly useful as a perceptual window into the way coupled inductors work in LTspice since linear transformers are more easily and simply built with standard coupled inductors.&nbsp; Note that the magnetizing inductance "core" is the single summing point for the ''ampere-turns'' from all the windings and is the sole source of ''impressed voltage'' (=L*di/dt) reflected onto all the windings.&nbsp; Although this subcircuit is an unnecessary and overly complex representation for a transformer with a linear core inductance, it will be absolutely required if multiple windings are to be "wrapped" onto LTspice's nonlinear Chan inductance model, so take a moment to read it through (the Chan version will follow shortly).<br />
<br />
<br />
* Parametize and wrap an inductor with a subcircuit:<br />
[[File: Linear_Core.gif|right|212px|(full: 423x165)|A linear core is simply an inductor with Rser=0]]<br />
.subckt Core_Linear C params: L=20m Rp=10k Cp=10p<br />
Lc C 0 {L} Rser=0 Rpar={Rp} Cpar={Cp}<br />
.ends Core_Linear<br />
<br />
[[File: Linear_Transformer.gif|right|187px|(full: 374x270)|Transformer with linear core]]<br />
* Linear Transformer Equivalent (Netlist Unprocessed):<br />
Xp P 0 C Winding n=1 L=1u Rs=1m Rp=100 ; primary winding of 1:1 transformer<br />
Xs S 0 C Winding n=1 L=1u Rs=1m Rp=100 ; secondary winding of 1:1 transformer<br />
Xc C Core_Linear L=20m Rp=10k Cp=10p ; subcircuit consisting of an inductor with Rs=0<br />
<br />
* Linear Transformer Equivalent (Netlist Flattened):<br />
[[File: Linear_Transformer_Full.gif|right|455px|(full: 909x236)|Transformer with linear core]]<br />
Lp Ps 1 1u Rser=1m Rpar=100 ; leakage and resistance<br />
Ep 1 Pf C 0 1 ; impose core volts/turn*turns onto winding<br />
Fp 0 C Ep 1 ; impose winding ampere*turns onto core<br />
Lc C 0 20m Rpar=10k Cpar=10p ; liner inductor core (no magnetic saturation)<br />
+ Rser=0 ; Rser must equal zero<br />
Fs 0 C Es 1 ; impose winding ampere*turns onto core<br />
Es 1 Sf C 0 1 ; impose core volts/turn*turns onto winding<br />
Ls Ss 1 1u Rser=1m Rpar=100 ; leakage and resistance<br />
<br />
=== Chan Transformer (saturating magnetizing inductance with hysteresis - limited energy storage) ===<br />
<br />
Now that the windings are separate from the core, a Chan inductor may simply be substituted for the linear inductor core.&nbsp; Since the inductance of a Chan inductor is not assigned, but is determined by its magnetic material, dimensional properties and winding turns, one must adjust inductance by iteratively adjusting the gap and/or winding turns.&nbsp; Measure inductancs by comparing slopes when subjected to the same stepped DC voltage.<br />
<br />
<br />
* Parametize and wrap a Chan inductor with a subcircuit:<br />
[[File: Chan_Core.gif|right|170px|(full: 340x288)|Physical properties based core with hysteresis and saturation]]<br />
.subckt Core_Chan C params:<br />
+ Bs=0.4 Br=0.1 Hc=20 ; Core default magnetic parameters<br />
+ A=25u1 Lm=19m8 Lg=0m7 ; Core default physical parameters<br />
+ Rp=10k Cp=10p ; Core default parallel loss and capacitance<br />
Lc C 0 Rser=0 n=1 ; force Rser=0 and n=1<br />
+ Bs={Bs} Br={Br} Hc={Hc}<br />
+ A={A} Lm={Lm} Lg={Lg}<br />
+ Rpar={Rp} Cpar={Cp}<br />
.ends Core_Chan<br />
<br />
[[File: Chan_Transformer.gif|right|172px|(full: 344x276)|Physically parameterized transformer with hysteresis and saturation]]<br />
* Chan Transformer Equivalent (Netlist Unprocessed):<br />
Xp P 0 C Winding n=100 L=1u Rs=1m Rp=100 ; primary winding of 1:1 transformer<br />
Xs S 0 C Winding n=100 L=1u Rs=1m Rp=100 ; secondary winding of 1:1 transformer<br />
Xc C Core_Chan ; Chan inductor subcircuit with forced Rs=0 and n=1<br />
+ Bs=0.4 Br=0.1 Hc=20 Br=.10 ; Assigned core magnetic parameters<br />
+ A=25u1 Lm=19m8 Lg=0m7 ; Assigned core physical parameters<br />
+ Rp=10k Cp=10p ; Assigned core parallel loss and capacitance<br />
<br />
=== Now how do I plot a B-H curve to see the Chan model's hysteresis-saturation curves? ===<br />
<br />
Plotting hysteresis-saturation curves of the Chan Transformer in LTspice<br />
<br />
''Under construction.''<br />
<br />
1 ampere∙turns/meter = 4∙π/1000 Oersted(Oe)<br />
<br />
1 volt∙seconds/turn/meter² = 1 Tesla(T) = 10,000 gauss(G)<br />
<br />
<br />
{{#widget:DISQUS<br />
|id=ltwiki<br />
|uniqid={{PAGENAME}}<br />
|url={{fullurl:{{PAGENAME}}}}<br />
}}</div>Analogspicemanhttp://ltwiki.org/index.php?title=Transformers&diff=2116Transformers2019-11-19T14:49:39Z<p>Analogspiceman: /* Transformers */ updated graphics + minor edits</p>
<hr />
<div>== Transformers ==<br />
<br />
=== Introduction ===<br />
<br />
Do you wish to study the behavior of transformers and inductors and explore their mysteries?&nbsp; LTspice is the ideal learning tool for this purpose. LTspice will faithfully model both ideal and real magnetic devices.&nbsp; However, caution is advised when first experimenting with unfamiliar concepts in inductors and transformers.&nbsp; Be sure to minimize simulation problems by including reasonably realistic parasitic resistances (both series and parallel) directly into each inductor, whether used individually or as part of a transformer.<br />
<br />
A good learning and reference resource is the [http://coefs.uncc.edu/mnoras/files/2013/03/Transformer-and-Inductor-Design-Handbook_Chapter_17.pdf <i>Transformer and Inductor Design Handbook</i> Chapter 17, Winding Capacitance and Leakage Inductance] 4th Edition by Colonel William. T. McLyman.&nbsp; Mike Engelhardt, the author of LTspice, explains how to make transformers in LTspice in a [https://www.analog.com/en/technical-articles/using-transformers-in-ltspice-switcher-cadiii.html 2006 LT-Magazine article].<br />
<br />
Always keep in mind that starting a simulation with a dc voltage bias on an inductor or transformer winding will cause an initial inductor current only limited by the inductor's series resistance (this would be like trying to initialize an ideal capacitor with a current source - no matter how small the source, the dc voltage will increase without bounds - or at least until the capacitor breaks down).&nbsp; In fact, if you are like most engineers, you are much more comfortable with the behavior of capacitors.&nbsp; If so, use this to your advantage by applying duality to think of what to expect when dealing with inductors.<br />
<br />
=== How do I make a transformer in LTspice? === <br />
<br />
[[File:LTspice_Transformer.gif|right|179x143px|Two lines were used to draw the core]]<br />
<br />
Although it is very possible to make a dedicated subcircuit for a specific transformer, the preferred method of making a generic transformer when drafting a simulation schematic is to simply place a separate inductor for each separate transformer winding and then couple them all together magnetically via a single ''[[Mutual Inductance]] (K) statement'' placed as a [[SPICE Directive]] on the schematic.&nbsp; Note that inductors called out in a [[Mutual Inductance]] statement will be automatically given a phasing dot if one does not already exist.<br />
<br />
K1 L1 L2 L3 1 ; causes phasing dots to automatically appear on L1-L3 inductor symbols<br />
<br />
When creating a new transformer this way, especially for use in a switched-mode power circuit, it is generally best to first specify the mutual coupling coefficient to be exactly unity.&nbsp; By starting with unity coupling there will be no leakage inductance in any winding and this will minimize the likelihood of the windings ringing at extremely high frequencies (which can slow the simulation to a crawl at each switching edge).&nbsp; However, be aware that a mutual inductance value of plus (or minus) unity ''may'' lead to simulation difficulties if ''Skip-the-initial-operating-point-solution'' (UIC) is specified for the .tran command.&nbsp; Prevent this by specifying a realistic resistance for each inductor "winding" (ctrl-right-mouse-click).&nbsp; Note that when coupled inductors are used as transformer windings, individual winding inductances rather than turns ratios must be specified (''inductance ratios should be set to be proportional to <u>the '''square''' of the turns ratios''</u>).<br />
<br />
=== I've created an ideal transformer so it should work at all frequencies, even including DC, right? ===<br />
<br />
No, but lots of users completely misunderstand or overlook this when setting up their simulation.&nbsp; This common mistake can lead to a lot of needless doubt following unexpected and puzzling simulation results produced by LTspice when presented with an ideal transformer that is inadvertently initialized with a large amount of dc voltage applied to its windings.&nbsp; This is probably the most common self-inflicted pitfall that trips up users improperly specifying ac voltage sources.<br />
<br />
When LTspice calculates initial conditions for voltage sources, it uses the values at time = 0.&nbsp; Depending on the starting phase angle and delay specified for a sine source, this can be as much as the voltage at the peak of the sine wave.&nbsp; When the simulator attempts to find the circuit's initial solution, this is the equivalent to hooking the transformer up to a large dc voltage source.&nbsp; Current will only be limited by winding resistance (which, in the ideal case, may be zero).&nbsp; Note that a real transformer will saturate at a relatively low current and would normally not store much energy (it would also probably burn up with so much dc applied), but an ideal transformer with an ideal magnetizing inductance may store a physically impossible amount of simulated "virtual" energy.<br />
<br />
Without realizing it, many users may instruct LTspice to initialize the transformer magnetizing inductance with huge starting currents.&nbsp; Since they have used an ideal inductance that does not saturate (like a real transformer would), it starts out with dc current that may take many hundreds of line (or switching) cycles to die away.&nbsp; This completely unrealistic energy source then may dominate the simulation, causing strange and unexpectedly puzzling behavior.&nbsp; In such cases, LTspice is just innocently following the instructions given it and accurately computing the unrealistic results (garbage in, garbage out).<br />
<br />
To avoid this bogus and unwanted result, you must either arrange '''''the ac source to be zero at time zero''''' or '''''instruct LTspice not to use a dc solution for the starting point (UIC).'''''<br />
<br />
=== I want to model leakage inductance - how should I do that? ===<br />
<br />
The most flexible method is to keep the windings' mutual inductance statement at unity and add a small discrete leakage inductance in series with each winding.&nbsp; This is the most straightforward way to model transformers with asymmetrical leakage inductances.&nbsp; However, if your transformer is electrically symmetrical, it may be more convenient to simply set the mutual inductance to a value less than one.&nbsp; For each winding the resulting leakage inductance will be (1-K) times that winding's inductance.&nbsp; Also, each winding's coupled inductance also will decrease to K times that winding's inductance, but for typical values of K (>>0.9) this effect will be very small.&nbsp; Note that physical transformer leakage inductance measured in the laboratory typically is close to the sum of the leakage inductance of two windings in series combination (with coupled inductance and perhaps several windings partially in parallel).<br />
<br />
'''This is how LTspice "sees" coupled inductors:'''<br />
<br />
For n inductors coupled together with a K statement, each inductor L1 through Ln is divided into two parts, a completely non-coupled "leakage" inductance equal to (1-K)*Lx (where Lx is the particular inductor in question) and a completely coupled "mutual" inductance equal to K*Lx.&nbsp; Voltage and current ratios of the coupled parts are related by the ratio of the square root of the the inductances L1 through Ln (this is the apparent "turns ratio").<br />
<br />
[[File:Loosely_Coupled_Transformer.gif|right|186px|(full: 371x322)|Coupling is only K=0.2]]<br />
<br />
* For example, given two inductors coupled by a K statement:<br />
L1 1 0 1H<br />
L2 2 0 1H<br />
K12 L1 L2 0.2<br />
<br />
[[File:Loosely_Coupled_Equivalent.gif|right|185px|(full: 370x312)|"Winding" inductance is 1H]]<br />
<br />
* In LTspice, this is the same as:<br />
L1 1 m 0.8H<br />
Lm m 0 0.2H<br />
L2 2 m 0.8H<br />
<br />
Other engineering conventions regarding the definition of K, coupling and formula for leakage inductance are irrelevant to LTspice.&nbsp; Other formula for leakage inductance are intended to find total leakage inductance from an input winding through to an output winding(s) rather than the partial leakage inductance for each individual winding.<br />
<br />
=== How about transformer saturation effects?&nbsp; Can LTspice model those? ===<br />
<br />
Yes, LTspice comes with a non-linear hysteretic core model built in!&nbsp; This is the 1991 model by John Chan et al.&nbsp; Compared to older core models, [[the Chan model]] is particularly robust, computationally efficient and compact, requiring only three parameters to define most any commonly encountered magnetic hysteresis loop.&nbsp; (LTspice also allows building an arbitrary inductance based on self flux and/or any valid function of node voltages and branch currents.&nbsp; [[The Arbitrary Inductor model|The arbitrary inductor model]] can be very efficiently used to create saturation without hysteresis.) <br />
<br />
Once the core material's generic magnetic properties are set, establishing the circuit-level non-linear inductance requires specifying three more parameters to set the geometry of the specific core and specifying one additional parameter for the core winding turn-count.&nbsp; The Chan inductor <font color="green" title="(has been mentioned as a possibility for a future release)">does not currently</font> directly support [[Mutual Inductance]], so unless only a single-winding inductor is being modeled, multiple windings must be added via additional circuitry.&nbsp; The simplest way to do this is to construct an ideal, unity coupled transformer with as many windings as required and then put the Chan inductor directly in parallel with any one of the windings (taking care to set the turns to match that particular winding).&nbsp; Since the magnetic effects (including non-saturated inductance) are already modeled by the Chan inductor, the inductance of the transformer's parallel winding must be enough larger (>>10) not to significantly load the Chan inductance.&nbsp; As before, the inductances for the other windings should be scaled by the square of their individual turns ratios (with respect to the paralleled winding).<br />
<br />
=== Okay, but calculating winding inductances is tedious.&nbsp; Is there some way to just enter a turns count for all the windings? ===<br />
<br />
Yes, this can be done in any of a number of ways.&nbsp; For example, the values for each of the inductances may be directly parametrized via <font color="green"><b title="Lx node1 node2 {Lm*(Nx/Nm)**2}">curly braces</b></font> to be a function of turns ratios (squared), or a subcircuit that accepts turns as a parameter may be used to encapsulate the windings implementation details.<br />
<br />
* Use parameters to to convert input of winding turns to inductance:<br />
[[File: Parameterized_Transformer.gif|right|307px|(full: 613x236)|Turns are entered as parameters from which the inductance is calculated]]<br />
.param Lp=20m Np=200 Ns=20 ; inputs: primary inductance, primary turns, secondary turns<br />
.param Kn=Lp/Np**2 ; calculated inductance per turn squared<br />
Lp 1 0 {Np**2*Kn} ; primary inductance = 200t**2*Kn<br />
Ls 2 0 {Ns**2*Kn} ; secondary inductance = 20t**2*Kn<br />
Kx Lp Ls 1 ; core coupling factor = 1<br />
<br />
Below is a schematic of a simple LTspice subcircuit that is functionally equivalent to a winding (without a core).&nbsp; Its symbol appears just to the right of the schematic.&nbsp; LTspice's fully extended inductor parasitics are included within this model.&nbsp; Observe that the winding is presented with a voltage equal to the core's volts/turn*primary_turns and that the core is presented with a current equal to the winding's ampere-turns = winding's amps*primary_turns.&nbsp; Also note if the leakage inductance and resistances are zero, the winding is completely floating with respect to the core and that the winding performs a voltage ratio transformation (set by the turns ratio) from DC to light.<br />
<br />
* First, the basic winding: Start (dot), Finish, Core:<br />
[[File: Simple Winding Symbol & Subcircuit.gif|right|480px|(full: 959x270)|This simple subcircuit is equivalent to an inductor or transformer winding]]<br />
.subckt Winding s f c params: n=100 L=1u Rs=1m Rp=100<br />
Lw s 1 {L} Rser={Rs} Rpar={Rp} ; leakage and resistance<br />
Ew 1 f c 0 {n} ; impose core volts/turn*turns onto winding<br />
Fw 0 c Ew {n} ; impose winding amperes*turns onto core<br />
.ends Winding<br />
<br />
<br />
=== DC to DC Transformer (no magnetizing inductance - no energy storage) ===<br />
<br />
The transformer winding subcircuits are DC coupled and, when connected to a "core" (1TΩ in parallel with 1pF) that supports DC without drawing current, they combine to make a transformer that draws no magnetizing current, stores no energy and therefore is immune to errant initial conditions.&nbsp; This may be an advantage when first experimenting with new power circuits.<br />
<br />
For better cosmetics the simple DC core may encapsulated in its own subcircuit and symbol.&nbsp;<br />
<br />
[[File: DC_to_DC_Transformer.gif|right|188px|(full: 376x288)|DC to DC (because of "core") transformer with two windings]]<br />
* Here is a DC "core" that does not draw increasing current with time:<br />
.subckt Core_DC C<br />
Cc C 0 1p Rpar=1T ; dump the "core's" ampere-turns into a small conductance<br />
.ends Core_DC<br />
<br />
[[File: DC_to_DC_Transformer_&_Core.gif|right|186px|(full: 372x266)|DC to DC transformer with DC core symbol for aesthetics]]<br />
* DC-to-DC Transformer Equivalent (Netlist Uprocessed):<br />
Xp P 0 C Winding n=1 L=1u Rs=1m Rp=100 ; primary winding of 1:1 transformer<br />
Xs S 0 C Winding n=1 L=1u Rs=1m Rp=100 ; secondary winding of 1:1 transformer<br />
Xc C CoreDC ; subcircuit consisting of 1TΩ in parallel with 1pF<br />
<br />
=== Linear Transformer (linear magnetizing inductance - potentially unlimited energy storage) ===<br />
<br />
A standard linear transformer may easily be created simply by changing the core to a standard inductor with Rs=0.&nbsp; In this form (with a standard ''linear'' magnetizing inductance "core") the model is mostly useful as a perceptual window into the way coupled inductors work in LTspice since linear transformers are more easily and simply built with standard coupled inductors.&nbsp; Note that the magnetizing inductance "core" is the single summing point for the ''ampere-turns'' from all the windings and is the sole source of ''impressed voltage'' (=L*di/dt) reflected onto all the windings.&nbsp; Although this subcircuit is an unnecessary and overly complex representation for a transformer with a linear core inductance, it will be absolutely required if multiple windings are to be "wrapped" onto LTspice's nonlinear Chan inductance model, so take a moment to read it through (the Chan version will follow shortly).<br />
<br />
<br />
* Parametize and wrap an inductor with a subcircuit:<br />
[[File: Linear_Core.gif|right|212px|(full: 423x165)|A linear core is simply an inductor with Rser=0]]<br />
.subckt Core_Linear C params: L=20m Rp=10k Cp=10p<br />
Lc C 0 {L} Rser=0 Rpar={Rp} Cpar={Cp}<br />
.ends Core_Linear<br />
<br />
[[File: Linear_Transformer.gif|right|187px|(full: 374x270)|Transformer with linear core]]<br />
* Linear Transformer Equivalent (Netlist Unprocessed):<br />
Xp P 0 C Winding n=1 L=1u Rs=1m Rp=100 ; primary winding of 1:1 transformer<br />
Xs S 0 C Winding n=1 L=1u Rs=1m Rp=100 ; secondary winding of 1:1 transformer<br />
Xc C Core_Linear L=20m Rp=10k Cp=10p ; subcircuit consisting of an inductor with Rs=0<br />
<br />
* Linear Transformer Equivalent (Netlist Flattened):<br />
[[File: Linear_Transformer_Full.gif|right|455px|(full: 909x236)|Transformer with linear core]]<br />
Lp Ps 1 1u Rser=1m Rpar=100 ; leakage and resistance<br />
Ep 1 Pf C 0 1 ; impose core volts/turn*turns onto winding<br />
Fp 0 C Ep 1 ; impose winding ampere*turns onto core<br />
Lc C 0 20m Rpar=10k Cpar=10p ; liner inductor core (no magnetic saturation)<br />
+ Rser=0 ; Rser must equal zero<br />
Fs 0 C Es 1 ; impose winding ampere*turns onto core<br />
Es 1 Sf C 0 1 ; impose core volts/turn*turns onto winding<br />
Ls Ss 1 1u Rser=1m Rpar=100 ; leakage and resistance<br />
<br />
=== Chan Transformer (saturating magnetizing inductance with hysteresis - limited energy storage) ===<br />
<br />
Now that the windings are separate from the core, a Chan inductor may simply be substituted for the linear inductor core. Since the inductance of a Chan is not assigned, but is determined by its magnetic material, dimensional properties and winding turns, one must adjust inductance by iteratively adjusting the gap and/or winding turns.<br />
<br />
<br />
* Parametize and wrap a Chan inductor with a subcircuit:<br />
[[File: Chan_Core.gif|right|170px|(full: 340x288)|Physical properties based core with hysteresis and saturation]]<br />
.subckt Core_Chan C params:<br />
+ Bs=0.4 Br=0.1 Hc=20 ; Core default magnetic parameters<br />
+ A=25u1 Lm=19m8 Lg=0m7 ; Core default physical parameters<br />
+ Rp=10k Cp=10p ; Core default parallel loss and capacitance<br />
Lc C 0 Rser=0 n=1 ; force Rser=0 and n=1<br />
+ Bs={Bs} Br={Br} Hc={Hc}<br />
+ A={A} Lm={Lm} Lg={Lg}<br />
+ Rpar={Rp} Cpar={Cp}<br />
.ends Core_Chan<br />
<br />
[[File: Chan_Transformer.gif|right|172px|(full: 344x276)|Physically parameterized transformer with hysteresis and saturation]]<br />
* Chan Transformer Equivalent (Netlist Unprocessed):<br />
Xp P 0 C Winding n=100 L=1u Rs=1m Rp=100 ; primary winding of 1:1 transformer<br />
Xs S 0 C Winding n=100 L=1u Rs=1m Rp=100 ; secondary winding of 1:1 transformer<br />
Xc C Core_Chan ; Chan inductor subcircuit with forced Rs=0 and n=1<br />
+ Bs=0.4 Br=0.1 Hc=20 Br=.10 ; Assigned core magnetic parameters<br />
+ A=25u1 Lm=19m8 Lg=0m7 ; Assigned core physical parameters<br />
+ Rp=10k Cp=10p ; Assigned core parallel loss and capacitance<br />
<br />
=== Now how do I plot a B-H curve to see the Chan model's hysteresis-saturation curves? ===<br />
<br />
Plotting hysteresis-saturation curves of the Chan Transformer in LTspice<br />
<br />
''Under construction.''<br />
<br />
1 ampere∙turns/meter = 4∙π/1000 Oersted(Oe)<br />
<br />
1 volt∙seconds/turn/meter² = 1 Tesla(T) = 10,000 gauss(G)<br />
<br />
<br />
{{#widget:DISQUS<br />
|id=ltwiki<br />
|uniqid={{PAGENAME}}<br />
|url={{fullurl:{{PAGENAME}}}}<br />
}}</div>Analogspicemanhttp://ltwiki.org/index.php?title=File:Chan_Core.gif&diff=2115File:Chan Core.gif2019-11-19T14:46:46Z<p>Analogspiceman: Analogspiceman uploaded a new version of File:Chan Core.gif</p>
<hr />
<div>== Summary ==<br />
Physical properties based core with hysteresis and saturation</div>Analogspicemanhttp://ltwiki.org/index.php?title=File:Linear_Transformer_Full.gif&diff=2114File:Linear Transformer Full.gif2019-11-19T14:42:31Z<p>Analogspiceman: Analogspiceman uploaded a new version of File:Linear Transformer Full.gif</p>
<hr />
<div>== Summary ==<br />
Transformer with linear core</div>Analogspicemanhttp://ltwiki.org/index.php?title=File:Linear_Transformer.gif&diff=2113File:Linear Transformer.gif2019-11-19T14:40:38Z<p>Analogspiceman: Analogspiceman uploaded a new version of File:Linear Transformer.gif</p>
<hr />
<div>== Summary ==<br />
Transformer with linear core</div>Analogspicemanhttp://ltwiki.org/index.php?title=File:Linear_Core.gif&diff=2112File:Linear Core.gif2019-11-19T14:27:20Z<p>Analogspiceman: Analogspiceman uploaded a new version of File:Linear Core.gif</p>
<hr />
<div>== Summary ==<br />
A linear core is simply an inductor with Rser=0</div>Analogspicemanhttp://ltwiki.org/index.php?title=File:DC_to_DC_Transformer_%26_Core.gif&diff=2111File:DC to DC Transformer & Core.gif2019-11-19T14:24:43Z<p>Analogspiceman: Analogspiceman uploaded a new version of File:DC to DC Transformer & Core.gif</p>
<hr />
<div>== Summary ==<br />
DC to DC transformer with DC core symbol for aesthetics.</div>Analogspicemanhttp://ltwiki.org/index.php?title=File:DC_to_DC_Transformer.gif&diff=2110File:DC to DC Transformer.gif2019-11-19T14:21:45Z<p>Analogspiceman: Analogspiceman uploaded a new version of File:DC to DC Transformer.gif</p>
<hr />
<div>== Summary ==<br />
DC to DC (because of "core") transformer with two windings.</div>Analogspicemanhttp://ltwiki.org/index.php?title=File:Simple_Winding_Symbol_%26_Subcircuit.gif&diff=2109File:Simple Winding Symbol & Subcircuit.gif2019-11-19T14:14:49Z<p>Analogspiceman: Analogspiceman uploaded a new version of File:Simple Winding Symbol & Subcircuit.gif</p>
<hr />
<div>== Summary ==<br />
Simple winding: its symbol and subcircuit</div>Analogspicemanhttp://ltwiki.org/index.php?title=File:Parameterized_Transformer.gif&diff=2108File:Parameterized Transformer.gif2019-11-19T14:11:55Z<p>Analogspiceman: Analogspiceman uploaded a new version of File:Parameterized Transformer.gif</p>
<hr />
<div>== Summary ==<br />
Turns are entered as parameters from which the inductance is calculated</div>Analogspicemanhttp://ltwiki.org/index.php?title=File:Loosely_Coupled_Equivalent.gif&diff=2107File:Loosely Coupled Equivalent.gif2019-11-19T08:29:39Z<p>Analogspiceman: Analogspiceman uploaded a new version of File:Loosely Coupled Equivalent.gif</p>
<hr />
<div>== Summary ==<br />
"Winding" inductance is 1H</div>Analogspicemanhttp://ltwiki.org/index.php?title=File:Loosely_Coupled_Transformer.gif&diff=2106File:Loosely Coupled Transformer.gif2019-11-19T08:25:44Z<p>Analogspiceman: Analogspiceman uploaded a new version of File:Loosely Coupled Transformer.gif</p>
<hr />
<div>== Summary ==<br />
Coupling is only K=0.2</div>Analogspicemanhttp://ltwiki.org/index.php?title=File:LTspice_Transformer.gif&diff=2105File:LTspice Transformer.gif2019-11-19T08:15:01Z<p>Analogspiceman: Analogspiceman uploaded a new version of File:LTspice Transformer.gif</p>
<hr />
<div>== Summary ==<br />
Typical LTspice transformer using inductors as windings.</div>Analogspicemanhttp://ltwiki.org/index.php?title=File:Chan_Transformer.gif&diff=2104File:Chan Transformer.gif2019-11-19T07:40:06Z<p>Analogspiceman: Analogspiceman uploaded a new version of File:Chan Transformer.gif</p>
<hr />
<div>== Summary ==<br />
Physically parameterized transformer with hysteresis and saturation</div>Analogspicemanhttp://ltwiki.org/index.php?title=Transformers&diff=2103Transformers2019-11-15T21:57:47Z<p>Analogspiceman: /* Transformers */ reorganized and update for Chan core in process</p>
<hr />
<div>== Transformers ==<br />
<br />
=== Introduction ===<br />
<br />
Do you wish to study the behavior of transformers and inductors and explore their mysteries?&nbsp; LTspice is the ideal learning tool for this purpose. LTspice will faithfully model both ideal and real magnetic devices.&nbsp; However, caution is advised when first experimenting with unfamiliar concepts in inductors and transformers.&nbsp; Be sure to minimize simulation problems by including reasonably realistic parasitic resistances (both series and parallel) directly into each inductor, whether used individually or as part of a transformer.<br />
<br />
A good learning and reference resource is the [http://coefs.uncc.edu/mnoras/files/2013/03/Transformer-and-Inductor-Design-Handbook_Chapter_17.pdf <i>Transformer and Inductor Design Handbook</i> Chapter 17, Winding Capacitance and Leakage Inductance] 4th Edition by Colonel William. T. McLyman.&nbsp; Mike Engelhardt, the author of LTspice, explains how to make transformers in LTspice in a [https://www.analog.com/en/technical-articles/using-transformers-in-ltspice-switcher-cadiii.html 2006 LT-Magazine article].<br />
<br />
Always keep in mind that starting a simulation with a dc voltage bias on an inductor or transformer winding will cause an initial inductor current only limited by the inductor's series resistance (this would be like trying to initialize an ideal capacitor with a current source - no matter how small the source, the dc voltage will increase without bounds - or at least until the capacitor breaks down).&nbsp; In fact, if you are like most engineers, you are much more comfortable with the behavior of capacitors.&nbsp; If so, use this to your advantage by applying duality to think of what to expect when dealing with inductors.<br />
<br />
=== How do I make a transformer in LTspice? === <br />
<br />
[[File:LTspice_Transformer.gif|right|174px|Two lines were used to draw the core]]<br />
<br />
Although it is very possible to make a dedicated subcircuit for a specific transformer, the preferred method of making a generic transformer when drafting a simulation schematic is to simply place a separate inductor for each separate transformer winding and then couple them all together magnetically via a single ''[[Mutual Inductance]] (K) statement'' placed as a [[SPICE Directive]] on the schematic.&nbsp; Note that inductors called out in a [[Mutual Inductance]] statement will be automatically given a phasing dot if one does not already exist.<br />
<br />
K1 L1 L2 L3 1 ; causes phasing dots to automatically appear on L1-L3 inductor symbols<br />
<br />
When creating a new transformer this way, especially for use in a switched-mode power circuit, it is generally best to first specify the mutual coupling coefficient to be exactly unity.&nbsp; By starting with unity coupling there will be no leakage inductance in any winding and this will minimize the likelihood of the windings ringing at extremely high frequencies (which can slow the simulation to a crawl at each switching edge).&nbsp; However, be aware that a mutual inductance value of plus (or minus) unity ''may'' lead to simulation difficulties if ''Skip-the-initial-operating-point-solution'' (UIC) is specified for the .tran command.&nbsp; Prevent this by specifying a realistic resistance for each inductor "winding" (ctrl-right-mouse-click).&nbsp; Note that when coupled inductors are used as transformer windings, individual winding inductances rather than turns ratios must be specified (''inductance ratios should be set to be proportional to <u>the '''square''' of the turns ratios''</u>).<br />
<br />
=== I've created an ideal transformer so it should work at all frequencies, even including DC, right? ===<br />
<br />
No, but lots of users completely misunderstand or overlook this when setting up their simulation.&nbsp; This common mistake can lead to a lot of needless doubt following unexpected and puzzling simulation results produced by LTspice when presented with an ideal transformer that is inadvertently initialized with a large amount of dc voltage applied to its windings.&nbsp; This is probably the most common self-inflicted pitfall that trips up users improperly specifying ac voltage sources.<br />
<br />
When LTspice calculates initial conditions for voltage sources, it uses the values at time = 0.&nbsp; Depending on the starting phase angle and delay specified for a sine source, this can be as much as the voltage at the peak of the sine wave.&nbsp; When the simulator attempts to find the circuit's initial solution, this is the equivalent to hooking the transformer up to a large dc voltage source.&nbsp; Current will only be limited by winding resistance (which, in the ideal case, may be zero).&nbsp; Note that a real transformer will saturate at a relatively low current and would normally not store much energy (it would also probably burn up with so much dc applied), but an ideal transformer with an ideal magnetizing inductance may store a physically impossible amount of simulated "virtual" energy.<br />
<br />
Without realizing it, many users may instruct LTspice to initialize the transformer magnetizing inductance with huge starting currents.&nbsp; Since they have used an ideal inductance that does not saturate (like a real transformer would), it starts out with dc current that may take many hundreds of line (or switching) cycles to die away.&nbsp; This completely unrealistic energy source then may dominate the simulation, causing strange and unexpectedly puzzling behavior.&nbsp; In such cases, LTspice is just innocently following the instructions given it and accurately computing the unrealistic results (garbage in, garbage out).<br />
<br />
To avoid this bogus and unwanted result, you must either arrange '''''the ac source to be zero at time zero''''' or '''''instruct LTspice not to use a dc solution for the starting point (UIC).'''''<br />
<br />
=== I want to model leakage inductance - how should I do that? ===<br />
<br />
The most flexible method is to keep the windings' mutual inductance statement at unity and add a small discrete leakage inductance in series with each winding.&nbsp; This is the most straightforward way to model transformers with asymmetrical leakage inductances.&nbsp; However, if your transformer is electrically symmetrical, it may be more convenient to simply set the mutual inductance to a value less than one.&nbsp; For each winding the resulting leakage inductance will be (1-K) times that winding's inductance.&nbsp; Also, each winding's coupled inductance also will decrease to K times that winding's inductance, but for typical values of K (>>0.9) this effect will be very small.&nbsp; Note that physical transformer leakage inductance measured in the laboratory typically is close to the sum of the leakage inductance of two windings in series combination (with coupled inductance and perhaps several windings partially in parallel).<br />
<br />
'''This is how LTspice "sees" coupled inductors:'''<br />
<br />
For n inductors coupled together with a K statement, each inductor L1 through Ln is divided into two parts, a completely non-coupled "leakage" inductance equal to (1-K)*Lx (where Lx is the particular inductor in question) and a completely coupled "mutual" inductance equal to K*Lx.&nbsp; Voltage and current ratios of the coupled parts are related by the ratio of the square root of the the inductances L1 through Ln (this is the apparent "turns ratio").<br />
<br />
* For example, given two inductors coupled by a K statement:<br />
[[File:Loosely_Coupled_Transformer.gif|right|153px|Coupling is only K=0.2]]<br />
L1 1 0 1H<br />
L2 2 0 1H<br />
Km L1 L2 0.2<br />
<br />
[[File:Loosely_Coupled_Equivalent.gif|right|182px|"Winding" inductance is 1H]]<br />
<br />
* In LTspice, this is the same as:<br />
L1 1 m 0.8H<br />
Lm m 0 0.2H<br />
L2 2 m 0.8H<br />
<br />
Other engineering conventions regarding the definition of K, coupling and formula for leakage inductance are irrelevant to LTspice.&nbsp; Other formula for leakage inductance are intended to find total leakage inductance from an input winding through to an output winding(s) rather than the partial leakage inductance for each individual winding.<br />
<br />
=== How about transformer saturation effects?&nbsp; Can LTspice model those? ===<br />
<br />
Yes, LTspice comes with a non-linear hysteretic core model built in!&nbsp; This is the 1991 model by John Chan et al.&nbsp; Compared to older core models, [[the Chan model]] is particularly robust, computationally efficient and compact, requiring only three parameters to define most any commonly encountered magnetic hysteresis loop.&nbsp; (LTspice also allows building an arbitrary inductance based on self flux and/or any valid function of node voltages and branch currents.&nbsp; [[The Arbitrary Inductor model|The arbitrary inductor model]] can be very efficiently used to create saturation without hysteresis.) <br />
<br />
Once the core material's generic magnetic properties are set, establishing the circuit-level non-linear inductance requires specifying three more parameters to set the geometry of the specific core and specifying one additional parameter for the core winding turn-count.&nbsp; The Chan inductor <font color="green" title="(has been mentioned as a possibility for a future release)">does not currently</font> directly support [[Mutual Inductance]], so unless only a single-winding inductor is being modeled, multiple windings must be added via additional circuitry.&nbsp; The simplest way to do this is to construct an ideal, unity coupled transformer with as many windings as required and then put the Chan inductor directly in parallel with any one of the windings (taking care to set the turns to match that particular winding).&nbsp; Since the magnetic effects (including non-saturated inductance) are already modeled by the Chan inductor, the inductance of the transformer's parallel winding must be enough larger (>>10) not to significantly load the Chan inductance.&nbsp; As before, the inductances for the other windings should be scaled by the square of their individual turns ratios (with respect to the paralleled winding).<br />
<br />
=== Okay, but calculating winding inductances is tedious.&nbsp; Is there some way to just enter a turns count for all the windings? ===<br />
<br />
Yes, this can be done in any of a number of ways.&nbsp; For example, the values for each of the inductances may be directly parametrized via <font color="green"><b title="Lx node1 node2 {Lm*(Nx/Nm)**2}">curly braces</b></font> to be a function of turns ratios (squared), or a subcircuit that accepts turns as a parameter may be used to encapsulate the windings implementation details.<br />
<br />
* Use parameters to to convert input of winding turns to inductance:<br />
[[File: Parameterized_Transformer.gif|right|304px|Turns are entered as parameters from which the inductance is calculated]]<br />
.param Lp=20m Np=200 Ns=20 ; inputs: primary inductance, primary turns, secondary turns<br />
.param Kn=Lp/Np**2 ; calculated inductance per turn squared<br />
Lp 1 0 {Np**2*Kn} ; primary inductance = 200t**2*Kn<br />
Ls 2 0 {Ns**2*Kn} ; secondary inductance = 20t**2*Kn<br />
Kx Lp Ls 1 ; core coupling factor = 1<br />
<br />
Below is a schematic of a simple LTspice subcircuit that is functionally equivalent to a winding (without a core).&nbsp; Its symbol appears just to the right of the schematic.&nbsp; LTspice's fully extended inductor parasitics are included within this model.&nbsp; Observe that the winding is presented with a voltage equal to the core's volts/turn*primary_turns and that the core is presented with a current equal to the winding's ampere-turns = winding's amps*primary_turns.&nbsp; Also note if the leakage inductance and resistances are zero, the winding is completely floating with respect to the core and that the winding performs a voltage ratio transformation (set by the turns ratio) from DC to light.<br />
<br />
* First, the basic winding: Start (dot), Finish, Core:<br />
[[File: Simple Winding Symbol & Subcircuit.gif|right|479px|This simple subcircuit is equivalent to an inductor or transformer winding]]<br />
.subckt Winding s f c params: n=100 L=1u Rs=1m Rp=100<br />
Lw s 1 {L} Rser={Rs} Rpar={Rp} ; leakage and resistance<br />
Ew 1 f c 0 {n} ; impose core volts/turn*turns onto winding<br />
Fw 0 c Ew {n} ; impose winding amperes*turns onto core<br />
.ends Winding<br />
<br />
<br />
=== DC to DC Transformer (no magnetizing inductance - no energy storage) ===<br />
<br />
The transformer winding subcircuits are DC coupled and, when connected to a "core" (1TΩ in parallel with 1pF) that supports DC without drawing current, they combine to make a transformer that draws no magnetizing current, stores no energy and therefore is immune to errant initial conditions.&nbsp; This may be an advantage when first experimenting with new power circuits.<br />
<br />
For better cosmetics the simple DC core may encapsulated in its own subcircuit and symbol.&nbsp;<br />
<br />
[[File: DC_to_DC_Transformer.gif|right|190px|DC to DC (because of "core") transformer with two windings]]<br />
* Here is a DC "core" that does not draw increasing current with time:<br />
.subckt Core_DC C<br />
Cc C 0 1p Rpar=1T ; dump the "core's" ampere-turns into a small conductance<br />
.ends Core_DC<br />
<br />
[[File: DC_to_DC_Transformer_&_Core.gif|right|189px|DC to DC transformer with DC core symbol for aesthetics]]<br />
* DC-to-DC Transformer Equivalent (Netlist Uprocessed):<br />
Xp P 0 C Winding n=1 L=1u Rs=1m Rp=100 ; primary winding of 1:1 transformer<br />
Xs S 0 C Winding n=1 L=1u Rs=1m Rp=100 ; secondary winding of 1:1 transformer<br />
Xc C CoreDC ; subcircuit consisting of 1TΩ in parallel with 1pF<br />
<br />
=== Linear Transformer (linear magnetizing inductance - potentially unlimited energy storage) ===<br />
<br />
A standard linear transformer may easily be created simply by changing the core to a standard inductor with Rs=0.&nbsp; In this form (with a standard ''linear'' magnetizing inductance "core") the model is mostly useful as a perceptual window into the way coupled inductors work in LTspice since linear transformers are more easily and simply built with standard coupled inductors.&nbsp; Note that the magnetizing inductance "core" is the single summing point for the ''ampere-turns'' from all the windings and is the sole source of ''impressed voltage'' (=L*di/dt) reflected onto all the windings.&nbsp; Although this subcircuit is an unnecessary and overly complex representation for a transformer with a linear core inductance, it will be absolutely required if multiple windings are to be "wrapped" onto LTspice's nonlinear Chan inductance model, so take a moment to read it through (the Chan version will follow shortly).<br />
<br />
<br />
* Parametize and wrap an inductor with a subcircuit:<br />
[[File: Linear_Core.gif|right|191px|A linear core is simply an inductor with Rser=0]]<br />
.subckt Core_Linear C params: L=20m Rp=10k Cp=10p<br />
Lc C 0 {L} Rser=0 Rpar={Rp} Cpar={Cp}<br />
.ends Core_Linear<br />
<br />
[[File: Linear_Transformer.gif|right|176px|Transformer with linear core]]<br />
* Linear Transformer Equivalent (Netlist Unprocessed):<br />
Xp P 0 C Winding n=1 L=1u Rs=1m Rp=100 ; primary winding of 1:1 transformer<br />
Xs S 0 C Winding n=1 L=1u Rs=1m Rp=100 ; secondary winding of 1:1 transformer<br />
Xc C Core_Linear L=20m Rp=10k Cp=10p ; subcircuit consisting of an inductor with Rs=0<br />
<br />
* Linear Transformer Equivalent (Netlist Flattened):<br />
[[File: Linear_Transformer_Full.gif|right|438px|Transformer with linear core]]<br />
Lp Ps 1 1u Rser=1m Rpar=100 ; leakage and resistance<br />
Ep 1 Pf C 0 1 ; impose core volts/turn*turns onto winding<br />
Fp 0 C Ep 1 ; impose winding ampere*turns onto core<br />
Lc C 0 20m Rpar=10k Cpar=10p ; liner inductor core (no magnetic saturation)<br />
+ Rser=0 ; Rser must equal zero<br />
Fs 0 C Es 1 ; impose winding ampere*turns onto core<br />
Es 1 Sf C 0 1 ; impose core volts/turn*turns onto winding<br />
Ls Ss 1 1u Rser=1m Rpar=100 ; leakage and resistance<br />
<br />
=== Chan Transformer (saturating magnetizing inductance with hysteresis - limited energy storage) ===<br />
<br />
Now that the windings are separate from the core, a Chan inductor may simply be substituted for the linear inductor core. Since the inductance of a Chan is not assigned, but is determined by its magnetic material, dimensional properties and winding turns, one must adjust inductance by iteratively adjusting the gap and/or winding turns.<br />
<br />
<br />
* Parametize and wrap a Chan inductor with a subcircuit:<br />
[[File: Chan_Core.gif|right|167px|Physical properties based core with hysteresis and saturation]]<br />
.subckt Core_Chan C params:<br />
+ Bs=0.4 Br=0.1 Hc=20 ; Core default magnetic parameters<br />
+ A=25u1 Lm=19m8 Lg=0m7 ; Core default physical parameters<br />
+ Rp=10k Cp=10p ; Core default parallel loss and capacitance<br />
Lc C 0 Rser=0 n=1 ; force Rser=0 and n=1<br />
+ Bs={Bs} Br={Br} Hc={Hc}<br />
+ A={A} Lm={Lm} Lg={Lg}<br />
+ Rpar={Rp} Cpar={Cp}<br />
.ends Core_Chan<br />
<br />
[[File: Chan_Transformer.gif|right|167px|Physically parameterized transformer with hysteresis and saturation]]<br />
* Chan Transformer Equivalent (Netlist Unprocessed):<br />
Xp P 0 C Winding n=100 L=1u Rs=1m Rp=100 ; primary winding of 1:1 transformer<br />
Xs S 0 C Winding n=100 L=1u Rs=1m Rp=100 ; secondary winding of 1:1 transformer<br />
Xc C Core_Chan ; Chan inductor subcircuit with forced Rs=0 and n=1<br />
+ Bs=0.4 Br=0.1 Hc=20 Br=.10 ; Assigned core magnetic parameters<br />
+ A=25u1 Lm=19m8 Lg=0m7 ; Assigned core physical parameters<br />
+ Rp=10k Cp=10p ; Assigned core parallel loss and capacitance<br />
<br />
=== Now how do I plot a B-H curve to see the Chan model's hysteresis-saturation curves? ===<br />
<br />
Plotting hysteresis-saturation curves of the Chan Transformer in LTspice<br />
<br />
''Under construction.''<br />
<br />
1 ampere∙turns/meter = 4∙π/1000 Oersted(Oe)<br />
<br />
1 volt∙seconds/turn/meter² = 1 Tesla(T) = 10,000 gauss(G)<br />
<br />
<br />
{{#widget:DISQUS<br />
|id=ltwiki<br />
|uniqid={{PAGENAME}}<br />
|url={{fullurl:{{PAGENAME}}}}<br />
}}</div>Analogspicemanhttp://ltwiki.org/index.php?title=Transformers&diff=2102Transformers2019-11-15T21:30:21Z<p>Analogspiceman: /* Chan Transformer (saturating magnetizing inductance with hysteresis - limited energy storage) */</p>
<hr />
<div>== Transformers ==<br />
<br />
=== Introduction ===<br />
<br />
Do you wish to study the behavior of transformers and inductors and explore their mysteries?&nbsp; LTspice is the ideal learning tool for this purpose. LTspice will faithfully model both ideal and real magnetic devices.&nbsp; However, caution is advised when first experimenting with unfamiliar concepts in inductors and transformers.&nbsp; Be sure to minimize simulation problems by including reasonably realistic parasitic resistances (both series and parallel) directly into each inductor, whether used individually or as part of a transformer.<br />
<br />
A good learning and reference resource is the [http://coefs.uncc.edu/mnoras/files/2013/03/Transformer-and-Inductor-Design-Handbook_Chapter_17.pdf <i>Transformer and Inductor Design Handbook</i> Chapter 17, Winding Capacitance and Leakage Inductance] 4th Edition by Colonel William. T. McLyman.&nbsp; Mike Engelhardt, the author of LTspice, explains how to make transformers in LTspice in a [https://www.analog.com/en/technical-articles/using-transformers-in-ltspice-switcher-cadiii.html 2006 LT-Magazine article].<br />
<br />
Always keep in mind that starting a simulation with a dc voltage bias on an inductor or transformer winding will cause an initial inductor current only limited by the inductor's series resistance (this would be like trying to initialize an ideal capacitor with a current source - no matter how small the source, the dc voltage will increase without bounds - or at least until the capacitor breaks down).&nbsp; In fact, if you are like most engineers, you are much more comfortable with the behavior of capacitors.&nbsp; If so, use this to your advantage by applying duality to think of what to expect when dealing with inductors.<br />
<br />
=== How do I make a transformer in LTspice? === <br />
<br />
[[File:LTspice_Transformer.gif|right|174px|Two lines were used to draw the core]]<br />
<br />
Although it is very possible to make a dedicated subcircuit for a specific transformer, the preferred method of making a generic transformer when drafting a simulation schematic is to simply place a separate inductor for each separate transformer winding and then couple them all together magnetically via a single ''[[Mutual Inductance]] (K) statement'' placed as a [[SPICE Directive]] on the schematic.&nbsp; Note that inductors called out in a [[Mutual Inductance]] statement will be automatically given a phasing dot if one does not already exist.<br />
<br />
K1 L1 L2 L3 1 ; causes phasing dots to automatically appear on L1-L3 inductor symbols<br />
<br />
When creating a new transformer this way, especially for use in a switched-mode power circuit, it is generally best to first specify the mutual coupling coefficient to be exactly unity.&nbsp; By starting with unity coupling there will be no leakage inductance in any winding and this will minimize the likelihood of the windings ringing at extremely high frequencies (which can slow the simulation to a crawl at each switching edge).&nbsp; However, be aware that a mutual inductance value of plus (or minus) unity ''may'' lead to simulation difficulties if ''Skip-the-initial-operating-point-solution'' (UIC) is specified for the .tran command.&nbsp; Prevent this by specifying a realistic resistance for each inductor "winding" (ctrl-right-mouse-click).&nbsp; Note that when coupled inductors are used as transformer windings, individual winding inductances rather than turns ratios must be specified (''inductance ratios should be set to be proportional to <u>the '''square''' of the turns ratios''</u>).<br />
<br />
=== I've created an ideal transformer so it should work at all frequencies, even including DC, right? ===<br />
<br />
No, but lots of users completely misunderstand or overlook this when setting up their simulation.&nbsp; This common mistake can lead to a lot of needless doubt following unexpected and puzzling simulation results produced by LTspice when presented with an ideal transformer that is inadvertently initialized with a large amount of dc voltage applied to its windings.&nbsp; This is probably the most common self-inflicted pitfall that trips up users improperly specifying ac voltage sources.<br />
<br />
When LTspice calculates initial conditions for voltage sources, it uses the values at time = 0.&nbsp; Depending on the starting phase angle and delay specified for a sine source, this can be as much as the voltage at the peak of the sine wave.&nbsp; When the simulator attempts to find the circuit's initial solution, this is the equivalent to hooking the transformer up to a large dc voltage source.&nbsp; Current will only be limited by winding resistance (which, in the ideal case, may be zero).&nbsp; Note that a real transformer will saturate at a relatively low current and would normally not store much energy (it would also probably burn up with so much dc applied), but an ideal transformer with an ideal magnetizing inductance may store a physically impossible amount of simulated "virtual" energy.<br />
<br />
Without realizing it, many users may instruct LTspice to initialize the transformer magnetizing inductance with huge starting currents.&nbsp; Since they have used an ideal inductance that does not saturate (like a real transformer would), it starts out with dc current that may take many hundreds of line (or switching) cycles to die away.&nbsp; This completely unrealistic energy source then may dominate the simulation, causing strange and unexpectedly puzzling behavior.&nbsp; In such cases, LTspice is just innocently following the instructions given it and accurately computing the unrealistic results (garbage in, garbage out).<br />
<br />
To avoid this bogus and unwanted result, you must either arrange '''''the ac source to be zero at time zero''''' or '''''instruct LTspice not to use a dc solution for the starting point (UIC).'''''<br />
<br />
=== I want to model leakage inductance - how should I do that? ===<br />
<br />
The most flexible method is to keep the windings' mutual inductance statement at unity and add a small discrete leakage inductance in series with each winding.&nbsp; This is the most straightforward way to model transformers with asymmetrical leakage inductances.&nbsp; However, if your transformer is electrically symmetrical, it may be more convenient to simply set the mutual inductance to a value less than one.&nbsp; For each winding the resulting leakage inductance will be (1-K) times that winding's inductance.&nbsp; Also, each winding's coupled inductance also will decrease to K times that winding's inductance, but for typical values of K (>>0.9) this effect will be very small.&nbsp; Note that physical transformer leakage inductance measured in the laboratory typically is close to the sum of the leakage inductance of two windings in series combination (with coupled inductance and perhaps several windings partially in parallel).<br />
<br />
'''This is how LTspice "sees" coupled inductors:'''<br />
<br />
For n inductors coupled together with a K statement, each inductor L1 through Ln is divided into two parts, a completely non-coupled "leakage" inductance equal to (1-K)*Lx (where Lx is the particular inductor in question) and a completely coupled "mutual" inductance equal to K*Lx.&nbsp; Voltage and current ratios of the coupled parts are related by the ratio of the square root of the the inductances L1 through Ln (this is the apparent "turns ratio").<br />
<br />
* For example, given two inductors coupled by a K statement:<br />
[[File:Loosely_Coupled_Transformer.gif|right|153px|Coupling is only K=0.2]]<br />
L1 1 0 1H<br />
L2 2 0 1H<br />
Km L1 L2 0.2<br />
<br />
[[File:Loosely_Coupled_Equivalent.gif|right|182px|"Winding" inductance is 1H]]<br />
<br />
* In LTspice, this is the same as:<br />
L1 1 m 0.8H<br />
Lm m 0 0.2H<br />
L2 2 m 0.8H<br />
<br />
Other engineering conventions regarding the definition of K, coupling and formula for leakage inductance are irrelevant to LTspice.&nbsp; Other formula for leakage inductance are intended to find total leakage inductance from an input winding through to an output winding(s) rather than the partial leakage inductance for each individual winding.<br />
<br />
=== How about transformer saturation effects?&nbsp; Can LTspice model those? ===<br />
<br />
Yes, LTspice comes with a non-linear hysteretic core model built in!&nbsp; This is the 1991 model by John Chan et al.&nbsp; Compared to older core models, [[the Chan model]] is particularly robust, computationally efficient and compact, requiring only three parameters to define most any commonly encountered magnetic hysteresis loop.&nbsp; (LTspice also allows building an arbitrary inductance based on self flux and/or any valid function of node voltages and branch currents.&nbsp; [[The Arbitrary Inductor model|The arbitrary inductor model]] can be very efficiently used to create saturation without hysteresis.) <br />
<br />
Once the core material's generic magnetic properties are set, establishing the circuit-level non-linear inductance requires specifying three more parameters to set the geometry of the specific core and specifying one additional parameter for the core winding turn-count.&nbsp; The Chan inductor <font color="green" title="(has been mentioned as a possibility for a future release)">does not currently</font> directly support [[Mutual Inductance]], so unless only a single-winding inductor is being modeled, multiple windings must be added via additional circuitry.&nbsp; The simplest way to do this is to construct an ideal, unity coupled transformer with as many windings as required and then put the Chan inductor directly in parallel with any one of the windings (taking care to set the turns to match that particular winding).&nbsp; Since the magnetic effects (including non-saturated inductance) are already modeled by the Chan inductor, the inductance of the transformer's parallel winding must be enough larger (>>10) not to significantly load the Chan inductance.&nbsp; As before, the inductances for the other windings should be scaled by the square of their individual turns ratios (with respect to the paralleled winding).<br />
<br />
=== Okay, but calculating winding inductances is tedious.&nbsp; Is there some way to just enter a turns count for all the windings? ===<br />
<br />
Yes, this can be done in any of a number of ways.&nbsp; For example, the values for each of the inductances may be directly parametrized via <font color="green"><b title="Lx node1 node2 {Lm*(Nx/Nm)**2}">curly braces</b></font> to be a function of turns ratios (squared), or a subcircuit that accepts turns as a parameter may be used to encapsulate the windings implementation details.<br />
<br />
* Use parameters to to convert input of winding turns to inductance:<br />
[[File: Parameterized_Transformer.gif|right|304px|Turns are entered as parameters from which the inductance is calculated]]<br />
.param Lp=20m Np=200 Ns=20 ; inputs: primary inductance, primary turns, secondary turns<br />
.param Kn=Lp/Np**2 ; calculated inductance per turn squared<br />
Lp 1 0 {Np**2*Kn} ; primary inductance = 200t**2*Kn<br />
Ls 2 0 {Ns**2*Kn} ; secondary inductance = 20t**2*Kn<br />
Kx Lp Ls 1 ; core coupling factor = 1<br />
<br />
Below is a schematic of a simple LTspice subcircuit that is functionally equivalent to a winding (without a core).&nbsp; Its symbol appears just to the right of the schematic.&nbsp; LTspice's fully extended inductor parasitics are included within this model.&nbsp; Observe that the winding is presented with a voltage equal to the core's volts/turn*primary_turns and that the core is presented with a current equal to the winding's ampere-turns = winding's amps*primary_turns.&nbsp; Also note if the leakage inductance and resistances are zero, the winding is completely floating with respect to the core and that the winding performs a voltage ratio transformation (set by the turns ratio) from DC to light.<br />
<br />
* First, the basic winding: Start (dot), Finish, Core:<br />
[[File: Simple Winding Symbol & Subcircuit.gif|right|479px|This simple subcircuit is equivalent to an inductor or transformer winding]]<br />
.subckt Winding s f c params: n=100 L=1u Rs=1m Rp=100<br />
Lw s 1 {L} Rser={Rs} Rpar={Rp} ; leakage and resistance<br />
Ew 1 f c 0 {n} ; impose core volts/turn*turns onto winding<br />
Fw 0 c Ew {n} ; impose winding amperes*turns onto core<br />
.ends Winding<br />
<br />
<br />
==== DC to DC Transformer (no magnetizing inductance - no energy storage) ====<br />
<br />
The transformer winding subcircuits are DC coupled and, when connected to a "core" (1TΩ in parallel with 1pF) that supports DC without drawing current, they combine to make a transformer that draws no magnetizing current, stores no energy and therefore is immune to errant initial conditions.&nbsp; This may be an advantage when first experimenting with new power circuits.<br />
<br />
For better cosmetics the simple DC core may encapsulated in its own subcircuit and symbol.&nbsp;<br />
<br />
[[File: DC_to_DC_Transformer.gif|right|190px|DC to DC (because of "core") transformer with two windings]]<br />
* Here is a DC "core" that does not draw increasing current with time:<br />
.subckt Core_DC C<br />
Cc C 0 1p Rpar=1T ; dump the "core's" ampere-turns into a small conductance<br />
.ends Core_DC<br />
<br />
[[File: DC_to_DC_Transformer_&_Core.gif|right|189px|DC to DC transformer with DC core symbol for aesthetics]]<br />
* DC-to-DC Transformer Equivalent (Netlist Uprocessed):<br />
Xp P 0 C Winding n=1 L=1u Rs=1m Rp=100 ; primary winding of 1:1 transformer<br />
Xs S 0 C Winding n=1 L=1u Rs=1m Rp=100 ; secondary winding of 1:1 transformer<br />
Xc C CoreDC ; subcircuit consisting of 1TΩ in parallel with 1pF<br />
<br />
==== Linear Transformer (linear magnetizing inductance - potentially unlimited energy storage) ====<br />
<br />
A standard linear transformer may easily be created simply by changing the core to a standard inductor with Rs=0.&nbsp; In this form (with a standard ''linear'' magnetizing inductance "core") the model is mostly useful as a perceptual window into the way coupled inductors work in LTspice since linear transformers are more easily and simply built with standard coupled inductors.&nbsp; Note that the magnetizing inductance "core" is the single summing point for the ''ampere-turns'' from all the windings and is the sole source of ''impressed voltage'' (=L*di/dt) reflected onto all the windings.&nbsp; Although this subcircuit is an unnecessary and overly complex representation for a transformer with a linear core inductance, it will be absolutely required if multiple windings are to be "wrapped" onto LTspice's nonlinear Chan inductance model, so take a moment to read it through (the Chan version will follow shortly).<br />
<br />
<br />
* Parametize and wrap an inductor with a subcircuit:<br />
[[File: Linear_Core.gif|right|191px|A linear core is simply an inductor with Rser=0]]<br />
.subckt Core_Linear C params: L=20m Rp=10k Cp=10p<br />
Lc C 0 {L} Rser=0 Rpar={Rp} Cpar={Cp}<br />
.ends Core_Linear<br />
<br />
[[File: Linear_Transformer.gif|right|176px|Transformer with linear core]]<br />
* Linear Transformer Equivalent (Netlist Unprocessed):<br />
Xp P 0 C Winding n=1 L=1u Rs=1m Rp=100 ; primary winding of 1:1 transformer<br />
Xs S 0 C Winding n=1 L=1u Rs=1m Rp=100 ; secondary winding of 1:1 transformer<br />
Xc C Core_Linear L=20m Rp=10k Cp=10p ; subcircuit consisting of an inductor with Rs=0<br />
<br />
* Linear Transformer Equivalent (Netlist Flattened):<br />
[[File: Linear_Transformer_Full.gif|right|438px|Transformer with linear core]]<br />
Lp Ps 1 1u Rser=1m Rpar=100 ; leakage and resistance<br />
Ep 1 Pf C 0 1 ; impose core volts/turn*turns onto winding<br />
Fp 0 C Ep 1 ; impose winding ampere*turns onto core<br />
Lc C 0 20m Rpar=10k Cpar=10p ; liner inductor core (no magnetic saturation)<br />
+ Rser=0 ; Rser must equal zero<br />
Fs 0 C Es 1 ; impose winding ampere*turns onto core<br />
Es 1 Sf C 0 1 ; impose core volts/turn*turns onto winding<br />
Ls Ss 1 1u Rser=1m Rpar=100 ; leakage and resistance<br />
<br />
==== Chan Transformer (saturating magnetizing inductance with hysteresis - limited energy storage) ====<br />
<br />
Now that the windings are separate from the core, a Chan inductor may simply be substituted for the linear inductor core. Since the inductance of a Chan is not assigned, but is determined by its magnetic material, dimensional properties and winding turns, one must adjust inductance by iteratively adjusting the gap and/or winding turns.<br />
<br />
<br />
* Parametize and wrap a Chan inductor with a subcircuit:<br />
[[File: Chan_Core.gif|right|167px|Physical properties based core with hysteresis and saturation]]<br />
.subckt Core_Chan C params:<br />
+ Bs=0.4 Br=0.1 Hc=20 ; Core default magnetic parameters<br />
+ A=25u1 Lm=19m8 Lg=0m7 ; Core default physical parameters<br />
+ Rp=10k Cp=10p ; Core default parallel loss and capacitance<br />
Lc C 0 Rser=0 n=1 ; force Rser=0 and n=1<br />
+ Bs={Bs} Br={Br} Hc={Hc}<br />
+ A={A} Lm={Lm} Lg={Lg}<br />
+ Rpar={Rp} Cpar={Cp}<br />
.ends Core_Chan<br />
<br />
[[File: Chan_Transformer.gif|right|167px|Physically parameterized transformer with hysteresis and saturation]]<br />
* Chan Transformer Equivalent (Netlist Unprocessed):<br />
Xp P 0 C Winding n=100 L=1u Rs=1m Rp=100 ; primary winding of 1:1 transformer<br />
Xs S 0 C Winding n=100 L=1u Rs=1m Rp=100 ; secondary winding of 1:1 transformer<br />
Xc C Core_Chan ; Chan inductor subcircuit with forced Rs=0 and n=1<br />
+ Bs=0.4 Br=0.1 Hc=20 Br=.10 ; Assigned core magnetic parameters<br />
+ A=25u1 Lm=19m8 Lg=0m7 ; Assigned core physical parameters<br />
+ Rp=10k Cp=10p ; Assigned core parallel loss and capacitance<br />
<br />
==== Now how do I plot a B-H curve to see the Chan model's hysteresis-saturation curves? ====<br />
<br />
Plotting hysteresis-saturation curves of the Chan Transformer in LTspice<br />
<br />
''Under construction.''<br />
<br />
1 ampere∙turns/meter = 4∙π/1000 Oersted(Oe)<br />
<br />
1 volt∙seconds/turn/meter² = 1 Tesla(T) = 10,000 gauss(G)<br />
<br />
<br />
{{#widget:DISQUS<br />
|id=ltwiki<br />
|uniqid={{PAGENAME}}<br />
|url={{fullurl:{{PAGENAME}}}}<br />
}}</div>Analogspicemanhttp://ltwiki.org/index.php?title=Transformers&diff=2101Transformers2019-11-15T12:21:32Z<p>Analogspiceman: /* Chan Transformer (saturating magnetizing inductance with hysteresis - limited energy storage) */</p>
<hr />
<div>== Transformers ==<br />
<br />
=== Introduction ===<br />
<br />
Do you wish to study the behavior of transformers and inductors and explore their mysteries?&nbsp; LTspice is the ideal learning tool for this purpose. LTspice will faithfully model both ideal and real magnetic devices.&nbsp; However, caution is advised when first experimenting with unfamiliar concepts in inductors and transformers.&nbsp; Be sure to minimize simulation problems by including reasonably realistic parasitic resistances (both series and parallel) directly into each inductor, whether used individually or as part of a transformer.<br />
<br />
A good learning and reference resource is the [http://coefs.uncc.edu/mnoras/files/2013/03/Transformer-and-Inductor-Design-Handbook_Chapter_17.pdf <i>Transformer and Inductor Design Handbook</i> Chapter 17, Winding Capacitance and Leakage Inductance] 4th Edition by Colonel William. T. McLyman.&nbsp; Mike Engelhardt, the author of LTspice, explains how to make transformers in LTspice in a [https://www.analog.com/en/technical-articles/using-transformers-in-ltspice-switcher-cadiii.html 2006 LT-Magazine article].<br />
<br />
Always keep in mind that starting a simulation with a dc voltage bias on an inductor or transformer winding will cause an initial inductor current only limited by the inductor's series resistance (this would be like trying to initialize an ideal capacitor with a current source - no matter how small the source, the dc voltage will increase without bounds - or at least until the capacitor breaks down).&nbsp; In fact, if you are like most engineers, you are much more comfortable with the behavior of capacitors.&nbsp; If so, use this to your advantage by applying duality to think of what to expect when dealing with inductors.<br />
<br />
=== How do I make a transformer in LTspice? === <br />
<br />
[[File:LTspice_Transformer.gif|right|174px|Two lines were used to draw the core]]<br />
<br />
Although it is very possible to make a dedicated subcircuit for a specific transformer, the preferred method of making a generic transformer when drafting a simulation schematic is to simply place a separate inductor for each separate transformer winding and then couple them all together magnetically via a single ''[[Mutual Inductance]] (K) statement'' placed as a [[SPICE Directive]] on the schematic.&nbsp; Note that inductors called out in a [[Mutual Inductance]] statement will be automatically given a phasing dot if one does not already exist.<br />
<br />
K1 L1 L2 L3 1 ; causes phasing dots to automatically appear on L1-L3 inductor symbols<br />
<br />
When creating a new transformer this way, especially for use in a switched-mode power circuit, it is generally best to first specify the mutual coupling coefficient to be exactly unity.&nbsp; By starting with unity coupling there will be no leakage inductance in any winding and this will minimize the likelihood of the windings ringing at extremely high frequencies (which can slow the simulation to a crawl at each switching edge).&nbsp; However, be aware that a mutual inductance value of plus (or minus) unity ''may'' lead to simulation difficulties if ''Skip-the-initial-operating-point-solution'' (UIC) is specified for the .tran command.&nbsp; Prevent this by specifying a realistic resistance for each inductor "winding" (ctrl-right-mouse-click).&nbsp; Note that when coupled inductors are used as transformer windings, individual winding inductances rather than turns ratios must be specified (''inductance ratios should be set to be proportional to <u>the '''square''' of the turns ratios''</u>).<br />
<br />
=== I've created an ideal transformer so it should work at all frequencies, even including DC, right? ===<br />
<br />
No, but lots of users completely misunderstand or overlook this when setting up their simulation.&nbsp; This common mistake can lead to a lot of needless doubt following unexpected and puzzling simulation results produced by LTspice when presented with an ideal transformer that is inadvertently initialized with a large amount of dc voltage applied to its windings.&nbsp; This is probably the most common self-inflicted pitfall that trips up users improperly specifying ac voltage sources.<br />
<br />
When LTspice calculates initial conditions for voltage sources, it uses the values at time = 0.&nbsp; Depending on the starting phase angle and delay specified for a sine source, this can be as much as the voltage at the peak of the sine wave.&nbsp; When the simulator attempts to find the circuit's initial solution, this is the equivalent to hooking the transformer up to a large dc voltage source.&nbsp; Current will only be limited by winding resistance (which, in the ideal case, may be zero).&nbsp; Note that a real transformer will saturate at a relatively low current and would normally not store much energy (it would also probably burn up with so much dc applied), but an ideal transformer with an ideal magnetizing inductance may store a physically impossible amount of simulated "virtual" energy.<br />
<br />
Without realizing it, many users may instruct LTspice to initialize the transformer magnetizing inductance with huge starting currents.&nbsp; Since they have used an ideal inductance that does not saturate (like a real transformer would), it starts out with dc current that may take many hundreds of line (or switching) cycles to die away.&nbsp; This completely unrealistic energy source then may dominate the simulation, causing strange and unexpectedly puzzling behavior.&nbsp; In such cases, LTspice is just innocently following the instructions given it and accurately computing the unrealistic results (garbage in, garbage out).<br />
<br />
To avoid this bogus and unwanted result, you must either arrange '''''the ac source to be zero at time zero''''' or '''''instruct LTspice not to use a dc solution for the starting point (UIC).'''''<br />
<br />
=== I want to model leakage inductance - how should I do that? ===<br />
<br />
The most flexible method is to keep the windings' mutual inductance statement at unity and add a small discrete leakage inductance in series with each winding.&nbsp; This is the most straightforward way to model transformers with asymmetrical leakage inductances.&nbsp; However, if your transformer is electrically symmetrical, it may be more convenient to simply set the mutual inductance to a value less than one.&nbsp; For each winding the resulting leakage inductance will be (1-K) times that winding's inductance.&nbsp; Also, each winding's coupled inductance also will decrease to K times that winding's inductance, but for typical values of K (>>0.9) this effect will be very small.&nbsp; Note that physical transformer leakage inductance measured in the laboratory typically is close to the sum of the leakage inductance of two windings in series combination (with coupled inductance and perhaps several windings partially in parallel).<br />
<br />
'''This is how LTspice "sees" coupled inductors:'''<br />
<br />
For n inductors coupled together with a K statement, each inductor L1 through Ln is divided into two parts, a completely non-coupled "leakage" inductance equal to (1-K)*Lx (where Lx is the particular inductor in question) and a completely coupled "mutual" inductance equal to K*Lx.&nbsp; Voltage and current ratios of the coupled parts are related by the ratio of the square root of the the inductances L1 through Ln (this is the apparent "turns ratio").<br />
<br />
* For example, given two inductors coupled by a K statement:<br />
[[File:Loosely_Coupled_Transformer.gif|right|153px|Coupling is only K=0.2]]<br />
L1 1 0 1H<br />
L2 2 0 1H<br />
Km L1 L2 0.2<br />
<br />
[[File:Loosely_Coupled_Equivalent.gif|right|182px|"Winding" inductance is 1H]]<br />
<br />
* In LTspice, this is the same as:<br />
L1 1 m 0.8H<br />
Lm m 0 0.2H<br />
L2 2 m 0.8H<br />
<br />
Other engineering conventions regarding the definition of K, coupling and formula for leakage inductance are irrelevant to LTspice.&nbsp; Other formula for leakage inductance are intended to find total leakage inductance from an input winding through to an output winding(s) rather than the partial leakage inductance for each individual winding.<br />
<br />
=== How about transformer saturation effects?&nbsp; Can LTspice model those? ===<br />
<br />
Yes, LTspice comes with a non-linear hysteretic core model built in!&nbsp; This is the 1991 model by John Chan et al.&nbsp; Compared to older core models, [[the Chan model]] is particularly robust, computationally efficient and compact, requiring only three parameters to define most any commonly encountered magnetic hysteresis loop.&nbsp; (LTspice also allows building an arbitrary inductance based on self flux and/or any valid function of node voltages and branch currents.&nbsp; [[The Arbitrary Inductor model|The arbitrary inductor model]] can be very efficiently used to create saturation without hysteresis.) <br />
<br />
Once the core material's generic magnetic properties are set, establishing the circuit-level non-linear inductance requires specifying three more parameters to set the geometry of the specific core and specifying one additional parameter for the core winding turn-count.&nbsp; The Chan inductor <font color="green" title="(has been mentioned as a possibility for a future release)">does not currently</font> directly support [[Mutual Inductance]], so unless only a single-winding inductor is being modeled, multiple windings must be added via additional circuitry.&nbsp; The simplest way to do this is to construct an ideal, unity coupled transformer with as many windings as required and then put the Chan inductor directly in parallel with any one of the windings (taking care to set the turns to match that particular winding).&nbsp; Since the magnetic effects (including non-saturated inductance) are already modeled by the Chan inductor, the inductance of the transformer's parallel winding must be enough larger (>>10) not to significantly load the Chan inductance.&nbsp; As before, the inductances for the other windings should be scaled by the square of their individual turns ratios (with respect to the paralleled winding).<br />
<br />
=== Okay, but calculating winding inductances is tedious.&nbsp; Is there some way to just enter a turns count for all the windings? ===<br />
<br />
Yes, this can be done in any of a number of ways.&nbsp; For example, the values for each of the inductances may be directly parametrized via <font color="green"><b title="Lx node1 node2 {Lm*(Nx/Nm)**2}">curly braces</b></font> to be a function of turns ratios (squared), or a subcircuit that accepts turns as a parameter may be used to encapsulate the windings implementation details.<br />
<br />
* Use parameters to to convert input of winding turns to inductance:<br />
[[File: Parameterized_Transformer.gif|right|304px|Turns are entered as parameters from which the inductance is calculated]]<br />
.param Lp=20m Np=200 Ns=20 ; inputs: primary inductance, primary turns, secondary turns<br />
.param Kn=Lp/Np**2 ; calculated inductance per turn squared<br />
Lp 1 0 {Np**2*Kn} ; primary inductance = 200t**2*Kn<br />
Ls 2 0 {Ns**2*Kn} ; secondary inductance = 20t**2*Kn<br />
Kx Lp Ls 1 ; core coupling factor = 1<br />
<br />
Below is a schematic of a simple LTspice subcircuit that is functionally equivalent to a winding (without a core).&nbsp; Its symbol appears just to the right of the schematic.&nbsp; LTspice's fully extended inductor parasitics are included within this model.&nbsp; Observe that the winding is presented with a voltage equal to the core's volts/turn*primary_turns and that the core is presented with a current equal to the winding's ampere-turns = winding's amps*primary_turns.&nbsp; Also note if the leakage inductance and resistances are zero, the winding is completely floating with respect to the core and that the winding performs a voltage ratio transformation (set by the turns ratio) from DC to light.<br />
<br />
* First, the basic winding: Start (dot), Finish, Core:<br />
[[File: Simple Winding Symbol & Subcircuit.gif|right|479px|This simple subcircuit is equivalent to an inductor or transformer winding]]<br />
.subckt Winding s f c params: n=100 L=1u Rs=1m Rp=100<br />
Lw s 1 {L} Rser={Rs} Rpar={Rp} ; leakage and resistance<br />
Ew 1 f c 0 {n} ; impose core volts/turn*turns onto winding<br />
Fw 0 c Ew {n} ; impose winding amperes*turns onto core<br />
.ends Winding<br />
<br />
<br />
==== DC to DC Transformer (no magnetizing inductance - no energy storage) ====<br />
<br />
The transformer winding subcircuits are DC coupled and, when connected to a "core" (1TΩ in parallel with 1pF) that supports DC without drawing current, they combine to make a transformer that draws no magnetizing current, stores no energy and therefore is immune to errant initial conditions.&nbsp; This may be an advantage when first experimenting with new power circuits.<br />
<br />
For better cosmetics the simple DC core may encapsulated in its own subcircuit and symbol.&nbsp;<br />
<br />
[[File: DC_to_DC_Transformer.gif|right|190px|DC to DC (because of "core") transformer with two windings]]<br />
* Here is a DC "core" that does not draw increasing current with time:<br />
.subckt Core_DC C<br />
Cc C 0 1p Rpar=1T ; dump the "core's" ampere-turns into a small conductance<br />
.ends Core_DC<br />
<br />
[[File: DC_to_DC_Transformer_&_Core.gif|right|189px|DC to DC transformer with DC core symbol for aesthetics]]<br />
* DC-to-DC Transformer Equivalent (Netlist Uprocessed):<br />
Xp P 0 C Winding n=1 L=1u Rs=1m Rp=100 ; primary winding of 1:1 transformer<br />
Xs S 0 C Winding n=1 L=1u Rs=1m Rp=100 ; secondary winding of 1:1 transformer<br />
Xc C CoreDC ; subcircuit consisting of 1TΩ in parallel with 1pF<br />
<br />
==== Linear Transformer (linear magnetizing inductance - potentially unlimited energy storage) ====<br />
<br />
A standard linear transformer may easily be created simply by changing the core to a standard inductor with Rs=0.&nbsp; In this form (with a standard ''linear'' magnetizing inductance "core") the model is mostly useful as a perceptual window into the way coupled inductors work in LTspice since linear transformers are more easily and simply built with standard coupled inductors.&nbsp; Note that the magnetizing inductance "core" is the single summing point for the ''ampere-turns'' from all the windings and is the sole source of ''impressed voltage'' (=L*di/dt) reflected onto all the windings.&nbsp; Although this subcircuit is an unnecessary and overly complex representation for a transformer with a linear core inductance, it will be absolutely required if multiple windings are to be "wrapped" onto LTspice's nonlinear Chan inductance model, so take a moment to read it through (the Chan version will follow shortly).<br />
<br />
<br />
* Parametize and wrap an inductor with a subcircuit:<br />
[[File: Linear_Core.gif|right|191px|A linear core is simply an inductor with Rser=0]]<br />
.subckt Core_Linear C params: L=20m Rp=10k Cp=10p<br />
Lc C 0 {L} Rser=0 Rpar={Rp} Cpar={Cp}<br />
.ends Core_Linear<br />
<br />
[[File: Linear_Transformer.gif|right|176px|Transformer with linear core]]<br />
* Linear Transformer Equivalent (Netlist Unprocessed):<br />
Xp P 0 C Winding n=1 L=1u Rs=1m Rp=100 ; primary winding of 1:1 transformer<br />
Xs S 0 C Winding n=1 L=1u Rs=1m Rp=100 ; secondary winding of 1:1 transformer<br />
Xc C Core_Linear L=20m Rp=10k Cp=10p ; subcircuit consisting of an inductor with Rs=0<br />
<br />
* Linear Transformer Equivalent (Netlist Flattened):<br />
[[File: Linear_Transformer_Full.gif|right|438px|Transformer with linear core]]<br />
Lp Ps 1 1u Rser=1m Rpar=100 ; leakage and resistance<br />
Ep 1 Pf C 0 1 ; impose core volts/turn*turns onto winding<br />
Fp 0 C Ep 1 ; impose winding ampere*turns onto core<br />
Lc C 0 20m Rpar=10k Cpar=10p ; liner inductor core (no magnetic saturation)<br />
+ Rser=0 ; Rser must equal zero<br />
Fs 0 C Es 1 ; impose winding ampere*turns onto core<br />
Es 1 Sf C 0 1 ; impose core volts/turn*turns onto winding<br />
Ls Ss 1 1u Rser=1m Rpar=100 ; leakage and resistance<br />
<br />
==== Chan Transformer (saturating magnetizing inductance with hysteresis - limited energy storage) ====<br />
<br />
Now that the windings are separate from the core, a Chan inductor may simply be substituted for the linear inductor core. Since the inductance of a Chan is not assigned, but is determined by its magnetic material, dimensional properties and winding turns, one must adjust inductance by iteratively adjusting the gap and/or winding turns.<br />
<br />
<br />
* Parametize and wrap a Chan inductor with a subcircuit:<br />
[[File: Chan_Core.gif|right|167px|Physical properties based core with hysteresis and saturation]]<br />
.subckt Core_Chan C params:<br />
+ Bs=0.4 Br=0.1 Hc=20 ; Core default magnetic parameters<br />
+ A=25u1 Lm=19m8 Lg=0m7 ; Core default physical parameters<br />
+ Rp=10k Cp=10p ; Core default parallel loss and capacitance<br />
Lc C 0 Rser=0 n=1 ; force Rser=0 and n=1<br />
+ Bs={Bs} Br={Br} Hc={Hc}<br />
+ A={A} Lm={Lm} Lg={Lg}<br />
+ Rpar={Rp} Cpar={Cp}<br />
.ends Core_Chan<br />
<br />
[[File: Chan_Transformer.gif|right|167px|Physically parameterized transformer with hysteresis and saturation]]<br />
* Chan Transformer Equivalent (Netlist Unprocessed):<br />
Xp P 0 C Winding n=100 L=1u Rs=1m Rp=100 ; primary winding of 1:1 transformer<br />
Xs S 0 C Winding n=100 L=1u Rs=1m Rp=100 ; secondary winding of 1:1 transformer<br />
Xc C Core_Chan ; Chan inductor subcircuit with forced Rs=0 and n=1<br />
+ Bs=0.4 Br=0.1 Hc=20 Br=.10 ; Assigned core magnetic parameters<br />
+ A=25u1 Lm=19m8 Lg=0m7 ; Assigned core physical parameters<br />
+ Rp=10k Cp=10p ; Assigned core parallel loss and capacitance<br />
<br />
----<br />
<br />
<br />
'''Temporary Junk'''<br />
<br />
</pre><br />
Explain how to plot hysteresis curves.<br />
<br />
And here is the same thing using parameters within curly braces to give value to LTspice's extended inductors and to a coupling statement (mutual inductance).&nbsp; Note that there is no need to create a subcircuit with this method because Lp and Ls can be placed directly on the schematic as symbols and K1 and the .param statement may be placed as SPICE text (this is the section of netlist that would then result).&nbsp; The prior subcircuit form (or something like it) only becomes necessary in conjunction with a custom two-winding transformer symbol or if a nonlinear core (magnetizing inductance) model must be used.<br />
<pre><br />
.param Npri=300 Nsec=30 L=1u K=0.95 Rs=1u Rp=10 Cp=1u<br />
+ Np2=Npri**2 Ns2=Nsec**2 ; turns squared for primary and secondary<br />
Lp P1 P2 {L*Np2} Rser={Rs*Np2} Rpar={Rp*Np2} Cpar={Cp/Np2}<br />
Ls S1 S2 {L*Ns2} Rser={Rs*Ns2} Rpar={Rp*Ns2} Cpar={Cp/Ns2}<br />
K1 Lp Ls {K}<br />
</pre><br />
<br />
Knowing the internal workings of LTspice's coupled inductor style transformer is all very interesting, but how do I make something that uses separate standard inductor symbols for winding, yet also uses the Chan core model with full saturation and hysteresis?<br />
<br />
The following method allows this:<br />
<br />
[[File:Separate_Winding.png]]&nbsp; [''obviously, this section is not yet complete'']<br />
<br />
This model uses the standard inductor symbol edited to appear as a winding subcircuit on a core (connected through a global node).&nbsp; The core may be linear or nonlinear (e.g., LTspice's built in Chan model) and may have as many windings as required.&nbsp; Due to the use of a global core node (which must be different for each core), a different subcircuit is required for each core.<br />
<br />
<br />
{{#widget:DISQUS<br />
|id=ltwiki<br />
|uniqid={{PAGENAME}}<br />
|url={{fullurl:{{PAGENAME}}}}<br />
}}</div>Analogspicemanhttp://ltwiki.org/index.php?title=Transformers&diff=2100Transformers2019-11-15T11:41:04Z<p>Analogspiceman: /* I want to model leakage inductance - how should I do that? */ added comments about the difference between leakage inductance of a winding versus of a transformer</p>
<hr />
<div>== Transformers ==<br />
<br />
=== Introduction ===<br />
<br />
Do you wish to study the behavior of transformers and inductors and explore their mysteries?&nbsp; LTspice is the ideal learning tool for this purpose. LTspice will faithfully model both ideal and real magnetic devices.&nbsp; However, caution is advised when first experimenting with unfamiliar concepts in inductors and transformers.&nbsp; Be sure to minimize simulation problems by including reasonably realistic parasitic resistances (both series and parallel) directly into each inductor, whether used individually or as part of a transformer.<br />
<br />
A good learning and reference resource is the [http://coefs.uncc.edu/mnoras/files/2013/03/Transformer-and-Inductor-Design-Handbook_Chapter_17.pdf <i>Transformer and Inductor Design Handbook</i> Chapter 17, Winding Capacitance and Leakage Inductance] 4th Edition by Colonel William. T. McLyman.&nbsp; Mike Engelhardt, the author of LTspice, explains how to make transformers in LTspice in a [https://www.analog.com/en/technical-articles/using-transformers-in-ltspice-switcher-cadiii.html 2006 LT-Magazine article].<br />
<br />
Always keep in mind that starting a simulation with a dc voltage bias on an inductor or transformer winding will cause an initial inductor current only limited by the inductor's series resistance (this would be like trying to initialize an ideal capacitor with a current source - no matter how small the source, the dc voltage will increase without bounds - or at least until the capacitor breaks down).&nbsp; In fact, if you are like most engineers, you are much more comfortable with the behavior of capacitors.&nbsp; If so, use this to your advantage by applying duality to think of what to expect when dealing with inductors.<br />
<br />
=== How do I make a transformer in LTspice? === <br />
<br />
[[File:LTspice_Transformer.gif|right|174px|Two lines were used to draw the core]]<br />
<br />
Although it is very possible to make a dedicated subcircuit for a specific transformer, the preferred method of making a generic transformer when drafting a simulation schematic is to simply place a separate inductor for each separate transformer winding and then couple them all together magnetically via a single ''[[Mutual Inductance]] (K) statement'' placed as a [[SPICE Directive]] on the schematic.&nbsp; Note that inductors called out in a [[Mutual Inductance]] statement will be automatically given a phasing dot if one does not already exist.<br />
<br />
K1 L1 L2 L3 1 ; causes phasing dots to automatically appear on L1-L3 inductor symbols<br />
<br />
When creating a new transformer this way, especially for use in a switched-mode power circuit, it is generally best to first specify the mutual coupling coefficient to be exactly unity.&nbsp; By starting with unity coupling there will be no leakage inductance in any winding and this will minimize the likelihood of the windings ringing at extremely high frequencies (which can slow the simulation to a crawl at each switching edge).&nbsp; However, be aware that a mutual inductance value of plus (or minus) unity ''may'' lead to simulation difficulties if ''Skip-the-initial-operating-point-solution'' (UIC) is specified for the .tran command.&nbsp; Prevent this by specifying a realistic resistance for each inductor "winding" (ctrl-right-mouse-click).&nbsp; Note that when coupled inductors are used as transformer windings, individual winding inductances rather than turns ratios must be specified (''inductance ratios should be set to be proportional to <u>the '''square''' of the turns ratios''</u>).<br />
<br />
=== I've created an ideal transformer so it should work at all frequencies, even including DC, right? ===<br />
<br />
No, but lots of users completely misunderstand or overlook this when setting up their simulation.&nbsp; This common mistake can lead to a lot of needless doubt following unexpected and puzzling simulation results produced by LTspice when presented with an ideal transformer that is inadvertently initialized with a large amount of dc voltage applied to its windings.&nbsp; This is probably the most common self-inflicted pitfall that trips up users improperly specifying ac voltage sources.<br />
<br />
When LTspice calculates initial conditions for voltage sources, it uses the values at time = 0.&nbsp; Depending on the starting phase angle and delay specified for a sine source, this can be as much as the voltage at the peak of the sine wave.&nbsp; When the simulator attempts to find the circuit's initial solution, this is the equivalent to hooking the transformer up to a large dc voltage source.&nbsp; Current will only be limited by winding resistance (which, in the ideal case, may be zero).&nbsp; Note that a real transformer will saturate at a relatively low current and would normally not store much energy (it would also probably burn up with so much dc applied), but an ideal transformer with an ideal magnetizing inductance may store a physically impossible amount of simulated "virtual" energy.<br />
<br />
Without realizing it, many users may instruct LTspice to initialize the transformer magnetizing inductance with huge starting currents.&nbsp; Since they have used an ideal inductance that does not saturate (like a real transformer would), it starts out with dc current that may take many hundreds of line (or switching) cycles to die away.&nbsp; This completely unrealistic energy source then may dominate the simulation, causing strange and unexpectedly puzzling behavior.&nbsp; In such cases, LTspice is just innocently following the instructions given it and accurately computing the unrealistic results (garbage in, garbage out).<br />
<br />
To avoid this bogus and unwanted result, you must either arrange '''''the ac source to be zero at time zero''''' or '''''instruct LTspice not to use a dc solution for the starting point (UIC).'''''<br />
<br />
=== I want to model leakage inductance - how should I do that? ===<br />
<br />
The most flexible method is to keep the windings' mutual inductance statement at unity and add a small discrete leakage inductance in series with each winding.&nbsp; This is the most straightforward way to model transformers with asymmetrical leakage inductances.&nbsp; However, if your transformer is electrically symmetrical, it may be more convenient to simply set the mutual inductance to a value less than one.&nbsp; For each winding the resulting leakage inductance will be (1-K) times that winding's inductance.&nbsp; Also, each winding's coupled inductance also will decrease to K times that winding's inductance, but for typical values of K (>>0.9) this effect will be very small.&nbsp; Note that physical transformer leakage inductance measured in the laboratory typically is close to the sum of the leakage inductance of two windings in series combination (with coupled inductance and perhaps several windings partially in parallel).<br />
<br />
'''This is how LTspice "sees" coupled inductors:'''<br />
<br />
For n inductors coupled together with a K statement, each inductor L1 through Ln is divided into two parts, a completely non-coupled "leakage" inductance equal to (1-K)*Lx (where Lx is the particular inductor in question) and a completely coupled "mutual" inductance equal to K*Lx.&nbsp; Voltage and current ratios of the coupled parts are related by the ratio of the square root of the the inductances L1 through Ln (this is the apparent "turns ratio").<br />
<br />
* For example, given two inductors coupled by a K statement:<br />
[[File:Loosely_Coupled_Transformer.gif|right|153px|Coupling is only K=0.2]]<br />
L1 1 0 1H<br />
L2 2 0 1H<br />
Km L1 L2 0.2<br />
<br />
[[File:Loosely_Coupled_Equivalent.gif|right|182px|"Winding" inductance is 1H]]<br />
<br />
* In LTspice, this is the same as:<br />
L1 1 m 0.8H<br />
Lm m 0 0.2H<br />
L2 2 m 0.8H<br />
<br />
Other engineering conventions regarding the definition of K, coupling and formula for leakage inductance are irrelevant to LTspice.&nbsp; Other formula for leakage inductance are intended to find total leakage inductance from an input winding through to an output winding(s) rather than the partial leakage inductance for each individual winding.<br />
<br />
=== How about transformer saturation effects?&nbsp; Can LTspice model those? ===<br />
<br />
Yes, LTspice comes with a non-linear hysteretic core model built in!&nbsp; This is the 1991 model by John Chan et al.&nbsp; Compared to older core models, [[the Chan model]] is particularly robust, computationally efficient and compact, requiring only three parameters to define most any commonly encountered magnetic hysteresis loop.&nbsp; (LTspice also allows building an arbitrary inductance based on self flux and/or any valid function of node voltages and branch currents.&nbsp; [[The Arbitrary Inductor model|The arbitrary inductor model]] can be very efficiently used to create saturation without hysteresis.) <br />
<br />
Once the core material's generic magnetic properties are set, establishing the circuit-level non-linear inductance requires specifying three more parameters to set the geometry of the specific core and specifying one additional parameter for the core winding turn-count.&nbsp; The Chan inductor <font color="green" title="(has been mentioned as a possibility for a future release)">does not currently</font> directly support [[Mutual Inductance]], so unless only a single-winding inductor is being modeled, multiple windings must be added via additional circuitry.&nbsp; The simplest way to do this is to construct an ideal, unity coupled transformer with as many windings as required and then put the Chan inductor directly in parallel with any one of the windings (taking care to set the turns to match that particular winding).&nbsp; Since the magnetic effects (including non-saturated inductance) are already modeled by the Chan inductor, the inductance of the transformer's parallel winding must be enough larger (>>10) not to significantly load the Chan inductance.&nbsp; As before, the inductances for the other windings should be scaled by the square of their individual turns ratios (with respect to the paralleled winding).<br />
<br />
=== Okay, but calculating winding inductances is tedious.&nbsp; Is there some way to just enter a turns count for all the windings? ===<br />
<br />
Yes, this can be done in any of a number of ways.&nbsp; For example, the values for each of the inductances may be directly parametrized via <font color="green"><b title="Lx node1 node2 {Lm*(Nx/Nm)**2}">curly braces</b></font> to be a function of turns ratios (squared), or a subcircuit that accepts turns as a parameter may be used to encapsulate the windings implementation details.<br />
<br />
* Use parameters to to convert input of winding turns to inductance:<br />
[[File: Parameterized_Transformer.gif|right|304px|Turns are entered as parameters from which the inductance is calculated]]<br />
.param Lp=20m Np=200 Ns=20 ; inputs: primary inductance, primary turns, secondary turns<br />
.param Kn=Lp/Np**2 ; calculated inductance per turn squared<br />
Lp 1 0 {Np**2*Kn} ; primary inductance = 200t**2*Kn<br />
Ls 2 0 {Ns**2*Kn} ; secondary inductance = 20t**2*Kn<br />
Kx Lp Ls 1 ; core coupling factor = 1<br />
<br />
Below is a schematic of a simple LTspice subcircuit that is functionally equivalent to a winding (without a core).&nbsp; Its symbol appears just to the right of the schematic.&nbsp; LTspice's fully extended inductor parasitics are included within this model.&nbsp; Observe that the winding is presented with a voltage equal to the core's volts/turn*primary_turns and that the core is presented with a current equal to the winding's ampere-turns = winding's amps*primary_turns.&nbsp; Also note if the leakage inductance and resistances are zero, the winding is completely floating with respect to the core and that the winding performs a voltage ratio transformation (set by the turns ratio) from DC to light.<br />
<br />
* First, the basic winding: Start (dot), Finish, Core:<br />
[[File: Simple Winding Symbol & Subcircuit.gif|right|479px|This simple subcircuit is equivalent to an inductor or transformer winding]]<br />
.subckt Winding s f c params: n=100 L=1u Rs=1m Rp=100<br />
Lw s 1 {L} Rser={Rs} Rpar={Rp} ; leakage and resistance<br />
Ew 1 f c 0 {n} ; impose core volts/turn*turns onto winding<br />
Fw 0 c Ew {n} ; impose winding amperes*turns onto core<br />
.ends Winding<br />
<br />
<br />
==== DC to DC Transformer (no magnetizing inductance - no energy storage) ====<br />
<br />
The transformer winding subcircuits are DC coupled and, when connected to a "core" (1TΩ in parallel with 1pF) that supports DC without drawing current, they combine to make a transformer that draws no magnetizing current, stores no energy and therefore is immune to errant initial conditions.&nbsp; This may be an advantage when first experimenting with new power circuits.<br />
<br />
For better cosmetics the simple DC core may encapsulated in its own subcircuit and symbol.&nbsp;<br />
<br />
[[File: DC_to_DC_Transformer.gif|right|190px|DC to DC (because of "core") transformer with two windings]]<br />
* Here is a DC "core" that does not draw increasing current with time:<br />
.subckt Core_DC C<br />
Cc C 0 1p Rpar=1T ; dump the "core's" ampere-turns into a small conductance<br />
.ends Core_DC<br />
<br />
[[File: DC_to_DC_Transformer_&_Core.gif|right|189px|DC to DC transformer with DC core symbol for aesthetics]]<br />
* DC-to-DC Transformer Equivalent (Netlist Uprocessed):<br />
Xp P 0 C Winding n=1 L=1u Rs=1m Rp=100 ; primary winding of 1:1 transformer<br />
Xs S 0 C Winding n=1 L=1u Rs=1m Rp=100 ; secondary winding of 1:1 transformer<br />
Xc C CoreDC ; subcircuit consisting of 1TΩ in parallel with 1pF<br />
<br />
==== Linear Transformer (linear magnetizing inductance - potentially unlimited energy storage) ====<br />
<br />
A standard linear transformer may easily be created simply by changing the core to a standard inductor with Rs=0.&nbsp; In this form (with a standard ''linear'' magnetizing inductance "core") the model is mostly useful as a perceptual window into the way coupled inductors work in LTspice since linear transformers are more easily and simply built with standard coupled inductors.&nbsp; Note that the magnetizing inductance "core" is the single summing point for the ''ampere-turns'' from all the windings and is the sole source of ''impressed voltage'' (=L*di/dt) reflected onto all the windings.&nbsp; Although this subcircuit is an unnecessary and overly complex representation for a transformer with a linear core inductance, it will be absolutely required if multiple windings are to be "wrapped" onto LTspice's nonlinear Chan inductance model, so take a moment to read it through (the Chan version will follow shortly).<br />
<br />
<br />
* Parametize and wrap an inductor with a subcircuit:<br />
[[File: Linear_Core.gif|right|191px|A linear core is simply an inductor with Rser=0]]<br />
.subckt Core_Linear C params: L=20m Rp=10k Cp=10p<br />
Lc C 0 {L} Rser=0 Rpar={Rp} Cpar={Cp}<br />
.ends Core_Linear<br />
<br />
[[File: Linear_Transformer.gif|right|176px|Transformer with linear core]]<br />
* Linear Transformer Equivalent (Netlist Unprocessed):<br />
Xp P 0 C Winding n=1 L=1u Rs=1m Rp=100 ; primary winding of 1:1 transformer<br />
Xs S 0 C Winding n=1 L=1u Rs=1m Rp=100 ; secondary winding of 1:1 transformer<br />
Xc C Core_Linear L=20m Rp=10k Cp=10p ; subcircuit consisting of an inductor with Rs=0<br />
<br />
* Linear Transformer Equivalent (Netlist Flattened):<br />
[[File: Linear_Transformer_Full.gif|right|438px|Transformer with linear core]]<br />
Lp Ps 1 1u Rser=1m Rpar=100 ; leakage and resistance<br />
Ep 1 Pf C 0 1 ; impose core volts/turn*turns onto winding<br />
Fp 0 C Ep 1 ; impose winding ampere*turns onto core<br />
Lc C 0 20m Rpar=10k Cpar=10p ; liner inductor core (no magnetic saturation)<br />
+ Rser=0 ; Rser must equal zero<br />
Fs 0 C Es 1 ; impose winding ampere*turns onto core<br />
Es 1 Sf C 0 1 ; impose core volts/turn*turns onto winding<br />
Ls Ss 1 1u Rser=1m Rpar=100 ; leakage and resistance<br />
<br />
==== Chan Transformer (saturating magnetizing inductance with hysteresis - limited energy storage) ====<br />
<br />
Now that the windings are separate from the core, a Chan inductor may simply be substituted for the linear inductor core. Since the inductance of a Chan is not assigned, but is determined by its magnetic material, dimensional properties and winding turns, one must adjust inductance by iteratively adjusting the gap and/or winding turns.<br />
<br />
<br />
* Parametize and wrap a Chan inductor with a subcircuit:<br />
[[File: Chan_Core.gif|right|167px|Physical properties based core with hysteresis and saturation]]<br />
.subckt Core_Chan C params:<br />
+ Bs=0.4 Br=0.1 Hc=20 ; Core default magnetic parameters<br />
+ A=25u1 Lm=19m8 Lg=0m7 ; Core default physical parameters<br />
+ Rp=10k Cp=10p ; Core default parallel loss and capacitance<br />
Lc C 0 Rser=0 n=1 ; force Rser=0 and n=1<br />
+ Bs={Bs} Br={Br} Hc={Hc}<br />
+ A={A} Lm={Lm} Lg={Lg}<br />
+ Rpar={Rp} Cpar={Cp}<br />
.ends Core_Chan<br />
<br />
[[File: Chan_Transformer.gif|right|167px|Physically parameterized transformer with hysteresis and saturation]]<br />
* Chan Transformer Equivalent (Netlist Unprocessed):<br />
Xp P 0 C Winding n=100 L=1u Rs=1m Rp=100 ; primary winding of 1:1 transformer<br />
Xs S 0 C Winding n=100 L=1u Rs=1m Rp=100 ; secondary winding of 1:1 transformer<br />
Xc C Core_Chan ; Chan inductor subcircuit with forced Rs=0 and n=1<br />
+ Bs=0.4 Br=0.1 Hc=20 Br=.10 ; Assigned core magnetic parameters<br />
+ A=25u1 Lm=19m8 Lg=0m7 ; Assigned core physical parameters<br />
+ Rp=10k Cp=10p ; Assigned core parallel loss and capacitance<br />
<br />
----<br />
<br />
<br />
'''Temporary Junk'''<br />
<br />
</pre><br />
And here is the same thing using parameters within curly braces to give value to LTspice's extended inductors and to a coupling statement (mutual inductance).&nbsp; Note that there is no need to create a subcircuit with this method because Lp and Ls can be placed directly on the schematic as symbols and K1 and the .param statement may be placed as SPICE text (this is the section of netlist that would then result).&nbsp; The prior subcircuit form (or something like it) only becomes necessary in conjunction with a custom two-winding transformer symbol or if a nonlinear core (magnetizing inductance) model must be used.<br />
<pre><br />
.param Npri=300 Nsec=30 L=1u K=0.95 Rs=1u Rp=10 Cp=1u<br />
+ Np2=Npri**2 Ns2=Nsec**2 ; turns squared for primary and secondary<br />
Lp P1 P2 {L*Np2} Rser={Rs*Np2} Rpar={Rp*Np2} Cpar={Cp/Np2}<br />
Ls S1 S2 {L*Ns2} Rser={Rs*Ns2} Rpar={Rp*Ns2} Cpar={Cp/Ns2}<br />
K1 Lp Ls {K}<br />
</pre><br />
<br />
Knowing the internal workings of LTspice's coupled inductor style transformer is all very interesting, but how do I make something that uses separate standard inductor symbols for winding, yet also uses the Chan core model with full saturation and hysteresis?<br />
<br />
The following method allows this:<br />
<br />
[[File:Separate_Winding.png]]&nbsp; [''obviously, this section is not yet complete'']<br />
<br />
This model uses the standard inductor symbol edited to appear as a winding subcircuit on a core (connected through a global node).&nbsp; The core may be linear or nonlinear (e.g., LTspice's built in Chan model) and may have as many windings as required.&nbsp; Due to the use of a global core node (which must be different for each core), a different subcircuit is required for each core.<br />
<br />
<br />
{{#widget:DISQUS<br />
|id=ltwiki<br />
|uniqid={{PAGENAME}}<br />
|url={{fullurl:{{PAGENAME}}}}<br />
}}</div>Analogspicemanhttp://ltwiki.org/index.php?title=Transformers&diff=2099Transformers2019-11-15T11:20:16Z<p>Analogspiceman: /* I've created an ideal transformer so it should work at all frequencies, even including DC, right? */</p>
<hr />
<div>== Transformers ==<br />
<br />
=== Introduction ===<br />
<br />
Do you wish to study the behavior of transformers and inductors and explore their mysteries?&nbsp; LTspice is the ideal learning tool for this purpose. LTspice will faithfully model both ideal and real magnetic devices.&nbsp; However, caution is advised when first experimenting with unfamiliar concepts in inductors and transformers.&nbsp; Be sure to minimize simulation problems by including reasonably realistic parasitic resistances (both series and parallel) directly into each inductor, whether used individually or as part of a transformer.<br />
<br />
A good learning and reference resource is the [http://coefs.uncc.edu/mnoras/files/2013/03/Transformer-and-Inductor-Design-Handbook_Chapter_17.pdf <i>Transformer and Inductor Design Handbook</i> Chapter 17, Winding Capacitance and Leakage Inductance] 4th Edition by Colonel William. T. McLyman.&nbsp; Mike Engelhardt, the author of LTspice, explains how to make transformers in LTspice in a [https://www.analog.com/en/technical-articles/using-transformers-in-ltspice-switcher-cadiii.html 2006 LT-Magazine article].<br />
<br />
Always keep in mind that starting a simulation with a dc voltage bias on an inductor or transformer winding will cause an initial inductor current only limited by the inductor's series resistance (this would be like trying to initialize an ideal capacitor with a current source - no matter how small the source, the dc voltage will increase without bounds - or at least until the capacitor breaks down).&nbsp; In fact, if you are like most engineers, you are much more comfortable with the behavior of capacitors.&nbsp; If so, use this to your advantage by applying duality to think of what to expect when dealing with inductors.<br />
<br />
=== How do I make a transformer in LTspice? === <br />
<br />
[[File:LTspice_Transformer.gif|right|174px|Two lines were used to draw the core]]<br />
<br />
Although it is very possible to make a dedicated subcircuit for a specific transformer, the preferred method of making a generic transformer when drafting a simulation schematic is to simply place a separate inductor for each separate transformer winding and then couple them all together magnetically via a single ''[[Mutual Inductance]] (K) statement'' placed as a [[SPICE Directive]] on the schematic.&nbsp; Note that inductors called out in a [[Mutual Inductance]] statement will be automatically given a phasing dot if one does not already exist.<br />
<br />
K1 L1 L2 L3 1 ; causes phasing dots to automatically appear on L1-L3 inductor symbols<br />
<br />
When creating a new transformer this way, especially for use in a switched-mode power circuit, it is generally best to first specify the mutual coupling coefficient to be exactly unity.&nbsp; By starting with unity coupling there will be no leakage inductance in any winding and this will minimize the likelihood of the windings ringing at extremely high frequencies (which can slow the simulation to a crawl at each switching edge).&nbsp; However, be aware that a mutual inductance value of plus (or minus) unity ''may'' lead to simulation difficulties if ''Skip-the-initial-operating-point-solution'' (UIC) is specified for the .tran command.&nbsp; Prevent this by specifying a realistic resistance for each inductor "winding" (ctrl-right-mouse-click).&nbsp; Note that when coupled inductors are used as transformer windings, individual winding inductances rather than turns ratios must be specified (''inductance ratios should be set to be proportional to <u>the '''square''' of the turns ratios''</u>).<br />
<br />
=== I've created an ideal transformer so it should work at all frequencies, even including DC, right? ===<br />
<br />
No, but lots of users completely misunderstand or overlook this when setting up their simulation.&nbsp; This common mistake can lead to a lot of needless doubt following unexpected and puzzling simulation results produced by LTspice when presented with an ideal transformer that is inadvertently initialized with a large amount of dc voltage applied to its windings.&nbsp; This is probably the most common self-inflicted pitfall that trips up users improperly specifying ac voltage sources.<br />
<br />
When LTspice calculates initial conditions for voltage sources, it uses the values at time = 0.&nbsp; Depending on the starting phase angle and delay specified for a sine source, this can be as much as the voltage at the peak of the sine wave.&nbsp; When the simulator attempts to find the circuit's initial solution, this is the equivalent to hooking the transformer up to a large dc voltage source.&nbsp; Current will only be limited by winding resistance (which, in the ideal case, may be zero).&nbsp; Note that a real transformer will saturate at a relatively low current and would normally not store much energy (it would also probably burn up with so much dc applied), but an ideal transformer with an ideal magnetizing inductance may store a physically impossible amount of simulated "virtual" energy.<br />
<br />
Without realizing it, many users may instruct LTspice to initialize the transformer magnetizing inductance with huge starting currents.&nbsp; Since they have used an ideal inductance that does not saturate (like a real transformer would), it starts out with dc current that may take many hundreds of line (or switching) cycles to die away.&nbsp; This completely unrealistic energy source then may dominate the simulation, causing strange and unexpectedly puzzling behavior.&nbsp; In such cases, LTspice is just innocently following the instructions given it and accurately computing the unrealistic results (garbage in, garbage out).<br />
<br />
To avoid this bogus and unwanted result, you must either arrange '''''the ac source to be zero at time zero''''' or '''''instruct LTspice not to use a dc solution for the starting point (UIC).'''''<br />
<br />
=== I want to model leakage inductance - how should I do that? ===<br />
<br />
The most flexible method is to keep the windings' mutual inductance statement at unity and add a small discrete leakage inductance in series with each winding.&nbsp; This is the most straightforward way to model transformers with asymmetrical leakage inductances.&nbsp; However, if your transformer is electrically symmetrical, it may be more convenient to simply set the mutual inductance to a value less than one.&nbsp; For each winding the resulting leakage inductance will be (1-K) times that winding's inductance.&nbsp; Note that each winding's coupled inductance also will decrease to K times that winding's inductance, but for typical values of K (>>0.9) this effect will be very small.<br />
<br />
This is how LTspice "sees" coupled inductors:<br />
<br />
For n inductors coupled together with a K statement, each inductor L1 through Ln is divided into two parts, a completely non-coupled "leakage" inductance equal to (1-K)*Lx (where Lx is the particular inductor in question) and a completely coupled "mutual" inductance equal to K*Lx.&nbsp; Voltage and current ratios of the coupled parts are related by the ratio of the square root of the the inductances L1 through Ln (this is the apparent "turns ratio").<br />
<br />
* For example, given two inductors coupled by a K statement:<br />
[[File:Loosely_Coupled_Transformer.gif|right|153px|Coupling is only K=0.2]]<br />
L1 1 0 1H<br />
L2 2 0 1H<br />
Km L1 L2 0.2<br />
<br />
[[File:Loosely_Coupled_Equivalent.gif|right|182px|"Winding" inductance is 1H]]<br />
<br />
* In LTspice, this is the same as:<br />
L1 1 m 0.8H<br />
Lm m 0 0.2H<br />
L2 2 m 0.8H<br />
<br />
Other engineering conventions regarding the definition of K, coupling and formula for leakage inductance are irrelevant to LTspice.&nbsp; Other formula for leakage inductance are intended to find total leakage inductance from an input winding through to an output winding(s) rather than for each individual winding.<br />
<br />
=== How about transformer saturation effects?&nbsp; Can LTspice model those? ===<br />
<br />
Yes, LTspice comes with a non-linear hysteretic core model built in!&nbsp; This is the 1991 model by John Chan et al.&nbsp; Compared to older core models, [[the Chan model]] is particularly robust, computationally efficient and compact, requiring only three parameters to define most any commonly encountered magnetic hysteresis loop.&nbsp; (LTspice also allows building an arbitrary inductance based on self flux and/or any valid function of node voltages and branch currents.&nbsp; [[The Arbitrary Inductor model|The arbitrary inductor model]] can be very efficiently used to create saturation without hysteresis.) <br />
<br />
Once the core material's generic magnetic properties are set, establishing the circuit-level non-linear inductance requires specifying three more parameters to set the geometry of the specific core and specifying one additional parameter for the core winding turn-count.&nbsp; The Chan inductor <font color="green" title="(has been mentioned as a possibility for a future release)">does not currently</font> directly support [[Mutual Inductance]], so unless only a single-winding inductor is being modeled, multiple windings must be added via additional circuitry.&nbsp; The simplest way to do this is to construct an ideal, unity coupled transformer with as many windings as required and then put the Chan inductor directly in parallel with any one of the windings (taking care to set the turns to match that particular winding).&nbsp; Since the magnetic effects (including non-saturated inductance) are already modeled by the Chan inductor, the inductance of the transformer's parallel winding must be enough larger (>>10) not to significantly load the Chan inductance.&nbsp; As before, the inductances for the other windings should be scaled by the square of their individual turns ratios (with respect to the paralleled winding).<br />
<br />
=== Okay, but calculating winding inductances is tedious.&nbsp; Is there some way to just enter a turns count for all the windings? ===<br />
<br />
Yes, this can be done in any of a number of ways.&nbsp; For example, the values for each of the inductances may be directly parametrized via <font color="green"><b title="Lx node1 node2 {Lm*(Nx/Nm)**2}">curly braces</b></font> to be a function of turns ratios (squared), or a subcircuit that accepts turns as a parameter may be used to encapsulate the windings implementation details.<br />
<br />
* Use parameters to to convert input of winding turns to inductance:<br />
[[File: Parameterized_Transformer.gif|right|304px|Turns are entered as parameters from which the inductance is calculated]]<br />
.param Lp=20m Np=200 Ns=20 ; inputs: primary inductance, primary turns, secondary turns<br />
.param Kn=Lp/Np**2 ; calculated inductance per turn squared<br />
Lp 1 0 {Np**2*Kn} ; primary inductance = 200t**2*Kn<br />
Ls 2 0 {Ns**2*Kn} ; secondary inductance = 20t**2*Kn<br />
Kx Lp Ls 1 ; core coupling factor = 1<br />
<br />
Below is a schematic of a simple LTspice subcircuit that is functionally equivalent to a winding (without a core).&nbsp; Its symbol appears just to the right of the schematic.&nbsp; LTspice's fully extended inductor parasitics are included within this model.&nbsp; Observe that the winding is presented with a voltage equal to the core's volts/turn*primary_turns and that the core is presented with a current equal to the winding's ampere-turns = winding's amps*primary_turns.&nbsp; Also note if the leakage inductance and resistances are zero, the winding is completely floating with respect to the core and that the winding performs a voltage ratio transformation (set by the turns ratio) from DC to light.<br />
<br />
* First, the basic winding: Start (dot), Finish, Core:<br />
[[File: Simple Winding Symbol & Subcircuit.gif|right|479px|This simple subcircuit is equivalent to an inductor or transformer winding]]<br />
.subckt Winding s f c params: n=100 L=1u Rs=1m Rp=100<br />
Lw s 1 {L} Rser={Rs} Rpar={Rp} ; leakage and resistance<br />
Ew 1 f c 0 {n} ; impose core volts/turn*turns onto winding<br />
Fw 0 c Ew {n} ; impose winding amperes*turns onto core<br />
.ends Winding<br />
<br />
<br />
==== DC to DC Transformer (no magnetizing inductance - no energy storage) ====<br />
<br />
The transformer winding subcircuits are DC coupled and, when connected to a "core" (1TΩ in parallel with 1pF) that supports DC without drawing current, they combine to make a transformer that draws no magnetizing current, stores no energy and therefore is immune to errant initial conditions.&nbsp; This may be an advantage when first experimenting with new power circuits.<br />
<br />
For better cosmetics the simple DC core may encapsulated in its own subcircuit and symbol.&nbsp;<br />
<br />
[[File: DC_to_DC_Transformer.gif|right|190px|DC to DC (because of "core") transformer with two windings]]<br />
* Here is a DC "core" that does not draw increasing current with time:<br />
.subckt Core_DC C<br />
Cc C 0 1p Rpar=1T ; dump the "core's" ampere-turns into a small conductance<br />
.ends Core_DC<br />
<br />
[[File: DC_to_DC_Transformer_&_Core.gif|right|189px|DC to DC transformer with DC core symbol for aesthetics]]<br />
* DC-to-DC Transformer Equivalent (Netlist Uprocessed):<br />
Xp P 0 C Winding n=1 L=1u Rs=1m Rp=100 ; primary winding of 1:1 transformer<br />
Xs S 0 C Winding n=1 L=1u Rs=1m Rp=100 ; secondary winding of 1:1 transformer<br />
Xc C CoreDC ; subcircuit consisting of 1TΩ in parallel with 1pF<br />
<br />
==== Linear Transformer (linear magnetizing inductance - potentially unlimited energy storage) ====<br />
<br />
A standard linear transformer may easily be created simply by changing the core to a standard inductor with Rs=0.&nbsp; In this form (with a standard ''linear'' magnetizing inductance "core") the model is mostly useful as a perceptual window into the way coupled inductors work in LTspice since linear transformers are more easily and simply built with standard coupled inductors.&nbsp; Note that the magnetizing inductance "core" is the single summing point for the ''ampere-turns'' from all the windings and is the sole source of ''impressed voltage'' (=L*di/dt) reflected onto all the windings.&nbsp; Although this subcircuit is an unnecessary and overly complex representation for a transformer with a linear core inductance, it will be absolutely required if multiple windings are to be "wrapped" onto LTspice's nonlinear Chan inductance model, so take a moment to read it through (the Chan version will follow shortly).<br />
<br />
<br />
* Parametize and wrap an inductor with a subcircuit:<br />
[[File: Linear_Core.gif|right|191px|A linear core is simply an inductor with Rser=0]]<br />
.subckt Core_Linear C params: L=20m Rp=10k Cp=10p<br />
Lc C 0 {L} Rser=0 Rpar={Rp} Cpar={Cp}<br />
.ends Core_Linear<br />
<br />
[[File: Linear_Transformer.gif|right|176px|Transformer with linear core]]<br />
* Linear Transformer Equivalent (Netlist Unprocessed):<br />
Xp P 0 C Winding n=1 L=1u Rs=1m Rp=100 ; primary winding of 1:1 transformer<br />
Xs S 0 C Winding n=1 L=1u Rs=1m Rp=100 ; secondary winding of 1:1 transformer<br />
Xc C Core_Linear L=20m Rp=10k Cp=10p ; subcircuit consisting of an inductor with Rs=0<br />
<br />
* Linear Transformer Equivalent (Netlist Flattened):<br />
[[File: Linear_Transformer_Full.gif|right|438px|Transformer with linear core]]<br />
Lp Ps 1 1u Rser=1m Rpar=100 ; leakage and resistance<br />
Ep 1 Pf C 0 1 ; impose core volts/turn*turns onto winding<br />
Fp 0 C Ep 1 ; impose winding ampere*turns onto core<br />
Lc C 0 20m Rpar=10k Cpar=10p ; liner inductor core (no magnetic saturation)<br />
+ Rser=0 ; Rser must equal zero<br />
Fs 0 C Es 1 ; impose winding ampere*turns onto core<br />
Es 1 Sf C 0 1 ; impose core volts/turn*turns onto winding<br />
Ls Ss 1 1u Rser=1m Rpar=100 ; leakage and resistance<br />
<br />
==== Chan Transformer (saturating magnetizing inductance with hysteresis - limited energy storage) ====<br />
<br />
Now that the windings are separate from the core, a Chan inductor may simply be substituted for the linear inductor core. Since the inductance of a Chan is not assigned, but is determined by its magnetic material, dimensional properties and winding turns, one must adjust inductance by iteratively adjusting the gap and/or winding turns.<br />
<br />
<br />
* Parametize and wrap a Chan inductor with a subcircuit:<br />
[[File: Chan_Core.gif|right|167px|Physical properties based core with hysteresis and saturation]]<br />
.subckt Core_Chan C params:<br />
+ Bs=0.4 Br=0.1 Hc=20 ; Core default magnetic parameters<br />
+ A=25u1 Lm=19m8 Lg=0m7 ; Core default physical parameters<br />
+ Rp=10k Cp=10p ; Core default parallel loss and capacitance<br />
Lc C 0 Rser=0 n=1 ; force Rser=0 and n=1<br />
+ Bs={Bs} Br={Br} Hc={Hc}<br />
+ A={A} Lm={Lm} Lg={Lg}<br />
+ Rpar={Rp} Cpar={Cp}<br />
.ends Core_Chan<br />
<br />
[[File: Chan_Transformer.gif|right|167px|Physically parameterized transformer with hysteresis and saturation]]<br />
* Chan Transformer Equivalent (Netlist Unprocessed):<br />
Xp P 0 C Winding n=100 L=1u Rs=1m Rp=100 ; primary winding of 1:1 transformer<br />
Xs S 0 C Winding n=100 L=1u Rs=1m Rp=100 ; secondary winding of 1:1 transformer<br />
Xc C Core_Chan ; Chan inductor subcircuit with forced Rs=0 and n=1<br />
+ Bs=0.4 Br=0.1 Hc=20 Br=.10 ; Assigned core magnetic parameters<br />
+ A=25u1 Lm=19m8 Lg=0m7 ; Assigned core physical parameters<br />
+ Rp=10k Cp=10p ; Assigned core parallel loss and capacitance<br />
<br />
----<br />
<br />
<br />
'''Temporary Junk'''<br />
<br />
</pre><br />
And here is the same thing using parameters within curly braces to give value to LTspice's extended inductors and to a coupling statement (mutual inductance).&nbsp; Note that there is no need to create a subcircuit with this method because Lp and Ls can be placed directly on the schematic as symbols and K1 and the .param statement may be placed as SPICE text (this is the section of netlist that would then result).&nbsp; The prior subcircuit form (or something like it) only becomes necessary in conjunction with a custom two-winding transformer symbol or if a nonlinear core (magnetizing inductance) model must be used.<br />
<pre><br />
.param Npri=300 Nsec=30 L=1u K=0.95 Rs=1u Rp=10 Cp=1u<br />
+ Np2=Npri**2 Ns2=Nsec**2 ; turns squared for primary and secondary<br />
Lp P1 P2 {L*Np2} Rser={Rs*Np2} Rpar={Rp*Np2} Cpar={Cp/Np2}<br />
Ls S1 S2 {L*Ns2} Rser={Rs*Ns2} Rpar={Rp*Ns2} Cpar={Cp/Ns2}<br />
K1 Lp Ls {K}<br />
</pre><br />
<br />
Knowing the internal workings of LTspice's coupled inductor style transformer is all very interesting, but how do I make something that uses separate standard inductor symbols for winding, yet also uses the Chan core model with full saturation and hysteresis?<br />
<br />
The following method allows this:<br />
<br />
[[File:Separate_Winding.png]]&nbsp; [''obviously, this section is not yet complete'']<br />
<br />
This model uses the standard inductor symbol edited to appear as a winding subcircuit on a core (connected through a global node).&nbsp; The core may be linear or nonlinear (e.g., LTspice's built in Chan model) and may have as many windings as required.&nbsp; Due to the use of a global core node (which must be different for each core), a different subcircuit is required for each core.<br />
<br />
<br />
{{#widget:DISQUS<br />
|id=ltwiki<br />
|uniqid={{PAGENAME}}<br />
|url={{fullurl:{{PAGENAME}}}}<br />
}}</div>Analogspicemanhttp://ltwiki.org/index.php?title=Transformers&diff=2098Transformers2019-11-15T11:18:59Z<p>Analogspiceman: /* I've created an ideal transformer so it should work at all frequencies, even including DC, right? */</p>
<hr />
<div>== Transformers ==<br />
<br />
=== Introduction ===<br />
<br />
Do you wish to study the behavior of transformers and inductors and explore their mysteries?&nbsp; LTspice is the ideal learning tool for this purpose. LTspice will faithfully model both ideal and real magnetic devices.&nbsp; However, caution is advised when first experimenting with unfamiliar concepts in inductors and transformers.&nbsp; Be sure to minimize simulation problems by including reasonably realistic parasitic resistances (both series and parallel) directly into each inductor, whether used individually or as part of a transformer.<br />
<br />
A good learning and reference resource is the [http://coefs.uncc.edu/mnoras/files/2013/03/Transformer-and-Inductor-Design-Handbook_Chapter_17.pdf <i>Transformer and Inductor Design Handbook</i> Chapter 17, Winding Capacitance and Leakage Inductance] 4th Edition by Colonel William. T. McLyman.&nbsp; Mike Engelhardt, the author of LTspice, explains how to make transformers in LTspice in a [https://www.analog.com/en/technical-articles/using-transformers-in-ltspice-switcher-cadiii.html 2006 LT-Magazine article].<br />
<br />
Always keep in mind that starting a simulation with a dc voltage bias on an inductor or transformer winding will cause an initial inductor current only limited by the inductor's series resistance (this would be like trying to initialize an ideal capacitor with a current source - no matter how small the source, the dc voltage will increase without bounds - or at least until the capacitor breaks down).&nbsp; In fact, if you are like most engineers, you are much more comfortable with the behavior of capacitors.&nbsp; If so, use this to your advantage by applying duality to think of what to expect when dealing with inductors.<br />
<br />
=== How do I make a transformer in LTspice? === <br />
<br />
[[File:LTspice_Transformer.gif|right|174px|Two lines were used to draw the core]]<br />
<br />
Although it is very possible to make a dedicated subcircuit for a specific transformer, the preferred method of making a generic transformer when drafting a simulation schematic is to simply place a separate inductor for each separate transformer winding and then couple them all together magnetically via a single ''[[Mutual Inductance]] (K) statement'' placed as a [[SPICE Directive]] on the schematic.&nbsp; Note that inductors called out in a [[Mutual Inductance]] statement will be automatically given a phasing dot if one does not already exist.<br />
<br />
K1 L1 L2 L3 1 ; causes phasing dots to automatically appear on L1-L3 inductor symbols<br />
<br />
When creating a new transformer this way, especially for use in a switched-mode power circuit, it is generally best to first specify the mutual coupling coefficient to be exactly unity.&nbsp; By starting with unity coupling there will be no leakage inductance in any winding and this will minimize the likelihood of the windings ringing at extremely high frequencies (which can slow the simulation to a crawl at each switching edge).&nbsp; However, be aware that a mutual inductance value of plus (or minus) unity ''may'' lead to simulation difficulties if ''Skip-the-initial-operating-point-solution'' (UIC) is specified for the .tran command.&nbsp; Prevent this by specifying a realistic resistance for each inductor "winding" (ctrl-right-mouse-click).&nbsp; Note that when coupled inductors are used as transformer windings, individual winding inductances rather than turns ratios must be specified (''inductance ratios should be set to be proportional to <u>the '''square''' of the turns ratios''</u>).<br />
<br />
=== I've created an ideal transformer so it should work at all frequencies, even including DC, right? ===<br />
<br />
No, but lots of users completely misunderstand or overlook this when setting up their simulation.&nbsp; This common mistake can lead to a lot of needless doubt following unexpected and puzzling simulation results produced by LTspice when presented with an ideal transformer that is inadvertently initialized with a large amount of dc voltage applied to its windings.&nbsp; This is probably the most common self-inflicted pitfall that trips up users improperly specifying ac voltage sources.<br />
<br />
When LTspice calculates initial conditions for voltage sources, it uses the values at time = 0.&nbsp; Depending on the starting phase angle and delay specified for a sine source, this can be as much as the voltage at the peak of the sine wave.&nbsp; When the simulator attempts to find the circuit's initial solution, this is the equivalent to hooking the transformer up to a large dc voltage source.&nbsp; Current will only be limited by winding resistance (which, in the ideal case, may be zero).&nbsp; Note that a real transformer will saturate at a relatively low current and would normally not store much energy (it would also probably burn up with so much dc applied), but an ideal transformer with an ideal magnetizing inductance may store a physically impossible amount of simulated "virtual" energy.<br />
<br />
Without realizing it, many users may instruct LTspice to initialize the transformer magnetizing inductance with huge starting currents.&nbsp; Since they have used an ideal inductance that does not saturate (like a real transformer would), it starts out with dc current that may take many hundreds of line (or switching) cycles to die away.&nbsp; This completely unrealistic energy source then may dominate the simulation, causing strange and unexpectedly puzzling behavior.&nbsp; In such cases, LTspice is just innocently following the instructions given it and accurately computing the results (garbage in, garbage out).<br />
<br />
To avoid this bogus and unwanted result, you must either arrange '''''the ac source to be zero at time zero''''' or '''''instruct LTspice not to use a dc solution for the starting point (UIC).'''''<br />
<br />
=== I want to model leakage inductance - how should I do that? ===<br />
<br />
The most flexible method is to keep the windings' mutual inductance statement at unity and add a small discrete leakage inductance in series with each winding.&nbsp; This is the most straightforward way to model transformers with asymmetrical leakage inductances.&nbsp; However, if your transformer is electrically symmetrical, it may be more convenient to simply set the mutual inductance to a value less than one.&nbsp; For each winding the resulting leakage inductance will be (1-K) times that winding's inductance.&nbsp; Note that each winding's coupled inductance also will decrease to K times that winding's inductance, but for typical values of K (>>0.9) this effect will be very small.<br />
<br />
This is how LTspice "sees" coupled inductors:<br />
<br />
For n inductors coupled together with a K statement, each inductor L1 through Ln is divided into two parts, a completely non-coupled "leakage" inductance equal to (1-K)*Lx (where Lx is the particular inductor in question) and a completely coupled "mutual" inductance equal to K*Lx.&nbsp; Voltage and current ratios of the coupled parts are related by the ratio of the square root of the the inductances L1 through Ln (this is the apparent "turns ratio").<br />
<br />
* For example, given two inductors coupled by a K statement:<br />
[[File:Loosely_Coupled_Transformer.gif|right|153px|Coupling is only K=0.2]]<br />
L1 1 0 1H<br />
L2 2 0 1H<br />
Km L1 L2 0.2<br />
<br />
[[File:Loosely_Coupled_Equivalent.gif|right|182px|"Winding" inductance is 1H]]<br />
<br />
* In LTspice, this is the same as:<br />
L1 1 m 0.8H<br />
Lm m 0 0.2H<br />
L2 2 m 0.8H<br />
<br />
Other engineering conventions regarding the definition of K, coupling and formula for leakage inductance are irrelevant to LTspice.&nbsp; Other formula for leakage inductance are intended to find total leakage inductance from an input winding through to an output winding(s) rather than for each individual winding.<br />
<br />
=== How about transformer saturation effects?&nbsp; Can LTspice model those? ===<br />
<br />
Yes, LTspice comes with a non-linear hysteretic core model built in!&nbsp; This is the 1991 model by John Chan et al.&nbsp; Compared to older core models, [[the Chan model]] is particularly robust, computationally efficient and compact, requiring only three parameters to define most any commonly encountered magnetic hysteresis loop.&nbsp; (LTspice also allows building an arbitrary inductance based on self flux and/or any valid function of node voltages and branch currents.&nbsp; [[The Arbitrary Inductor model|The arbitrary inductor model]] can be very efficiently used to create saturation without hysteresis.) <br />
<br />
Once the core material's generic magnetic properties are set, establishing the circuit-level non-linear inductance requires specifying three more parameters to set the geometry of the specific core and specifying one additional parameter for the core winding turn-count.&nbsp; The Chan inductor <font color="green" title="(has been mentioned as a possibility for a future release)">does not currently</font> directly support [[Mutual Inductance]], so unless only a single-winding inductor is being modeled, multiple windings must be added via additional circuitry.&nbsp; The simplest way to do this is to construct an ideal, unity coupled transformer with as many windings as required and then put the Chan inductor directly in parallel with any one of the windings (taking care to set the turns to match that particular winding).&nbsp; Since the magnetic effects (including non-saturated inductance) are already modeled by the Chan inductor, the inductance of the transformer's parallel winding must be enough larger (>>10) not to significantly load the Chan inductance.&nbsp; As before, the inductances for the other windings should be scaled by the square of their individual turns ratios (with respect to the paralleled winding).<br />
<br />
=== Okay, but calculating winding inductances is tedious.&nbsp; Is there some way to just enter a turns count for all the windings? ===<br />
<br />
Yes, this can be done in any of a number of ways.&nbsp; For example, the values for each of the inductances may be directly parametrized via <font color="green"><b title="Lx node1 node2 {Lm*(Nx/Nm)**2}">curly braces</b></font> to be a function of turns ratios (squared), or a subcircuit that accepts turns as a parameter may be used to encapsulate the windings implementation details.<br />
<br />
* Use parameters to to convert input of winding turns to inductance:<br />
[[File: Parameterized_Transformer.gif|right|304px|Turns are entered as parameters from which the inductance is calculated]]<br />
.param Lp=20m Np=200 Ns=20 ; inputs: primary inductance, primary turns, secondary turns<br />
.param Kn=Lp/Np**2 ; calculated inductance per turn squared<br />
Lp 1 0 {Np**2*Kn} ; primary inductance = 200t**2*Kn<br />
Ls 2 0 {Ns**2*Kn} ; secondary inductance = 20t**2*Kn<br />
Kx Lp Ls 1 ; core coupling factor = 1<br />
<br />
Below is a schematic of a simple LTspice subcircuit that is functionally equivalent to a winding (without a core).&nbsp; Its symbol appears just to the right of the schematic.&nbsp; LTspice's fully extended inductor parasitics are included within this model.&nbsp; Observe that the winding is presented with a voltage equal to the core's volts/turn*primary_turns and that the core is presented with a current equal to the winding's ampere-turns = winding's amps*primary_turns.&nbsp; Also note if the leakage inductance and resistances are zero, the winding is completely floating with respect to the core and that the winding performs a voltage ratio transformation (set by the turns ratio) from DC to light.<br />
<br />
* First, the basic winding: Start (dot), Finish, Core:<br />
[[File: Simple Winding Symbol & Subcircuit.gif|right|479px|This simple subcircuit is equivalent to an inductor or transformer winding]]<br />
.subckt Winding s f c params: n=100 L=1u Rs=1m Rp=100<br />
Lw s 1 {L} Rser={Rs} Rpar={Rp} ; leakage and resistance<br />
Ew 1 f c 0 {n} ; impose core volts/turn*turns onto winding<br />
Fw 0 c Ew {n} ; impose winding amperes*turns onto core<br />
.ends Winding<br />
<br />
<br />
==== DC to DC Transformer (no magnetizing inductance - no energy storage) ====<br />
<br />
The transformer winding subcircuits are DC coupled and, when connected to a "core" (1TΩ in parallel with 1pF) that supports DC without drawing current, they combine to make a transformer that draws no magnetizing current, stores no energy and therefore is immune to errant initial conditions.&nbsp; This may be an advantage when first experimenting with new power circuits.<br />
<br />
For better cosmetics the simple DC core may encapsulated in its own subcircuit and symbol.&nbsp;<br />
<br />
[[File: DC_to_DC_Transformer.gif|right|190px|DC to DC (because of "core") transformer with two windings]]<br />
* Here is a DC "core" that does not draw increasing current with time:<br />
.subckt Core_DC C<br />
Cc C 0 1p Rpar=1T ; dump the "core's" ampere-turns into a small conductance<br />
.ends Core_DC<br />
<br />
[[File: DC_to_DC_Transformer_&_Core.gif|right|189px|DC to DC transformer with DC core symbol for aesthetics]]<br />
* DC-to-DC Transformer Equivalent (Netlist Uprocessed):<br />
Xp P 0 C Winding n=1 L=1u Rs=1m Rp=100 ; primary winding of 1:1 transformer<br />
Xs S 0 C Winding n=1 L=1u Rs=1m Rp=100 ; secondary winding of 1:1 transformer<br />
Xc C CoreDC ; subcircuit consisting of 1TΩ in parallel with 1pF<br />
<br />
==== Linear Transformer (linear magnetizing inductance - potentially unlimited energy storage) ====<br />
<br />
A standard linear transformer may easily be created simply by changing the core to a standard inductor with Rs=0.&nbsp; In this form (with a standard ''linear'' magnetizing inductance "core") the model is mostly useful as a perceptual window into the way coupled inductors work in LTspice since linear transformers are more easily and simply built with standard coupled inductors.&nbsp; Note that the magnetizing inductance "core" is the single summing point for the ''ampere-turns'' from all the windings and is the sole source of ''impressed voltage'' (=L*di/dt) reflected onto all the windings.&nbsp; Although this subcircuit is an unnecessary and overly complex representation for a transformer with a linear core inductance, it will be absolutely required if multiple windings are to be "wrapped" onto LTspice's nonlinear Chan inductance model, so take a moment to read it through (the Chan version will follow shortly).<br />
<br />
<br />
* Parametize and wrap an inductor with a subcircuit:<br />
[[File: Linear_Core.gif|right|191px|A linear core is simply an inductor with Rser=0]]<br />
.subckt Core_Linear C params: L=20m Rp=10k Cp=10p<br />
Lc C 0 {L} Rser=0 Rpar={Rp} Cpar={Cp}<br />
.ends Core_Linear<br />
<br />
[[File: Linear_Transformer.gif|right|176px|Transformer with linear core]]<br />
* Linear Transformer Equivalent (Netlist Unprocessed):<br />
Xp P 0 C Winding n=1 L=1u Rs=1m Rp=100 ; primary winding of 1:1 transformer<br />
Xs S 0 C Winding n=1 L=1u Rs=1m Rp=100 ; secondary winding of 1:1 transformer<br />
Xc C Core_Linear L=20m Rp=10k Cp=10p ; subcircuit consisting of an inductor with Rs=0<br />
<br />
* Linear Transformer Equivalent (Netlist Flattened):<br />
[[File: Linear_Transformer_Full.gif|right|438px|Transformer with linear core]]<br />
Lp Ps 1 1u Rser=1m Rpar=100 ; leakage and resistance<br />
Ep 1 Pf C 0 1 ; impose core volts/turn*turns onto winding<br />
Fp 0 C Ep 1 ; impose winding ampere*turns onto core<br />
Lc C 0 20m Rpar=10k Cpar=10p ; liner inductor core (no magnetic saturation)<br />
+ Rser=0 ; Rser must equal zero<br />
Fs 0 C Es 1 ; impose winding ampere*turns onto core<br />
Es 1 Sf C 0 1 ; impose core volts/turn*turns onto winding<br />
Ls Ss 1 1u Rser=1m Rpar=100 ; leakage and resistance<br />
<br />
==== Chan Transformer (saturating magnetizing inductance with hysteresis - limited energy storage) ====<br />
<br />
Now that the windings are separate from the core, a Chan inductor may simply be substituted for the linear inductor core. Since the inductance of a Chan is not assigned, but is determined by its magnetic material, dimensional properties and winding turns, one must adjust inductance by iteratively adjusting the gap and/or winding turns.<br />
<br />
<br />
* Parametize and wrap a Chan inductor with a subcircuit:<br />
[[File: Chan_Core.gif|right|167px|Physical properties based core with hysteresis and saturation]]<br />
.subckt Core_Chan C params:<br />
+ Bs=0.4 Br=0.1 Hc=20 ; Core default magnetic parameters<br />
+ A=25u1 Lm=19m8 Lg=0m7 ; Core default physical parameters<br />
+ Rp=10k Cp=10p ; Core default parallel loss and capacitance<br />
Lc C 0 Rser=0 n=1 ; force Rser=0 and n=1<br />
+ Bs={Bs} Br={Br} Hc={Hc}<br />
+ A={A} Lm={Lm} Lg={Lg}<br />
+ Rpar={Rp} Cpar={Cp}<br />
.ends Core_Chan<br />
<br />
[[File: Chan_Transformer.gif|right|167px|Physically parameterized transformer with hysteresis and saturation]]<br />
* Chan Transformer Equivalent (Netlist Unprocessed):<br />
Xp P 0 C Winding n=100 L=1u Rs=1m Rp=100 ; primary winding of 1:1 transformer<br />
Xs S 0 C Winding n=100 L=1u Rs=1m Rp=100 ; secondary winding of 1:1 transformer<br />
Xc C Core_Chan ; Chan inductor subcircuit with forced Rs=0 and n=1<br />
+ Bs=0.4 Br=0.1 Hc=20 Br=.10 ; Assigned core magnetic parameters<br />
+ A=25u1 Lm=19m8 Lg=0m7 ; Assigned core physical parameters<br />
+ Rp=10k Cp=10p ; Assigned core parallel loss and capacitance<br />
<br />
----<br />
<br />
<br />
'''Temporary Junk'''<br />
<br />
</pre><br />
And here is the same thing using parameters within curly braces to give value to LTspice's extended inductors and to a coupling statement (mutual inductance).&nbsp; Note that there is no need to create a subcircuit with this method because Lp and Ls can be placed directly on the schematic as symbols and K1 and the .param statement may be placed as SPICE text (this is the section of netlist that would then result).&nbsp; The prior subcircuit form (or something like it) only becomes necessary in conjunction with a custom two-winding transformer symbol or if a nonlinear core (magnetizing inductance) model must be used.<br />
<pre><br />
.param Npri=300 Nsec=30 L=1u K=0.95 Rs=1u Rp=10 Cp=1u<br />
+ Np2=Npri**2 Ns2=Nsec**2 ; turns squared for primary and secondary<br />
Lp P1 P2 {L*Np2} Rser={Rs*Np2} Rpar={Rp*Np2} Cpar={Cp/Np2}<br />
Ls S1 S2 {L*Ns2} Rser={Rs*Ns2} Rpar={Rp*Ns2} Cpar={Cp/Ns2}<br />
K1 Lp Ls {K}<br />
</pre><br />
<br />
Knowing the internal workings of LTspice's coupled inductor style transformer is all very interesting, but how do I make something that uses separate standard inductor symbols for winding, yet also uses the Chan core model with full saturation and hysteresis?<br />
<br />
The following method allows this:<br />
<br />
[[File:Separate_Winding.png]]&nbsp; [''obviously, this section is not yet complete'']<br />
<br />
This model uses the standard inductor symbol edited to appear as a winding subcircuit on a core (connected through a global node).&nbsp; The core may be linear or nonlinear (e.g., LTspice's built in Chan model) and may have as many windings as required.&nbsp; Due to the use of a global core node (which must be different for each core), a different subcircuit is required for each core.<br />
<br />
<br />
{{#widget:DISQUS<br />
|id=ltwiki<br />
|uniqid={{PAGENAME}}<br />
|url={{fullurl:{{PAGENAME}}}}<br />
}}</div>Analogspicemanhttp://ltwiki.org/index.php?title=Transformers&diff=2097Transformers2019-11-15T10:37:35Z<p>Analogspiceman: /* I've created an ideal transformer so it should work at all frequencies, even including DC, right? */</p>
<hr />
<div>== Transformers ==<br />
<br />
=== Introduction ===<br />
<br />
Do you wish to study the behavior of transformers and inductors and explore their mysteries?&nbsp; LTspice is the ideal learning tool for this purpose. LTspice will faithfully model both ideal and real magnetic devices.&nbsp; However, caution is advised when first experimenting with unfamiliar concepts in inductors and transformers.&nbsp; Be sure to minimize simulation problems by including reasonably realistic parasitic resistances (both series and parallel) directly into each inductor, whether used individually or as part of a transformer.<br />
<br />
A good learning and reference resource is the [http://coefs.uncc.edu/mnoras/files/2013/03/Transformer-and-Inductor-Design-Handbook_Chapter_17.pdf <i>Transformer and Inductor Design Handbook</i> Chapter 17, Winding Capacitance and Leakage Inductance] 4th Edition by Colonel William. T. McLyman.&nbsp; Mike Engelhardt, the author of LTspice, explains how to make transformers in LTspice in a [https://www.analog.com/en/technical-articles/using-transformers-in-ltspice-switcher-cadiii.html 2006 LT-Magazine article].<br />
<br />
Always keep in mind that starting a simulation with a dc voltage bias on an inductor or transformer winding will cause an initial inductor current only limited by the inductor's series resistance (this would be like trying to initialize an ideal capacitor with a current source - no matter how small the source, the dc voltage will increase without bounds - or at least until the capacitor breaks down).&nbsp; In fact, if you are like most engineers, you are much more comfortable with the behavior of capacitors.&nbsp; If so, use this to your advantage by applying duality to think of what to expect when dealing with inductors.<br />
<br />
=== How do I make a transformer in LTspice? === <br />
<br />
[[File:LTspice_Transformer.gif|right|174px|Two lines were used to draw the core]]<br />
<br />
Although it is very possible to make a dedicated subcircuit for a specific transformer, the preferred method of making a generic transformer when drafting a simulation schematic is to simply place a separate inductor for each separate transformer winding and then couple them all together magnetically via a single ''[[Mutual Inductance]] (K) statement'' placed as a [[SPICE Directive]] on the schematic.&nbsp; Note that inductors called out in a [[Mutual Inductance]] statement will be automatically given a phasing dot if one does not already exist.<br />
<br />
K1 L1 L2 L3 1 ; causes phasing dots to automatically appear on L1-L3 inductor symbols<br />
<br />
When creating a new transformer this way, especially for use in a switched-mode power circuit, it is generally best to first specify the mutual coupling coefficient to be exactly unity.&nbsp; By starting with unity coupling there will be no leakage inductance in any winding and this will minimize the likelihood of the windings ringing at extremely high frequencies (which can slow the simulation to a crawl at each switching edge).&nbsp; However, be aware that a mutual inductance value of plus (or minus) unity ''may'' lead to simulation difficulties if ''Skip-the-initial-operating-point-solution'' (UIC) is specified for the .tran command.&nbsp; Prevent this by specifying a realistic resistance for each inductor "winding" (ctrl-right-mouse-click).&nbsp; Note that when coupled inductors are used as transformer windings, individual winding inductances rather than turns ratios must be specified (''inductance ratios should be set to be proportional to <u>the '''square''' of the turns ratios''</u>).<br />
<br />
=== I've created an ideal transformer so it should work at all frequencies, even including DC, right? ===<br />
<br />
No, but lots of users completely misunderstand or overlook this when setting up their simulation.&nbsp; This common mistake can lead to a lot of needless doubt following unexpected and puzzling simulation results produced by LTspice when presented with an ideal transformer that is inadvertently initialized with a large amount of dc voltage applied to its windings.&nbsp; This is probably the most common self-inflicted pitfall that trips up users improperly specifying ac voltage sources.<br />
<br />
When LTspice calculates initial conditions for voltage sources, it uses the values at time = 0.&nbsp; Depending on the starting phase angle and delay specified for a sine source, this can be as much as the voltage at the peak of the sine wave.&nbsp; When the simulator attempts to find the circuit's initial solution, this is the equivalent to hooking the transformer up to a large dc voltage source.&nbsp; Current will only be limited by winding resistance (which, in the ideal case, may be zero).&nbsp; Note that a real transformer will saturate at a relatively low current and would normally not store much energy (it would also probably burn up with so much dc applied), but an ideal transformer with an ideal magnetizing inductance may store a physically impossible amount of simulated "virtual" energy.<br />
<br />
Without realizing it, many users may instruct LTspice to initialize the transformer magnetizing inductance with huge starting currents.&nbsp; Since they have used an ideal inductance that does not saturate (like a real transformer would), it starts out with dc current that may take many hundreds of line (or switching) cycles to die away.&nbsp; This completely unrealistic energy source then may dominate the simulation, causing strange and unexpected puzzling behavior.&nbsp; In such cases, LTspice is just innocently following the instructions given it and accurately computing the results (garbage in, garbage out).<br />
<br />
To avoid this bogus and unwanted result, you must either arrange '''''the ac source to be zero at time zero''''' or '''''instruct LTspice not to use a dc solution for the starting point (UIC).'''''<br />
<br />
=== I want to model leakage inductance - how should I do that? ===<br />
<br />
The most flexible method is to keep the windings' mutual inductance statement at unity and add a small discrete leakage inductance in series with each winding.&nbsp; This is the most straightforward way to model transformers with asymmetrical leakage inductances.&nbsp; However, if your transformer is electrically symmetrical, it may be more convenient to simply set the mutual inductance to a value less than one.&nbsp; For each winding the resulting leakage inductance will be (1-K) times that winding's inductance.&nbsp; Note that each winding's coupled inductance also will decrease to K times that winding's inductance, but for typical values of K (>>0.9) this effect will be very small.<br />
<br />
This is how LTspice "sees" coupled inductors:<br />
<br />
For n inductors coupled together with a K statement, each inductor L1 through Ln is divided into two parts, a completely non-coupled "leakage" inductance equal to (1-K)*Lx (where Lx is the particular inductor in question) and a completely coupled "mutual" inductance equal to K*Lx.&nbsp; Voltage and current ratios of the coupled parts are related by the ratio of the square root of the the inductances L1 through Ln (this is the apparent "turns ratio").<br />
<br />
* For example, given two inductors coupled by a K statement:<br />
[[File:Loosely_Coupled_Transformer.gif|right|153px|Coupling is only K=0.2]]<br />
L1 1 0 1H<br />
L2 2 0 1H<br />
Km L1 L2 0.2<br />
<br />
[[File:Loosely_Coupled_Equivalent.gif|right|182px|"Winding" inductance is 1H]]<br />
<br />
* In LTspice, this is the same as:<br />
L1 1 m 0.8H<br />
Lm m 0 0.2H<br />
L2 2 m 0.8H<br />
<br />
Other engineering conventions regarding the definition of K, coupling and formula for leakage inductance are irrelevant to LTspice.&nbsp; Other formula for leakage inductance are intended to find total leakage inductance from an input winding through to an output winding(s) rather than for each individual winding.<br />
<br />
=== How about transformer saturation effects?&nbsp; Can LTspice model those? ===<br />
<br />
Yes, LTspice comes with a non-linear hysteretic core model built in!&nbsp; This is the 1991 model by John Chan et al.&nbsp; Compared to older core models, [[the Chan model]] is particularly robust, computationally efficient and compact, requiring only three parameters to define most any commonly encountered magnetic hysteresis loop.&nbsp; (LTspice also allows building an arbitrary inductance based on self flux and/or any valid function of node voltages and branch currents.&nbsp; [[The Arbitrary Inductor model|The arbitrary inductor model]] can be very efficiently used to create saturation without hysteresis.) <br />
<br />
Once the core material's generic magnetic properties are set, establishing the circuit-level non-linear inductance requires specifying three more parameters to set the geometry of the specific core and specifying one additional parameter for the core winding turn-count.&nbsp; The Chan inductor <font color="green" title="(has been mentioned as a possibility for a future release)">does not currently</font> directly support [[Mutual Inductance]], so unless only a single-winding inductor is being modeled, multiple windings must be added via additional circuitry.&nbsp; The simplest way to do this is to construct an ideal, unity coupled transformer with as many windings as required and then put the Chan inductor directly in parallel with any one of the windings (taking care to set the turns to match that particular winding).&nbsp; Since the magnetic effects (including non-saturated inductance) are already modeled by the Chan inductor, the inductance of the transformer's parallel winding must be enough larger (>>10) not to significantly load the Chan inductance.&nbsp; As before, the inductances for the other windings should be scaled by the square of their individual turns ratios (with respect to the paralleled winding).<br />
<br />
=== Okay, but calculating winding inductances is tedious.&nbsp; Is there some way to just enter a turns count for all the windings? ===<br />
<br />
Yes, this can be done in any of a number of ways.&nbsp; For example, the values for each of the inductances may be directly parametrized via <font color="green"><b title="Lx node1 node2 {Lm*(Nx/Nm)**2}">curly braces</b></font> to be a function of turns ratios (squared), or a subcircuit that accepts turns as a parameter may be used to encapsulate the windings implementation details.<br />
<br />
* Use parameters to to convert input of winding turns to inductance:<br />
[[File: Parameterized_Transformer.gif|right|304px|Turns are entered as parameters from which the inductance is calculated]]<br />
.param Lp=20m Np=200 Ns=20 ; inputs: primary inductance, primary turns, secondary turns<br />
.param Kn=Lp/Np**2 ; calculated inductance per turn squared<br />
Lp 1 0 {Np**2*Kn} ; primary inductance = 200t**2*Kn<br />
Ls 2 0 {Ns**2*Kn} ; secondary inductance = 20t**2*Kn<br />
Kx Lp Ls 1 ; core coupling factor = 1<br />
<br />
Below is a schematic of a simple LTspice subcircuit that is functionally equivalent to a winding (without a core).&nbsp; Its symbol appears just to the right of the schematic.&nbsp; LTspice's fully extended inductor parasitics are included within this model.&nbsp; Observe that the winding is presented with a voltage equal to the core's volts/turn*primary_turns and that the core is presented with a current equal to the winding's ampere-turns = winding's amps*primary_turns.&nbsp; Also note if the leakage inductance and resistances are zero, the winding is completely floating with respect to the core and that the winding performs a voltage ratio transformation (set by the turns ratio) from DC to light.<br />
<br />
* First, the basic winding: Start (dot), Finish, Core:<br />
[[File: Simple Winding Symbol & Subcircuit.gif|right|479px|This simple subcircuit is equivalent to an inductor or transformer winding]]<br />
.subckt Winding s f c params: n=100 L=1u Rs=1m Rp=100<br />
Lw s 1 {L} Rser={Rs} Rpar={Rp} ; leakage and resistance<br />
Ew 1 f c 0 {n} ; impose core volts/turn*turns onto winding<br />
Fw 0 c Ew {n} ; impose winding amperes*turns onto core<br />
.ends Winding<br />
<br />
<br />
==== DC to DC Transformer (no magnetizing inductance - no energy storage) ====<br />
<br />
The transformer winding subcircuits are DC coupled and, when connected to a "core" (1TΩ in parallel with 1pF) that supports DC without drawing current, they combine to make a transformer that draws no magnetizing current, stores no energy and therefore is immune to errant initial conditions.&nbsp; This may be an advantage when first experimenting with new power circuits.<br />
<br />
For better cosmetics the simple DC core may encapsulated in its own subcircuit and symbol.&nbsp;<br />
<br />
[[File: DC_to_DC_Transformer.gif|right|190px|DC to DC (because of "core") transformer with two windings]]<br />
* Here is a DC "core" that does not draw increasing current with time:<br />
.subckt Core_DC C<br />
Cc C 0 1p Rpar=1T ; dump the "core's" ampere-turns into a small conductance<br />
.ends Core_DC<br />
<br />
[[File: DC_to_DC_Transformer_&_Core.gif|right|189px|DC to DC transformer with DC core symbol for aesthetics]]<br />
* DC-to-DC Transformer Equivalent (Netlist Uprocessed):<br />
Xp P 0 C Winding n=1 L=1u Rs=1m Rp=100 ; primary winding of 1:1 transformer<br />
Xs S 0 C Winding n=1 L=1u Rs=1m Rp=100 ; secondary winding of 1:1 transformer<br />
Xc C CoreDC ; subcircuit consisting of 1TΩ in parallel with 1pF<br />
<br />
==== Linear Transformer (linear magnetizing inductance - potentially unlimited energy storage) ====<br />
<br />
A standard linear transformer may easily be created simply by changing the core to a standard inductor with Rs=0.&nbsp; In this form (with a standard ''linear'' magnetizing inductance "core") the model is mostly useful as a perceptual window into the way coupled inductors work in LTspice since linear transformers are more easily and simply built with standard coupled inductors.&nbsp; Note that the magnetizing inductance "core" is the single summing point for the ''ampere-turns'' from all the windings and is the sole source of ''impressed voltage'' (=L*di/dt) reflected onto all the windings.&nbsp; Although this subcircuit is an unnecessary and overly complex representation for a transformer with a linear core inductance, it will be absolutely required if multiple windings are to be "wrapped" onto LTspice's nonlinear Chan inductance model, so take a moment to read it through (the Chan version will follow shortly).<br />
<br />
<br />
* Parametize and wrap an inductor with a subcircuit:<br />
[[File: Linear_Core.gif|right|191px|A linear core is simply an inductor with Rser=0]]<br />
.subckt Core_Linear C params: L=20m Rp=10k Cp=10p<br />
Lc C 0 {L} Rser=0 Rpar={Rp} Cpar={Cp}<br />
.ends Core_Linear<br />
<br />
[[File: Linear_Transformer.gif|right|176px|Transformer with linear core]]<br />
* Linear Transformer Equivalent (Netlist Unprocessed):<br />
Xp P 0 C Winding n=1 L=1u Rs=1m Rp=100 ; primary winding of 1:1 transformer<br />
Xs S 0 C Winding n=1 L=1u Rs=1m Rp=100 ; secondary winding of 1:1 transformer<br />
Xc C Core_Linear L=20m Rp=10k Cp=10p ; subcircuit consisting of an inductor with Rs=0<br />
<br />
* Linear Transformer Equivalent (Netlist Flattened):<br />
[[File: Linear_Transformer_Full.gif|right|438px|Transformer with linear core]]<br />
Lp Ps 1 1u Rser=1m Rpar=100 ; leakage and resistance<br />
Ep 1 Pf C 0 1 ; impose core volts/turn*turns onto winding<br />
Fp 0 C Ep 1 ; impose winding ampere*turns onto core<br />
Lc C 0 20m Rpar=10k Cpar=10p ; liner inductor core (no magnetic saturation)<br />
+ Rser=0 ; Rser must equal zero<br />
Fs 0 C Es 1 ; impose winding ampere*turns onto core<br />
Es 1 Sf C 0 1 ; impose core volts/turn*turns onto winding<br />
Ls Ss 1 1u Rser=1m Rpar=100 ; leakage and resistance<br />
<br />
==== Chan Transformer (saturating magnetizing inductance with hysteresis - limited energy storage) ====<br />
<br />
Now that the windings are separate from the core, a Chan inductor may simply be substituted for the linear inductor core. Since the inductance of a Chan is not assigned, but is determined by its magnetic material, dimensional properties and winding turns, one must adjust inductance by iteratively adjusting the gap and/or winding turns.<br />
<br />
<br />
* Parametize and wrap a Chan inductor with a subcircuit:<br />
[[File: Chan_Core.gif|right|167px|Physical properties based core with hysteresis and saturation]]<br />
.subckt Core_Chan C params:<br />
+ Bs=0.4 Br=0.1 Hc=20 ; Core default magnetic parameters<br />
+ A=25u1 Lm=19m8 Lg=0m7 ; Core default physical parameters<br />
+ Rp=10k Cp=10p ; Core default parallel loss and capacitance<br />
Lc C 0 Rser=0 n=1 ; force Rser=0 and n=1<br />
+ Bs={Bs} Br={Br} Hc={Hc}<br />
+ A={A} Lm={Lm} Lg={Lg}<br />
+ Rpar={Rp} Cpar={Cp}<br />
.ends Core_Chan<br />
<br />
[[File: Chan_Transformer.gif|right|167px|Physically parameterized transformer with hysteresis and saturation]]<br />
* Chan Transformer Equivalent (Netlist Unprocessed):<br />
Xp P 0 C Winding n=100 L=1u Rs=1m Rp=100 ; primary winding of 1:1 transformer<br />
Xs S 0 C Winding n=100 L=1u Rs=1m Rp=100 ; secondary winding of 1:1 transformer<br />
Xc C Core_Chan ; Chan inductor subcircuit with forced Rs=0 and n=1<br />
+ Bs=0.4 Br=0.1 Hc=20 Br=.10 ; Assigned core magnetic parameters<br />
+ A=25u1 Lm=19m8 Lg=0m7 ; Assigned core physical parameters<br />
+ Rp=10k Cp=10p ; Assigned core parallel loss and capacitance<br />
<br />
----<br />
<br />
<br />
'''Temporary Junk'''<br />
<br />
</pre><br />
And here is the same thing using parameters within curly braces to give value to LTspice's extended inductors and to a coupling statement (mutual inductance).&nbsp; Note that there is no need to create a subcircuit with this method because Lp and Ls can be placed directly on the schematic as symbols and K1 and the .param statement may be placed as SPICE text (this is the section of netlist that would then result).&nbsp; The prior subcircuit form (or something like it) only becomes necessary in conjunction with a custom two-winding transformer symbol or if a nonlinear core (magnetizing inductance) model must be used.<br />
<pre><br />
.param Npri=300 Nsec=30 L=1u K=0.95 Rs=1u Rp=10 Cp=1u<br />
+ Np2=Npri**2 Ns2=Nsec**2 ; turns squared for primary and secondary<br />
Lp P1 P2 {L*Np2} Rser={Rs*Np2} Rpar={Rp*Np2} Cpar={Cp/Np2}<br />
Ls S1 S2 {L*Ns2} Rser={Rs*Ns2} Rpar={Rp*Ns2} Cpar={Cp/Ns2}<br />
K1 Lp Ls {K}<br />
</pre><br />
<br />
Knowing the internal workings of LTspice's coupled inductor style transformer is all very interesting, but how do I make something that uses separate standard inductor symbols for winding, yet also uses the Chan core model with full saturation and hysteresis?<br />
<br />
The following method allows this:<br />
<br />
[[File:Separate_Winding.png]]&nbsp; [''obviously, this section is not yet complete'']<br />
<br />
This model uses the standard inductor symbol edited to appear as a winding subcircuit on a core (connected through a global node).&nbsp; The core may be linear or nonlinear (e.g., LTspice's built in Chan model) and may have as many windings as required.&nbsp; Due to the use of a global core node (which must be different for each core), a different subcircuit is required for each core.<br />
<br />
<br />
{{#widget:DISQUS<br />
|id=ltwiki<br />
|uniqid={{PAGENAME}}<br />
|url={{fullurl:{{PAGENAME}}}}<br />
}}</div>Analogspicemanhttp://ltwiki.org/index.php?title=Transformers&diff=2096Transformers2019-11-14T19:31:41Z<p>Analogspiceman: /* Introduction */ edited wording for readability</p>
<hr />
<div>== Transformers ==<br />
<br />
=== Introduction ===<br />
<br />
Do you wish to study the behavior of transformers and inductors and explore their mysteries?&nbsp; LTspice is the ideal learning tool for this purpose. LTspice will faithfully model both ideal and real magnetic devices.&nbsp; However, caution is advised when first experimenting with unfamiliar concepts in inductors and transformers.&nbsp; Be sure to minimize simulation problems by including reasonably realistic parasitic resistances (both series and parallel) directly into each inductor, whether used individually or as part of a transformer.<br />
<br />
A good learning and reference resource is the [http://coefs.uncc.edu/mnoras/files/2013/03/Transformer-and-Inductor-Design-Handbook_Chapter_17.pdf <i>Transformer and Inductor Design Handbook</i> Chapter 17, Winding Capacitance and Leakage Inductance] 4th Edition by Colonel William. T. McLyman.&nbsp; Mike Engelhardt, the author of LTspice, explains how to make transformers in LTspice in a [https://www.analog.com/en/technical-articles/using-transformers-in-ltspice-switcher-cadiii.html 2006 LT-Magazine article].<br />
<br />
Always keep in mind that starting a simulation with a dc voltage bias on an inductor or transformer winding will cause an initial inductor current only limited by the inductor's series resistance (this would be like trying to initialize an ideal capacitor with a current source - no matter how small the source, the dc voltage will increase without bounds - or at least until the capacitor breaks down).&nbsp; In fact, if you are like most engineers, you are much more comfortable with the behavior of capacitors.&nbsp; If so, use this to your advantage by applying duality to think of what to expect when dealing with inductors.<br />
<br />
=== How do I make a transformer in LTspice? === <br />
<br />
[[File:LTspice_Transformer.gif|right|174px|Two lines were used to draw the core]]<br />
<br />
Although it is very possible to make a dedicated subcircuit for a specific transformer, the preferred method of making a generic transformer when drafting a simulation schematic is to simply place a separate inductor for each separate transformer winding and then couple them all together magnetically via a single ''[[Mutual Inductance]] (K) statement'' placed as a [[SPICE Directive]] on the schematic.&nbsp; Note that inductors called out in a [[Mutual Inductance]] statement will be automatically given a phasing dot if one does not already exist.<br />
<br />
K1 L1 L2 L3 1 ; causes phasing dots to automatically appear on L1-L3 inductor symbols<br />
<br />
When creating a new transformer this way, especially for use in a switched-mode power circuit, it is generally best to first specify the mutual coupling coefficient to be exactly unity.&nbsp; By starting with unity coupling there will be no leakage inductance in any winding and this will minimize the likelihood of the windings ringing at extremely high frequencies (which can slow the simulation to a crawl at each switching edge).&nbsp; However, be aware that a mutual inductance value of plus (or minus) unity ''may'' lead to simulation difficulties if ''Skip-the-initial-operating-point-solution'' (UIC) is specified for the .tran command.&nbsp; Prevent this by specifying a realistic resistance for each inductor "winding" (ctrl-right-mouse-click).&nbsp; Note that when coupled inductors are used as transformer windings, individual winding inductances rather than turns ratios must be specified (''inductance ratios should be set to be proportional to <u>the '''square''' of the turns ratios''</u>).<br />
<br />
=== I've created an ideal transformer so it should work at all frequencies, even including DC, right? ===<br />
<br />
No, but lots of users completely misunderstand or overlook this when setting up their simulation.&nbsp; This common mistake can lead to a lot of needless doubt following unexpected and puzzling simulation results produced by LTspice when presented with an ideal transformer that is inadvertently initialized with a large amount of dc voltage applied to its windings.&nbsp; This is probably the most commonly self-inflicted pitfall that trips up users improperly specifying ac voltage sources.<br />
<br />
When LTspice calculates initial conditions for voltage sources, it uses the values at time = 0.&nbsp; Depending on the starting phase angle and delay specified for a sine source, this can be as much as the voltage at the peak of the sine wave.&nbsp; When the simulator attempts to find the circuit's initial solution, this is the equivalent to hooking the transformer up to a large dc voltage source.&nbsp; Current will only be limited by winding resistance (which, in the ideal case, may be zero).&nbsp; Note that a real transformer will saturate at a relatively low current and would normally not store much energy (it would also probably burn up with so much dc applied), but an ideal transformer with an ideal magnetizing inductance may store a physically impossible amount of simulated "virtual" energy.<br />
<br />
Without realizing it, many users may instruct LTspice to initialize the transformer magnetizing inductance with huge starting currents.&nbsp; Since they have used an ideal inductance that does not saturate (like a real transformer would), it starts out with dc current that may take many hundreds of line (or switching) cycles to die away.&nbsp; This completely unrealistic energy source then may dominate the simulation, causing strange and unexpected puzzling behavior.&nbsp; In such cases, LTspice is just innocently following the instructions given it and accurately computing the results (garbage in, garbage out).<br />
<br />
To avoid this bogus and unwanted result, you must either arrange '''''the ac source to be zero at time zero''''' or '''''instruct LTspice not to use a dc solution for the starting point (UIC).'''''<br />
<br />
=== I want to model leakage inductance - how should I do that? ===<br />
<br />
The most flexible method is to keep the windings' mutual inductance statement at unity and add a small discrete leakage inductance in series with each winding.&nbsp; This is the most straightforward way to model transformers with asymmetrical leakage inductances.&nbsp; However, if your transformer is electrically symmetrical, it may be more convenient to simply set the mutual inductance to a value less than one.&nbsp; For each winding the resulting leakage inductance will be (1-K) times that winding's inductance.&nbsp; Note that each winding's coupled inductance also will decrease to K times that winding's inductance, but for typical values of K (>>0.9) this effect will be very small.<br />
<br />
This is how LTspice "sees" coupled inductors:<br />
<br />
For n inductors coupled together with a K statement, each inductor L1 through Ln is divided into two parts, a completely non-coupled "leakage" inductance equal to (1-K)*Lx (where Lx is the particular inductor in question) and a completely coupled "mutual" inductance equal to K*Lx.&nbsp; Voltage and current ratios of the coupled parts are related by the ratio of the square root of the the inductances L1 through Ln (this is the apparent "turns ratio").<br />
<br />
* For example, given two inductors coupled by a K statement:<br />
[[File:Loosely_Coupled_Transformer.gif|right|153px|Coupling is only K=0.2]]<br />
L1 1 0 1H<br />
L2 2 0 1H<br />
Km L1 L2 0.2<br />
<br />
[[File:Loosely_Coupled_Equivalent.gif|right|182px|"Winding" inductance is 1H]]<br />
<br />
* In LTspice, this is the same as:<br />
L1 1 m 0.8H<br />
Lm m 0 0.2H<br />
L2 2 m 0.8H<br />
<br />
Other engineering conventions regarding the definition of K, coupling and formula for leakage inductance are irrelevant to LTspice.&nbsp; Other formula for leakage inductance are intended to find total leakage inductance from an input winding through to an output winding(s) rather than for each individual winding.<br />
<br />
=== How about transformer saturation effects?&nbsp; Can LTspice model those? ===<br />
<br />
Yes, LTspice comes with a non-linear hysteretic core model built in!&nbsp; This is the 1991 model by John Chan et al.&nbsp; Compared to older core models, [[the Chan model]] is particularly robust, computationally efficient and compact, requiring only three parameters to define most any commonly encountered magnetic hysteresis loop.&nbsp; (LTspice also allows building an arbitrary inductance based on self flux and/or any valid function of node voltages and branch currents.&nbsp; [[The Arbitrary Inductor model|The arbitrary inductor model]] can be very efficiently used to create saturation without hysteresis.) <br />
<br />
Once the core material's generic magnetic properties are set, establishing the circuit-level non-linear inductance requires specifying three more parameters to set the geometry of the specific core and specifying one additional parameter for the core winding turn-count.&nbsp; The Chan inductor <font color="green" title="(has been mentioned as a possibility for a future release)">does not currently</font> directly support [[Mutual Inductance]], so unless only a single-winding inductor is being modeled, multiple windings must be added via additional circuitry.&nbsp; The simplest way to do this is to construct an ideal, unity coupled transformer with as many windings as required and then put the Chan inductor directly in parallel with any one of the windings (taking care to set the turns to match that particular winding).&nbsp; Since the magnetic effects (including non-saturated inductance) are already modeled by the Chan inductor, the inductance of the transformer's parallel winding must be enough larger (>>10) not to significantly load the Chan inductance.&nbsp; As before, the inductances for the other windings should be scaled by the square of their individual turns ratios (with respect to the paralleled winding).<br />
<br />
=== Okay, but calculating winding inductances is tedious.&nbsp; Is there some way to just enter a turns count for all the windings? ===<br />
<br />
Yes, this can be done in any of a number of ways.&nbsp; For example, the values for each of the inductances may be directly parametrized via <font color="green"><b title="Lx node1 node2 {Lm*(Nx/Nm)**2}">curly braces</b></font> to be a function of turns ratios (squared), or a subcircuit that accepts turns as a parameter may be used to encapsulate the windings implementation details.<br />
<br />
* Use parameters to to convert input of winding turns to inductance:<br />
[[File: Parameterized_Transformer.gif|right|304px|Turns are entered as parameters from which the inductance is calculated]]<br />
.param Lp=20m Np=200 Ns=20 ; inputs: primary inductance, primary turns, secondary turns<br />
.param Kn=Lp/Np**2 ; calculated inductance per turn squared<br />
Lp 1 0 {Np**2*Kn} ; primary inductance = 200t**2*Kn<br />
Ls 2 0 {Ns**2*Kn} ; secondary inductance = 20t**2*Kn<br />
Kx Lp Ls 1 ; core coupling factor = 1<br />
<br />
Below is a schematic of a simple LTspice subcircuit that is functionally equivalent to a winding (without a core).&nbsp; Its symbol appears just to the right of the schematic.&nbsp; LTspice's fully extended inductor parasitics are included within this model.&nbsp; Observe that the winding is presented with a voltage equal to the core's volts/turn*primary_turns and that the core is presented with a current equal to the winding's ampere-turns = winding's amps*primary_turns.&nbsp; Also note if the leakage inductance and resistances are zero, the winding is completely floating with respect to the core and that the winding performs a voltage ratio transformation (set by the turns ratio) from DC to light.<br />
<br />
* First, the basic winding: Start (dot), Finish, Core:<br />
[[File: Simple Winding Symbol & Subcircuit.gif|right|479px|This simple subcircuit is equivalent to an inductor or transformer winding]]<br />
.subckt Winding s f c params: n=100 L=1u Rs=1m Rp=100<br />
Lw s 1 {L} Rser={Rs} Rpar={Rp} ; leakage and resistance<br />
Ew 1 f c 0 {n} ; impose core volts/turn*turns onto winding<br />
Fw 0 c Ew {n} ; impose winding amperes*turns onto core<br />
.ends Winding<br />
<br />
<br />
==== DC to DC Transformer (no magnetizing inductance - no energy storage) ====<br />
<br />
The transformer winding subcircuits are DC coupled and, when connected to a "core" (1TΩ in parallel with 1pF) that supports DC without drawing current, they combine to make a transformer that draws no magnetizing current, stores no energy and therefore is immune to errant initial conditions.&nbsp; This may be an advantage when first experimenting with new power circuits.<br />
<br />
For better cosmetics the simple DC core may encapsulated in its own subcircuit and symbol.&nbsp;<br />
<br />
[[File: DC_to_DC_Transformer.gif|right|190px|DC to DC (because of "core") transformer with two windings]]<br />
* Here is a DC "core" that does not draw increasing current with time:<br />
.subckt Core_DC C<br />
Cc C 0 1p Rpar=1T ; dump the "core's" ampere-turns into a small conductance<br />
.ends Core_DC<br />
<br />
[[File: DC_to_DC_Transformer_&_Core.gif|right|189px|DC to DC transformer with DC core symbol for aesthetics]]<br />
* DC-to-DC Transformer Equivalent (Netlist Uprocessed):<br />
Xp P 0 C Winding n=1 L=1u Rs=1m Rp=100 ; primary winding of 1:1 transformer<br />
Xs S 0 C Winding n=1 L=1u Rs=1m Rp=100 ; secondary winding of 1:1 transformer<br />
Xc C CoreDC ; subcircuit consisting of 1TΩ in parallel with 1pF<br />
<br />
==== Linear Transformer (linear magnetizing inductance - potentially unlimited energy storage) ====<br />
<br />
A standard linear transformer may easily be created simply by changing the core to a standard inductor with Rs=0.&nbsp; In this form (with a standard ''linear'' magnetizing inductance "core") the model is mostly useful as a perceptual window into the way coupled inductors work in LTspice since linear transformers are more easily and simply built with standard coupled inductors.&nbsp; Note that the magnetizing inductance "core" is the single summing point for the ''ampere-turns'' from all the windings and is the sole source of ''impressed voltage'' (=L*di/dt) reflected onto all the windings.&nbsp; Although this subcircuit is an unnecessary and overly complex representation for a transformer with a linear core inductance, it will be absolutely required if multiple windings are to be "wrapped" onto LTspice's nonlinear Chan inductance model, so take a moment to read it through (the Chan version will follow shortly).<br />
<br />
<br />
* Parametize and wrap an inductor with a subcircuit:<br />
[[File: Linear_Core.gif|right|191px|A linear core is simply an inductor with Rser=0]]<br />
.subckt Core_Linear C params: L=20m Rp=10k Cp=10p<br />
Lc C 0 {L} Rser=0 Rpar={Rp} Cpar={Cp}<br />
.ends Core_Linear<br />
<br />
[[File: Linear_Transformer.gif|right|176px|Transformer with linear core]]<br />
* Linear Transformer Equivalent (Netlist Unprocessed):<br />
Xp P 0 C Winding n=1 L=1u Rs=1m Rp=100 ; primary winding of 1:1 transformer<br />
Xs S 0 C Winding n=1 L=1u Rs=1m Rp=100 ; secondary winding of 1:1 transformer<br />
Xc C Core_Linear L=20m Rp=10k Cp=10p ; subcircuit consisting of an inductor with Rs=0<br />
<br />
* Linear Transformer Equivalent (Netlist Flattened):<br />
[[File: Linear_Transformer_Full.gif|right|438px|Transformer with linear core]]<br />
Lp Ps 1 1u Rser=1m Rpar=100 ; leakage and resistance<br />
Ep 1 Pf C 0 1 ; impose core volts/turn*turns onto winding<br />
Fp 0 C Ep 1 ; impose winding ampere*turns onto core<br />
Lc C 0 20m Rpar=10k Cpar=10p ; liner inductor core (no magnetic saturation)<br />
+ Rser=0 ; Rser must equal zero<br />
Fs 0 C Es 1 ; impose winding ampere*turns onto core<br />
Es 1 Sf C 0 1 ; impose core volts/turn*turns onto winding<br />
Ls Ss 1 1u Rser=1m Rpar=100 ; leakage and resistance<br />
<br />
==== Chan Transformer (saturating magnetizing inductance with hysteresis - limited energy storage) ====<br />
<br />
Now that the windings are separate from the core, a Chan inductor may simply be substituted for the linear inductor core. Since the inductance of a Chan is not assigned, but is determined by its magnetic material, dimensional properties and winding turns, one must adjust inductance by iteratively adjusting the gap and/or winding turns.<br />
<br />
<br />
* Parametize and wrap a Chan inductor with a subcircuit:<br />
[[File: Chan_Core.gif|right|167px|Physical properties based core with hysteresis and saturation]]<br />
.subckt Core_Chan C params:<br />
+ Bs=0.4 Br=0.1 Hc=20 ; Core default magnetic parameters<br />
+ A=25u1 Lm=19m8 Lg=0m7 ; Core default physical parameters<br />
+ Rp=10k Cp=10p ; Core default parallel loss and capacitance<br />
Lc C 0 Rser=0 n=1 ; force Rser=0 and n=1<br />
+ Bs={Bs} Br={Br} Hc={Hc}<br />
+ A={A} Lm={Lm} Lg={Lg}<br />
+ Rpar={Rp} Cpar={Cp}<br />
.ends Core_Chan<br />
<br />
[[File: Chan_Transformer.gif|right|167px|Physically parameterized transformer with hysteresis and saturation]]<br />
* Chan Transformer Equivalent (Netlist Unprocessed):<br />
Xp P 0 C Winding n=100 L=1u Rs=1m Rp=100 ; primary winding of 1:1 transformer<br />
Xs S 0 C Winding n=100 L=1u Rs=1m Rp=100 ; secondary winding of 1:1 transformer<br />
Xc C Core_Chan ; Chan inductor subcircuit with forced Rs=0 and n=1<br />
+ Bs=0.4 Br=0.1 Hc=20 Br=.10 ; Assigned core magnetic parameters<br />
+ A=25u1 Lm=19m8 Lg=0m7 ; Assigned core physical parameters<br />
+ Rp=10k Cp=10p ; Assigned core parallel loss and capacitance<br />
<br />
----<br />
<br />
<br />
'''Temporary Junk'''<br />
<br />
</pre><br />
And here is the same thing using parameters within curly braces to give value to LTspice's extended inductors and to a coupling statement (mutual inductance).&nbsp; Note that there is no need to create a subcircuit with this method because Lp and Ls can be placed directly on the schematic as symbols and K1 and the .param statement may be placed as SPICE text (this is the section of netlist that would then result).&nbsp; The prior subcircuit form (or something like it) only becomes necessary in conjunction with a custom two-winding transformer symbol or if a nonlinear core (magnetizing inductance) model must be used.<br />
<pre><br />
.param Npri=300 Nsec=30 L=1u K=0.95 Rs=1u Rp=10 Cp=1u<br />
+ Np2=Npri**2 Ns2=Nsec**2 ; turns squared for primary and secondary<br />
Lp P1 P2 {L*Np2} Rser={Rs*Np2} Rpar={Rp*Np2} Cpar={Cp/Np2}<br />
Ls S1 S2 {L*Ns2} Rser={Rs*Ns2} Rpar={Rp*Ns2} Cpar={Cp/Ns2}<br />
K1 Lp Ls {K}<br />
</pre><br />
<br />
Knowing the internal workings of LTspice's coupled inductor style transformer is all very interesting, but how do I make something that uses separate standard inductor symbols for winding, yet also uses the Chan core model with full saturation and hysteresis?<br />
<br />
The following method allows this:<br />
<br />
[[File:Separate_Winding.png]]&nbsp; [''obviously, this section is not yet complete'']<br />
<br />
This model uses the standard inductor symbol edited to appear as a winding subcircuit on a core (connected through a global node).&nbsp; The core may be linear or nonlinear (e.g., LTspice's built in Chan model) and may have as many windings as required.&nbsp; Due to the use of a global core node (which must be different for each core), a different subcircuit is required for each core.<br />
<br />
<br />
{{#widget:DISQUS<br />
|id=ltwiki<br />
|uniqid={{PAGENAME}}<br />
|url={{fullurl:{{PAGENAME}}}}<br />
}}</div>Analogspicemanhttp://ltwiki.org/index.php?title=Transformers&diff=2095Transformers2019-11-13T07:57:57Z<p>Analogspiceman: /* Chan Transformer (saturating magnetizing inductance with hysteresis - limited energy storage) */</p>
<hr />
<div>== Transformers ==<br />
<br />
=== Introduction ===<br />
<br />
Do you wish to study the behavior of transformers and inductors and explore their mysteries?&nbsp; LTspice is the ideal learning tool for this purpose. LTspice will faithfully model both ideal and real magnetic devices, but caution is advised when first experimenting with unfamiliar concepts in inductors and transformers.&nbsp; Minimize simulation problems by including reasonably realistic parasitic resistances (both series and parallel) directly into each inductor, whether used individually or as part of a transformer.<br />
<br />
A good learning and reference resource is the [http://coefs.uncc.edu/mnoras/files/2013/03/Transformer-and-Inductor-Design-Handbook_Chapter_17.pdf <i>Transformer and Inductor Design Handbook</i> Chapter 17, Winding Capacitance and Leakage Inductance] 4th Edition by Colonel William. T. McLyman.&nbsp; Mike Engelhardt, the author of LTspice, explains how to make transformers in LTspice in a [https://www.analog.com/en/technical-articles/using-transformers-in-ltspice-switcher-cadiii.html 2006 LT-Magazine article].<br />
<br />
Please keep in mind that starting a simulation with a dc voltage bias on an inductor or transformer winding will cause an initial inductor current only limited by the inductor's series resistance (this would be like trying to initialize an ideal capacitor with a current source - no matter how small the source, the dc voltage reached will approach infinity).&nbsp; In fact, if you are like most engineers, you are much more comfortable with the behavior of capacitors.&nbsp; If so, use this to your advantage by applying duality to think of what to expect when dealing with inductors.<br />
<br />
=== How do I make a transformer in LTspice? === <br />
<br />
[[File:LTspice_Transformer.gif|right|174px|Two lines were used to draw the core]]<br />
<br />
Although it is very possible to make a dedicated subcircuit for a specific transformer, the preferred method of making a generic transformer when drafting a simulation schematic is to simply place a separate inductor for each separate transformer winding and then couple them all together magnetically via a single ''[[Mutual Inductance]] (K) statement'' placed as a [[SPICE Directive]] on the schematic.&nbsp; Note that inductors called out in a [[Mutual Inductance]] statement will be automatically given a phasing dot if one does not already exist.<br />
<br />
K1 L1 L2 L3 1 ; causes phasing dots to automatically appear on L1-L3 inductor symbols<br />
<br />
When creating a new transformer this way, especially for use in a switched-mode power circuit, it is generally best to first specify the mutual coupling coefficient to be exactly unity.&nbsp; By starting with unity coupling there will be no leakage inductance in any winding and this will minimize the likelihood of the windings ringing at extremely high frequencies (which can slow the simulation to a crawl at each switching edge).&nbsp; However, be aware that a mutual inductance value of plus (or minus) unity ''may'' lead to simulation difficulties if ''Skip-the-initial-operating-point-solution'' (UIC) is specified for the .tran command.&nbsp; Prevent this by specifying a realistic resistance for each inductor "winding" (ctrl-right-mouse-click).&nbsp; Note that when coupled inductors are used as transformer windings, individual winding inductances rather than turns ratios must be specified (''inductance ratios should be set to be proportional to <u>the '''square''' of the turns ratios''</u>).<br />
<br />
=== I've created an ideal transformer so it should work at all frequencies, even including DC, right? ===<br />
<br />
No, but lots of users completely misunderstand or overlook this when setting up their simulation.&nbsp; This common mistake can lead to a lot of needless doubt following unexpected and puzzling simulation results produced by LTspice when presented with an ideal transformer that is inadvertently initialized with a large amount of dc voltage applied to its windings.&nbsp; This is probably the most commonly self-inflicted pitfall that trips up users improperly specifying ac voltage sources.<br />
<br />
When LTspice calculates initial conditions for voltage sources, it uses the values at time = 0.&nbsp; Depending on the starting phase angle and delay specified for a sine source, this can be as much as the voltage at the peak of the sine wave.&nbsp; When the simulator attempts to find the circuit's initial solution, this is the equivalent to hooking the transformer up to a large dc voltage source.&nbsp; Current will only be limited by winding resistance (which, in the ideal case, may be zero).&nbsp; Note that a real transformer will saturate at a relatively low current and would normally not store much energy (it would also probably burn up with so much dc applied), but an ideal transformer with an ideal magnetizing inductance may store a physically impossible amount of simulated "virtual" energy.<br />
<br />
Without realizing it, many users may instruct LTspice to initialize the transformer magnetizing inductance with huge starting currents.&nbsp; Since they have used an ideal inductance that does not saturate (like a real transformer would), it starts out with dc current that may take many hundreds of line (or switching) cycles to die away.&nbsp; This completely unrealistic energy source then may dominate the simulation, causing strange and unexpected puzzling behavior.&nbsp; In such cases, LTspice is just innocently following the instructions given it and accurately computing the results (garbage in, garbage out).<br />
<br />
To avoid this bogus and unwanted result, you must either arrange '''''the ac source to be zero at time zero''''' or '''''instruct LTspice not to use a dc solution for the starting point (UIC).'''''<br />
<br />
=== I want to model leakage inductance - how should I do that? ===<br />
<br />
The most flexible method is to keep the windings' mutual inductance statement at unity and add a small discrete leakage inductance in series with each winding.&nbsp; This is the most straightforward way to model transformers with asymmetrical leakage inductances.&nbsp; However, if your transformer is electrically symmetrical, it may be more convenient to simply set the mutual inductance to a value less than one.&nbsp; For each winding the resulting leakage inductance will be (1-K) times that winding's inductance.&nbsp; Note that each winding's coupled inductance also will decrease to K times that winding's inductance, but for typical values of K (>>0.9) this effect will be very small.<br />
<br />
This is how LTspice "sees" coupled inductors:<br />
<br />
For n inductors coupled together with a K statement, each inductor L1 through Ln is divided into two parts, a completely non-coupled "leakage" inductance equal to (1-K)*Lx (where Lx is the particular inductor in question) and a completely coupled "mutual" inductance equal to K*Lx.&nbsp; Voltage and current ratios of the coupled parts are related by the ratio of the square root of the the inductances L1 through Ln (this is the apparent "turns ratio").<br />
<br />
* For example, given two inductors coupled by a K statement:<br />
[[File:Loosely_Coupled_Transformer.gif|right|153px|Coupling is only K=0.2]]<br />
L1 1 0 1H<br />
L2 2 0 1H<br />
Km L1 L2 0.2<br />
<br />
[[File:Loosely_Coupled_Equivalent.gif|right|182px|"Winding" inductance is 1H]]<br />
<br />
* In LTspice, this is the same as:<br />
L1 1 m 0.8H<br />
Lm m 0 0.2H<br />
L2 2 m 0.8H<br />
<br />
Other engineering conventions regarding the definition of K, coupling and formula for leakage inductance are irrelevant to LTspice.&nbsp; Other formula for leakage inductance are intended to find total leakage inductance from an input winding through to an output winding(s) rather than for each individual winding.<br />
<br />
=== How about transformer saturation effects?&nbsp; Can LTspice model those? ===<br />
<br />
Yes, LTspice comes with a non-linear hysteretic core model built in!&nbsp; This is the 1991 model by John Chan et al.&nbsp; Compared to older core models, [[the Chan model]] is particularly robust, computationally efficient and compact, requiring only three parameters to define most any commonly encountered magnetic hysteresis loop.&nbsp; (LTspice also allows building an arbitrary inductance based on self flux and/or any valid function of node voltages and branch currents.&nbsp; [[The Arbitrary Inductor model|The arbitrary inductor model]] can be very efficiently used to create saturation without hysteresis.) <br />
<br />
Once the core material's generic magnetic properties are set, establishing the circuit-level non-linear inductance requires specifying three more parameters to set the geometry of the specific core and specifying one additional parameter for the core winding turn-count.&nbsp; The Chan inductor <font color="green" title="(has been mentioned as a possibility for a future release)">does not currently</font> directly support [[Mutual Inductance]], so unless only a single-winding inductor is being modeled, multiple windings must be added via additional circuitry.&nbsp; The simplest way to do this is to construct an ideal, unity coupled transformer with as many windings as required and then put the Chan inductor directly in parallel with any one of the windings (taking care to set the turns to match that particular winding).&nbsp; Since the magnetic effects (including non-saturated inductance) are already modeled by the Chan inductor, the inductance of the transformer's parallel winding must be enough larger (>>10) not to significantly load the Chan inductance.&nbsp; As before, the inductances for the other windings should be scaled by the square of their individual turns ratios (with respect to the paralleled winding).<br />
<br />
=== Okay, but calculating winding inductances is tedious.&nbsp; Is there some way to just enter a turns count for all the windings? ===<br />
<br />
Yes, this can be done in any of a number of ways.&nbsp; For example, the values for each of the inductances may be directly parametrized via <font color="green"><b title="Lx node1 node2 {Lm*(Nx/Nm)**2}">curly braces</b></font> to be a function of turns ratios (squared), or a subcircuit that accepts turns as a parameter may be used to encapsulate the windings implementation details.<br />
<br />
* Use parameters to to convert input of winding turns to inductance:<br />
[[File: Parameterized_Transformer.gif|right|304px|Turns are entered as parameters from which the inductance is calculated]]<br />
.param Lp=20m Np=200 Ns=20 ; inputs: primary inductance, primary turns, secondary turns<br />
.param Kn=Lp/Np**2 ; calculated inductance per turn squared<br />
Lp 1 0 {Np**2*Kn} ; primary inductance = 200t**2*Kn<br />
Ls 2 0 {Ns**2*Kn} ; secondary inductance = 20t**2*Kn<br />
Kx Lp Ls 1 ; core coupling factor = 1<br />
<br />
Below is a schematic of a simple LTspice subcircuit that is functionally equivalent to a winding (without a core).&nbsp; Its symbol appears just to the right of the schematic.&nbsp; LTspice's fully extended inductor parasitics are included within this model.&nbsp; Observe that the winding is presented with a voltage equal to the core's volts/turn*primary_turns and that the core is presented with a current equal to the winding's ampere-turns = winding's amps*primary_turns.&nbsp; Also note if the leakage inductance and resistances are zero, the winding is completely floating with respect to the core and that the winding performs a voltage ratio transformation (set by the turns ratio) from DC to light.<br />
<br />
* First, the basic winding: Start (dot), Finish, Core:<br />
[[File: Simple Winding Symbol & Subcircuit.gif|right|479px|This simple subcircuit is equivalent to an inductor or transformer winding]]<br />
.subckt Winding s f c params: n=100 L=1u Rs=1m Rp=100<br />
Lw s 1 {L} Rser={Rs} Rpar={Rp} ; leakage and resistance<br />
Ew 1 f c 0 {n} ; impose core volts/turn*turns onto winding<br />
Fw 0 c Ew {n} ; impose winding amperes*turns onto core<br />
.ends Winding<br />
<br />
<br />
==== DC to DC Transformer (no magnetizing inductance - no energy storage) ====<br />
<br />
The transformer winding subcircuits are DC coupled and, when connected to a "core" (1TΩ in parallel with 1pF) that supports DC without drawing current, they combine to make a transformer that draws no magnetizing current, stores no energy and therefore is immune to errant initial conditions.&nbsp; This may be an advantage when first experimenting with new power circuits.<br />
<br />
For better cosmetics the simple DC core may encapsulated in its own subcircuit and symbol.&nbsp;<br />
<br />
[[File: DC_to_DC_Transformer.gif|right|190px|DC to DC (because of "core") transformer with two windings]]<br />
* Here is a DC "core" that does not draw increasing current with time:<br />
.subckt Core_DC C<br />
Cc C 0 1p Rpar=1T ; dump the "core's" ampere-turns into a small conductance<br />
.ends Core_DC<br />
<br />
[[File: DC_to_DC_Transformer_&_Core.gif|right|189px|DC to DC transformer with DC core symbol for aesthetics]]<br />
* DC-to-DC Transformer Equivalent (Netlist Uprocessed):<br />
Xp P 0 C Winding n=1 L=1u Rs=1m Rp=100 ; primary winding of 1:1 transformer<br />
Xs S 0 C Winding n=1 L=1u Rs=1m Rp=100 ; secondary winding of 1:1 transformer<br />
Xc C CoreDC ; subcircuit consisting of 1TΩ in parallel with 1pF<br />
<br />
==== Linear Transformer (linear magnetizing inductance - potentially unlimited energy storage) ====<br />
<br />
A standard linear transformer may easily be created simply by changing the core to a standard inductor with Rs=0.&nbsp; In this form (with a standard ''linear'' magnetizing inductance "core") the model is mostly useful as a perceptual window into the way coupled inductors work in LTspice since linear transformers are more easily and simply built with standard coupled inductors.&nbsp; Note that the magnetizing inductance "core" is the single summing point for the ''ampere-turns'' from all the windings and is the sole source of ''impressed voltage'' (=L*di/dt) reflected onto all the windings.&nbsp; Although this subcircuit is an unnecessary and overly complex representation for a transformer with a linear core inductance, it will be absolutely required if multiple windings are to be "wrapped" onto LTspice's nonlinear Chan inductance model, so take a moment to read it through (the Chan version will follow shortly).<br />
<br />
<br />
* Parametize and wrap an inductor with a subcircuit:<br />
[[File: Linear_Core.gif|right|191px|A linear core is simply an inductor with Rser=0]]<br />
.subckt Core_Linear C params: L=20m Rp=10k Cp=10p<br />
Lc C 0 {L} Rser=0 Rpar={Rp} Cpar={Cp}<br />
.ends Core_Linear<br />
<br />
[[File: Linear_Transformer.gif|right|176px|Transformer with linear core]]<br />
* Linear Transformer Equivalent (Netlist Unprocessed):<br />
Xp P 0 C Winding n=1 L=1u Rs=1m Rp=100 ; primary winding of 1:1 transformer<br />
Xs S 0 C Winding n=1 L=1u Rs=1m Rp=100 ; secondary winding of 1:1 transformer<br />
Xc C Core_Linear L=20m Rp=10k Cp=10p ; subcircuit consisting of an inductor with Rs=0<br />
<br />
* Linear Transformer Equivalent (Netlist Flattened):<br />
[[File: Linear_Transformer_Full.gif|right|438px|Transformer with linear core]]<br />
Lp Ps 1 1u Rser=1m Rpar=100 ; leakage and resistance<br />
Ep 1 Pf C 0 1 ; impose core volts/turn*turns onto winding<br />
Fp 0 C Ep 1 ; impose winding ampere*turns onto core<br />
Lc C 0 20m Rpar=10k Cpar=10p ; liner inductor core (no magnetic saturation)<br />
+ Rser=0 ; Rser must equal zero<br />
Fs 0 C Es 1 ; impose winding ampere*turns onto core<br />
Es 1 Sf C 0 1 ; impose core volts/turn*turns onto winding<br />
Ls Ss 1 1u Rser=1m Rpar=100 ; leakage and resistance<br />
<br />
==== Chan Transformer (saturating magnetizing inductance with hysteresis - limited energy storage) ====<br />
<br />
Now that the windings are separate from the core, a Chan inductor may simply be substituted for the linear inductor core. Since the inductance of a Chan is not assigned, but is determined by its magnetic material, dimensional properties and winding turns, one must adjust inductance by iteratively adjusting the gap and/or winding turns.<br />
<br />
<br />
* Parametize and wrap a Chan inductor with a subcircuit:<br />
[[File: Chan_Core.gif|right|167px|Physical properties based core with hysteresis and saturation]]<br />
.subckt Core_Chan C params:<br />
+ Bs=0.4 Br=0.1 Hc=20 ; Core default magnetic parameters<br />
+ A=25u1 Lm=19m8 Lg=0m7 ; Core default physical parameters<br />
+ Rp=10k Cp=10p ; Core default parallel loss and capacitance<br />
Lc C 0 Rser=0 n=1 ; force Rser=0 and n=1<br />
+ Bs={Bs} Br={Br} Hc={Hc}<br />
+ A={A} Lm={Lm} Lg={Lg}<br />
+ Rpar={Rp} Cpar={Cp}<br />
.ends Core_Chan<br />
<br />
[[File: Chan_Transformer.gif|right|167px|Physically parameterized transformer with hysteresis and saturation]]<br />
* Chan Transformer Equivalent (Netlist Unprocessed):<br />
Xp P 0 C Winding n=100 L=1u Rs=1m Rp=100 ; primary winding of 1:1 transformer<br />
Xs S 0 C Winding n=100 L=1u Rs=1m Rp=100 ; secondary winding of 1:1 transformer<br />
Xc C Core_Chan ; Chan inductor subcircuit with forced Rs=0 and n=1<br />
+ Bs=0.4 Br=0.1 Hc=20 Br=.10 ; Assigned core magnetic parameters<br />
+ A=25u1 Lm=19m8 Lg=0m7 ; Assigned core physical parameters<br />
+ Rp=10k Cp=10p ; Assigned core parallel loss and capacitance<br />
<br />
----<br />
<br />
<br />
'''Temporary Junk'''<br />
<br />
</pre><br />
And here is the same thing using parameters within curly braces to give value to LTspice's extended inductors and to a coupling statement (mutual inductance).&nbsp; Note that there is no need to create a subcircuit with this method because Lp and Ls can be placed directly on the schematic as symbols and K1 and the .param statement may be placed as SPICE text (this is the section of netlist that would then result).&nbsp; The prior subcircuit form (or something like it) only becomes necessary in conjunction with a custom two-winding transformer symbol or if a nonlinear core (magnetizing inductance) model must be used.<br />
<pre><br />
.param Npri=300 Nsec=30 L=1u K=0.95 Rs=1u Rp=10 Cp=1u<br />
+ Np2=Npri**2 Ns2=Nsec**2 ; turns squared for primary and secondary<br />
Lp P1 P2 {L*Np2} Rser={Rs*Np2} Rpar={Rp*Np2} Cpar={Cp/Np2}<br />
Ls S1 S2 {L*Ns2} Rser={Rs*Ns2} Rpar={Rp*Ns2} Cpar={Cp/Ns2}<br />
K1 Lp Ls {K}<br />
</pre><br />
<br />
Knowing the internal workings of LTspice's coupled inductor style transformer is all very interesting, but how do I make something that uses separate standard inductor symbols for winding, yet also uses the Chan core model with full saturation and hysteresis?<br />
<br />
The following method allows this:<br />
<br />
[[File:Separate_Winding.png]]&nbsp; [''obviously, this section is not yet complete'']<br />
<br />
This model uses the standard inductor symbol edited to appear as a winding subcircuit on a core (connected through a global node).&nbsp; The core may be linear or nonlinear (e.g., LTspice's built in Chan model) and may have as many windings as required.&nbsp; Due to the use of a global core node (which must be different for each core), a different subcircuit is required for each core.<br />
<br />
<br />
{{#widget:DISQUS<br />
|id=ltwiki<br />
|uniqid={{PAGENAME}}<br />
|url={{fullurl:{{PAGENAME}}}}<br />
}}</div>Analogspicemanhttp://ltwiki.org/index.php?title=Transformers&diff=2094Transformers2019-11-13T07:56:00Z<p>Analogspiceman: /* Transformers */</p>
<hr />
<div>== Transformers ==<br />
<br />
=== Introduction ===<br />
<br />
Do you wish to study the behavior of transformers and inductors and explore their mysteries?&nbsp; LTspice is the ideal learning tool for this purpose. LTspice will faithfully model both ideal and real magnetic devices, but caution is advised when first experimenting with unfamiliar concepts in inductors and transformers.&nbsp; Minimize simulation problems by including reasonably realistic parasitic resistances (both series and parallel) directly into each inductor, whether used individually or as part of a transformer.<br />
<br />
A good learning and reference resource is the [http://coefs.uncc.edu/mnoras/files/2013/03/Transformer-and-Inductor-Design-Handbook_Chapter_17.pdf <i>Transformer and Inductor Design Handbook</i> Chapter 17, Winding Capacitance and Leakage Inductance] 4th Edition by Colonel William. T. McLyman.&nbsp; Mike Engelhardt, the author of LTspice, explains how to make transformers in LTspice in a [https://www.analog.com/en/technical-articles/using-transformers-in-ltspice-switcher-cadiii.html 2006 LT-Magazine article].<br />
<br />
Please keep in mind that starting a simulation with a dc voltage bias on an inductor or transformer winding will cause an initial inductor current only limited by the inductor's series resistance (this would be like trying to initialize an ideal capacitor with a current source - no matter how small the source, the dc voltage reached will approach infinity).&nbsp; In fact, if you are like most engineers, you are much more comfortable with the behavior of capacitors.&nbsp; If so, use this to your advantage by applying duality to think of what to expect when dealing with inductors.<br />
<br />
=== How do I make a transformer in LTspice? === <br />
<br />
[[File:LTspice_Transformer.gif|right|174px|Two lines were used to draw the core]]<br />
<br />
Although it is very possible to make a dedicated subcircuit for a specific transformer, the preferred method of making a generic transformer when drafting a simulation schematic is to simply place a separate inductor for each separate transformer winding and then couple them all together magnetically via a single ''[[Mutual Inductance]] (K) statement'' placed as a [[SPICE Directive]] on the schematic.&nbsp; Note that inductors called out in a [[Mutual Inductance]] statement will be automatically given a phasing dot if one does not already exist.<br />
<br />
K1 L1 L2 L3 1 ; causes phasing dots to automatically appear on L1-L3 inductor symbols<br />
<br />
When creating a new transformer this way, especially for use in a switched-mode power circuit, it is generally best to first specify the mutual coupling coefficient to be exactly unity.&nbsp; By starting with unity coupling there will be no leakage inductance in any winding and this will minimize the likelihood of the windings ringing at extremely high frequencies (which can slow the simulation to a crawl at each switching edge).&nbsp; However, be aware that a mutual inductance value of plus (or minus) unity ''may'' lead to simulation difficulties if ''Skip-the-initial-operating-point-solution'' (UIC) is specified for the .tran command.&nbsp; Prevent this by specifying a realistic resistance for each inductor "winding" (ctrl-right-mouse-click).&nbsp; Note that when coupled inductors are used as transformer windings, individual winding inductances rather than turns ratios must be specified (''inductance ratios should be set to be proportional to <u>the '''square''' of the turns ratios''</u>).<br />
<br />
=== I've created an ideal transformer so it should work at all frequencies, even including DC, right? ===<br />
<br />
No, but lots of users completely misunderstand or overlook this when setting up their simulation.&nbsp; This common mistake can lead to a lot of needless doubt following unexpected and puzzling simulation results produced by LTspice when presented with an ideal transformer that is inadvertently initialized with a large amount of dc voltage applied to its windings.&nbsp; This is probably the most commonly self-inflicted pitfall that trips up users improperly specifying ac voltage sources.<br />
<br />
When LTspice calculates initial conditions for voltage sources, it uses the values at time = 0.&nbsp; Depending on the starting phase angle and delay specified for a sine source, this can be as much as the voltage at the peak of the sine wave.&nbsp; When the simulator attempts to find the circuit's initial solution, this is the equivalent to hooking the transformer up to a large dc voltage source.&nbsp; Current will only be limited by winding resistance (which, in the ideal case, may be zero).&nbsp; Note that a real transformer will saturate at a relatively low current and would normally not store much energy (it would also probably burn up with so much dc applied), but an ideal transformer with an ideal magnetizing inductance may store a physically impossible amount of simulated "virtual" energy.<br />
<br />
Without realizing it, many users may instruct LTspice to initialize the transformer magnetizing inductance with huge starting currents.&nbsp; Since they have used an ideal inductance that does not saturate (like a real transformer would), it starts out with dc current that may take many hundreds of line (or switching) cycles to die away.&nbsp; This completely unrealistic energy source then may dominate the simulation, causing strange and unexpected puzzling behavior.&nbsp; In such cases, LTspice is just innocently following the instructions given it and accurately computing the results (garbage in, garbage out).<br />
<br />
To avoid this bogus and unwanted result, you must either arrange '''''the ac source to be zero at time zero''''' or '''''instruct LTspice not to use a dc solution for the starting point (UIC).'''''<br />
<br />
=== I want to model leakage inductance - how should I do that? ===<br />
<br />
The most flexible method is to keep the windings' mutual inductance statement at unity and add a small discrete leakage inductance in series with each winding.&nbsp; This is the most straightforward way to model transformers with asymmetrical leakage inductances.&nbsp; However, if your transformer is electrically symmetrical, it may be more convenient to simply set the mutual inductance to a value less than one.&nbsp; For each winding the resulting leakage inductance will be (1-K) times that winding's inductance.&nbsp; Note that each winding's coupled inductance also will decrease to K times that winding's inductance, but for typical values of K (>>0.9) this effect will be very small.<br />
<br />
This is how LTspice "sees" coupled inductors:<br />
<br />
For n inductors coupled together with a K statement, each inductor L1 through Ln is divided into two parts, a completely non-coupled "leakage" inductance equal to (1-K)*Lx (where Lx is the particular inductor in question) and a completely coupled "mutual" inductance equal to K*Lx.&nbsp; Voltage and current ratios of the coupled parts are related by the ratio of the square root of the the inductances L1 through Ln (this is the apparent "turns ratio").<br />
<br />
* For example, given two inductors coupled by a K statement:<br />
[[File:Loosely_Coupled_Transformer.gif|right|153px|Coupling is only K=0.2]]<br />
L1 1 0 1H<br />
L2 2 0 1H<br />
Km L1 L2 0.2<br />
<br />
[[File:Loosely_Coupled_Equivalent.gif|right|182px|"Winding" inductance is 1H]]<br />
<br />
* In LTspice, this is the same as:<br />
L1 1 m 0.8H<br />
Lm m 0 0.2H<br />
L2 2 m 0.8H<br />
<br />
Other engineering conventions regarding the definition of K, coupling and formula for leakage inductance are irrelevant to LTspice.&nbsp; Other formula for leakage inductance are intended to find total leakage inductance from an input winding through to an output winding(s) rather than for each individual winding.<br />
<br />
=== How about transformer saturation effects?&nbsp; Can LTspice model those? ===<br />
<br />
Yes, LTspice comes with a non-linear hysteretic core model built in!&nbsp; This is the 1991 model by John Chan et al.&nbsp; Compared to older core models, [[the Chan model]] is particularly robust, computationally efficient and compact, requiring only three parameters to define most any commonly encountered magnetic hysteresis loop.&nbsp; (LTspice also allows building an arbitrary inductance based on self flux and/or any valid function of node voltages and branch currents.&nbsp; [[The Arbitrary Inductor model|The arbitrary inductor model]] can be very efficiently used to create saturation without hysteresis.) <br />
<br />
Once the core material's generic magnetic properties are set, establishing the circuit-level non-linear inductance requires specifying three more parameters to set the geometry of the specific core and specifying one additional parameter for the core winding turn-count.&nbsp; The Chan inductor <font color="green" title="(has been mentioned as a possibility for a future release)">does not currently</font> directly support [[Mutual Inductance]], so unless only a single-winding inductor is being modeled, multiple windings must be added via additional circuitry.&nbsp; The simplest way to do this is to construct an ideal, unity coupled transformer with as many windings as required and then put the Chan inductor directly in parallel with any one of the windings (taking care to set the turns to match that particular winding).&nbsp; Since the magnetic effects (including non-saturated inductance) are already modeled by the Chan inductor, the inductance of the transformer's parallel winding must be enough larger (>>10) not to significantly load the Chan inductance.&nbsp; As before, the inductances for the other windings should be scaled by the square of their individual turns ratios (with respect to the paralleled winding).<br />
<br />
=== Okay, but calculating winding inductances is tedious.&nbsp; Is there some way to just enter a turns count for all the windings? ===<br />
<br />
Yes, this can be done in any of a number of ways.&nbsp; For example, the values for each of the inductances may be directly parametrized via <font color="green"><b title="Lx node1 node2 {Lm*(Nx/Nm)**2}">curly braces</b></font> to be a function of turns ratios (squared), or a subcircuit that accepts turns as a parameter may be used to encapsulate the windings implementation details.<br />
<br />
* Use parameters to to convert input of winding turns to inductance:<br />
[[File: Parameterized_Transformer.gif|right|304px|Turns are entered as parameters from which the inductance is calculated]]<br />
.param Lp=20m Np=200 Ns=20 ; inputs: primary inductance, primary turns, secondary turns<br />
.param Kn=Lp/Np**2 ; calculated inductance per turn squared<br />
Lp 1 0 {Np**2*Kn} ; primary inductance = 200t**2*Kn<br />
Ls 2 0 {Ns**2*Kn} ; secondary inductance = 20t**2*Kn<br />
Kx Lp Ls 1 ; core coupling factor = 1<br />
<br />
Below is a schematic of a simple LTspice subcircuit that is functionally equivalent to a winding (without a core).&nbsp; Its symbol appears just to the right of the schematic.&nbsp; LTspice's fully extended inductor parasitics are included within this model.&nbsp; Observe that the winding is presented with a voltage equal to the core's volts/turn*primary_turns and that the core is presented with a current equal to the winding's ampere-turns = winding's amps*primary_turns.&nbsp; Also note if the leakage inductance and resistances are zero, the winding is completely floating with respect to the core and that the winding performs a voltage ratio transformation (set by the turns ratio) from DC to light.<br />
<br />
* First, the basic winding: Start (dot), Finish, Core:<br />
[[File: Simple Winding Symbol & Subcircuit.gif|right|479px|This simple subcircuit is equivalent to an inductor or transformer winding]]<br />
.subckt Winding s f c params: n=100 L=1u Rs=1m Rp=100<br />
Lw s 1 {L} Rser={Rs} Rpar={Rp} ; leakage and resistance<br />
Ew 1 f c 0 {n} ; impose core volts/turn*turns onto winding<br />
Fw 0 c Ew {n} ; impose winding amperes*turns onto core<br />
.ends Winding<br />
<br />
<br />
==== DC to DC Transformer (no magnetizing inductance - no energy storage) ====<br />
<br />
The transformer winding subcircuits are DC coupled and, when connected to a "core" (1TΩ in parallel with 1pF) that supports DC without drawing current, they combine to make a transformer that draws no magnetizing current, stores no energy and therefore is immune to errant initial conditions.&nbsp; This may be an advantage when first experimenting with new power circuits.<br />
<br />
For better cosmetics the simple DC core may encapsulated in its own subcircuit and symbol.&nbsp;<br />
<br />
[[File: DC_to_DC_Transformer.gif|right|190px|DC to DC (because of "core") transformer with two windings]]<br />
* Here is a DC "core" that does not draw increasing current with time:<br />
.subckt Core_DC C<br />
Cc C 0 1p Rpar=1T ; dump the "core's" ampere-turns into a small conductance<br />
.ends Core_DC<br />
<br />
[[File: DC_to_DC_Transformer_&_Core.gif|right|189px|DC to DC transformer with DC core symbol for aesthetics]]<br />
* DC-to-DC Transformer Equivalent (Netlist Uprocessed):<br />
Xp P 0 C Winding n=1 L=1u Rs=1m Rp=100 ; primary winding of 1:1 transformer<br />
Xs S 0 C Winding n=1 L=1u Rs=1m Rp=100 ; secondary winding of 1:1 transformer<br />
Xc C CoreDC ; subcircuit consisting of 1TΩ in parallel with 1pF<br />
<br />
==== Linear Transformer (linear magnetizing inductance - potentially unlimited energy storage) ====<br />
<br />
A standard linear transformer may easily be created simply by changing the core to a standard inductor with Rs=0.&nbsp; In this form (with a standard ''linear'' magnetizing inductance "core") the model is mostly useful as a perceptual window into the way coupled inductors work in LTspice since linear transformers are more easily and simply built with standard coupled inductors.&nbsp; Note that the magnetizing inductance "core" is the single summing point for the ''ampere-turns'' from all the windings and is the sole source of ''impressed voltage'' (=L*di/dt) reflected onto all the windings.&nbsp; Although this subcircuit is an unnecessary and overly complex representation for a transformer with a linear core inductance, it will be absolutely required if multiple windings are to be "wrapped" onto LTspice's nonlinear Chan inductance model, so take a moment to read it through (the Chan version will follow shortly).<br />
<br />
<br />
* Parametize and wrap an inductor with a subcircuit:<br />
[[File: Linear_Core.gif|right|191px|A linear core is simply an inductor with Rser=0]]<br />
.subckt Core_Linear C params: L=20m Rp=10k Cp=10p<br />
Lc C 0 {L} Rser=0 Rpar={Rp} Cpar={Cp}<br />
.ends Core_Linear<br />
<br />
[[File: Linear_Transformer.gif|right|176px|Transformer with linear core]]<br />
* Linear Transformer Equivalent (Netlist Unprocessed):<br />
Xp P 0 C Winding n=1 L=1u Rs=1m Rp=100 ; primary winding of 1:1 transformer<br />
Xs S 0 C Winding n=1 L=1u Rs=1m Rp=100 ; secondary winding of 1:1 transformer<br />
Xc C Core_Linear L=20m Rp=10k Cp=10p ; subcircuit consisting of an inductor with Rs=0<br />
<br />
* Linear Transformer Equivalent (Netlist Flattened):<br />
[[File: Linear_Transformer_Full.gif|right|438px|Transformer with linear core]]<br />
Lp Ps 1 1u Rser=1m Rpar=100 ; leakage and resistance<br />
Ep 1 Pf C 0 1 ; impose core volts/turn*turns onto winding<br />
Fp 0 C Ep 1 ; impose winding ampere*turns onto core<br />
Lc C 0 20m Rpar=10k Cpar=10p ; liner inductor core (no magnetic saturation)<br />
+ Rser=0 ; Rser must equal zero<br />
Fs 0 C Es 1 ; impose winding ampere*turns onto core<br />
Es 1 Sf C 0 1 ; impose core volts/turn*turns onto winding<br />
Ls Ss 1 1u Rser=1m Rpar=100 ; leakage and resistance<br />
<br />
==== Chan Transformer (saturating magnetizing inductance with hysteresis - limited energy storage) ====<br />
<br />
Now that the windings are separate from the core, a Chan inductor may simply be substituted for the linear inductor core. Since the inductance of a Chan is not assigned, but is determined by its magnetic material, dimensional properties and winding turns, one must adjust inductance by iteratively adjusting the gap and/or winding turns.<br />
<br />
<br />
* Parametize and wrap a Chan inductor with a subcircuit:<br />
[[File: Chan_Core.gif|right|167px|Physical properties based core with hysteresis and saturation]]<br />
.subckt Core_Chan C params:<br />
+ Bs=0.4 Br=0.1 Hc=20 ; Core default magnetic parameters<br />
+ A=25u1 Lm=19m8 Lg=0m7 ; Core default physical parameters<br />
+ Rp=10k Cp=10p ; Core default parallel loss and capacitance<br />
Lc C 0 Rser=0 n=1 ; force Rser=0 and n=1<br />
+ Bs={Bs} Br={Br} Hc={Hc}<br />
+ A={A} Lm={Lm} Lg={Lg}<br />
+ Rpar={Rp} Cpar={Cp}<br />
.ends Core_Chan<br />
<br />
[[File: Chan_Transformer.gif|right|172px|Physically parameterized transformer with hysteresis and saturation]]<br />
* Chan Transformer Equivalent (Netlist Unprocessed):<br />
Xp P 0 C Winding n=100 L=1u Rs=1m Rp=100 ; primary winding of 1:1 transformer<br />
Xs S 0 C Winding n=100 L=1u Rs=1m Rp=100 ; secondary winding of 1:1 transformer<br />
Xc C Core_Chan ; Chan inductor subcircuit with forced Rs=0 and n=1<br />
+ Bs=0.4 Br=0.1 Hc=20 Br=.10 ; Assigned core magnetic parameters<br />
+ A=25u1 Lm=19m8 Lg=0m7 ; Assigned core physical parameters<br />
+ Rp=10k Cp=10p ; Assigned core parallel loss and capacitance<br />
<br />
----<br />
<br />
<br />
'''Temporary Junk'''<br />
<br />
</pre><br />
And here is the same thing using parameters within curly braces to give value to LTspice's extended inductors and to a coupling statement (mutual inductance).&nbsp; Note that there is no need to create a subcircuit with this method because Lp and Ls can be placed directly on the schematic as symbols and K1 and the .param statement may be placed as SPICE text (this is the section of netlist that would then result).&nbsp; The prior subcircuit form (or something like it) only becomes necessary in conjunction with a custom two-winding transformer symbol or if a nonlinear core (magnetizing inductance) model must be used.<br />
<pre><br />
.param Npri=300 Nsec=30 L=1u K=0.95 Rs=1u Rp=10 Cp=1u<br />
+ Np2=Npri**2 Ns2=Nsec**2 ; turns squared for primary and secondary<br />
Lp P1 P2 {L*Np2} Rser={Rs*Np2} Rpar={Rp*Np2} Cpar={Cp/Np2}<br />
Ls S1 S2 {L*Ns2} Rser={Rs*Ns2} Rpar={Rp*Ns2} Cpar={Cp/Ns2}<br />
K1 Lp Ls {K}<br />
</pre><br />
<br />
Knowing the internal workings of LTspice's coupled inductor style transformer is all very interesting, but how do I make something that uses separate standard inductor symbols for winding, yet also uses the Chan core model with full saturation and hysteresis?<br />
<br />
The following method allows this:<br />
<br />
[[File:Separate_Winding.png]]&nbsp; [''obviously, this section is not yet complete'']<br />
<br />
This model uses the standard inductor symbol edited to appear as a winding subcircuit on a core (connected through a global node).&nbsp; The core may be linear or nonlinear (e.g., LTspice's built in Chan model) and may have as many windings as required.&nbsp; Due to the use of a global core node (which must be different for each core), a different subcircuit is required for each core.<br />
<br />
<br />
{{#widget:DISQUS<br />
|id=ltwiki<br />
|uniqid={{PAGENAME}}<br />
|url={{fullurl:{{PAGENAME}}}}<br />
}}</div>Analogspicemanhttp://ltwiki.org/index.php?title=File:Chan_Transformer.gif&diff=2093File:Chan Transformer.gif2019-11-13T07:52:51Z<p>Analogspiceman: Physically parameterized transformer with hysteresis and saturation</p>
<hr />
<div>== Summary ==<br />
Physically parameterized transformer with hysteresis and saturation</div>Analogspicemanhttp://ltwiki.org/index.php?title=File:Chan_Core.gif&diff=2091File:Chan Core.gif2019-11-13T06:49:36Z<p>Analogspiceman: Analogspiceman uploaded a new version of File:Chan Core.gif</p>
<hr />
<div>== Summary ==<br />
Physical properties based core with hysteresis and saturation</div>Analogspicemanhttp://ltwiki.org/index.php?title=Transformers&diff=2090Transformers2019-11-12T18:33:36Z<p>Analogspiceman: /* Chan Transformer (saturating magnetizing inductance with hysteresis - limited energy storage) */</p>
<hr />
<div>== Transformers ==<br />
<br />
=== Introduction ===<br />
<br />
Do you wish to study the behavior of transformers and inductors and explore their mysteries?&nbsp; LTspice is the ideal learning tool for this purpose. LTspice will faithfully model both ideal and real magnetic devices, but caution is advised when first experimenting with unfamiliar concepts in inductors and transformers.&nbsp; Minimize simulation problems by including reasonably realistic parasitic resistances (both series and parallel) directly into each inductor, whether used individually or as part of a transformer.<br />
<br />
A good learning and reference resource is the [http://coefs.uncc.edu/mnoras/files/2013/03/Transformer-and-Inductor-Design-Handbook_Chapter_17.pdf <i>Transformer and Inductor Design Handbook</i> Chapter 17, Winding Capacitance and Leakage Inductance] 4th Edition by Colonel William. T. McLyman.&nbsp; Mike Engelhardt, the author of LTspice, explains how to make transformers in LTspice in a [https://www.analog.com/en/technical-articles/using-transformers-in-ltspice-switcher-cadiii.html 2006 LT-Magazine article].<br />
<br />
Please keep in mind that starting a simulation with a dc voltage bias on an inductor or transformer winding will cause an initial inductor current only limited by the inductor's series resistance (this would be like trying to initialize an ideal capacitor with a current source - no matter how small the source, the dc voltage reached will approach infinity).&nbsp; In fact, if you are like most engineers, you are much more comfortable with the behavior of capacitors.&nbsp; If so, use this to your advantage by applying duality to think of what to expect when dealing with inductors.<br />
<br />
=== How do I make a transformer in LTspice? === <br />
<br />
[[File:LTspice_Transformer.gif|right|174px|Two lines were used to draw the core]]<br />
<br />
Although it is very possible to make a dedicated subcircuit for a specific transformer, the preferred method of making a generic transformer when drafting a simulation schematic is to simply place a separate inductor for each separate transformer winding and then couple them all together magnetically via a single ''[[Mutual Inductance]] (K) statement'' placed as a [[SPICE Directive]] on the schematic.&nbsp; Note that inductors called out in a [[Mutual Inductance]] statement will be automatically given a phasing dot if one does not already exist.<br />
<br />
K1 L1 L2 L3 1 ; causes phasing dots to automatically appear on L1-L3 inductor symbols<br />
<br />
When creating a new transformer this way, especially for use in a switched-mode power circuit, it is generally best to first specify the mutual coupling coefficient to be exactly unity.&nbsp; By starting with unity coupling there will be no leakage inductance in any winding and this will minimize the likelihood of the windings ringing at extremely high frequencies (which can slow the simulation to a crawl at each switching edge).&nbsp; However, be aware that a mutual inductance value of plus (or minus) unity ''may'' lead to simulation difficulties if ''Skip-the-initial-operating-point-solution'' (UIC) is specified for the .tran command.&nbsp; Prevent this by specifying a realistic resistance for each inductor "winding" (ctrl-right-mouse-click).&nbsp; Note that when coupled inductors are used as transformer windings, individual winding inductances rather than turns ratios must be specified (''inductance ratios should be set to be proportional to <u>the '''square''' of the turns ratios''</u>).<br />
<br />
=== I've created an ideal transformer so it should work at all frequencies, even including DC, right? ===<br />
<br />
No, but lots of users completely misunderstand or overlook this when setting up their simulation.&nbsp; This common mistake can lead to a lot of needless doubt following unexpected and puzzling simulation results produced by LTspice when presented with an ideal transformer that is inadvertently initialized with a large amount of dc voltage applied to its windings.&nbsp; This is probably the most commonly self-inflicted pitfall that trips up users improperly specifying ac voltage sources.<br />
<br />
When LTspice calculates initial conditions for voltage sources, it uses the values at time = 0.&nbsp; Depending on the starting phase angle and delay specified for a sine source, this can be as much as the voltage at the peak of the sine wave.&nbsp; When the simulator attempts to find the circuit's initial solution, this is the equivalent to hooking the transformer up to a large dc voltage source.&nbsp; Current will only be limited by winding resistance (which, in the ideal case, may be zero).&nbsp; Note that a real transformer will saturate at a relatively low current and would normally not store much energy (it would also probably burn up with so much dc applied), but an ideal transformer with an ideal magnetizing inductance may store a physically impossible amount of simulated "virtual" energy.<br />
<br />
Without realizing it, many users may instruct LTspice to initialize the transformer magnetizing inductance with huge starting currents.&nbsp; Since they have used an ideal inductance that does not saturate (like a real transformer would), it starts out with dc current that may take many hundreds of line (or switching) cycles to die away.&nbsp; This completely unrealistic energy source then may dominate the simulation, causing strange and unexpected puzzling behavior.&nbsp; In such cases, LTspice is just innocently following the instructions given it and accurately computing the results (garbage in, garbage out).<br />
<br />
To avoid this bogus and unwanted result, you must either arrange '''''the ac source to be zero at time zero''''' or '''''instruct LTspice not to use a dc solution for the starting point (UIC).'''''<br />
<br />
=== I want to model leakage inductance - how should I do that? ===<br />
<br />
The most flexible method is to keep the windings' mutual inductance statement at unity and add a small discrete leakage inductance in series with each winding.&nbsp; This is the most straightforward way to model transformers with asymmetrical leakage inductances.&nbsp; However, if your transformer is electrically symmetrical, it may be more convenient to simply set the mutual inductance to a value less than one.&nbsp; For each winding the resulting leakage inductance will be (1-K) times that winding's inductance.&nbsp; Note that each winding's coupled inductance also will decrease to K times that winding's inductance, but for typical values of K (>>0.9) this effect will be very small.<br />
<br />
This is how LTspice "sees" coupled inductors:<br />
<br />
For n inductors coupled together with a K statement, each inductor L1 through Ln is divided into two parts, a completely non-coupled "leakage" inductance equal to (1-K)*Lx (where Lx is the particular inductor in question) and a completely coupled "mutual" inductance equal to K*Lx.&nbsp; Voltage and current ratios of the coupled parts are related by the ratio of the square root of the the inductances L1 through Ln (this is the apparent "turns ratio").<br />
<br />
* For example, given two inductors coupled by a K statement:<br />
[[File:Loosely_Coupled_Transformer.gif|right|153px|Coupling is only K=0.2]]<br />
L1 1 0 1H<br />
L2 2 0 1H<br />
Km L1 L2 0.2<br />
<br />
[[File:Loosely_Coupled_Equivalent.gif|right|182px|"Winding" inductance is 1H]]<br />
<br />
* In LTspice, this is the same as:<br />
L1 1 m 0.8H<br />
Lm m 0 0.2H<br />
L2 2 m 0.8H<br />
<br />
Other engineering conventions regarding the definition of K, coupling and formula for leakage inductance are irrelevant to LTspice.&nbsp; Other formula for leakage inductance are intended to find total leakage inductance from an input winding through to an output winding(s) rather than for each individual winding.<br />
<br />
=== How about transformer saturation effects?&nbsp; Can LTspice model those? ===<br />
<br />
Yes, LTspice comes with a non-linear hysteretic core model built in!&nbsp; This is the 1991 model by John Chan et al.&nbsp; Compared to older core models, [[the Chan model]] is particularly robust, computationally efficient and compact, requiring only three parameters to define most any commonly encountered magnetic hysteresis loop.&nbsp; (LTspice also allows building an arbitrary inductance based on self flux and/or any valid function of node voltages and branch currents.&nbsp; [[The Arbitrary Inductor model|The arbitrary inductor model]] can be very efficiently used to create saturation without hysteresis.) <br />
<br />
Once the core material's generic magnetic properties are set, establishing the circuit-level non-linear inductance requires specifying three more parameters to set the geometry of the specific core and specifying one additional parameter for the core winding turn-count.&nbsp; The Chan inductor <font color="green" title="(has been mentioned as a possibility for a future release)">does not currently</font> directly support [[Mutual Inductance]], so unless only a single-winding inductor is being modeled, multiple windings must be added via additional circuitry.&nbsp; The simplest way to do this is to construct an ideal, unity coupled transformer with as many windings as required and then put the Chan inductor directly in parallel with any one of the windings (taking care to set the turns to match that particular winding).&nbsp; Since the magnetic effects (including non-saturated inductance) are already modeled by the Chan inductor, the inductance of the transformer's parallel winding must be enough larger (>>10) not to significantly load the Chan inductance.&nbsp; As before, the inductances for the other windings should be scaled by the square of their individual turns ratios (with respect to the paralleled winding).<br />
<br />
=== Okay, but calculating winding inductances is tedious.&nbsp; Is there some way to just enter a turns count for all the windings? ===<br />
<br />
Yes, this can be done in any of a number of ways.&nbsp; For example, the values for each of the inductances may be directly parametrized via <font color="green"><b title="Lx node1 node2 {Lm*(Nx/Nm)**2}">curly braces</b></font> to be a function of turns ratios (squared), or a subcircuit that accepts turns as a parameter may be used to encapsulate the windings implementation details.<br />
<br />
* Use parameters to to convert input of winding turns to inductance:<br />
[[File: Parameterized_Transformer.gif|right|304px|Turns are entered as parameters from which the inductance is calculated]]<br />
.param Lp=20m Np=200 Ns=20 ; inputs: primary inductance, primary turns, secondary turns<br />
.param Kn=Lp/Np**2 ; calculated inductance per turn squared<br />
Lp 1 0 {Np**2*Kn} ; primary inductance = 200t**2*Kn<br />
Ls 2 0 {Ns**2*Kn} ; secondary inductance = 20t**2*Kn<br />
Kx Lp Ls 1 ; core coupling factor = 1<br />
<br />
Below is a schematic of a simple LTspice subcircuit that is functionally equivalent to a winding (without a core).&nbsp; Its symbol appears just to the right of the schematic.&nbsp; LTspice's fully extended inductor parasitics are included within this model.&nbsp; Observe that the winding is presented with a voltage equal to the core's volts/turn*primary_turns and that the core is presented with a current equal to the winding's ampere-turns = winding's amps*primary_turns.&nbsp; Also note if the leakage inductance and resistances are zero, the winding is completely floating with respect to the core and that the winding performs a voltage ratio transformation (set by the turns ratio) from DC to light.<br />
<br />
* First, the basic winding: Start (dot), Finish, Core:<br />
[[File: Simple Winding Symbol & Subcircuit.gif|right|479px|This simple subcircuit is equivalent to an inductor or transformer winding]]<br />
.subckt Winding s f c params: n=100 L=1u Rs=1m Rp=100<br />
Lw s 1 {L} Rser={Rs} Rpar={Rp} ; leakage and resistance<br />
Ew 1 f c 0 {n} ; impose core volts/turn*turns onto winding<br />
Fw 0 c Ew {n} ; impose winding amperes*turns onto core<br />
.ends Winding<br />
<br />
<br />
==== DC to DC Transformer (no magnetizing inductance - no energy storage) ====<br />
<br />
The transformer winding subcircuits are DC coupled and, when connected to a "core" (1TΩ in parallel with 1pF) that supports DC without drawing current, they combine to make a transformer that draws no magnetizing current, stores no energy and therefore is immune to errant initial conditions.&nbsp; This may be an advantage when first experimenting with new power circuits.<br />
<br />
For better cosmetics the simple DC core may encapsulated in its own subcircuit and symbol.&nbsp;<br />
<br />
[[File: DC_to_DC_Transformer.gif|right|190px|DC to DC (because of "core") transformer with two windings]]<br />
* Here is a DC "core" that does not draw increasing current with time:<br />
.subckt Core_DC C<br />
Cc C 0 1p Rpar=1T ; dump the "core's" ampere-turns into a small conductance<br />
.ends Core_DC<br />
<br />
[[File: DC_to_DC_Transformer_&_Core.gif|right|189px|DC to DC transformer with DC core symbol for aesthetics]]<br />
* DC-to-DC Transformer Equivalent (Netlist Uprocessed):<br />
Xp P 0 C Winding n=1 L=1u Rs=1m Rp=100 ; primary winding of 1:1 transformer<br />
Xs S 0 C Winding n=1 L=1u Rs=1m Rp=100 ; secondary winding of 1:1 transformer<br />
Xc C CoreDC ; subcircuit consisting of 1TΩ in parallel with 1pF<br />
<br />
==== Linear Transformer (linear magnetizing inductance - potentially unlimited energy storage) ====<br />
<br />
A standard linear transformer may easily be created simply by changing the core to a standard inductor with Rs=0.&nbsp; In this form (with a standard ''linear'' magnetizing inductance "core") the model is mostly useful as a perceptual window into the way coupled inductors work in LTspice since linear transformers are more easily and simply built with standard coupled inductors.&nbsp; Note that the magnetizing inductance "core" is the single summing point for the ''ampere-turns'' from all the windings and is the sole source of ''impressed voltage'' (=L*di/dt) reflected onto all the windings.&nbsp; Although this subcircuit is an unnecessary and overly complex representation for a transformer with a linear core inductance, it will be absolutely required if multiple windings are to be "wrapped" onto LTspice's nonlinear Chan inductance model, so take a moment to read it through (the Chan version will follow shortly).<br />
<br />
<br />
* Parametize and wrap an inductor with a subcircuit:<br />
[[File: Linear_Core.gif|right|191px|A linear core is simply an inductor with Rser=0]]<br />
.subckt Core_Linear C params: L=20m Rp=10k Cp=10p<br />
Lc C 0 {L} Rser=0 Rpar={Rp} Cpar={Cp}<br />
.ends Core_Linear<br />
<br />
[[File: Linear_Transformer.gif|right|176px|Transformer with linear core]]<br />
* Linear Transformer Equivalent (Netlist Unprocessed):<br />
Xp P 0 C Winding n=1 L=1u Rs=1m Rp=100 ; primary winding of 1:1 transformer<br />
Xs S 0 C Winding n=1 L=1u Rs=1m Rp=100 ; secondary winding of 1:1 transformer<br />
Xc C Core_Linear L=20m Rp=10k Cp=10p ; subcircuit consisting of an inductor with Rs=0<br />
<br />
* Linear Transformer Equivalent (Netlist Flattened):<br />
[[File: Linear_Transformer_Full.gif|right|438px|Transformer with linear core]]<br />
Lp Ps 1 1u Rser=1m Rpar=100 ; leakage and resistance<br />
Ep 1 Pf C 0 1 ; impose core volts/turn*turns onto winding<br />
Fp 0 C Ep 1 ; impose winding ampere*turns onto core<br />
Lc C 0 20m Rpar=10k Cpar=10p ; liner inductor core (no magnetic saturation)<br />
+ Rser=0 ; Rser must equal zero<br />
Fs 0 C Es 1 ; impose winding ampere*turns onto core<br />
Es 1 Sf C 0 1 ; impose core volts/turn*turns onto winding<br />
Ls Ss 1 1u Rser=1m Rpar=100 ; leakage and resistance<br />
<br />
==== Chan Transformer (saturating magnetizing inductance with hysteresis - limited energy storage) ====<br />
<br />
Now that the windings are separate from the core, a Chan inductor may simply be substituted for the linear inductor core. Since the inductance of a Chan is not assigned, but is determined by its magnetic material, dimensional properties and winding turns, one must adjust inductance by iteratively adjusting the gap and/or winding turns.<br />
<br />
<br />
* Parametize and wrap a Chan inductor with a subcircuit:<br />
[[File: Chan_Core.gif|right|173px|Physical properties based core with hysteresis and saturation]]<br />
.subckt Core_Chan C params:<br />
+ Bs=0.4 Br=0.1 Hc=20 ; Core default magnetic parameters<br />
+ A=25u1 Lm=19m8 Lg=0m7 ; Core default physical parameters<br />
+ Rp=10k Cp=10p ; Core default parallel loss and capacitance<br />
Lc C 0 Rser=0 n=1 ; force Rser=0 and n=1<br />
+ Bs={Bs} Br={Br} Hc={Hc}<br />
+ A={A} Lm={Lm} Lg={Lg}<br />
+ Rpar={Rp} Cpar={Cp}<br />
.ends Core_Chan<br />
<br />
[[File: Chan_Transformer.gif|right|172px|Physically parameterized transformer with hysteresis and saturation]]<br />
* Chan Transformer Equivalent (Netlist Unprocessed):<br />
Xp P 0 C Winding n=100 L=1u Rs=1m Rp=100 ; primary winding of 1:1 transformer<br />
Xs S 0 C Winding n=100 L=1u Rs=1m Rp=100 ; secondary winding of 1:1 transformer<br />
Xc C Core_Chan ; Chan inductor subcircuit with forced Rs=0 and n=1<br />
+ Bs=0.4 Br=0.1 Hc=20 Br=.10 ; Assigned core magnetic parameters<br />
+ A=25u1 Lm=19m8 Lg=0m7 ; Assigned core physical parameters<br />
+ Rp=10k Cp=10p ; Assigned core parallel loss and capacitance<br />
<br />
----<br />
<br />
<br />
'''Temporary Junk'''<br />
<br />
</pre><br />
And here is the same thing using parameters within curly braces to give value to LTspice's extended inductors and to a coupling statement (mutual inductance).&nbsp; Note that there is no need to create a subcircuit with this method because Lp and Ls can be placed directly on the schematic as symbols and K1 and the .param statement may be placed as SPICE text (this is the section of netlist that would then result).&nbsp; The prior subcircuit form (or something like it) only becomes necessary in conjunction with a custom two-winding transformer symbol or if a nonlinear core (magnetizing inductance) model must be used.<br />
<pre><br />
.param Npri=300 Nsec=30 L=1u K=0.95 Rs=1u Rp=10 Cp=1u<br />
+ Np2=Npri**2 Ns2=Nsec**2 ; turns squared for primary and secondary<br />
Lp P1 P2 {L*Np2} Rser={Rs*Np2} Rpar={Rp*Np2} Cpar={Cp/Np2}<br />
Ls S1 S2 {L*Ns2} Rser={Rs*Ns2} Rpar={Rp*Ns2} Cpar={Cp/Ns2}<br />
K1 Lp Ls {K}<br />
</pre><br />
<br />
Knowing the internal workings of LTspice's coupled inductor style transformer is all very interesting, but how do I make something that uses separate standard inductor symbols for winding, yet also uses the Chan core model with full saturation and hysteresis?<br />
<br />
The following method allows this:<br />
<br />
[[File:Separate_Winding.png]]&nbsp; [''obviously, this section is not yet complete'']<br />
<br />
This model uses the standard inductor symbol edited to appear as a winding subcircuit on a core (connected through a global node).&nbsp; The core may be linear or nonlinear (e.g., LTspice's built in Chan model) and may have as many windings as required.&nbsp; Due to the use of a global core node (which must be different for each core), a different subcircuit is required for each core.<br />
<br />
<br />
{{#widget:DISQUS<br />
|id=ltwiki<br />
|uniqid={{PAGENAME}}<br />
|url={{fullurl:{{PAGENAME}}}}<br />
}}</div>Analogspicemanhttp://ltwiki.org/index.php?title=Transformers&diff=2088Transformers2019-11-12T17:01:33Z<p>Analogspiceman: /* Chan Transformer (saturating magnetizing inductance with hysteresis - limited energy storage) */</p>
<hr />
<div>== Transformers ==<br />
<br />
=== Introduction ===<br />
<br />
Do you wish to study the behavior of transformers and inductors and explore their mysteries?&nbsp; LTspice is the ideal learning tool for this purpose. LTspice will faithfully model both ideal and real magnetic devices, but caution is advised when first experimenting with unfamiliar concepts in inductors and transformers.&nbsp; Minimize simulation problems by including reasonably realistic parasitic resistances (both series and parallel) directly into each inductor, whether used individually or as part of a transformer.<br />
<br />
A good learning and reference resource is the [http://coefs.uncc.edu/mnoras/files/2013/03/Transformer-and-Inductor-Design-Handbook_Chapter_17.pdf <i>Transformer and Inductor Design Handbook</i> Chapter 17, Winding Capacitance and Leakage Inductance] 4th Edition by Colonel William. T. McLyman.&nbsp; Mike Engelhardt, the author of LTspice, explains how to make transformers in LTspice in a [https://www.analog.com/en/technical-articles/using-transformers-in-ltspice-switcher-cadiii.html 2006 LT-Magazine article].<br />
<br />
Please keep in mind that starting a simulation with a dc voltage bias on an inductor or transformer winding will cause an initial inductor current only limited by the inductor's series resistance (this would be like trying to initialize an ideal capacitor with a current source - no matter how small the source, the dc voltage reached will approach infinity).&nbsp; In fact, if you are like most engineers, you are much more comfortable with the behavior of capacitors.&nbsp; If so, use this to your advantage by applying duality to think of what to expect when dealing with inductors.<br />
<br />
=== How do I make a transformer in LTspice? === <br />
<br />
[[File:LTspice_Transformer.gif|right|174px|Two lines were used to draw the core]]<br />
<br />
Although it is very possible to make a dedicated subcircuit for a specific transformer, the preferred method of making a generic transformer when drafting a simulation schematic is to simply place a separate inductor for each separate transformer winding and then couple them all together magnetically via a single ''[[Mutual Inductance]] (K) statement'' placed as a [[SPICE Directive]] on the schematic.&nbsp; Note that inductors called out in a [[Mutual Inductance]] statement will be automatically given a phasing dot if one does not already exist.<br />
<br />
K1 L1 L2 L3 1 ; causes phasing dots to automatically appear on L1-L3 inductor symbols<br />
<br />
When creating a new transformer this way, especially for use in a switched-mode power circuit, it is generally best to first specify the mutual coupling coefficient to be exactly unity.&nbsp; By starting with unity coupling there will be no leakage inductance in any winding and this will minimize the likelihood of the windings ringing at extremely high frequencies (which can slow the simulation to a crawl at each switching edge).&nbsp; However, be aware that a mutual inductance value of plus (or minus) unity ''may'' lead to simulation difficulties if ''Skip-the-initial-operating-point-solution'' (UIC) is specified for the .tran command.&nbsp; Prevent this by specifying a realistic resistance for each inductor "winding" (ctrl-right-mouse-click).&nbsp; Note that when coupled inductors are used as transformer windings, individual winding inductances rather than turns ratios must be specified (''inductance ratios should be set to be proportional to <u>the '''square''' of the turns ratios''</u>).<br />
<br />
=== I've created an ideal transformer so it should work at all frequencies, even including DC, right? ===<br />
<br />
No, but lots of users completely misunderstand or overlook this when setting up their simulation.&nbsp; This common mistake can lead to a lot of needless doubt following unexpected and puzzling simulation results produced by LTspice when presented with an ideal transformer that is inadvertently initialized with a large amount of dc voltage applied to its windings.&nbsp; This is probably the most commonly self-inflicted pitfall that trips up users improperly specifying ac voltage sources.<br />
<br />
When LTspice calculates initial conditions for voltage sources, it uses the values at time = 0.&nbsp; Depending on the starting phase angle and delay specified for a sine source, this can be as much as the voltage at the peak of the sine wave.&nbsp; When the simulator attempts to find the circuit's initial solution, this is the equivalent to hooking the transformer up to a large dc voltage source.&nbsp; Current will only be limited by winding resistance (which, in the ideal case, may be zero).&nbsp; Note that a real transformer will saturate at a relatively low current and would normally not store much energy (it would also probably burn up with so much dc applied), but an ideal transformer with an ideal magnetizing inductance may store a physically impossible amount of simulated "virtual" energy.<br />
<br />
Without realizing it, many users may instruct LTspice to initialize the transformer magnetizing inductance with huge starting currents.&nbsp; Since they have used an ideal inductance that does not saturate (like a real transformer would), it starts out with dc current that may take many hundreds of line (or switching) cycles to die away.&nbsp; This completely unrealistic energy source then may dominate the simulation, causing strange and unexpected puzzling behavior.&nbsp; In such cases, LTspice is just innocently following the instructions given it and accurately computing the results (garbage in, garbage out).<br />
<br />
To avoid this bogus and unwanted result, you must either arrange '''''the ac source to be zero at time zero''''' or '''''instruct LTspice not to use a dc solution for the starting point (UIC).'''''<br />
<br />
=== I want to model leakage inductance - how should I do that? ===<br />
<br />
The most flexible method is to keep the windings' mutual inductance statement at unity and add a small discrete leakage inductance in series with each winding.&nbsp; This is the most straightforward way to model transformers with asymmetrical leakage inductances.&nbsp; However, if your transformer is electrically symmetrical, it may be more convenient to simply set the mutual inductance to a value less than one.&nbsp; For each winding the resulting leakage inductance will be (1-K) times that winding's inductance.&nbsp; Note that each winding's coupled inductance also will decrease to K times that winding's inductance, but for typical values of K (>>0.9) this effect will be very small.<br />
<br />
This is how LTspice "sees" coupled inductors:<br />
<br />
For n inductors coupled together with a K statement, each inductor L1 through Ln is divided into two parts, a completely non-coupled "leakage" inductance equal to (1-K)*Lx (where Lx is the particular inductor in question) and a completely coupled "mutual" inductance equal to K*Lx.&nbsp; Voltage and current ratios of the coupled parts are related by the ratio of the square root of the the inductances L1 through Ln (this is the apparent "turns ratio").<br />
<br />
* For example, given two inductors coupled by a K statement:<br />
[[File:Loosely_Coupled_Transformer.gif|right|153px|Coupling is only K=0.2]]<br />
L1 1 0 1H<br />
L2 2 0 1H<br />
Km L1 L2 0.2<br />
<br />
[[File:Loosely_Coupled_Equivalent.gif|right|182px|"Winding" inductance is 1H]]<br />
<br />
* In LTspice, this is the same as:<br />
L1 1 m 0.8H<br />
Lm m 0 0.2H<br />
L2 2 m 0.8H<br />
<br />
Other engineering conventions regarding the definition of K, coupling and formula for leakage inductance are irrelevant to LTspice.&nbsp; Other formula for leakage inductance are intended to find total leakage inductance from an input winding through to an output winding(s) rather than for each individual winding.<br />
<br />
=== How about transformer saturation effects?&nbsp; Can LTspice model those? ===<br />
<br />
Yes, LTspice comes with a non-linear hysteretic core model built in!&nbsp; This is the 1991 model by John Chan et al.&nbsp; Compared to older core models, [[the Chan model]] is particularly robust, computationally efficient and compact, requiring only three parameters to define most any commonly encountered magnetic hysteresis loop.&nbsp; (LTspice also allows building an arbitrary inductance based on self flux and/or any valid function of node voltages and branch currents.&nbsp; [[The Arbitrary Inductor model|The arbitrary inductor model]] can be very efficiently used to create saturation without hysteresis.) <br />
<br />
Once the core material's generic magnetic properties are set, establishing the circuit-level non-linear inductance requires specifying three more parameters to set the geometry of the specific core and specifying one additional parameter for the core winding turn-count.&nbsp; The Chan inductor <font color="green" title="(has been mentioned as a possibility for a future release)">does not currently</font> directly support [[Mutual Inductance]], so unless only a single-winding inductor is being modeled, multiple windings must be added via additional circuitry.&nbsp; The simplest way to do this is to construct an ideal, unity coupled transformer with as many windings as required and then put the Chan inductor directly in parallel with any one of the windings (taking care to set the turns to match that particular winding).&nbsp; Since the magnetic effects (including non-saturated inductance) are already modeled by the Chan inductor, the inductance of the transformer's parallel winding must be enough larger (>>10) not to significantly load the Chan inductance.&nbsp; As before, the inductances for the other windings should be scaled by the square of their individual turns ratios (with respect to the paralleled winding).<br />
<br />
=== Okay, but calculating winding inductances is tedious.&nbsp; Is there some way to just enter a turns count for all the windings? ===<br />
<br />
Yes, this can be done in any of a number of ways.&nbsp; For example, the values for each of the inductances may be directly parametrized via <font color="green"><b title="Lx node1 node2 {Lm*(Nx/Nm)**2}">curly braces</b></font> to be a function of turns ratios (squared), or a subcircuit that accepts turns as a parameter may be used to encapsulate the windings implementation details.<br />
<br />
* Use parameters to to convert input of winding turns to inductance:<br />
[[File: Parameterized_Transformer.gif|right|304px|Turns are entered as parameters from which the inductance is calculated]]<br />
.param Lp=20m Np=200 Ns=20 ; inputs: primary inductance, primary turns, secondary turns<br />
.param Kn=Lp/Np**2 ; calculated inductance per turn squared<br />
Lp 1 0 {Np**2*Kn} ; primary inductance = 200t**2*Kn<br />
Ls 2 0 {Ns**2*Kn} ; secondary inductance = 20t**2*Kn<br />
Kx Lp Ls 1 ; core coupling factor = 1<br />
<br />
Below is a schematic of a simple LTspice subcircuit that is functionally equivalent to a winding (without a core).&nbsp; Its symbol appears just to the right of the schematic.&nbsp; LTspice's fully extended inductor parasitics are included within this model.&nbsp; Observe that the winding is presented with a voltage equal to the core's volts/turn*primary_turns and that the core is presented with a current equal to the winding's ampere-turns = winding's amps*primary_turns.&nbsp; Also note if the leakage inductance and resistances are zero, the winding is completely floating with respect to the core and that the winding performs a voltage ratio transformation (set by the turns ratio) from DC to light.<br />
<br />
* First, the basic winding: Start (dot), Finish, Core:<br />
[[File: Simple Winding Symbol & Subcircuit.gif|right|479px|This simple subcircuit is equivalent to an inductor or transformer winding]]<br />
.subckt Winding s f c params: n=100 L=1u Rs=1m Rp=100<br />
Lw s 1 {L} Rser={Rs} Rpar={Rp} ; leakage and resistance<br />
Ew 1 f c 0 {n} ; impose core volts/turn*turns onto winding<br />
Fw 0 c Ew {n} ; impose winding amperes*turns onto core<br />
.ends Winding<br />
<br />
<br />
==== DC to DC Transformer (no magnetizing inductance - no energy storage) ====<br />
<br />
The transformer winding subcircuits are DC coupled and, when connected to a "core" (1TΩ in parallel with 1pF) that supports DC without drawing current, they combine to make a transformer that draws no magnetizing current, stores no energy and therefore is immune to errant initial conditions.&nbsp; This may be an advantage when first experimenting with new power circuits.<br />
<br />
For better cosmetics the simple DC core may encapsulated in its own subcircuit and symbol.&nbsp;<br />
<br />
[[File: DC_to_DC_Transformer.gif|right|190px|DC to DC (because of "core") transformer with two windings]]<br />
* Here is a DC "core" that does not draw increasing current with time:<br />
.subckt Core_DC C<br />
Cc C 0 1p Rpar=1T ; dump the "core's" ampere-turns into a small conductance<br />
.ends Core_DC<br />
<br />
[[File: DC_to_DC_Transformer_&_Core.gif|right|189px|DC to DC transformer with DC core symbol for aesthetics]]<br />
* DC-to-DC Transformer Equivalent (Netlist Uprocessed):<br />
Xp P 0 C Winding n=1 L=1u Rs=1m Rp=100 ; primary winding of 1:1 transformer<br />
Xs S 0 C Winding n=1 L=1u Rs=1m Rp=100 ; secondary winding of 1:1 transformer<br />
Xc C CoreDC ; subcircuit consisting of 1TΩ in parallel with 1pF<br />
<br />
==== Linear Transformer (linear magnetizing inductance - potentially unlimited energy storage) ====<br />
<br />
A standard linear transformer may easily be created simply by changing the core to a standard inductor with Rs=0.&nbsp; In this form (with a standard ''linear'' magnetizing inductance "core") the model is mostly useful as a perceptual window into the way coupled inductors work in LTspice since linear transformers are more easily and simply built with standard coupled inductors.&nbsp; Note that the magnetizing inductance "core" is the single summing point for the ''ampere-turns'' from all the windings and is the sole source of ''impressed voltage'' (=L*di/dt) reflected onto all the windings.&nbsp; Although this subcircuit is an unnecessary and overly complex representation for a transformer with a linear core inductance, it will be absolutely required if multiple windings are to be "wrapped" onto LTspice's nonlinear Chan inductance model, so take a moment to read it through (the Chan version will follow shortly).<br />
<br />
<br />
* Parametize and wrap an inductor with a subcircuit:<br />
[[File: Linear_Core.gif|right|191px|A linear core is simply an inductor with Rser=0]]<br />
.subckt Core_Linear C params: L=20m Rp=10k Cp=10p<br />
Lc C 0 {L} Rser=0 Rpar={Rp} Cpar={Cp}<br />
.ends Core_Linear<br />
<br />
[[File: Linear_Transformer.gif|right|176px|Transformer with linear core]]<br />
* Linear Transformer Equivalent (Netlist Unprocessed):<br />
Xp P 0 C Winding n=1 L=1u Rs=1m Rp=100 ; primary winding of 1:1 transformer<br />
Xs S 0 C Winding n=1 L=1u Rs=1m Rp=100 ; secondary winding of 1:1 transformer<br />
Xc C Core_Linear L=20m Rp=10k Cp=10p ; subcircuit consisting of an inductor with Rs=0<br />
<br />
* Linear Transformer Equivalent (Netlist Flattened):<br />
[[File: Linear_Transformer_Full.gif|right|438px|Transformer with linear core]]<br />
Lp Ps 1 1u Rser=1m Rpar=100 ; leakage and resistance<br />
Ep 1 Pf C 0 1 ; impose core volts/turn*turns onto winding<br />
Fp 0 C Ep 1 ; impose winding ampere*turns onto core<br />
Lc C 0 20m Rpar=10k Cpar=10p ; liner inductor core (no magnetic saturation)<br />
+ Rser=0 ; Rser must equal zero<br />
Fs 0 C Es 1 ; impose winding ampere*turns onto core<br />
Es 1 Sf C 0 1 ; impose core volts/turn*turns onto winding<br />
Ls Ss 1 1u Rser=1m Rpar=100 ; leakage and resistance<br />
<br />
==== Chan Transformer (saturating magnetizing inductance with hysteresis - limited energy storage) ====<br />
<br />
Now that the windings are separate from the core, a Chan inductor may simply be substituted for the linear inductor core. Since the inductance of a Chan is not assigned, but is determined by its magnetic material, dimensional properties and winding turns, one must adjust inductance by iteratively adjusting the gap and/or winding turns.<br />
<br />
<br />
* Parametize and wrap a Chan inductor with a subcircuit:<br />
[[File: Chan_Core.gif|right|140px|Physical properties based core with hysteresis and saturation]]<br />
.subckt Core_Chan C params:<br />
+ Bs=0.4 Br=0.1 Hc=20 ; Core default magnetic parameters<br />
+ A=25u1 Lm=19m8 Lg=0m7 ; Core default physical parameters<br />
+ Rp=10k Cp=10p ; Core default parallel loss and capacitance<br />
Lc C 0 Rser=0 n=1 ; force Rser=0 and n=1<br />
+ Bs={Bs} Br={Br} Hc={Hc}<br />
+ A={A} Lm={Lm} Lg={Lg}<br />
+ Rpar={Rp} Cpar={Cp}<br />
.ends Core_Chan<br />
<br />
* Chan Transformer Equivalent (Netlist Unprocessed):<br />
Xp P 0 C Winding n=100 L=1u Rs=1m Rp=100 ; primary winding of 1:1 transformer<br />
Xs S 0 C Winding n=100 L=1u Rs=1m Rp=100 ; secondary winding of 1:1 transformer<br />
Xc C Core_Chan ; Chan inductor subcircuit with forced Rs=0 and n=1<br />
+ Bs=0.4 Br=0.1 Hc=20 Br=.10 ; Assigned core magnetic parameters<br />
+ A=25u1 Lm=19m8 Lg=0m7 ; Assigned core physical parameters<br />
+ Rp=10k Cp=10p ; Assigned core parallel loss and capacitance<br />
<br />
----<br />
<br />
<br />
'''Temporary Junk'''<br />
<br />
</pre><br />
And here is the same thing using parameters within curly braces to give value to LTspice's extended inductors and to a coupling statement (mutual inductance).&nbsp; Note that there is no need to create a subcircuit with this method because Lp and Ls can be placed directly on the schematic as symbols and K1 and the .param statement may be placed as SPICE text (this is the section of netlist that would then result).&nbsp; The prior subcircuit form (or something like it) only becomes necessary in conjunction with a custom two-winding transformer symbol or if a nonlinear core (magnetizing inductance) model must be used.<br />
<pre><br />
.param Npri=300 Nsec=30 L=1u K=0.95 Rs=1u Rp=10 Cp=1u<br />
+ Np2=Npri**2 Ns2=Nsec**2 ; turns squared for primary and secondary<br />
Lp P1 P2 {L*Np2} Rser={Rs*Np2} Rpar={Rp*Np2} Cpar={Cp/Np2}<br />
Ls S1 S2 {L*Ns2} Rser={Rs*Ns2} Rpar={Rp*Ns2} Cpar={Cp/Ns2}<br />
K1 Lp Ls {K}<br />
</pre><br />
<br />
Knowing the internal workings of LTspice's coupled inductor style transformer is all very interesting, but how do I make something that uses separate standard inductor symbols for winding, yet also uses the Chan core model with full saturation and hysteresis?<br />
<br />
The following method allows this:<br />
<br />
[[File:Separate_Winding.png]]&nbsp; [''obviously, this section is not yet complete'']<br />
<br />
This model uses the standard inductor symbol edited to appear as a winding subcircuit on a core (connected through a global node).&nbsp; The core may be linear or nonlinear (e.g., LTspice's built in Chan model) and may have as many windings as required.&nbsp; Due to the use of a global core node (which must be different for each core), a different subcircuit is required for each core.<br />
<br />
<br />
{{#widget:DISQUS<br />
|id=ltwiki<br />
|uniqid={{PAGENAME}}<br />
|url={{fullurl:{{PAGENAME}}}}<br />
}}</div>Analogspicemanhttp://ltwiki.org/index.php?title=File:Chan_Core.gif&diff=2087File:Chan Core.gif2019-11-12T17:01:23Z<p>Analogspiceman: Analogspiceman uploaded a new version of File:Chan Core.gif</p>
<hr />
<div>== Summary ==<br />
Physical properties based core with hysteresis and saturation</div>Analogspicemanhttp://ltwiki.org/index.php?title=File:Chan_Core.gif&diff=2086File:Chan Core.gif2019-11-12T16:57:17Z<p>Analogspiceman: Analogspiceman uploaded a new version of File:Chan Core.gif</p>
<hr />
<div>== Summary ==<br />
Physical properties based core with hysteresis and saturation</div>Analogspicemanhttp://ltwiki.org/index.php?title=File:Chan_Core.gif&diff=2085File:Chan Core.gif2019-11-12T16:45:21Z<p>Analogspiceman: Physical properties based core with hysteresis and saturation</p>
<hr />
<div>== Summary ==<br />
Physical properties based core with hysteresis and saturation</div>Analogspicemanhttp://ltwiki.org/index.php?title=Transformers&diff=2084Transformers2019-11-12T05:38:36Z<p>Analogspiceman: /* Linear Transformer (linear magnetizing inductance - potentially unlimited energy storage) */ updated graphics</p>
<hr />
<div>== Transformers ==<br />
<br />
=== Introduction ===<br />
<br />
Do you wish to study the behavior of transformers and inductors and explore their mysteries?&nbsp; LTspice is the ideal learning tool for this purpose. LTspice will faithfully model both ideal and real magnetic devices, but caution is advised when first experimenting with unfamiliar concepts in inductors and transformers.&nbsp; Minimize simulation problems by including reasonably realistic parasitic resistances (both series and parallel) directly into each inductor, whether used individually or as part of a transformer.<br />
<br />
A good learning and reference resource is the [http://coefs.uncc.edu/mnoras/files/2013/03/Transformer-and-Inductor-Design-Handbook_Chapter_17.pdf <i>Transformer and Inductor Design Handbook</i> Chapter 17, Winding Capacitance and Leakage Inductance] 4th Edition by Colonel William. T. McLyman.&nbsp; Mike Engelhardt, the author of LTspice, explains how to make transformers in LTspice in a [https://www.analog.com/en/technical-articles/using-transformers-in-ltspice-switcher-cadiii.html 2006 LT-Magazine article].<br />
<br />
Please keep in mind that starting a simulation with a dc voltage bias on an inductor or transformer winding will cause an initial inductor current only limited by the inductor's series resistance (this would be like trying to initialize an ideal capacitor with a current source - no matter how small the source, the dc voltage reached will approach infinity).&nbsp; In fact, if you are like most engineers, you are much more comfortable with the behavior of capacitors.&nbsp; If so, use this to your advantage by applying duality to think of what to expect when dealing with inductors.<br />
<br />
=== How do I make a transformer in LTspice? === <br />
<br />
[[File:LTspice_Transformer.gif|right|174px|Two lines were used to draw the core]]<br />
<br />
Although it is very possible to make a dedicated subcircuit for a specific transformer, the preferred method of making a generic transformer when drafting a simulation schematic is to simply place a separate inductor for each separate transformer winding and then couple them all together magnetically via a single ''[[Mutual Inductance]] (K) statement'' placed as a [[SPICE Directive]] on the schematic.&nbsp; Note that inductors called out in a [[Mutual Inductance]] statement will be automatically given a phasing dot if one does not already exist.<br />
<br />
K1 L1 L2 L3 1 ; causes phasing dots to automatically appear on L1-L3 inductor symbols<br />
<br />
When creating a new transformer this way, especially for use in a switched-mode power circuit, it is generally best to first specify the mutual coupling coefficient to be exactly unity.&nbsp; By starting with unity coupling there will be no leakage inductance in any winding and this will minimize the likelihood of the windings ringing at extremely high frequencies (which can slow the simulation to a crawl at each switching edge).&nbsp; However, be aware that a mutual inductance value of plus (or minus) unity ''may'' lead to simulation difficulties if ''Skip-the-initial-operating-point-solution'' (UIC) is specified for the .tran command.&nbsp; Prevent this by specifying a realistic resistance for each inductor "winding" (ctrl-right-mouse-click).&nbsp; Note that when coupled inductors are used as transformer windings, individual winding inductances rather than turns ratios must be specified (''inductance ratios should be set to be proportional to <u>the '''square''' of the turns ratios''</u>).<br />
<br />
=== I've created an ideal transformer so it should work at all frequencies, even including DC, right? ===<br />
<br />
No, but lots of users completely misunderstand or overlook this when setting up their simulation.&nbsp; This common mistake can lead to a lot of needless doubt following unexpected and puzzling simulation results produced by LTspice when presented with an ideal transformer that is inadvertently initialized with a large amount of dc voltage applied to its windings.&nbsp; This is probably the most commonly self-inflicted pitfall that trips up users improperly specifying ac voltage sources.<br />
<br />
When LTspice calculates initial conditions for voltage sources, it uses the values at time = 0.&nbsp; Depending on the starting phase angle and delay specified for a sine source, this can be as much as the voltage at the peak of the sine wave.&nbsp; When the simulator attempts to find the circuit's initial solution, this is the equivalent to hooking the transformer up to a large dc voltage source.&nbsp; Current will only be limited by winding resistance (which, in the ideal case, may be zero).&nbsp; Note that a real transformer will saturate at a relatively low current and would normally not store much energy (it would also probably burn up with so much dc applied), but an ideal transformer with an ideal magnetizing inductance may store a physically impossible amount of simulated "virtual" energy.<br />
<br />
Without realizing it, many users may instruct LTspice to initialize the transformer magnetizing inductance with huge starting currents.&nbsp; Since they have used an ideal inductance that does not saturate (like a real transformer would), it starts out with dc current that may take many hundreds of line (or switching) cycles to die away.&nbsp; This completely unrealistic energy source then may dominate the simulation, causing strange and unexpected puzzling behavior.&nbsp; In such cases, LTspice is just innocently following the instructions given it and accurately computing the results (garbage in, garbage out).<br />
<br />
To avoid this bogus and unwanted result, you must either arrange '''''the ac source to be zero at time zero''''' or '''''instruct LTspice not to use a dc solution for the starting point (UIC).'''''<br />
<br />
=== I want to model leakage inductance - how should I do that? ===<br />
<br />
The most flexible method is to keep the windings' mutual inductance statement at unity and add a small discrete leakage inductance in series with each winding.&nbsp; This is the most straightforward way to model transformers with asymmetrical leakage inductances.&nbsp; However, if your transformer is electrically symmetrical, it may be more convenient to simply set the mutual inductance to a value less than one.&nbsp; For each winding the resulting leakage inductance will be (1-K) times that winding's inductance.&nbsp; Note that each winding's coupled inductance also will decrease to K times that winding's inductance, but for typical values of K (>>0.9) this effect will be very small.<br />
<br />
This is how LTspice "sees" coupled inductors:<br />
<br />
For n inductors coupled together with a K statement, each inductor L1 through Ln is divided into two parts, a completely non-coupled "leakage" inductance equal to (1-K)*Lx (where Lx is the particular inductor in question) and a completely coupled "mutual" inductance equal to K*Lx.&nbsp; Voltage and current ratios of the coupled parts are related by the ratio of the square root of the the inductances L1 through Ln (this is the apparent "turns ratio").<br />
<br />
* For example, given two inductors coupled by a K statement:<br />
[[File:Loosely_Coupled_Transformer.gif|right|153px|Coupling is only K=0.2]]<br />
L1 1 0 1H<br />
L2 2 0 1H<br />
Km L1 L2 0.2<br />
<br />
[[File:Loosely_Coupled_Equivalent.gif|right|182px|"Winding" inductance is 1H]]<br />
<br />
* In LTspice, this is the same as:<br />
L1 1 m 0.8H<br />
Lm m 0 0.2H<br />
L2 2 m 0.8H<br />
<br />
Other engineering conventions regarding the definition of K, coupling and formula for leakage inductance are irrelevant to LTspice.&nbsp; Other formula for leakage inductance are intended to find total leakage inductance from an input winding through to an output winding(s) rather than for each individual winding.<br />
<br />
=== How about transformer saturation effects?&nbsp; Can LTspice model those? ===<br />
<br />
Yes, LTspice comes with a non-linear hysteretic core model built in!&nbsp; This is the 1991 model by John Chan et al.&nbsp; Compared to older core models, [[the Chan model]] is particularly robust, computationally efficient and compact, requiring only three parameters to define most any commonly encountered magnetic hysteresis loop.&nbsp; (LTspice also allows building an arbitrary inductance based on self flux and/or any valid function of node voltages and branch currents.&nbsp; [[The Arbitrary Inductor model|The arbitrary inductor model]] can be very efficiently used to create saturation without hysteresis.) <br />
<br />
Once the core material's generic magnetic properties are set, establishing the circuit-level non-linear inductance requires specifying three more parameters to set the geometry of the specific core and specifying one additional parameter for the core winding turn-count.&nbsp; The Chan inductor <font color="green" title="(has been mentioned as a possibility for a future release)">does not currently</font> directly support [[Mutual Inductance]], so unless only a single-winding inductor is being modeled, multiple windings must be added via additional circuitry.&nbsp; The simplest way to do this is to construct an ideal, unity coupled transformer with as many windings as required and then put the Chan inductor directly in parallel with any one of the windings (taking care to set the turns to match that particular winding).&nbsp; Since the magnetic effects (including non-saturated inductance) are already modeled by the Chan inductor, the inductance of the transformer's parallel winding must be enough larger (>>10) not to significantly load the Chan inductance.&nbsp; As before, the inductances for the other windings should be scaled by the square of their individual turns ratios (with respect to the paralleled winding).<br />
<br />
=== Okay, but calculating winding inductances is tedious.&nbsp; Is there some way to just enter a turns count for all the windings? ===<br />
<br />
Yes, this can be done in any of a number of ways.&nbsp; For example, the values for each of the inductances may be directly parametrized via <font color="green"><b title="Lx node1 node2 {Lm*(Nx/Nm)**2}">curly braces</b></font> to be a function of turns ratios (squared), or a subcircuit that accepts turns as a parameter may be used to encapsulate the windings implementation details.<br />
<br />
* Use parameters to to convert input of winding turns to inductance:<br />
[[File: Parameterized_Transformer.gif|right|304px|Turns are entered as parameters from which the inductance is calculated]]<br />
.param Lp=20m Np=200 Ns=20 ; inputs: primary inductance, primary turns, secondary turns<br />
.param Kn=Lp/Np**2 ; calculated inductance per turn squared<br />
Lp 1 0 {Np**2*Kn} ; primary inductance = 200t**2*Kn<br />
Ls 2 0 {Ns**2*Kn} ; secondary inductance = 20t**2*Kn<br />
Kx Lp Ls 1 ; core coupling factor = 1<br />
<br />
Below is a schematic of a simple LTspice subcircuit that is functionally equivalent to a winding (without a core).&nbsp; Its symbol appears just to the right of the schematic.&nbsp; LTspice's fully extended inductor parasitics are included within this model.&nbsp; Observe that the winding is presented with a voltage equal to the core's volts/turn*primary_turns and that the core is presented with a current equal to the winding's ampere-turns = winding's amps*primary_turns.&nbsp; Also note if the leakage inductance and resistances are zero, the winding is completely floating with respect to the core and that the winding performs a voltage ratio transformation (set by the turns ratio) from DC to light.<br />
<br />
* First, the basic winding: Start (dot), Finish, Core:<br />
[[File: Simple Winding Symbol & Subcircuit.gif|right|479px|This simple subcircuit is equivalent to an inductor or transformer winding]]<br />
.subckt Winding s f c params: n=100 L=1u Rs=1m Rp=100<br />
Lw s 1 {L} Rser={Rs} Rpar={Rp} ; leakage and resistance<br />
Ew 1 f c 0 {n} ; impose core volts/turn*turns onto winding<br />
Fw 0 c Ew {n} ; impose winding amperes*turns onto core<br />
.ends Winding<br />
<br />
<br />
==== DC to DC Transformer (no magnetizing inductance - no energy storage) ====<br />
<br />
The transformer winding subcircuits are DC coupled and, when connected to a "core" (1TΩ in parallel with 1pF) that supports DC without drawing current, they combine to make a transformer that draws no magnetizing current, stores no energy and therefore is immune to errant initial conditions.&nbsp; This may be an advantage when first experimenting with new power circuits.<br />
<br />
For better cosmetics the simple DC core may encapsulated in its own subcircuit and symbol.&nbsp;<br />
<br />
[[File: DC_to_DC_Transformer.gif|right|190px|DC to DC (because of "core") transformer with two windings]]<br />
* Here is a DC "core" that does not draw increasing current with time:<br />
.subckt Core_DC C<br />
Cc C 0 1p Rpar=1T ; dump the "core's" ampere-turns into a small conductance<br />
.ends Core_DC<br />
<br />
[[File: DC_to_DC_Transformer_&_Core.gif|right|189px|DC to DC transformer with DC core symbol for aesthetics]]<br />
* DC-to-DC Transformer Equivalent (Netlist Uprocessed):<br />
Xp P 0 C Winding n=1 L=1u Rs=1m Rp=100 ; primary winding of 1:1 transformer<br />
Xs S 0 C Winding n=1 L=1u Rs=1m Rp=100 ; secondary winding of 1:1 transformer<br />
Xc C CoreDC ; subcircuit consisting of 1TΩ in parallel with 1pF<br />
<br />
==== Linear Transformer (linear magnetizing inductance - potentially unlimited energy storage) ====<br />
<br />
A standard linear transformer may easily be created simply by changing the core to a standard inductor with Rs=0.&nbsp; In this form (with a standard ''linear'' magnetizing inductance "core") the model is mostly useful as a perceptual window into the way coupled inductors work in LTspice since linear transformers are more easily and simply built with standard coupled inductors.&nbsp; Note that the magnetizing inductance "core" is the single summing point for the ''ampere-turns'' from all the windings and is the sole source of ''impressed voltage'' (=L*di/dt) reflected onto all the windings.&nbsp; Although this subcircuit is an unnecessary and overly complex representation for a transformer with a linear core inductance, it will be absolutely required if multiple windings are to be "wrapped" onto LTspice's nonlinear Chan inductance model, so take a moment to read it through (the Chan version will follow shortly).<br />
<br />
<br />
* Parametize and wrap an inductor with a subcircuit:<br />
[[File: Linear_Core.gif|right|191px|A linear core is simply an inductor with Rser=0]]<br />
.subckt Core_Linear C params: L=20m Rp=10k Cp=10p<br />
Lc C 0 {L} Rser=0 Rpar={Rp} Cpar={Cp}<br />
.ends Core_Linear<br />
<br />
[[File: Linear_Transformer.gif|right|176px|Transformer with linear core]]<br />
* Linear Transformer Equivalent (Netlist Unprocessed):<br />
Xp P 0 C Winding n=1 L=1u Rs=1m Rp=100 ; primary winding of 1:1 transformer<br />
Xs S 0 C Winding n=1 L=1u Rs=1m Rp=100 ; secondary winding of 1:1 transformer<br />
Xc C Core_Linear L=20m Rp=10k Cp=10p ; subcircuit consisting of an inductor with Rs=0<br />
<br />
* Linear Transformer Equivalent (Netlist Flattened):<br />
[[File: Linear_Transformer_Full.gif|right|438px|Transformer with linear core]]<br />
Lp Ps 1 1u Rser=1m Rpar=100 ; leakage and resistance<br />
Ep 1 Pf C 0 1 ; impose core volts/turn*turns onto winding<br />
Fp 0 C Ep 1 ; impose winding ampere*turns onto core<br />
Lc C 0 20m Rpar=10k Cpar=10p ; liner inductor core (no magnetic saturation)<br />
+ Rser=0 ; Rser must equal zero<br />
Fs 0 C Es 1 ; impose winding ampere*turns onto core<br />
Es 1 Sf C 0 1 ; impose core volts/turn*turns onto winding<br />
Ls Ss 1 1u Rser=1m Rpar=100 ; leakage and resistance<br />
<br />
==== Chan Transformer (saturating magnetizing inductance with hysteresis - limited energy storage) ====<br />
<br />
Now that the windings are separate from the core, a Chan inductor may simply be substituted for the linear inductor core. Since the inductance of a Chan is not assigned, but is determined by its magnetic material, dimensional properties and winding turns, one must adjust inductance by iteratively adjusting the gap and/or winding turns.<br />
<br />
<br />
* Parametize and wrap a Chan inductor with a subcircuit:<br />
.subckt Core_Chan C params:<br />
+ Bs=0.4 Br=0.1 Hc=20 ; Core default magnetic parameters<br />
+ A=25u1 Lm=19m8 Lg=0m7 ; Core default physical parameters<br />
+ Rp=10k Cp=10p ; Core default parallel loss and capacitance<br />
Lc C 0 Rser=0 n=1 ; force Rser=0 and n=1<br />
+ Bs={Bs} Br={Br} Hc={Hc}<br />
+ A={A} Lm={Lm} Lg={Lg}<br />
+ Rpar={Rp} Cpar={Cp}<br />
.ends Core_Chan<br />
<br />
[[File: DC_to_DC_Transformer_&_Core.gif|right|180px|DC to DC transformer with DC core symbol for aesthetics.]]<br />
<br />
* Chan Transformer Equivalent (Netlist Unprocessed):<br />
Xp P 0 C Winding n=100 L=1u Rs=1m Rp=100 ; primary winding of 1:1 transformer<br />
Xs S 0 C Winding n=100 L=1u Rs=1m Rp=100 ; secondary winding of 1:1 transformer<br />
Xc C Core_Chan ; Chan inductor subcircuit with forced Rs=0 and n=1<br />
+ Bs=0.4 Br=0.1 Hc=20 Br=.10 ; Assigned core magnetic parameters<br />
+ A=25u1 Lm=19m8 Lg=0m7 ; Assigned core physical parameters<br />
+ Rp=10k Cp=10p ; Assigned core parallel loss and capacitance<br />
<br />
----<br />
<br />
<br />
'''Temporary Junk'''<br />
<br />
</pre><br />
And here is the same thing using parameters within curly braces to give value to LTspice's extended inductors and to a coupling statement (mutual inductance).&nbsp; Note that there is no need to create a subcircuit with this method because Lp and Ls can be placed directly on the schematic as symbols and K1 and the .param statement may be placed as SPICE text (this is the section of netlist that would then result).&nbsp; The prior subcircuit form (or something like it) only becomes necessary in conjunction with a custom two-winding transformer symbol or if a nonlinear core (magnetizing inductance) model must be used.<br />
<pre><br />
.param Npri=300 Nsec=30 L=1u K=0.95 Rs=1u Rp=10 Cp=1u<br />
+ Np2=Npri**2 Ns2=Nsec**2 ; turns squared for primary and secondary<br />
Lp P1 P2 {L*Np2} Rser={Rs*Np2} Rpar={Rp*Np2} Cpar={Cp/Np2}<br />
Ls S1 S2 {L*Ns2} Rser={Rs*Ns2} Rpar={Rp*Ns2} Cpar={Cp/Ns2}<br />
K1 Lp Ls {K}<br />
</pre><br />
<br />
Knowing the internal workings of LTspice's coupled inductor style transformer is all very interesting, but how do I make something that uses separate standard inductor symbols for winding, yet also uses the Chan core model with full saturation and hysteresis?<br />
<br />
The following method allows this:<br />
<br />
[[File:Separate_Winding.png]]&nbsp; [''obviously, this section is not yet complete'']<br />
<br />
This model uses the standard inductor symbol edited to appear as a winding subcircuit on a core (connected through a global node).&nbsp; The core may be linear or nonlinear (e.g., LTspice's built in Chan model) and may have as many windings as required.&nbsp; Due to the use of a global core node (which must be different for each core), a different subcircuit is required for each core.<br />
<br />
<br />
{{#widget:DISQUS<br />
|id=ltwiki<br />
|uniqid={{PAGENAME}}<br />
|url={{fullurl:{{PAGENAME}}}}<br />
}}</div>Analogspicemanhttp://ltwiki.org/index.php?title=File:Linear_Transformer_Full.gif&diff=2083File:Linear Transformer Full.gif2019-11-12T05:37:53Z<p>Analogspiceman: Analogspiceman uploaded a new version of File:Linear Transformer Full.gif</p>
<hr />
<div>== Summary ==<br />
Transformer with linear core</div>Analogspicemanhttp://ltwiki.org/index.php?title=File:Linear_Transformer_Full.gif&diff=2082File:Linear Transformer Full.gif2019-11-12T05:35:51Z<p>Analogspiceman: Analogspiceman uploaded a new version of File:Linear Transformer Full.gif</p>
<hr />
<div>== Summary ==<br />
Transformer with linear core</div>Analogspicemanhttp://ltwiki.org/index.php?title=File:Linear_Transformer_Full.gif&diff=2081File:Linear Transformer Full.gif2019-11-12T05:32:32Z<p>Analogspiceman: Transformer with linear core</p>
<hr />
<div>== Summary ==<br />
Transformer with linear core</div>Analogspicemanhttp://ltwiki.org/index.php?title=File:Linear_Transformer.gif&diff=2080File:Linear Transformer.gif2019-11-12T05:17:37Z<p>Analogspiceman: Transformer with linear core</p>
<hr />
<div>== Summary ==<br />
Transformer with linear core</div>Analogspicemanhttp://ltwiki.org/index.php?title=File:Linear_Core.gif&diff=2079File:Linear Core.gif2019-11-12T05:12:57Z<p>Analogspiceman: A linear core is simply an inductor with Rser=0</p>
<hr />
<div>== Summary ==<br />
A linear core is simply an inductor with Rser=0</div>Analogspicemanhttp://ltwiki.org/index.php?title=Transformers&diff=2076Transformers2019-11-12T04:57:04Z<p>Analogspiceman: /* DC to DC Transformer (no magnetizing inductance - no energy storage) */ updated graphics</p>
<hr />
<div>== Transformers ==<br />
<br />
=== Introduction ===<br />
<br />
Do you wish to study the behavior of transformers and inductors and explore their mysteries?&nbsp; LTspice is the ideal learning tool for this purpose. LTspice will faithfully model both ideal and real magnetic devices, but caution is advised when first experimenting with unfamiliar concepts in inductors and transformers.&nbsp; Minimize simulation problems by including reasonably realistic parasitic resistances (both series and parallel) directly into each inductor, whether used individually or as part of a transformer.<br />
<br />
A good learning and reference resource is the [http://coefs.uncc.edu/mnoras/files/2013/03/Transformer-and-Inductor-Design-Handbook_Chapter_17.pdf <i>Transformer and Inductor Design Handbook</i> Chapter 17, Winding Capacitance and Leakage Inductance] 4th Edition by Colonel William. T. McLyman.&nbsp; Mike Engelhardt, the author of LTspice, explains how to make transformers in LTspice in a [https://www.analog.com/en/technical-articles/using-transformers-in-ltspice-switcher-cadiii.html 2006 LT-Magazine article].<br />
<br />
Please keep in mind that starting a simulation with a dc voltage bias on an inductor or transformer winding will cause an initial inductor current only limited by the inductor's series resistance (this would be like trying to initialize an ideal capacitor with a current source - no matter how small the source, the dc voltage reached will approach infinity).&nbsp; In fact, if you are like most engineers, you are much more comfortable with the behavior of capacitors.&nbsp; If so, use this to your advantage by applying duality to think of what to expect when dealing with inductors.<br />
<br />
=== How do I make a transformer in LTspice? === <br />
<br />
[[File:LTspice_Transformer.gif|right|174px|Two lines were used to draw the core]]<br />
<br />
Although it is very possible to make a dedicated subcircuit for a specific transformer, the preferred method of making a generic transformer when drafting a simulation schematic is to simply place a separate inductor for each separate transformer winding and then couple them all together magnetically via a single ''[[Mutual Inductance]] (K) statement'' placed as a [[SPICE Directive]] on the schematic.&nbsp; Note that inductors called out in a [[Mutual Inductance]] statement will be automatically given a phasing dot if one does not already exist.<br />
<br />
K1 L1 L2 L3 1 ; causes phasing dots to automatically appear on L1-L3 inductor symbols<br />
<br />
When creating a new transformer this way, especially for use in a switched-mode power circuit, it is generally best to first specify the mutual coupling coefficient to be exactly unity.&nbsp; By starting with unity coupling there will be no leakage inductance in any winding and this will minimize the likelihood of the windings ringing at extremely high frequencies (which can slow the simulation to a crawl at each switching edge).&nbsp; However, be aware that a mutual inductance value of plus (or minus) unity ''may'' lead to simulation difficulties if ''Skip-the-initial-operating-point-solution'' (UIC) is specified for the .tran command.&nbsp; Prevent this by specifying a realistic resistance for each inductor "winding" (ctrl-right-mouse-click).&nbsp; Note that when coupled inductors are used as transformer windings, individual winding inductances rather than turns ratios must be specified (''inductance ratios should be set to be proportional to <u>the '''square''' of the turns ratios''</u>).<br />
<br />
=== I've created an ideal transformer so it should work at all frequencies, even including DC, right? ===<br />
<br />
No, but lots of users completely misunderstand or overlook this when setting up their simulation.&nbsp; This common mistake can lead to a lot of needless doubt following unexpected and puzzling simulation results produced by LTspice when presented with an ideal transformer that is inadvertently initialized with a large amount of dc voltage applied to its windings.&nbsp; This is probably the most commonly self-inflicted pitfall that trips up users improperly specifying ac voltage sources.<br />
<br />
When LTspice calculates initial conditions for voltage sources, it uses the values at time = 0.&nbsp; Depending on the starting phase angle and delay specified for a sine source, this can be as much as the voltage at the peak of the sine wave.&nbsp; When the simulator attempts to find the circuit's initial solution, this is the equivalent to hooking the transformer up to a large dc voltage source.&nbsp; Current will only be limited by winding resistance (which, in the ideal case, may be zero).&nbsp; Note that a real transformer will saturate at a relatively low current and would normally not store much energy (it would also probably burn up with so much dc applied), but an ideal transformer with an ideal magnetizing inductance may store a physically impossible amount of simulated "virtual" energy.<br />
<br />
Without realizing it, many users may instruct LTspice to initialize the transformer magnetizing inductance with huge starting currents.&nbsp; Since they have used an ideal inductance that does not saturate (like a real transformer would), it starts out with dc current that may take many hundreds of line (or switching) cycles to die away.&nbsp; This completely unrealistic energy source then may dominate the simulation, causing strange and unexpected puzzling behavior.&nbsp; In such cases, LTspice is just innocently following the instructions given it and accurately computing the results (garbage in, garbage out).<br />
<br />
To avoid this bogus and unwanted result, you must either arrange '''''the ac source to be zero at time zero''''' or '''''instruct LTspice not to use a dc solution for the starting point (UIC).'''''<br />
<br />
=== I want to model leakage inductance - how should I do that? ===<br />
<br />
The most flexible method is to keep the windings' mutual inductance statement at unity and add a small discrete leakage inductance in series with each winding.&nbsp; This is the most straightforward way to model transformers with asymmetrical leakage inductances.&nbsp; However, if your transformer is electrically symmetrical, it may be more convenient to simply set the mutual inductance to a value less than one.&nbsp; For each winding the resulting leakage inductance will be (1-K) times that winding's inductance.&nbsp; Note that each winding's coupled inductance also will decrease to K times that winding's inductance, but for typical values of K (>>0.9) this effect will be very small.<br />
<br />
This is how LTspice "sees" coupled inductors:<br />
<br />
For n inductors coupled together with a K statement, each inductor L1 through Ln is divided into two parts, a completely non-coupled "leakage" inductance equal to (1-K)*Lx (where Lx is the particular inductor in question) and a completely coupled "mutual" inductance equal to K*Lx.&nbsp; Voltage and current ratios of the coupled parts are related by the ratio of the square root of the the inductances L1 through Ln (this is the apparent "turns ratio").<br />
<br />
* For example, given two inductors coupled by a K statement:<br />
[[File:Loosely_Coupled_Transformer.gif|right|153px|Coupling is only K=0.2]]<br />
L1 1 0 1H<br />
L2 2 0 1H<br />
Km L1 L2 0.2<br />
<br />
[[File:Loosely_Coupled_Equivalent.gif|right|182px|"Winding" inductance is 1H]]<br />
<br />
* In LTspice, this is the same as:<br />
L1 1 m 0.8H<br />
Lm m 0 0.2H<br />
L2 2 m 0.8H<br />
<br />
Other engineering conventions regarding the definition of K, coupling and formula for leakage inductance are irrelevant to LTspice.&nbsp; Other formula for leakage inductance are intended to find total leakage inductance from an input winding through to an output winding(s) rather than for each individual winding.<br />
<br />
=== How about transformer saturation effects?&nbsp; Can LTspice model those? ===<br />
<br />
Yes, LTspice comes with a non-linear hysteretic core model built in!&nbsp; This is the 1991 model by John Chan et al.&nbsp; Compared to older core models, [[the Chan model]] is particularly robust, computationally efficient and compact, requiring only three parameters to define most any commonly encountered magnetic hysteresis loop.&nbsp; (LTspice also allows building an arbitrary inductance based on self flux and/or any valid function of node voltages and branch currents.&nbsp; [[The Arbitrary Inductor model|The arbitrary inductor model]] can be very efficiently used to create saturation without hysteresis.) <br />
<br />
Once the core material's generic magnetic properties are set, establishing the circuit-level non-linear inductance requires specifying three more parameters to set the geometry of the specific core and specifying one additional parameter for the core winding turn-count.&nbsp; The Chan inductor <font color="green" title="(has been mentioned as a possibility for a future release)">does not currently</font> directly support [[Mutual Inductance]], so unless only a single-winding inductor is being modeled, multiple windings must be added via additional circuitry.&nbsp; The simplest way to do this is to construct an ideal, unity coupled transformer with as many windings as required and then put the Chan inductor directly in parallel with any one of the windings (taking care to set the turns to match that particular winding).&nbsp; Since the magnetic effects (including non-saturated inductance) are already modeled by the Chan inductor, the inductance of the transformer's parallel winding must be enough larger (>>10) not to significantly load the Chan inductance.&nbsp; As before, the inductances for the other windings should be scaled by the square of their individual turns ratios (with respect to the paralleled winding).<br />
<br />
=== Okay, but calculating winding inductances is tedious.&nbsp; Is there some way to just enter a turns count for all the windings? ===<br />
<br />
Yes, this can be done in any of a number of ways.&nbsp; For example, the values for each of the inductances may be directly parametrized via <font color="green"><b title="Lx node1 node2 {Lm*(Nx/Nm)**2}">curly braces</b></font> to be a function of turns ratios (squared), or a subcircuit that accepts turns as a parameter may be used to encapsulate the windings implementation details.<br />
<br />
* Use parameters to to convert input of winding turns to inductance:<br />
[[File: Parameterized_Transformer.gif|right|304px|Turns are entered as parameters from which the inductance is calculated]]<br />
.param Lp=20m Np=200 Ns=20 ; inputs: primary inductance, primary turns, secondary turns<br />
.param Kn=Lp/Np**2 ; calculated inductance per turn squared<br />
Lp 1 0 {Np**2*Kn} ; primary inductance = 200t**2*Kn<br />
Ls 2 0 {Ns**2*Kn} ; secondary inductance = 20t**2*Kn<br />
Kx Lp Ls 1 ; core coupling factor = 1<br />
<br />
Below is a schematic of a simple LTspice subcircuit that is functionally equivalent to a winding (without a core).&nbsp; Its symbol appears just to the right of the schematic.&nbsp; LTspice's fully extended inductor parasitics are included within this model.&nbsp; Observe that the winding is presented with a voltage equal to the core's volts/turn*primary_turns and that the core is presented with a current equal to the winding's ampere-turns = winding's amps*primary_turns.&nbsp; Also note if the leakage inductance and resistances are zero, the winding is completely floating with respect to the core and that the winding performs a voltage ratio transformation (set by the turns ratio) from DC to light.<br />
<br />
* First, the basic winding: Start (dot), Finish, Core:<br />
[[File: Simple Winding Symbol & Subcircuit.gif|right|479px|This simple subcircuit is equivalent to an inductor or transformer winding]]<br />
.subckt Winding s f c params: n=100 L=1u Rs=1m Rp=100<br />
Lw s 1 {L} Rser={Rs} Rpar={Rp} ; leakage and resistance<br />
Ew 1 f c 0 {n} ; impose core volts/turn*turns onto winding<br />
Fw 0 c Ew {n} ; impose winding amperes*turns onto core<br />
.ends Winding<br />
<br />
<br />
==== DC to DC Transformer (no magnetizing inductance - no energy storage) ====<br />
<br />
The transformer winding subcircuits are DC coupled and, when connected to a "core" (1TΩ in parallel with 1pF) that supports DC without drawing current, they combine to make a transformer that draws no magnetizing current, stores no energy and therefore is immune to errant initial conditions.&nbsp; This may be an advantage when first experimenting with new power circuits.<br />
<br />
For better cosmetics the simple DC core may encapsulated in its own subcircuit and symbol.&nbsp;<br />
<br />
[[File: DC_to_DC_Transformer.gif|right|190px|DC to DC (because of "core") transformer with two windings]]<br />
* Here is a DC "core" that does not draw increasing current with time:<br />
.subckt Core_DC C<br />
Cc C 0 1p Rpar=1T ; dump the "core's" ampere-turns into a small conductance<br />
.ends Core_DC<br />
<br />
[[File: DC_to_DC_Transformer_&_Core.gif|right|189px|DC to DC transformer with DC core symbol for aesthetics]]<br />
* DC-to-DC Transformer Equivalent (Netlist Uprocessed):<br />
Xp P 0 C Winding n=1 L=1u Rs=1m Rp=100 ; primary winding of 1:1 transformer<br />
Xs S 0 C Winding n=1 L=1u Rs=1m Rp=100 ; secondary winding of 1:1 transformer<br />
Xc C CoreDC ; subcircuit consisting of 1TΩ in parallel with 1pF<br />
<br />
==== Linear Transformer (linear magnetizing inductance - potentially unlimited energy storage) ====<br />
<br />
A standard linear transformer may easily be created simply by changing the core to a standard inductor with Rs=0.&nbsp; In this form (with a standard ''linear'' magnetizing inductance "core") the model is mostly useful as a perceptual window into the way coupled inductors work in LTspice since linear transformers are more easily and simply built with standard coupled inductors.&nbsp; Note that the magnetizing inductance "core" is the single summing point for the ''ampere-turns'' from all the windings and is the sole source of ''impressed voltage'' (=L*di/dt) reflected onto all the windings.&nbsp; Although this subcircuit is an unnecessary and overly complex representation for a transformer with a linear core inductance, it will be absolutely required if multiple windings are to be "wrapped" onto LTspice's nonlinear Chan inductance model, so take a moment to read it through (the Chan version will follow shortly).<br />
<br />
<br />
* Parametize and wrap an inductor with a subcircuit:<br />
.subckt Core_Linear C params: L=20m Rp=10k Cp=10p<br />
Lc C 0 {L} Rser=0 Rpar={Rp} Cpar={Cp}<br />
.ends Core_Linear<br />
<br />
[[File: DC_to_DC_Transformer_&_Core.gif|right|180px|DC to DC transformer with DC core symbol for aesthetics.]]<br />
<br />
* Linear Transformer Equivalent (Netlist Unprocessed):<br />
Xp P 0 C Winding n=1 L=1u Rs=1m Rp=100 ; primary winding of 1:1 transformer<br />
Xs S 0 C Winding n=1 L=1u Rs=1m Rp=100 ; secondary winding of 1:1 transformer<br />
Xc C Core_Linear L=20m Rp=10k Cp=10p ; subcircuit consisting of an inductor with Rs=0<br />
<br />
* Linear Transformer Equivalent (Netlist Flattened):<br />
Lp Ps 1 1u Rser=1m Rpar=100 ; leakage and resistance<br />
Ep 1 Pf C 0 1 ; impose core volts/turn*turns onto winding<br />
Fp 0 C Ep 1 ; impose winding ampere*turns onto core<br />
Lc C 0 20m Rpar=10k Cpar=10p ; liner inductor core (no magnetic saturation)<br />
+ Rser=0 ; Rser must equal zero<br />
Fs 0 C Es 1 ; impose winding ampere*turns onto core<br />
Es 1 Sf C 0 1 ; impose core volts/turn*turns onto winding<br />
Ls Ss 1 1u Rser=1m Rpar=100 ; leakage and resistance<br />
<br />
==== Chan Transformer (saturating magnetizing inductance with hysteresis - limited energy storage) ====<br />
<br />
Now that the windings are separate from the core, a Chan inductor may simply be substituted for the linear inductor core. Since the inductance of a Chan is not assigned, but is determined by its magnetic material, dimensional properties and winding turns, one must adjust inductance by iteratively adjusting the gap and/or winding turns.<br />
<br />
<br />
* Parametize and wrap a Chan inductor with a subcircuit:<br />
.subckt Core_Chan C params:<br />
+ Bs=0.4 Br=0.1 Hc=20 ; Core default magnetic parameters<br />
+ A=25u1 Lm=19m8 Lg=0m7 ; Core default physical parameters<br />
+ Rp=10k Cp=10p ; Core default parallel loss and capacitance<br />
Lc C 0 Rser=0 n=1 ; force Rser=0 and n=1<br />
+ Bs={Bs} Br={Br} Hc={Hc}<br />
+ A={A} Lm={Lm} Lg={Lg}<br />
+ Rpar={Rp} Cpar={Cp}<br />
.ends Core_Chan<br />
<br />
[[File: DC_to_DC_Transformer_&_Core.gif|right|180px|DC to DC transformer with DC core symbol for aesthetics.]]<br />
<br />
* Chan Transformer Equivalent (Netlist Unprocessed):<br />
Xp P 0 C Winding n=100 L=1u Rs=1m Rp=100 ; primary winding of 1:1 transformer<br />
Xs S 0 C Winding n=100 L=1u Rs=1m Rp=100 ; secondary winding of 1:1 transformer<br />
Xc C Core_Chan ; Chan inductor subcircuit with forced Rs=0 and n=1<br />
+ Bs=0.4 Br=0.1 Hc=20 Br=.10 ; Assigned core magnetic parameters<br />
+ A=25u1 Lm=19m8 Lg=0m7 ; Assigned core physical parameters<br />
+ Rp=10k Cp=10p ; Assigned core parallel loss and capacitance<br />
<br />
----<br />
<br />
<br />
'''Temporary Junk'''<br />
<br />
</pre><br />
And here is the same thing using parameters within curly braces to give value to LTspice's extended inductors and to a coupling statement (mutual inductance).&nbsp; Note that there is no need to create a subcircuit with this method because Lp and Ls can be placed directly on the schematic as symbols and K1 and the .param statement may be placed as SPICE text (this is the section of netlist that would then result).&nbsp; The prior subcircuit form (or something like it) only becomes necessary in conjunction with a custom two-winding transformer symbol or if a nonlinear core (magnetizing inductance) model must be used.<br />
<pre><br />
.param Npri=300 Nsec=30 L=1u K=0.95 Rs=1u Rp=10 Cp=1u<br />
+ Np2=Npri**2 Ns2=Nsec**2 ; turns squared for primary and secondary<br />
Lp P1 P2 {L*Np2} Rser={Rs*Np2} Rpar={Rp*Np2} Cpar={Cp/Np2}<br />
Ls S1 S2 {L*Ns2} Rser={Rs*Ns2} Rpar={Rp*Ns2} Cpar={Cp/Ns2}<br />
K1 Lp Ls {K}<br />
</pre><br />
<br />
Knowing the internal workings of LTspice's coupled inductor style transformer is all very interesting, but how do I make something that uses separate standard inductor symbols for winding, yet also uses the Chan core model with full saturation and hysteresis?<br />
<br />
The following method allows this:<br />
<br />
[[File:Separate_Winding.png]]&nbsp; [''obviously, this section is not yet complete'']<br />
<br />
This model uses the standard inductor symbol edited to appear as a winding subcircuit on a core (connected through a global node).&nbsp; The core may be linear or nonlinear (e.g., LTspice's built in Chan model) and may have as many windings as required.&nbsp; Due to the use of a global core node (which must be different for each core), a different subcircuit is required for each core.<br />
<br />
<br />
{{#widget:DISQUS<br />
|id=ltwiki<br />
|uniqid={{PAGENAME}}<br />
|url={{fullurl:{{PAGENAME}}}}<br />
}}</div>Analogspicemanhttp://ltwiki.org/index.php?title=File:DC_to_DC_Transformer_%26_Core.gif&diff=2075File:DC to DC Transformer & Core.gif2019-11-12T04:56:32Z<p>Analogspiceman: Analogspiceman uploaded a new version of File:DC to DC Transformer & Core.gif</p>
<hr />
<div>== Summary ==<br />
DC to DC transformer with DC core symbol for aesthetics.</div>Analogspicemanhttp://ltwiki.org/index.php?title=File:DC_to_DC_Transformer_%26_Core.gif&diff=2074File:DC to DC Transformer & Core.gif2019-11-12T04:54:37Z<p>Analogspiceman: Analogspiceman uploaded a new version of File:DC to DC Transformer & Core.gif</p>
<hr />
<div>== Summary ==<br />
DC to DC transformer with DC core symbol for aesthetics.</div>Analogspicemanhttp://ltwiki.org/index.php?title=File:DC_to_DC_Transformer_%26_Core.gif&diff=2073File:DC to DC Transformer & Core.gif2019-11-12T04:51:12Z<p>Analogspiceman: Analogspiceman uploaded a new version of File:DC to DC Transformer & Core.gif</p>
<hr />
<div>== Summary ==<br />
DC to DC transformer with DC core symbol for aesthetics.</div>Analogspicemanhttp://ltwiki.org/index.php?title=File:DC_to_DC_Transformer_%26_Core.gif&diff=2072File:DC to DC Transformer & Core.gif2019-11-12T04:49:37Z<p>Analogspiceman: Analogspiceman uploaded a new version of File:DC to DC Transformer & Core.gif</p>
<hr />
<div>== Summary ==<br />
DC to DC transformer with DC core symbol for aesthetics.</div>Analogspicemanhttp://ltwiki.org/index.php?title=File:DC_to_DC_Transformer_%26_Core.gif&diff=2071File:DC to DC Transformer & Core.gif2019-11-12T04:47:45Z<p>Analogspiceman: Analogspiceman uploaded a new version of File:DC to DC Transformer & Core.gif</p>
<hr />
<div>== Summary ==<br />
DC to DC transformer with DC core symbol for aesthetics.</div>Analogspicemanhttp://ltwiki.org/index.php?title=File:DC_to_DC_Transformer_%26_Core.gif&diff=2070File:DC to DC Transformer & Core.gif2019-11-12T04:45:20Z<p>Analogspiceman: Analogspiceman uploaded a new version of File:DC to DC Transformer & Core.gif</p>
<hr />
<div>== Summary ==<br />
DC to DC transformer with DC core symbol for aesthetics.</div>Analogspiceman