Version 4
SHEET 1 1100 680
WIRE -384 288 -384 272
WIRE -384 400 -384 368
WIRE -112 176 -144 176
WIRE 0 176 -32 176
WIRE 0 272 -384 272
WIRE 64 176 0 176
WIRE 64 272 0 272
WIRE 176 432 176 400
WIRE 320 272 288 272
WIRE 336 176 288 176
WIRE 352 272 320 272
WIRE 464 32 432 32
WIRE 464 64 464 32
WIRE 464 176 464 144
WIRE 480 272 432 272
WIRE 480 272 480 240
WIRE 528 240 480 240
WIRE 528 288 528 240
WIRE 528 384 528 368
WIRE 576 240 528 240
WIRE 688 240 576 240
WIRE 688 272 688 240
WIRE 688 368 688 336
FLAG 336 176 VCC
FLAG 464 176 0
FLAG 688 368 0
FLAG -384 400 0
FLAG 432 32 VCC
FLAG 0 176 en
FLAG 0 272 in
FLAG 576 240 out
FLAG -144 176 vcc
FLAG 320 272 2
FLAG 528 384 0
FLAG 176 432 0
SYMBOL res -128 192 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 0 56 VBottom 0
SYMATTR InstName R1
SYMATTR Value 1k
SYMBOL voltage -384 272 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value PULSE(0 5 1u 10n 10n 5u 10u)
SYMBOL voltage 464 48 R0
SYMATTR InstName V2
SYMATTR Value 12
SYMBOL cap 672 272 R0
SYMATTR InstName C1
SYMATTR Value 5n
SYMBOL res 336 288 R270
WINDOW 0 -27 64 VTop 0
WINDOW 3 -1 95 VBottom 0
SYMATTR InstName R3
SYMATTR Value 1
SYMBOL res 512 272 R0
SYMATTR InstName R4
SYMATTR Value 1g
SYMBOL EXTRA\\IXYS\\GATEDRV\\IXDD430YI 176 272 R0
SYMATTR InstName U2
TEXT -328 72 Left 0 !.tran 0 30u 0 5n
TEXT -320 -552 Left 0 ;Gate driver IXDD414 from IXYS\nHelmut Sennewald 26/12/2005 \nhttp://www.ixys.com/99061.pdf\nhttp://www.ixys.com/9200-0231.pdf \n \nIXDD414.lib SPICE model changes for LTspice, HS\n \n Two NMOS parameter lines removed \n*+ DW =-0.18000E-06 DL =-0.72500E-06\n*+ XQC = 1\n \nDouble interface pins "out" have to be splitted into "out" and "out1"\n.SUBCKT IXDD414 VCC IN EN GND VCC OUT OUT GND   \n-->\n.SUBCKT IXDD414 VCC IN EN GND VCC OUT OUT1 GND   \nROUT1 OUT OUT1 1m\n \n Simplified 74ACTxx models added
TEXT 664 208 Left 0 ;MOSFET
TEXT -328 32 Left 0 !.options plotwinsize=0
RECTANGLE Normal 768 416 624 192