# Difference between revisions of "B sources (common examples)"

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the simulation step size, i.e. make it smaller and try again. (This is quite different than just testing if the magnitude of | the simulation step size, i.e. make it smaller and try again. (This is quite different than just testing if the magnitude of | ||

slope of the voltage across the source gets too large.) | slope of the voltage across the source gets too large.) | ||

+ | |||

+ | By experimentation, it seems Mike's description is not exactly correct, at least for the last time step while leaving the state change constraint where it seems the allowable tripdt limit is increased by two. Here is a netlist that illustrates LTspice invoking the time step state change constraint. | ||

+ | |||

+ | V1 1 0 SINE(0 1 1k)<br> | ||

+ | B1 2 0 V=u(V(1)) tripdv=0.1 tripdt=10n <br> | ||

+ | .opt plotwinsize=0 <br> | ||

+ | .tran 5m <br> | ||

+ | |||

+ | The u() function is digital in nature so changing tripdv over a wide range has little effect just so long as it is a bit smaller than the state change of the unit step function. However, tripdt directly controls the maximum allowable time change through the state change except the last of these time changes may be twice the limit (no doubt due to the standard way LTspice increases time steps by doubling). | ||

+ | |||

+ | The problem with the tripdv/tripdt constraint arises when the b-source voltage is analog rather than digital in nature because it is very possible to choose these limits such that normal voltage changes exceed them. That causes an effect much like a very small maximum time step and the simulation may run very slowly. | ||

Note that a transient simulation is not continuous with time, but is actually a collection of consecutive solutions to the circuit at a series of discrete time steps. In order to make the simulation run as quickly as possible, the simulation engine constantly monitors the nonlinear error between adjacent steps and will adjust step size dynamically for a step size that doesn't lead to an unacceptable error. If the error is too small, the step size is still used, but the *next* time step is made larger. If the error is too large, the step size is rejected, i.e., the solution results are discarded and another solution is attempted with a smaller step size. | Note that a transient simulation is not continuous with time, but is actually a collection of consecutive solutions to the circuit at a series of discrete time steps. In order to make the simulation run as quickly as possible, the simulation engine constantly monitors the nonlinear error between adjacent steps and will adjust step size dynamically for a step size that doesn't lead to an unacceptable error. If the error is too small, the step size is still used, but the *next* time step is made larger. If the error is too large, the step size is rejected, i.e., the solution results are discarded and another solution is attempted with a smaller step size. |

## Revision as of 13:23, 23 February 2016

Add examples such as:

### When, why and how to use *tripdt* and *tripdv* with explanation

Help states, "*If the voltage across a source changes by more than tripdv volts in tripdt seconds, that simulation time step is rejected.*"

This is rather terse, but it seems to mean, when attempting a solution for the next transient simulation step, in addition to comparing the non linear error of the next step to **reltol** and other step size acceptance limits, the simulation engine will perform the following test:

IF (the voltage change *across* the b-source > **tripdv** AND the time change across the simulation step > **tripdt**) THEN reject
the simulation step size, i.e. make it smaller and try again. (This is quite different than just testing if the magnitude of
slope of the voltage across the source gets too large.)

By experimentation, it seems Mike's description is not exactly correct, at least for the last time step while leaving the state change constraint where it seems the allowable tripdt limit is increased by two. Here is a netlist that illustrates LTspice invoking the time step state change constraint.

V1 1 0 SINE(0 1 1k)

B1 2 0 V=u(V(1)) tripdv=0.1 tripdt=10n

.opt plotwinsize=0

.tran 5m

The u() function is digital in nature so changing tripdv over a wide range has little effect just so long as it is a bit smaller than the state change of the unit step function. However, tripdt directly controls the maximum allowable time change through the state change except the last of these time changes may be twice the limit (no doubt due to the standard way LTspice increases time steps by doubling).

The problem with the tripdv/tripdt constraint arises when the b-source voltage is analog rather than digital in nature because it is very possible to choose these limits such that normal voltage changes exceed them. That causes an effect much like a very small maximum time step and the simulation may run very slowly.

Note that a transient simulation is not continuous with time, but is actually a collection of consecutive solutions to the circuit at a series of discrete time steps. In order to make the simulation run as quickly as possible, the simulation engine constantly monitors the nonlinear error between adjacent steps and will adjust step size dynamically for a step size that doesn't lead to an unacceptable error. If the error is too small, the step size is still used, but the *next* time step is made larger. If the error is too large, the step size is rejected, i.e., the solution results are discarded and another solution is attempted with a smaller step size.

It seems that even if **tripdt** and **tripdv** are not specified, LTspice still applies an internal default test to accept or reject a step based on whether or not the behavioral source changes too much in one time step. Perhaps this internal default function is separate from the **tripdv/tripdt** test, or perhaps a default value for **tripdt** is estimated based on something like the the simulation end time.

How to make a discretized (pseudo-digital) source

Various kinds of output limiters (tanh, limit, etc.) and explain why and where these are well worth using

Show how to convert a BV source into an equivalent BI source (with parallel capacitor) and explain why this is generally a much better form to use

other??

*I've got an equation in an arbitrary behavioral source that uses the variable *TIME* to plot. What I can't figure out is how to cause this to repeat at some interval.*

Time is a ramp that never resets. What you need is a replacement for time in your equation that resets to zero at your repeat interval, i.e., a sawtooth function.

You could set up a standalone voltage source to make the sawtooth and replace "time" in your equation with the sawtooth node, "v(x)" or you could do this directly in the equation by replacing "time" with either of the following expressions:

- time-int(time/m)*m ; where m is the modulus (repeat interval)
- idtmod(1,0,m) ; integrates 1*dt with 0 offset at modulus m

If you want, you could define such expressions with a .function statement in order to keep your b-source equation from getting too messy.

.function a(m)= time-int(time/m)*m .func b(m)= idtmod(1,0,m) ; .func is the short name .param r=4 ; r is the actual reset modulus you wish to use

Now, within your b-source equation, you could replace each instance of "time" with either "a(r)" or "b(r)" (or change the names to suit what makes sense to you).

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