LTspice/SwitcherCAD III is a complete and fully functional SPICE program (electronic circuit simulator) that is available free of charge from the Linear Technology Corporation (LTC). Because of its superior performance, excellent community support and ease of file sharing, it is rapidly replacing all other SPICE programs, regardless of price, as the simulator of choice for hobbyists, students and professionals alike.
The purpose of this topic is to explore and explain some of the many useful or quirky features that have never appeared in the standard documentation whether due to simple oversight, the feature being considered not important enough, not polished enough or functionally obsolete – or even due to the feature being considered proprietary to another brand of SPICE or to LTspice itself. LTC considers some of these undocumented features as fair game for open discussion in public forums such as the LTspice Yahoo users group, whereas for others, it considers any such open discussions as a violation of its License Agreement.
"Fair game" is any feature that is or has ever been part of the normal distribution, i.e., appears or ever has appeared in the Help file, as plain text in any of the included sample or example files, in any program menu available during normal use of the program, or in any of the materials, presentation files or handouts from any LTspice seminar presentation. Such items are all considered as having been officially "documented" and are specifically allowed as discussion topics in public forums such as the LTspice Yahoo users group. However, be advised that any items that have been dropped from the documentation, even if still functional, should generally be considered obsolete and in risk of being purged from the program code at any time (fortunately, such items are quite rare).
As to the classification of anything not covered above, you must make your own common sense judgment or ask the advice of the users group moderator or the program author via private email. Clearly any standard, generic SPICE feature that works in LTspice would be okay for general use and discussion regardless of its state of documentation in LTspice. A lot of the standard devices have undocumented parameters (e.g., tempcos) or syntax (e.g., Pspice specific compatibility) that would fall into this category. Just as clearly, any undocumented A-device that is specific to LTC’s encrypted, high performance SMPS IC models would likely be considered proprietary knowledge to be protected with due diligence from release to the public domain, lest LTC’s competitors gain the de facto permission to freely copy them in their own circuit simulator offerings (however, it is difficult to see how LTC could legitimately prevent private individuals from making use of such undocumented features in their own simulations or discussing them via private communications). For these reasons, this last category of undocumented features will not be directly discussed here.
A-devices are Linear Technology Corporation's proprietary special function/mixed mode circuit simulation elements. According to LTspice’s Help file, the behavior of a number of these is undocumented because they frequently change with each new set of models available for LTspice (this simply is not true and is most likely offered as both as a credible reason for keeping them hidden and to discourage anyone from bothering to attempt to explore and/or use them).
The Help file lists A-device syntax as:
Annn n001 n002 n003 n004 n005 n006 n007 n008 <model> [instance parameters]
Note that all A-devices have up to 8 possible active device connections, up to 5 inputs (terminals 1 through 5) usually 2 outputs (terminals 6 and 7), and with terminal 8 always as the device common. A-devices are always netlisted with the full eight connections. The netlister connects any unused inputs and outputs to terminal 8. The A-device compiler recognizes this condition as a flag that that terminal is not used and removes it from the simulation matrix. Current is sourced or sunk from the complementary outputs, terminals 6 and 7, and returned through device common, terminal 8.
A-devices are implemented this way to allow a single device type to act as any combination of a 1 to 5 input, 1 to 2 output device, but with no simulation speed penalty for unused terminals. Refer to the program Help file for more details about LTspice’s documented A-devices.
Here is a listing of all known LTspice A-devices.
Documented directly in Help:
- Buf (aka Buf1 Inv)
- XOR – when more than two inputs are present, uses the correct definition of true if one and only one input is true, rather than the more common incorrect definition of true if an odd number of inputs are true (which should be called an ODD/NODD gate rather than an XOR/XNOR gate).
- Schmitt (aka SchmittBuf SchmittInv DifSchmitt DiffSchmittBuf DiffSchmittInv)
- Modulator (aka Modulate Modulate2)
Not documented in Help but available via the schematic Component Selector:
- SRflop – located in Digital
- PhaseDet (aka PhiDet) – located in Digital
- SampleHold (aka Sample) – located in Special Functions
Documented in sample schematics included with the program distribution:
- PhaseDet (aka PhiDet) – located in examples/Educational/PLL2.asc
- SampleHold (aka Sample) – located in examples/Educational/S&H.asc
- OTA – used in UniversalOpamp plaintext subcircuits (in lib/sub), but users group posts (some long standing) containing information about additional aspects of this have been censored
Not documented anywhere by LTC:
- Counter – documented in the users group (has been officially approved for public use)
- XxxxxxXxxx – prior long standing users group posts about this digital toggle type device have now been censored
- XxXxxXXX – DAC type device never discussed in the users group
- XXXXX – DAC type device never discussed in the users group
- XXXX – DAC type device never discussed in the users group
- Xxx – amplifier type device never discussed in the users group
Not documented anywhere by LTC, but the first two of these devices were extensively documented in the users group. All three devices were eliminated /protected in June 2006 (approximately at release 2.17u ) and all users group posts (some long standing) about these devices have been censored /deleted from the users group archive:
- XXXxxxx – PWM current mode control comparator and latch
- XxxXxx – used for making PWM IC oscillators
- Xxxxx – used for making PWM IC oscillators
Obsolete devices that have been deleted from the LTspice executable:
The three DACs, XxXxxXXX, XxxXXX, XXXX, are specialized A-devices that probably are of little general interest (although their functions and pinouts could likely be easily guessed by examining the data sheets of the few specialized LTC ICs making use of them).
The XXXX seems to be the only straightforward, generic DAC, but very spice-efficient DACs are quite easy to make using standard, approved devices.
located in Digital
PhaseDet (aka PhiDet)
located in Digital located in examples/Educational/PLL2.asc
SampleHold (aka Sample)
located in Special Functions located in examples/Educational/S&H.asc
The OTA (Operational Transconductance Amplifier) is used in the various UniversalOpamp plaintext subcircuits (located in a standard LTspice program installation in lib/sub)
The default transfer function is a hyperbolic tangent (tanh), which closely approximates the transfer function of a bipolar transistor differential amplifier (this limit can be disabled by adding the flag parameter, linear). Two differential input pairs are available on pins 1 through 4 (+ –) (+ –). The transconductance output appears on pin 7. As usual pin 8, if connected, becomes the device's floating "gnd" reference. For reference, a dc "rail" voltage, which represents the maximum possible (positive) output (calculated from combining both voltage and current saturation limits), appears on pin 6.
- Ref is the input offset voltage
- G is the input gain, where input = (Ref – V(1,2) ) * V(3,4)
- Iout is the output saturation current, which may be superseded by one or both of
- Isrc is the output sourcing saturation current (= Iout if not specified)
- Isink is the output sinking saturation current (= -Iout if not specified)
- Linear is a flag parameter that, if present, disables output limiting
- Ioffset is the output offset current
- Rout is the internal output resistance
- Cout is the capacitance in parallel with Rout
- Vhigh is the positive output "rail" voltage
- Vlow is the negative output "rail" voltage
- Rclamp is the clamping resistance to the voltage rails
- EN is the voltage noise density
- ENk is the voltage noise knee frequency
- IN is the current noise density
- INk is the current noise knee frequency
- INcm is the common mode (?) current noise density
- INcmk is the common mode (?) current noise knee frequency
Output Current Limit:
- with no flag parameter: Io = tanh ( G * (Ref – V(1,2) ) * V(3,4) / Isat ) * Isat + Idc + Ioffset
where Isat = ( Isink – Isrc ) / 2 and Idc = ( Isink + Isrc ) / 2
- with the linear flag parameter: Io = G * (Ref – V(1,2) ) * V(3,4) + Ioffset
Output Voltage Limit:
- clamps through a resistance of Rclamp to "rails" of Vhigh and -Vlow
Noise Voltage Density:
- Vnoise = (EN + IN * Rin_equivalent) * G * Rout
Counter (divide by n):
This simple device divides the pulse stream on terminal 1 by round(n) where n is specified by the expression assigned to the cycles parameter (this expression may contain node voltages and branch currents). Standard complementary digital outputs are available on terminals 6 and 7. Key parameters (with non default example values) are: cycles=3 duty=0.2 (if omitted, defaults to 0.5). The width of output pulses is, width = round(cycles*duty). Most of the usual digital a-device parameters also apply, e.g.: Trise, Vhigh, Vlow, Ref, etc. with the exception of Td, which is ignored (the Counter accepts no delay).
Symbol and test circuit are available in the online Yahoo LTspice users group: Files > Tut > Digital A-Devices > A-counter_test1.asc and counter1.asy.
The implementation is fairly straightforward except for the Reset function. Resetting the Counter A-device requires that it be clocked when the value of the "cycles" is at (or near) zero.
While many b-source features were not documented until relatively recently (~2007), most are now at least touched upon in Help and the few that are not are covered in the B sources (complete reference) in this wiki.
- BR=f(x) arbitrary resistor where f is an arbitrary function of x (with the special meaning of the voltage across R in this context) and/or any valid node voltage, branch current, etc.
- [[units] Freq=<valuelist> [delay=<value>]] (Pspice compatible format)
The transfer function of the Freq circuit element is specified by an ordered list of points of freq(Hz), mag(dB) and phase(deg) as follows: <(f1,m1,p1)[(f2,m2,p2)...]> where f1<f2<f3, etc. The following units specifiers may optionally precede the Freq keyword: “rad”=radians, “mag”=non dB, (“dB” and “deg” return the defaults), “r_i”=real and imaginary in place of magnitude and phase. If a delay value is called out, the phases of the table values are modified to reflect the delay (delay is automatically adjusted to maintain causality in any case).
- NoJacob The optional NoJacob flag parameter unburdens a device from carrying the mathematical overhead of a Jacobian. For linear or certain well behaved b-source expressions, this small reduction in computational burden can reduce run times slightly. Use with extreme caution, as this greatly increases the risk of creating convergence problems or other errors if misapplied.
- ~ Boolean operator: convert succeeding expression to Boolean then invert
- == Boolean operator: true if preceding expression is equal to succeeding expression, otherwise false
- boltz Boltzmann constant = 1.38062 e-23
- planck Planck's constant = 6.62620 e-34
- echarge Charge of an electron = 1.6021765 e-19
- kelvin Absolute Zero in degrees C = -273.150
- square(x) Function = x**2
- tbl Alternate function name, aka table (look-up table)
- stp(x) Alternate function name, aka u(x) (unit step)
- fra(x) Function, very similar to white(x), but = 0 if not SMPS in steady state condition
Add documentation for data file input and triggered sources and the Pspice compatible behavioral forms for E and G sources (at some point, perhaps ~2007, these were added to Help).
The Piecewise Linear Voltage Source needs a writeup for these forms:
PWL (0 0 +0.1 1 +0.1 0 +0.1 1 +0.1 0 +0.1 0.5) ; PWL with incremental time (+) format PWL repeat for 7 file=pwl_data.txt endrepeat repeat for 6 file=pwl_data2.txt endrepeat PWL repeat forever file=pwl_data.txt endrepeat PWL value_scale_factor=0.5 time_scale_factor=0.7 FILE=pwl_data.txt * Scale the time and voltage values of a file PWL file=pwl_data.txt trigger V(trig)>0
Note that the Trigger is actually an enable output while true function.
Other Stuff I Forgot
... should be added here or given its own section if warranted.
LTspice has a cleaner syntax for voltage controlled switches, but has no problem with any PSpice voltage controlled switch syntax.
LTspice can execute behavioral sources in either 2G6, PSpice, or Berkeley SPICE syntax in addition to its own enlarged set of behavioral language.
It's not in the .model section of the Help file, but LTspice seems to recognize standard model statements for resistors (RES) and capacitors (CAP), but not inductors (IND).
As in many other SPICE simulators, "RES" and "CAP" are allowed as model keywords. For example, with the following line of spicetext
.model X7R cap (T_measured=20 Tc1=0 Tc2=-19u)
on a schematic, if a capacitor then has "X7R" entered into its "SpiceModel" field (via ctrl-right mouse click) its base value will be multiplied by the following temperature factor, TF
TF = 1 + Tc1*(T-Tmeasured) + Tc2*(T-Tmeasured)**2 where T = the global temperature TEMP or the local instance if specified.
I haven't checked if higher order factors are accepted or if voltage or current factors can be used (they work for some other SPICEs).
The Help file specifies the optional instance of [temp=<value>] syntax for resistors, capacitors and inductors, but only for capacitors does it define this as "instance temperature (for tempcos in a corresponding .model statement)," although nothing further about the model syntax is mentioned.
The help file does not document the "noiseless" control parameter which applies to the resistance in many LTspice circuit elements with resistive elements (resistors, switches, RC lines, others). As its name suggests, this parameter blocks its applicable element's contribution to noise calculations.
The Behavioral Resistor
Create a behavioral resistor by right-mouse-button clicking on its Value field and edit its value to read: R=<expression>. This feature is undocumented, but is considered permissible to use. The expression syntax is the same as for a general behavioral source (see B-sources in Help).
The resistance must not go to zero and negative values can lead to convergence problems, so it is advisable to restrict its values to within a meaningful range as per the following Value example:
R = limit(1,100k,V(1,2)*I(V1)) ; R stays between 1 ohm and 100k
To plot an I-V curve, start by using the differential cursor to plot the voltage across the resistor. First click and hold down the left-mouse-button (red probe icon) on one side of the resistor and then drag and drop the black probe icon on the other side. Finish by dragging the mouse pointer over the x-axis (a ruler icon will appear) and the click the left mouse button to bring up the Horizontal Axis menu. Change the Quantity Plotted from "time" to "I(R1)" (assuming R1 is your behavioral resistor).
There are a whole lot of .option parameters and other control parameters (mostly legacy from SPICE 2 and Pspice) that should be documented (a few probably actually could be useful).
Anyone else recall something?
.OPTIONS See message #20174
A-Devices See message #19378
Lossy Transmission Lines
There are two undocumented lossy transmission line models implemented in LTspice. One is CPL model (P device), and the other is TXL model (Y device).
The undocumented CPL is a KSPICE-like element, which in theory should be similar to the RLGC model, but without frequency dependent loss (neither skin effect and nor frequency dependent dielectric loss). It also has at least one bug causing an incorrect output voltage offset (a workaround is to only use signals with no dc offset).
Below are example netlists from Kspice, which have been translated as required (very little) into LTspice syntax.
****** test circuit for CPL transmission line simulation ******* * M1 0 268 299 0 MN0P9 w=18u l=1u M2 299 267 748 0 MN0P9 w=18u l=1u M3 0 168 648 0 MN0P9 w=18u l=0u9 M4 1 268 748 1 MP1P0 w=36u l=1u M5 1 267 748 1 MP1P0 w=36u l=1u M6 1 168 648 1 MP1P0 w=36u l=1u * CN648 648 0 25f4 CN651 651 0 7f4 CN748 748 0 25f4 CN751 751 0 9f4 CN299 299 0 5f4 * P1 648 748 0 651 751 0 Pline * vdd 1 0 DC 5 Vk 267 0 DC 5 * *Vs 168 0 PWL (4 15n9 0 16n1 5 31n9 5 32n1 0) *Vs 268 0 PWL (4 15n9 0 16n1 5 31n9 5 32n1 0) * Vs1 168 0 Pulse (0 5 15n9 0n2 0n2 15n8 60n) Vs2 268 0 Pulse (0 5 15n9 0n2 0n2 15n8 60n) * .tran 0n2 47n9 0 1n .model Pline CPL + R=0.2 0 0.2 + L=9n13 3n3 9n13 + G=0 0 0 + C=365f -90f 365f + Length=24 ********************** MODEL SPECIFICATION ********************** .model MN0P9 NMOS Vto=0.8 Kp=48u Gamma=0.30 Phi=0.55 Lambda=0 + Cgso=0 Cgdo=0 Cj=0 Cjsw=0 Tox=18u Ld=0 .model MP1P0 PMOS Vto=-0.8 Kp=21u Gamma=0.45 Phi=0.61 Lambda=0 + Cgso=0 Cgdo=0 Cj=0 Cjsw=0 Tox=18u Ld=0 .end ******* test circuit for TXL transmission line simulation ******* M5 0 168 2 0 MN0P9 w=18u l=0u9 M6 1 168 2 1 MP1P0 w=36u l=1u Cn2 2 0 25f4 Cn3 3 0 7f4 Y1 2 0 3 0 Ymod Vdd 1 0 dc 5.0 Vs 168 0 Pulse (0 5 15n9 0n2 0n2 15n8 32n) *Vs 168 0 PWL(15n9 0 16n1 5 31n9 5 32n1 0) .tran 0n2 47n 0 0n1 .model MN0P9 NMOS Vto=0.8 Kp=48u Gamma=0.3 Phi=0.55 Lambda=0 + Cgso=0 Cgdo=0 Cj=0 Cjsw=0 Tox=18u Ld=0 .model MP1P0 PMOS Vto=-0.8 Kp=21u Gamma=0.45 Phi=0.61 Lambda=0 + Cgso=0 Cgdo=0 Cj=0 Cjsw=0 Tox=18u Ld=0 .model Ymod Txl R=12.45 L=9u G=0 C=0p47 Length=16 .end
Miscellaneous Hints and Tricks
Schematic Editor Key Combinations:
- Shift-Ctrl-Alt-R: Permanently renumbers all reference designators within the schematic
- Shift-Ctrl-Alt-H: Temporarily highlights all hidden text within the schematic
There's a new option called tseed that lets you seed the integrator with a specific timestep guess. Just add the SPICE directive ".options tseed=100n" to your schematic (see section on .options).