Undocumented LTspice

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Revision as of 13:31, 10 August 2011 by Analogspiceman (talk | contribs) (OTA)

Introduction

LTspice/SwitcherCAD III is a complete and fully functional SPICE program (electronic circuit simulator) that is available free of charge from the Linear Technology Corporation (LTC).  Because of its superior performance, excellent community support and ease of file sharing, it is rapidly replacing all other SPICE programs, regardless of price, as the simulator of choice for hobbyists, students and professionals alike.

The purpose of this topic is to explore and explain some of the many useful or quirky features that have never appeared in the standard documentation whether due to simple oversight, the feature being considered not important enough, not polished enough or functionally obsolete – or even due to the feature being considered proprietary to another brand of SPICE or to LTspice itself.  LTC considers some of these undocumented features as fair game for open discussion in public forums such as the LTspice Yahoo users group, whereas for others, it considers any such open discussions as a violation of its License Agreement.

"Fair game" is any feature that is or has ever been part of the normal distribution, i.e., appears or ever has appeared in the Help file, as plain text in any of the included sample or example files, in any program menu available during normal use of the program, or in any of the materials, presentation files or handouts from any LTspice seminar presentation.  Such items are all considered as having been officially "documented" and are specifically allowed as discussion topics in public forums such as the LTspice Yahoo users group.  However, be advised that any items that have been dropped from the documentation, even if still functional, should generally be considered obsolete and in risk of being purged from the program code at any time (fortunately, such items are quite rare).

As to the classification of anything not covered above, you must make your own common sense judgment or ask the advice of the users group moderator or the program author via private email.  Clearly any standard, generic SPICE feature that works in LTspice would be okay for general use and discussion regardless of its state of documentation in LTspice.  A lot of the standard devices have undocumented parameters (e.g., tempcos) or syntax (e.g., Pspice specific compatibility) that would fall into this category.  Just as clearly, any undocumented A-device that is specific to LTC’s encrypted, high performance SMPS IC models would likely be considered proprietary knowledge to be protected with due diligence from release to the public domain, lest LTC’s competitors gain the de facto permission to freely copy them in their own circuit simulator offerings (however, it is difficult to see how LTC could legitimately prevent private individuals from making use of such undocumented features in their own simulations or discussing them via private communications).  For these reasons, this last category of undocumented features will not be directly discussed here.


Numerical Accuracy/Dynamic Range

LTspice generally represents numbers using 64 bit double precision arithmetic with the following data structure:

Sign: 1 bit, exponent: 11 bits, fraction: 52 bits.

For general component values LTspice will accept numbers that range in magnitude from as large as ± 1.798 x 10+308 down to as small as ± 2.225 x 10−308.  Values exceeding this range are interpreted as ± infinity or as zero.  However, because of the 52 bit precision of the fractional part of the significand, the practical numerical dynamic range will be circuit dependent.  A 53 bit binary significand gives LTspice about 16 significant figures for internal math computations.  Thus, if impedances vary by more than 16 orders of magnitude, numerical difficulties may ensue, depending on the topology of the circuit (this is because matrix solving frequently involves differencing two very similar numbers – for example, the next larger number than one is 1.0000000000000002 – anything closer is not resolvable).  LTspice's proprietary alternate solver extends this precision by about another 3 orders of magnitude at a cost of a modest speed penalty.


A-Devices

A-devices are Linear Technology Corporation's proprietary special function/mixed mode circuit simulation elements.  According to LTspice’s Help file, the behavior of a number of these is undocumented because they frequently change with each new set of models available for LTspice (this simply is not true and is most likely offered as both as a credible reason for keeping them hidden and to discourage anyone from bothering to attempt to explore and/or use them).

The Help file lists A-device syntax as:

Annn n001 n002 n003 n004 n005 n006 n007 n008 <model> [instance parameters]

Note that all A-devices have up to 8 possible active device connections, up to 5 inputs (terminals 1 through 5) usually 2 outputs (terminals 6 and 7), and with terminal 8 always as the device common.  A-devices are always netlisted with the full eight connections.  The netlister connects any unused inputs and outputs to terminal 8.  The A-device compiler recognizes this condition as a flag that that terminal is not used and removes it from the simulation matrix.  Current is sourced or sunk from the complementary outputs, terminals 6 and 7, and returned through device common, terminal 8.

A-devices are implemented this way to allow a single device type to act as any combination of a 1 to 5 input, 1 to 2 output device, but with no simulation speed penalty for unused terminals.  Refer to the program Help file for more details about LTspice’s documented A-devices.

Here is a listing of all known LTspice A-devices.

Documented directly in Help:

  • Buf (aka Buf1 Inv)
  • AND
  • OR
  • XOR – when more than two inputs are present, uses the correct definition of true if one and only one input is true, rather than the more common incorrect definition of true if an odd number of inputs are true (which should be called an ODD/NODD gate rather than an XOR/XNOR gate).
  • Schmitt (aka SchmittBuf SchmittInv DifSchmitt DiffSchmittBuf DiffSchmittInv)
  • Dflop
  • Varistor
  • Modulator (aka Modulate Modulate2)

Not documented in Help but available via the schematic Component Selector:

  • SRflop – located in Digital
  • PhaseDet (aka PhiDet) – located in Digital
  • SampleHold (aka Sample) – located in Special Functions

Documented in sample schematics included with the program distribution:

  • PhaseDet (aka PhiDet) – located in examples/Educational/PLL2.asc
  • SampleHold (aka Sample) – located in examples/Educational/S&H.asc
  • OTA – used in UniversalOpamp plaintext subcircuits (in lib/sub), but users group posts (some long standing) containing information about additional aspects of this have been censored

Not documented anywhere by LTC:

  • Counter – documented in the users group (has been officially approved for public use)
  • XxxxxxXxxx – prior long standing users group posts about this digital toggle type device have now been censored
  • XxXxxXXX – DAC type device never discussed in the users group
  • XXXXX – DAC type device never discussed in the users group
  • XXXX – DAC type device never discussed in the users group
  • Xxx – amplifier type device never discussed in the users group

Not documented anywhere by LTC, but the first two of these devices were extensively documented in the users group.  All three devices were eliminated /protected in June 2006 (approximately at release 2.17u ) and all users group posts (some long standing) about these devices have been censored /deleted from the users group archive:

  • XXXxxxx – PWM current mode control comparator and latch
  • XxxXxx – used for making PWM IC oscillators
  • Xxxxx – used for making PWM IC oscillators

Obsolete devices that have been deleted from the LTspice executable:

  • JKflop
  • PGateDrive
  • invPGateDrive
  • invGateDrive

The three DACs, XxXxxXXX, XxxXXX, XXXX, are specialized A-devices that probably are of little general interest (although their functions and pinouts could likely be easily guessed by examining the data sheets of the few specialized LTC ICs making use of them).

The XXXX seems to be the only straightforward, generic DAC, but very spice-efficient DACs are quite easy to make using standard, approved devices.



SRflop

located in Digital



PhaseDet (aka PhiDet)

located in Digital located in examples/Educational/PLL2.asc



SampleHold (aka Sample)

The SampleHold symbol is located in the Special Functions symbol folder.

An example schematic, S&H.asc, is located in the Examples/Educational schematic folder.

The behavioral a-device Sample and Hold has two modes of operation.  The output may follow the input whenever the S/H input is true or the output may latch to the input when the CLK input goes true.  Note that one and only one of these two inputs must be connected.

Parameters unique to the Sample and Hold a-device are as follows:

  • Rout defaults to 1kΩ (instead of the standard a-device 1Ω).
  • Vhigh defaults to 10V and Vlow defaults to -10V (note: these are output voltage saturation levels).



OTA

  • Update Note: The behavior of this a-device was revised by LTC (between 2005 and 2011).  The second, multiplier input was discarded and asymmetrical limiting was added.

The OTA (Operational Transconductance Amplifier) is used in the various UniversalOpamp plaintext subcircuits (located in a standard LTspice program installation in lib/sub).

The default transfer function is a hyperbolic tangent (tanh), which closely approximates the transfer function of a bipolar transistor differential amplifier (this limit can be disabled by adding the flag parameter, linear).  A differential input pair is available on pins 1 and 2 ( − + ).  The transconductance output appears on pin 7.  As usual pin 8, if connected, becomes the device's floating "gnd" reference.  For reference, a dc "rail" voltage, which represents the maximum possible (negative) output (calculated from combining both voltage and current saturation limits), appears on pin 6.


Parameters: (default values are zero unless otherwise noted)

  • Ref is the input offset voltage
  • G is the raw input "gain" (transconductance), where Vdiff = Ref – V(1,2)   and Iraw = G * Vdiff
  • Iout (default = 10u) is the output saturation current, which may be superseded by one or both of
    • Isrc (or Isource) is the output sourcing saturation current (= Iout if not specified)
    • Isink (a negative number) is the output sinking saturation current (= −Iout if not specified)
      • Asym is a flag parameter that, if present, enables independent asymmetrical limits for Isrc/Isource and Isink
      • Linear is a flag parameter that, if present, disables output limiting
  • Ioffset is the output offset current
  • Rout (default = 1k?) is the internal output resistance
  • Cout is the capacitance in parallel with Rout
  • Vhigh (default = 10?) is the positive output "rail" voltage (set to 1e308 to disable limit)
  • Vlow (default = −10?) is the negative output "rail" voltage (set to −1e308 to disable limit)
  • Rclamp (default = 1?) is the clamping resistance to the voltage rails
  • EN is the voltage noise density
  • ENk is the voltage noise knee frequency
  • IN is the current noise density
  • INk is the current noise knee frequency
  • INcm is the common mode (?) current noise density
  • INcmk is the common mode (?) current noise knee frequency


Output Current Limit:

  • with no flag parameter: Io = tanh ( Iraw / Isat ) * Isat + Idc + Ioffset
    where Vdiff = Ref – V(1,2) , Iraw = G * Vdiff , Isat = ( IsinkIsrc ) / 2   and Idc = ( Isink + Isrc ) / 2 ; (Isink is a negative number )
  • with the Asym flag parameter: Io = if ( Vdiff , tanh ( Iraw / Isrc ) * Isrc , tanh ( Iraw / Isink ) * Isink ) + Ioffset
    note that the "if ( <polarity test>, <then action>, <else action> )" conditional statement completely separates the positive and negative limits
  • with the Linear flag parameter: Io = Iraw + Ioffset (output current does not saturate)


Output Voltage Limit:

  • clamps through a resistance of Rclamp to "rails" of Vhigh and −Vlow


Noise Voltage Density:

  • Vnoise = (EN + IN * Rin_equivalent) * G * Rout



Counter (divide by n):

This simple device divides the pulse stream on terminal 1 by round(n) where n is specified by the expression assigned to the cycles parameter (this expression may contain node voltages and branch currents).  Standard complementary digital outputs are available on terminals 6 and 7.  Key parameters (with non default example values) are: cycles=3 duty=0.2 (if omitted, defaults to 0.5).  The width of output pulses is, width = round(cycles*duty).  Most of the usual digital a-device parameters also apply, e.g.: Trise, Vhigh, Vlow, Ref, etc. with the exception of Td, which is ignored (the Counter accepts no delay).

Symbol and test circuit are available in the online Yahoo LTspice users group: Files > Tut > Digital A-Devices > A-counter_test1.asc and counter1.asy.

The implementation is fairly straightforward except for the Reset function.  Resetting the Counter A-device requires that it be clocked when the value of the "cycles" is at (or near) zero.


B-Sources

While many b-source features were not documented until relatively recently (~2007), most are now at least touched upon in Help and the few that are not are covered in the B sources (complete reference) in this wiki.

  • BR=f(x)  arbitrary resistor where f is an arbitrary function of x (with the special meaning of the voltage across R in this context) and/or any valid node voltage, branch current, etc.
  • [[units] Freq=<valuelist> [delay=<value>]]  (Pspice compatible format)
    The transfer function of the Freq circuit element is specified by an ordered list of points of freq(Hz), mag(dB) and phase(deg) as follows: <(f1,m1,p1)[(f2,m2,p2)...]> where f1<f2<f3, etc.  The following units specifiers may optionally precede the Freq keyword: “rad”=radians, “mag”=non dB, (“dB” and “deg” return the defaults), “r_i”=real and imaginary in place of magnitude and phase.  If a delay value is called out, the phases of the table values are modified to reflect the delay (delay is automatically adjusted to maintain causality in any case).
  • NoJacob  The optional NoJacob flag parameter unburdens a device from carrying the mathematical overhead of a Jacobian.  For linear or certain well behaved b-source expressions, this small reduction in computational burden can reduce run times slightly.  Use with extreme caution, as this greatly increases the risk of creating convergence problems or other errors if misapplied.
  • ~  Boolean operator: convert succeeding expression to Boolean then invert
  • ==  Boolean operator: true if preceding expression is equal to succeeding expression, otherwise false
  • boltz  Boltzmann constant = 1.38062 e-23
  • planck  Planck's constant = 6.62620 e-34
  • echarge  Charge of an electron = 1.6021765 e-19
  • kelvin  Absolute Zero in degrees C = -273.150
  • Gmin  Minimum conductance = 1e-12 (or as set in the Control Panel or via an .option statement)
    • Gmin is added to every PN junction to aid convergence and is the default off-conductance for current or voltage controlled switches and LTspice's idealized diode model.
  • square(x)  Function = x**2
  • tbl  Alternate function name, aka table (look-up table)
  • stp(x)  Alternate function name, aka u(x) (unit step)
  • fra(x)  Function, very similar to white(x), but = 0 if not SMPS in steady state condition
  • UpLim(x, y, z)  Function, similar to Min(x, y), but "z" defines a zone with quadratic soft limiting (note: "x" and "y" are interchangeable, but "z" must be the end argument)
  • DnLim(x, y, z)  Function, similar to Max(x, y), but "z" defines a zone with quadratic soft limiting (note: "x" and "y" are interchangeable, but "z" must be the end argument)
  • UpLim(DnLim(w, x, z_dn), y, z_up)  Composite function, similar to Limit(w, x, y), but with up and down soft limit zones
    • As with the hard limit functions, any or all arguments may be constants or functions of time, node voltages, branch currents, etc.: UpLim(13, V(1,2)*I(Vs), Min(time**2, 5)).
    • When their soft limits are greater than zero, these functions have continuous derivatives for superior dc convergence over Min(), Max() and Limit().
    • Outside their soft limit zones these functions are perfectly linear which may make them superior to tanh() as a smooth limit function in amplifier macro-modeling applications.


Note that LTspice can execute behavioral sources in either 2G6, PSpice, or Berkeley SPICE syntax in addition to its own enlarged set of behavioral language.

Standard Sources

Add documentation for data file input and triggered sources and the Pspice compatible behavioral forms for E and G sources (at some point, perhaps ~2007, these were added to Help).

The Piecewise Linear Voltage Source needs a writeup for these forms:

PWL repeat forever 0,0 1,4 2,-1 3,9 endrepeat ; PWL endless repeat of table values
PWL (0 0 +0.1 1 +0.1 0 +0.1 1 +0.1 0 +0.1 0.5) ; PWL with incremental time (+) format
PWL repeat for 7 file=pwl_data.txt endrepeat repeat for 6 file=pwl_data2.txt endrepeat
PWL repeat forever file=pwl_data.txt endrepeat
PWL value_scale_factor=0.5 time_scale_factor=0.7 FILE=pwl_data.txt 
* Scale the time and voltage values of a file
PWL file=pwl_data.txt trigger V(trig)>0

Note that the Trigger is actually an enable output while true function.


Standard Devices

Diodes: Sidewall Parameters

LTspice (04/05/10) now supports the following diode sidewall parameters:

  • perim: Sidewall perimeter (periphery) ; default value = 0m.
  • Isw: Sidewall saturation current ; default value = 0A.
  • Ns: Sidewall junction emission coefficient ; default value = N (I when Level=11)?
  • Rsw: Sidewall series resistance ; default value = 0 ohm.
  • Cjsw: Sidewall zero-bias capacitance ; default value = 0.9F * perim?
  • Vjsw: Sidewall junction potential ; default value = Vj (1 when Level=11)?
  • Mjsw: Sidewall grating coefficient ; default value = 0.33.
  • Fcs: Sidewall forward-bias depletion capacitance coefficient ; default value = 0.5 (Fc when Level = 11)?



BJTs: Additional Gummel-Poon Parameters

Bipolar CB avalanche breakdown is modeled in the LTspice Gummel-Poon device:

  • BVcbo: C-B breakdown voltage.
  • nBVcbo: breakdown emission coefficient ; default value = 1?
  • TBVcbo1: linear temperature coefficient of breakdown voltage.
  • TBVcbo2: quadratic temperature coefficient of breakdown voltage.

Bipolar BE breakdown is also in the LTspice Gummel-Poon device:

  • BVbe: B-E breakdown voltage.
  • IBVbe: breakdown current at breakdown voltage.
  • nBVbe: breakdown emission coefficient.



VDMOS: Breakdown and Sub-threshold Enhancements

LTspice now contains a number of otherwise undocumented parameters to enhance its proprietary VDMOS model.  These allow for body diode breakdown and subthreshold conduction with independent fits to the saturation and linear regions of the output characteristics.

  • BV: breakdown voltage.
  • IBV: breakdown current at breakdown voltage.
  • nBV: breakdown emission coefficient.
  • Mtriode: A conductance multiplier for the triode region.  It allows independent matching of the saturation and linear regions of the MOSFET.
  • subthres: The current (per volt Vds) at which the square-law drain current verses Vgs switches over to exponential.


VDMOS Capacitance (Cgd Curve Fit Equation)

LTspice Help outlines how LTspice generates the VDMOS nonlinear gate-drain capacitance, presenting the general form of the equations used, but it does not reveal the details of the parameters used by the fit equations. Help states that the capacitance expression fit uses two expressions, one for negative gate-drain voltages and another for positive. These expressions meet at zero voltage and it may be assumed that at this point, they must be identical in value and slope. This reduces the system to two equations in two unknowns, allowing a solution for the remaining fit parameters to be obtained. For the following equations, "s" is the slope at the zero point, "y" is the offset and "x" is the gate-drain voltage (not the drain-source voltage).

  • Positive gate-drain voltage region: Cgd = s * tanh(a*x) + y (inversion region - switch is on)
  • Negative gate-drain voltage region: Cgd = s * atan(a*x) + y (Vds large - switch is off or turning off)

Where s = (Cgdmax - Cgdmin)/(1 + Pi/2) and y = Cgdmax - s and "a", Cgdmax and Cgdmin are existing VDMOS model parameters.

Note that in Help the unspecified parameters are given as A, B, C, and D. These parameters are equivalent to s and y as follows: A = C = s and B = D = y.



Resistors

Behavioral Resistors

Create a behavioral resistor by right-mouse-button clicking on its Value field and edit its value to read: R=<expression>.  This feature is undocumented, but is considered permissible to use.  The expression syntax is the same as for a general behavioral source (see B-sources in Help).

The resistance must not go to zero and negative values can lead to convergence problems, so it is advisable to restrict its values to within a meaningful range as per the following Value example:

R = limit(1,100k,V(1,2)*I(V1)) ; R stays between 1 ohm and 100k

To plot an I-V curve, start by using the differential cursor to plot the voltage across the resistor.  First click and hold down the left-mouse-button (red probe icon) on one side of the resistor and then drag and drop the black probe icon on the other side.  Finish by dragging the mouse pointer over the x-axis (a ruler icon will appear) and the click the left mouse button to bring up the Horizontal Axis menu.  Change the Quantity Plotted from "time" to "I(R1)" (assuming R1 is your behavioral resistor).


Dual Value Resistors (for ac analysis)

LTspice is like Hspice in that it allows resistors to have different dc and ac values.  If ac=<value> is specified as a resistor parameter (either immediately after the normal dc value or in the Value2 field), the operating point is calculated using the dc value of resistance, but the ac resistance value is used in the ac analysis.  This may be useful when analyzing operational amplifiers, since the operating point computation can be performed on the unity gain configuration using a low value for the feedback resistance and the ac analysis may then be performed on a nearly open loop configuration by specifying a very large value for the ac resistance.


Resistor (and Capacitor) Model Statements

It's not in the .model section of the Help file, but LTspice seems to recognize standard model statements for resistors (RES) and capacitors (CAP), but not inductors (IND).

As in many other SPICE simulators, "RES" and "CAP" are allowed as model keywords.  For example, with the following line of spicetext

.model X7R cap (T_measured=20 Tc1=0 Tc2=-19u)

on a schematic, if a capacitor then has "X7R" entered into its "SpiceModel" field (via ctrl-right mouse click) its base value will be multiplied by the following temperature factor, TF

TF = 1 + Tc1*(T-Tmeasured) + Tc2*(T-Tmeasured)**2
where T = the global temperature TEMP or the local instance if specified.

I haven't checked if higher order factors are accepted or if voltage or current factors can be used (they work for some other SPICEs).

The Help file specifies the optional instance of [temp=<value>] syntax for resistors, capacitors and inductors, but only for capacitors does it define this as "instance temperature (for tempcos in a corresponding .model statement)," although nothing further about the model syntax is mentioned.

The help file does not document the "noiseless" control parameter which applies to the resistance in many LTspice circuit elements with resistive elements (resistors, switches, RC lines, others).  As its name suggests, this parameter blocks its applicable element's contribution to noise calculations.



Lossy Transmission Lines

There are two undocumented lossy transmission line models implemented in LTspice.  One is CPL model (P device), and the other is TXL model (Y device).

The undocumented CPL is a KSPICE-like element, which in theory should be similar to the RLGC model, but without frequency dependent loss (neither skin effect and nor frequency dependent dielectric loss).  It also has at least one bug causing an incorrect output voltage offset (a workaround is to only use signals with no dc offset).

Below are example netlists from Kspice, which have been translated as required (very little) into LTspice syntax.

****** test circuit for CPL transmission line simulation *******
*
M1   0 268 299 0 MN0P9 w=18u l=1u
M2 299 267 748 0 MN0P9 w=18u l=1u
M3   0 168 648 0 MN0P9 w=18u l=0u9
M4   1 268 748 1 MP1P0 w=36u l=1u
M5   1 267 748 1 MP1P0 w=36u l=1u
M6   1 168 648 1 MP1P0 w=36u l=1u
*
CN648 648 0 25f4
CN651 651 0 7f4
CN748 748 0 25f4
CN751 751 0 9f4
CN299 299 0 5f4
*
P1 648 748 0 651 751 0 Pline
*
vdd  1 0 DC 5
Vk 267 0 DC 5
*
*Vs 168 0 PWL (4 15n9 0 16n1 5 31n9 5 32n1 0)
*Vs 268 0 PWL (4 15n9 0 16n1 5 31n9 5 32n1 0)
*
Vs1 168 0 Pulse (0 5 15n9 0n2 0n2 15n8 60n)
Vs2 268 0 Pulse (0 5 15n9 0n2 0n2 15n8 60n)
*
.tran 0n2 47n9 0 1n
.model Pline CPL
+ R=0.2 0 0.2
+ L=9n13 3n3 9n13
+ G=0 0 0
+ C=365f -90f 365f
+ Length=24
********************** MODEL SPECIFICATION **********************
.model MN0P9 NMOS Vto=0.8 Kp=48u Gamma=0.30 Phi=0.55 Lambda=0
+ Cgso=0 Cgdo=0 Cj=0 Cjsw=0 Tox=18u Ld=0
.model MP1P0 PMOS Vto=-0.8 Kp=21u Gamma=0.45 Phi=0.61 Lambda=0
+ Cgso=0 Cgdo=0 Cj=0 Cjsw=0 Tox=18u Ld=0
.end

******* test circuit for TXL transmission line simulation *******
M5 0 168 2 0 MN0P9 w=18u l=0u9
M6 1 168 2 1 MP1P0 w=36u l=1u
Cn2 2 0 25f4
Cn3 3 0 7f4
Y1 2 0 3 0 Ymod
Vdd 1 0 dc 5.0
Vs 168 0 Pulse (0 5 15n9 0n2 0n2 15n8 32n)
*Vs 168 0 PWL(15n9 0 16n1 5 31n9 5 32n1 0)
.tran 0n2 47n 0 0n1
.model MN0P9 NMOS Vto=0.8 Kp=48u Gamma=0.3 Phi=0.55 Lambda=0
+ Cgso=0 Cgdo=0 Cj=0 Cjsw=0 Tox=18u Ld=0
.model MP1P0 PMOS Vto=-0.8 Kp=21u Gamma=0.45 Phi=0.61 Lambda=0
+ Cgso=0 Cgdo=0 Cj=0 Cjsw=0 Tox=18u Ld=0
.model Ymod Txl R=12.45 L=9u G=0 C=0p47 Length=16
.end



Voltage Controlled Switches

LTspice has a cleaner syntax for voltage controlled switches, but has no problem with any PSpice voltage controlled switch syntax.


Miscellaneous Hints and Tricks

... should be added here or given its own section if warranted.

Here's a hint to anyone wishing to keep up-to-date with the latest additions to LTspice's great features - always read the changelog.txt file (located in the LTspiceIV program folder) after every web update /sync release.

There are a whole lot of .option parameters and other control parameters (mostly legacy from SPICE 2 and Pspice) that should be documented (a few probably actually could be useful).

Anyone else recall something?

.OPTIONS See message #20174

A-Devices See message #19378



AKO Aliases (A Kind Of)

Suppose I wished to modify a single parameter of an existing model but don't want to copy the full model out as a duplicate and adjust it. I want to pick up all of the specified and default parameter values for the given model name (and if it specifies yet another, to pick up those, as well) and simply modify one parameter or two in a new model.

A reason I may wish to do this is that I may, at some later time, decide to modify the underlying model and I'd like all of the dependent models to pick up the underlying changes, automatically. I just don't know if there is syntax for it. Do you know?

Yes. Try something like this:

.model 2N2222mod ako: 2N2222 bf=5 ; same except lower beta



> It appears that parameters must ultimately resolve to numbers instead of text.

You are correct in your supposition - parameters must be numbers.

> Is there a way to pass text to a subcircuit to do what I want?

Yes. Models can take numeric alias using the AKO ("A Kind Of") function. These numeric aliases will work with parameter passing:

.model 1 ako:2N3904 ;the existing 2N3904 model now also known as "1"
.model 2 ako:2N2222 ;the existing 2N2222 model now also known as "2"

This topic has been discussed many times in this forum before, but it may be difficult to search for because the name of the AKO function doesn't really correspond to "Also Known As" (it stands for "A Kind Of").

You can find many examples using AKO in the Group archive here:

Files -> Tut -> Stepping to the max


Schematic Editor

Schematic Editor Key Combinations:

  • Shift-Ctrl-Alt-R: Permanently renumbers all reference designators within the schematic.
  • Shift-Ctrl-Alt-H: Temporarily highlights all hidden text within the schematic.
  • Hold down Ctrl when placing wires to route at any angle.
  • Hold down Ctrl when drawing lines to draw off grid.
  • Hold down Ctrl or Shift for more movement with arrow keys.
  • Hold down Ctrl and Shift for most movement with arrow keys.
  • Text preceeded with an underscore ("_") character will be displayed as overbarred (for active LOW digital signals).


Schematic Editor Operating Point Data Labels (visible numeric dc bias values)

LTspice has the ability to display dc operating point voltages, currents and expressions (e.g., power, energy, efficiency, etc.) directly within the schematic. Normally, these .op Point Data Labels are placed upon wires (nodes) much like Net Labels.

To be able to invoke an .op Point Data Label, right mouse button click on an empty area of the schematic and select "View" from the drop down menu list.

  • Unchecking "Show .op Data Flags" hides (but does not delete) all operating point numerical information on the schematic.
  • Unchecking "Mark Unconn. Pins" (of the "View" drop down menu of the top/main menu bar) hides all operating point anchor boxes on the schematic.

Operating point data labels default to the direct display of the voltage of the node to which they are attached (signified by the dollar sign character "$"), but this may be edited to be any valid expression, including currents, powers or even the voltage of a specific node. Once placed, these data labels may be freely move or copied and then edit to be completely unrelated to the original node.

  • .op Point Data Label default value: $ -- aliases to V(x), where "x" is the specific node to which the label is physically attached.
  • .op Point Data Label edited value: V(n001) -- calls out a specific node (n001) regardless of label attachment point.

With fractional values, all available non-zero digits will be displayed, often resulting in unwanted numerical clutter. The number of visible digits may be aesthetically limited by appropriately editing the expression to be displayed:

round($*1k)/1k ; display no more than 3 digits (typically automatically expressed in engineering format).
round(I(R1)*1k)/1k ; same display format as above, but expression is of the current through R1.
round(V(1,2)*1k)/1k ; same format, but expression is of the voltage difference between nodes 1 & 2.


Schematic Editor Bussing of Connections and Components (BUS shorthand notation):

  • All bussing notation is resolved (flattened) by the schematic editor prior to netlisting (the netlister does not understand BUS notation).
  • A net (wire) becomes a BUS whenever any one of the following three conditions are met:
  1. it is labeled with a netname with an array suffix, e.g., Data[0:8] (an array suffix consists of two numbers separated by a colon and enclosed in brackets),
  2. it is connected to a bus pin that has an array type name, or
  3. it is connected to the wide end of a BUS tap (drop down menu: Edit => PlaceBUStap).
    Tap nets must be labeled with an array individual element suffix (a single number without colon enclosed in brackets).
  • Nets (wires) interpreted as busses automatically are drawn as extra thick lines.
  • A bus may be automatically connected (netlisted) to a corresponding array of devices by appending the instance name (reference designator) of a bus-connected single device with a bracketed array specifier, e.g. Q[1:4] would represent four identical transistors. Note that recursive connections are possible around a single device or device group through the use of appropriate net labeling.
    For example, a single digital DFLOP device may be annotated to represent a 64 shift-register string by:
  1. adding a 64 element array suffix to its instance name, e.g. A1 would become A1[0:63],
  2. placing on its D input a corresponding array net label, e.g., Data[0:63] (the particular name is unimportant), and
  3. placing on its Q output an appropriately displaced array net label, e.g., Data[1:64].
Example Notes:
As usual for any flip-flop, a delay parameter must be specified in the Value field, e.g., td=10ns.
The D input to the first gate may be individually accessed by its appropriate array index, e.g., Data[0]


Random Leftovers:

There's a new option called tseed that lets you seed the integrator with a specific timestep guess.  Just add the SPICE directive ".options tseed=100n" to your schematic (see section on .options).

From changelog.txt (often useful to find otherwise undocumented features):

  • 02/21/07 Added a check box on the Tools=>Control Panel=>Hacks! pane to allow the MC generator to be reseeded by the real time clock.



How to Probe Subcircuit Waveforms (naming conventions)

To be able to display subcircuit waveforms, you must first ensure that the Save Subcircuit Node Voltages and the Save Subcircuit Device Currents options are enabled in the Save Defaults tab of the Control Panel.  Then, if your simulation was created as a hierarchical design using LTspice's Schematic Capture window, you may simply use the probe tool to select an active subcircuit schematic's nodes as required.  But if the SPICE netlist was imported from an external source then the probe statement format is as follows:

  • a top level node:
.probe v(node)
  • a subcircuit node:
.probe v(subckt_name:node)
.probe v(subckt_name:subsubckt_name:node)
  • a subcircuit MOSFET drain current:
.probe id(subckt_name:mp1)