Version 4
SHEET 1 2740 696
WIRE 784 -768 784 -784
WIRE 528 -752 528 -784
WIRE 1328 -640 1328 -656
WIRE 784 -624 784 -688
WIRE 1312 -624 1296 -624
WIRE 1376 -624 1360 -624
WIRE 528 -608 528 -672
WIRE 1376 -592 1296 -592
WIRE 1376 -560 1296 -560
WIRE 1376 -528 1296 -528
WIRE 976 -496 960 -496
WIRE 1008 -496 976 -496
WIRE 1072 -496 1056 -496
WIRE 1376 -496 1296 -496
WIRE 976 -464 960 -464
WIRE 1072 -464 976 -464
WIRE 1376 -464 1296 -464
WIRE 1616 -448 1568 -448
WIRE 976 -432 960 -432
WIRE 1072 -432 976 -432
WIRE 1376 -432 1296 -432
WIRE 976 -400 960 -400
WIRE 1072 -400 976 -400
WIRE 1376 -400 1296 -400
WIRE 512 -384 448 -384
WIRE 768 -384 512 -384
WIRE 976 -368 960 -368
WIRE 1072 -368 976 -368
WIRE 1376 -368 1296 -368
WIRE 976 -336 960 -336
WIRE 1072 -336 976 -336
WIRE 1376 -336 1296 -336
WIRE 448 -320 448 -384
WIRE 976 -304 960 -304
WIRE 1072 -304 976 -304
WIRE 1376 -304 1296 -304
WIRE 976 -272 960 -272
WIRE 1072 -272 976 -272
WIRE 1376 -272 1296 -272
WIRE 816 -208 816 -224
WIRE 848 -208 848 -224
WIRE 448 -176 448 -240
FLAG 448 -176 0
FLAG 512 -384 Vin
FLAG 784 -624 0
FLAG 784 -784 clock
FLAG 528 -608 0
FLAG 528 -784 VDD
FLAG 1616 -448 Vout
FLAG 1472 -672 VDD
FLAG 1488 -224 0
FLAG 976 -464 B6
FLAG 976 -432 B5
FLAG 976 -400 B4
FLAG 976 -368 B3
FLAG 976 -336 B2
FLAG 976 -304 B1
FLAG 976 -272 B0
FLAG 1184 -688 VDD
FLAG 864 -544 VDD
FLAG 880 -224 0
FLAG 816 -208 Clock
FLAG 848 -208 VDD
FLAG 1184 -224 Clock
FLAG 1456 -224 VDD
FLAG 1024 -512 VDD
FLAG 1328 -656 VDD
FLAG 976 -496 B7
SYMBOL voltage 448 -336 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 11 104 Left 0
SYMATTR Value SINE(500m 400m 4MEG 50n)
SYMATTR InstName Vin
SYMBOL voltage 784 -784 R0
WINDOW 0 36 42 Left 0
WINDOW 3 35 69 Left 0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName Vclock
SYMATTR Value PULSE(0 1 0 0 0 4.9n 10n)
SYMBOL voltage 528 -768 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VDD
SYMATTR Value 1.0
SYMBOL Ideal_8_bit_ADC 784 -240 R0
SYMATTR InstName U1
SYMBOL Ideal_12_bit_DAC 1392 -240 R0
SYMATTR InstName X2
SYMBOL Integrator_delaying 1104 -256 R0
SYMATTR InstName X1
SYMBOL inverter 1008 -496 R0
SYMATTR InstName X3
SYMBOL inverter 1312 -624 R0
SYMATTR InstName X4
TEXT 448 -504 Left 0 !.tran 0 500n 0 .1n
TEXT 448 -472 Left 0 !.options plotwinsize=0
TEXT 856 -896 Left 0 ;Response seen in Fig. 1.27 scaled by 1/8.\nAt fs/2 gain is then 0.5/8 or 0.0625. The\nscaling was implemented to avoid overflow.
TEXT 384 -120 Left 0 ;Note that if you go too low in frequency you get overflow.\nTo avoid aliasing keep f < fs/2 or 50 MHz.
TEXT 1576 -416 Left 0 ;If the input is 400 mV peak at 4 MHz then using Eq. (1.62) we\nget a magnitude response |H(f)|=3.989. Dividing this by 8,\nbecause we extended the sign-bit in the integrator, we get\n3.989/8=0.499. Multiplying by our peak input of 400 mV gives\na peak output of 200 mV. Note that the integrator may start-off \nwith an initial condition so the DC offset may not be exactly 500 mV.
TEXT 952 -664 Left 0 ;Change to\ntwo's \ncomplement
TEXT 1280 -792 Left 0 ;Change back\nto binary \noffset