Version 4
SHEET 1 1324 932
WIRE 240 -784 160 -784
WIRE 160 -720 160 -784
WIRE -48 -640 -64 -640
WIRE 16 -640 -48 -640
WIRE 240 -624 208 -624
WIRE -288 -608 -320 -608
WIRE 0 -608 -16 -608
WIRE 16 -608 0 -608
WIRE 160 -416 160 -528
WIRE -32 -336 -64 -336
WIRE 16 -336 -32 -336
WIRE 240 -320 208 -320
WIRE -288 -304 -320 -304
WIRE 16 -304 -16 -304
FLAG -176 -384 VDD
IOPIN -176 -384 In
FLAG -176 -224 clock
IOPIN -176 -224 In
FLAG 64 -416 VDD
FLAG -320 -304 B0
IOPIN -320 -304 In
FLAG -32 -336 B0D
FLAG 240 -320 S0
IOPIN 240 -320 Out
FLAG -16 -304 B0
FLAG 160 -224 0
FLAG -176 -688 VDD
FLAG -176 -528 clock
FLAG -320 -608 B1
IOPIN -320 -608 In
FLAG 64 -720 VDD
FLAG 240 -624 S1
IOPIN 240 -624 Out
FLAG -48 -640 B1D
FLAG 0 -608 B1
FLAG 240 -784 S2
IOPIN 240 -784 Out
SYMBOL DFF -256 -256 R0
SYMATTR InstName X3
SYMBOL Adderbit 32 -240 R0
SYMATTR InstName X1
SYMBOL DFF -256 -560 R0
SYMATTR InstName X2
SYMBOL Adderbit 32 -544 R0
SYMATTR InstName X4
TEXT -80 -168 Left 0 ;Implements the function 1+z^-1\nSee Figure 1.16
TEXT -280 -800 Left 0 ;Doesn't use two's complement