Version 4
SHEET 1 1556 680
WIRE 80 -400 80 -432
WIRE 80 -288 80 -320
WIRE 80 -144 80 -176
WIRE 80 -32 80 -64
WIRE 352 -160 352 -192
WIRE 352 -48 352 -80
WIRE 656 -112 656 -144
WIRE 704 -144 656 -144
WIRE 752 -304 752 -320
WIRE 752 -288 752 -304
WIRE 752 -160 752 -192
WIRE 752 -48 752 -64
WIRE 752 64 752 32
WIRE 816 -64 752 -64
WIRE 848 -64 816 -64
WIRE 928 -304 752 -304
WIRE 928 -224 928 -240
FLAG 80 -288 0
FLAG 80 -432 VDD
FLAG 752 -368 VDD
FLAG 752 -416 VDD
FLAG 80 -32 0
FLAG 80 -176 Phi1
FLAG 352 -48 0
FLAG 352 -192 phi2
FLAG 752 -240 VDD
FLAG 752 -112 VDD
FLAG 656 -112 0
FLAG 704 -400 phi1
FLAG 704 -272 phi2
FLAG 752 64 0
FLAG 816 -64 vbit
FLAG 928 -224 0
SYMBOL voltage 80 -416 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 40 53 Left 0
SYMATTR Value 1
SYMATTR InstName VDD
SYMBOL pmos4 704 -320 M180
WINDOW 0 56 32 Invisible 0
WINDOW 3 56 72 Invisible 0
SYMATTR InstName M3
SYMATTR Value P_50n
SYMATTR Value2 l=50n w=1u
SYMBOL voltage 80 -160 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 -40 182 Left 0
SYMATTR Value PULSE(1 0 1n 10p 10p 4n 10n)
SYMATTR InstName Vphi1
SYMBOL voltage 352 -176 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 -83 163 Left 0
SYMATTR Value PULSE 1 0 6n 10p 10p 4n 10n
SYMATTR InstName Vphi2
SYMBOL pmos4 704 -192 M180
WINDOW 0 56 32 Invisible 0
WINDOW 3 56 72 Invisible 0
SYMATTR InstName M1
SYMATTR Value P_50n
SYMATTR Value2 l=50n w=1u
SYMBOL pmos4 704 -64 M180
WINDOW 0 56 32 Invisible 0
WINDOW 3 56 72 Invisible 0
SYMATTR InstName M2
SYMATTR Value P_50n
SYMATTR Value2 l=50n w=1u
SYMBOL voltage 752 -64 R0
WINDOW 0 47 46 Left 0
WINDOW 3 52 76 Left 0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName Vbit
SYMATTR Value Pulse 0.3 1 0 1000n
SYMBOL cap 912 -304 R0
SYMATTR InstName C1
SYMATTR Value 100f
TEXT 264 88 Left 0 !.lib cmosedu_models.txt
TEXT 264 64 Left 0 !.tran 0 1u 10n uic
TEXT 192 -424 Left 0 ;Plot phi1 phi2+1.25 then I(Vbit)