Version 4
SHEET 1 2920 932
WIRE 672 -592 640 -592
WIRE 640 -560 640 -592
WIRE 640 -448 640 -480
WIRE 864 -400 864 -432
WIRE 1552 -384 1552 -400
WIRE 1552 -352 1552 -384
WIRE 1888 -320 1872 -320
WIRE 640 -288 640 -320
WIRE 1888 -288 1872 -288
WIRE 2496 -288 2496 -336
WIRE 2528 -288 2528 -336
WIRE 2560 -288 2560 -336
WIRE 2592 -288 2592 -336
WIRE 2624 -288 2624 -336
WIRE 2656 -288 2656 -336
WIRE 2688 -288 2688 -336
WIRE 2720 -288 2720 -336
WIRE 2288 -272 2256 -272
WIRE 864 -256 864 -320
WIRE 1360 -256 1312 -256
WIRE 1392 -256 1360 -256
WIRE 1888 -256 1872 -256
WIRE 640 -176 640 -208
WIRE 2016 -144 2016 -176
WIRE 2048 -144 2048 -176
WIRE 2080 -144 2080 -176
WIRE 2112 -144 2112 -176
WIRE 2144 -144 2144 -176
WIRE 1120 -128 1120 -160
WIRE 1152 -128 1152 -160
WIRE 1184 -128 1184 -160
WIRE 1216 -128 1216 -160
WIRE 1488 -128 1488 -160
WIRE 1520 -128 1520 -160
WIRE 1552 -128 1552 -160
WIRE 1584 -128 1584 -160
FLAG 640 -448 0
FLAG 672 -592 Vin
FLAG 992 -272 VDD
FLAG 1360 -256 VDD
FLAG 992 -240 0
FLAG 1120 -128 D4
FLAG 1152 -128 D5
FLAG 1184 -128 D6
FLAG 1216 -128 D7
FLAG 1584 -128 D4
FLAG 1552 -128 D5
FLAG 1520 -128 D6
FLAG 1488 -128 D7
FLAG 1712 -240 VDD
FLAG 1712 -272 0
FLAG 1872 -288 VDD
FLAG 1872 -256 0
FLAG 2048 -144 D0
FLAG 2080 -144 D1
FLAG 2112 -144 D2
FLAG 2144 -144 D3
FLAG 2448 -208 VDD
FLAG 2448 -176 0
FLAG 2288 -272 VDD
FLAG 2768 -192 VDD
FLAG 2608 -96 Vout
FLAG 864 -256 0
FLAG 864 -432 clk
FLAG 1872 -320 clk
FLAG 640 -176 0
FLAG 640 -320 VDD
FLAG 2784 -448 VDD
FLAG 2432 -448 clk
FLAG 2496 -560 D0
FLAG 2528 -560 D1
FLAG 2560 -560 D2
FLAG 2592 -560 D3
FLAG 2624 -560 D4
FLAG 2656 -560 D5
FLAG 2688 -560 D6
FLAG 2720 -560 D7
FLAG 2016 -144 Vfold
FLAG 1552 -384 VoutM
FLAG 1152 -352 Vin
FLAG 2080 -368 Vin
FLAG 992 -304 clk
SYMBOL voltage 640 -576 R0
WINDOW 0 36 42 Left 0
WINDOW 3 -73 165 Left 0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName Vin1
SYMATTR Value PULSE(0 5 0 5u)
SYMBOL Ideal_4_bit_DAC 1696 -176 R270
SYMATTR InstName X3
SYMBOL Ideal_8_bit_DAC 2464 -272 R90
SYMATTR InstName X5
SYMBOL voltage 864 -416 R0
WINDOW 0 36 42 Left 0
WINDOW 3 -85 257 VLeft 0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName Vb1
SYMATTR Value PULSE(0 5 5n 100p 100p 4.9n 10n)
SYMBOL voltage 640 -304 R0
WINDOW 0 36 42 Left 0
WINDOW 3 44 15 Left 0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VDD
SYMATTR Value 5
SYMBOL 8_bit_register 2464 -528 R90
SYMATTR InstName X2
SYMBOL 4_bit_coase_ADC 1008 -336 R90
SYMATTR InstName X4
SYMBOL 4_bit_Folding_ADC 1936 -352 R90
SYMATTR InstName X1
TEXT 752 -88 Left 0 !.tran 0 5u 0 .1n uic
TEXT 752 -120 Left 0 !.options plotwinsize=0
TEXT 1200 -24 Left 0 ;Coarse ADC for MSBs
TEXT 1200 -672 Left 0 ;This simulation basically increases the resolution to 8-bit which combines 4-bit for coarse \nADC and the other 4-bit for fine ADC\nMeanwhile, to get rail-to-rail folding signal, a factor of 16 needs to be applied to\namplify the signal Vfold
TEXT 1880 -48 Left 0 ;Folder and Fine ADC for LSBs
TEXT 2392 40 Left 0 ;Ideal DAC for Signal Reconstruction