Version 4
SHEET 1 1636 680
WIRE 448 -592 448 -624
WIRE 448 -480 448 -512
WIRE 448 -352 448 -384
WIRE 448 -240 448 -272
WIRE 560 -592 560 -624
WIRE 560 -480 560 -512
WIRE 768 -656 768 -672
WIRE 768 -544 768 -560
WIRE 768 -528 768 -544
WIRE 768 -400 768 -448
WIRE 832 -640 816 -640
WIRE 832 -544 768 -544
WIRE 832 -544 832 -640
WIRE 944 -672 768 -672
WIRE 992 -288 992 -368
WIRE 992 -144 992 -160
WIRE 1008 -368 992 -368
WIRE 1056 -512 1056 -528
WIRE 1056 -384 1056 -416
WIRE 1056 -288 992 -288
WIRE 1056 -256 1056 -288
WIRE 1072 -640 832 -640
WIRE 1088 -160 992 -160
WIRE 1088 -64 1088 -96
WIRE 1120 -672 944 -672
WIRE 1120 -656 1120 -672
WIRE 1120 -528 1056 -528
WIRE 1120 -528 1120 -560
WIRE 1184 -528 1120 -528
WIRE 1184 -512 1184 -528
WIRE 1184 -160 1088 -160
WIRE 1184 -160 1184 -416
WIRE 1232 -160 1184 -160
WIRE 1264 -160 1232 -160
WIRE 1568 -144 1520 -144
WIRE 1568 -64 1520 -64
FLAG 448 -480 0
FLAG 448 -624 VDD
FLAG 1056 -336 VDD
FLAG 1184 -464 VDD
FLAG 1232 -160 vbit
FLAG 560 -480 0
FLAG 560 -624 VREF
FLAG 1392 -208 VDD
FLAG 448 -240 0
FLAG 448 -384 clock
FLAG 1264 -64 VREF
FLAG 1088 -64 0
FLAG 1344 -240 clock
FLAG 1392 -16 0
FLAG 1568 -64 Out
FLAG 992 -64 0
FLAG 1568 -144 Outi
FLAG 1056 -464 VDD
FLAG 1056 -256 0
FLAG 1232 -496 Outi
FLAG 1008 -496 Out
FLAG 1120 -608 VDD
FLAG 768 -608 VDD
FLAG 768 -400 0
FLAG 944 -672 VDD
SYMBOL voltage 448 -608 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 40 53 Left 0
SYMATTR Value 1
SYMATTR InstName VDD
SYMBOL pmos4 1008 -288 M180
WINDOW 0 56 32 Invisible 0
WINDOW 3 56 72 Invisible 0
SYMATTR InstName M3
SYMATTR Value P_50n
SYMATTR Value2 l=1u w=1u
SYMBOL pmos4 1232 -416 R180
WINDOW 0 56 32 Invisible 0
WINDOW 3 56 72 Invisible 0
SYMATTR InstName M1
SYMATTR Value P_50n
SYMATTR Value2 l=50n w=1u
SYMBOL voltage 560 -608 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 40 53 Left 0
SYMATTR Value 500m
SYMATTR InstName VREF
SYMBOL voltage 448 -368 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 -83 163 Left 0
SYMATTR Value PULSE 1 0 6n 10p 10p 4n 10n
SYMATTR InstName Vclock
SYMBOL cap 1072 -160 R0
WINDOW 0 43 22 Left 0
WINDOW 3 45 50 Left 0
SYMATTR InstName Cbit
SYMATTR Value 2p
SYMBOL Fig_17_16_no_Vos 1312 -112 R0
SYMATTR InstName U1
SYMBOL current 992 -144 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName I1
SYMATTR Value 100n
SYMBOL pmos4 1008 -416 M180
WINDOW 0 56 32 Invisible 0
WINDOW 3 56 72 Invisible 0
SYMATTR InstName M2
SYMATTR Value P_50n
SYMATTR Value2 l=50n w=1u
SYMBOL current 768 -528 R0
WINDOW 0 42 19 Left 0
WINDOW 3 43 49 Left 0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName Ibias
SYMATTR Value 1µ
SYMBOL pmos4 1072 -560 M180
WINDOW 0 56 32 Invisible 0
WINDOW 3 56 72 Invisible 0
SYMATTR InstName M4
SYMATTR Value P_50n
SYMATTR Value2 l=1u w=1u
SYMBOL pmos4 816 -560 R180
WINDOW 0 56 32 Invisible 0
WINDOW 3 56 72 Invisible 0
SYMATTR InstName M5
SYMATTR Value P_50n
SYMATTR Value2 l=1u w=1u
TEXT 1280 -632 Left 0 !.lib cmosedu_models.txt\n.ic v(vbit)=0.5
TEXT 600 -280 Left 0 !.tran 0 1.1u 100n uic
TEXT 1280 -360 Left 0 ;Plot Vbit VREF Out
TEXT 240 -144 Left 0 ;Models the current of a floating gate memory cell. Adjust\nbetween 0 and 1 uA. Note how increasing the simulation time\nwill increase the sense's SNR.