Version 4
SHEET 1 2556 1076
WIRE 448 -592 448 -624
WIRE 448 -480 448 -512
WIRE 448 -352 448 -384
WIRE 448 -240 448 -272
WIRE 448 224 448 192
WIRE 448 336 448 304
WIRE 560 -592 560 -624
WIRE 560 -480 560 -512
WIRE 768 -656 768 -672
WIRE 768 -544 768 -560
WIRE 768 -528 768 -544
WIRE 768 -400 768 -448
WIRE 768 224 768 192
WIRE 768 336 768 304
WIRE 832 -640 816 -640
WIRE 832 -544 768 -544
WIRE 832 -544 832 -640
WIRE 944 -672 768 -672
WIRE 992 -288 992 -368
WIRE 992 -144 992 -160
WIRE 1008 -368 992 -368
WIRE 1056 -512 1056 -528
WIRE 1056 -384 1056 -416
WIRE 1056 -288 992 -288
WIRE 1056 -256 1056 -288
WIRE 1072 -640 832 -640
WIRE 1072 224 1072 192
WIRE 1072 336 1072 304
WIRE 1088 -160 992 -160
WIRE 1088 -64 1088 -96
WIRE 1120 -672 944 -672
WIRE 1120 -656 1120 -672
WIRE 1120 -528 1056 -528
WIRE 1120 -528 1120 -560
WIRE 1184 -528 1120 -528
WIRE 1184 -512 1184 -528
WIRE 1184 -160 1088 -160
WIRE 1184 -160 1184 -416
WIRE 1232 -160 1184 -160
WIRE 1264 -160 1232 -160
WIRE 1440 304 1360 304
WIRE 1552 448 1536 448
WIRE 1552 448 1552 336
WIRE 1568 -64 1520 -64
WIRE 1568 272 1568 -64
WIRE 1584 272 1568 272
WIRE 1584 304 1440 304
WIRE 1584 336 1552 336
WIRE 1600 -144 1520 -144
WIRE 1936 464 1936 304
WIRE 1984 -768 1984 -848
WIRE 1984 -448 1984 -528
WIRE 1984 -128 1984 -208
WIRE 1984 192 1984 112
WIRE 1984 512 1984 432
WIRE 2064 -848 1984 -848
WIRE 2064 -528 1984 -528
WIRE 2064 -208 1984 -208
WIRE 2064 112 1984 112
WIRE 2064 432 1984 432
WIRE 2064 464 1936 464
WIRE 2288 -848 2272 -848
WIRE 2288 -800 2288 -848
WIRE 2288 -768 1984 -768
WIRE 2288 -768 2288 -800
WIRE 2288 -528 2272 -528
WIRE 2288 -480 2288 -528
WIRE 2288 -448 1984 -448
WIRE 2288 -448 2288 -480
WIRE 2288 -208 2272 -208
WIRE 2288 -160 2288 -208
WIRE 2288 -128 1984 -128
WIRE 2288 -128 2288 -160
WIRE 2288 112 2272 112
WIRE 2288 160 2288 112
WIRE 2288 192 1984 192
WIRE 2288 192 2288 160
WIRE 2288 432 2272 432
WIRE 2288 464 2288 432
WIRE 2288 512 1984 512
WIRE 2288 512 2288 464
WIRE 2368 -912 2272 -912
WIRE 2368 -592 2272 -592
WIRE 2368 -272 2272 -272
WIRE 2368 48 2272 48
WIRE 2368 368 2272 368
FLAG 448 -480 0
FLAG 448 -624 VDD
FLAG 1056 -336 VDD
FLAG 1184 -464 VDD
FLAG 1232 -160 vbit
FLAG 560 -480 0
FLAG 560 -624 VREF
FLAG 1392 -208 VDD
FLAG 448 -240 0
FLAG 448 -384 clock
FLAG 1264 -64 VREF
FLAG 1088 -64 0
FLAG 1344 -240 clock
FLAG 1392 -16 0
FLAG 1568 -64 Out
FLAG 992 -64 0
FLAG 1600 -144 Outi
FLAG 1056 -464 VDD
FLAG 1056 -256 0
FLAG 1232 -496 Outi
FLAG 1008 -496 Out
FLAG 1120 -608 VDD
FLAG 768 -608 VDD
FLAG 768 -400 0
FLAG 944 -672 VDD
FLAG 1760 384 0
FLAG 1760 224 VDD
FLAG 448 336 0
FLAG 448 192 enable
FLAG 1440 304 enable
FLAG 2176 288 VDD
FLAG 2368 368 B0
IOPIN 2368 368 Out
FLAG 2064 336 0
FLAG 2064 368 Store
FLAG 2064 400 Xfer
FLAG 2176 -32 VDD
FLAG 2368 48 B1
IOPIN 2368 48 Out
FLAG 2064 16 0
FLAG 2064 48 Store
FLAG 2064 80 Xfer
FLAG 2176 -352 VDD
FLAG 2368 -272 B2
IOPIN 2368 -272 Out
FLAG 2064 -304 0
FLAG 2064 -272 Store
FLAG 2064 -240 Xfer
FLAG 2176 -672 VDD
FLAG 2368 -592 B3
IOPIN 2368 -592 Out
FLAG 2064 -624 0
FLAG 2064 -592 Store
FLAG 2064 -560 Xfer
FLAG 2176 -992 VDD
FLAG 2368 -912 B4
IOPIN 2368 -912 Out
FLAG 2064 -944 0
FLAG 2064 -912 Store
FLAG 2064 -880 Xfer
FLAG 2288 464 b0i
FLAG 2064 144 b0i
FLAG 2288 160 b1i
FLAG 2064 -176 b1i
FLAG 2288 -160 b2i
FLAG 2064 -496 b2i
FLAG 2288 -480 b3i
FLAG 2064 -816 b3i
FLAG 2288 -800 b4i
FLAG 768 336 0
FLAG 768 192 Store
FLAG 1072 336 0
FLAG 1072 192 Xfer
FLAG 1392 368 VDD
FLAG 1392 528 0
FLAG 1280 448 clock
SYMBOL voltage 448 -608 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 40 53 Left 0
SYMATTR Value 1
SYMATTR InstName VDD
SYMBOL pmos4 1008 -288 M180
WINDOW 0 56 32 Invisible 0
WINDOW 3 56 72 Invisible 0
SYMATTR InstName M3
SYMATTR Value P_50n
SYMATTR Value2 l=1u w=1u
SYMBOL pmos4 1232 -416 R180
WINDOW 0 56 32 Invisible 0
WINDOW 3 56 72 Invisible 0
SYMATTR InstName M1
SYMATTR Value P_50n
SYMATTR Value2 l=50n w=1u
SYMBOL voltage 560 -608 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 40 53 Left 0
SYMATTR Value 500m
SYMATTR InstName VREF
SYMBOL voltage 448 -368 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 -83 163 Left 0
SYMATTR Value PULSE(1 0 6n 10p 10p 5n 10n)
SYMATTR InstName Vclock
SYMBOL cap 1072 -160 R0
WINDOW 0 43 22 Left 0
WINDOW 3 45 50 Left 0
SYMATTR InstName Cbit
SYMATTR Value 2p
SYMBOL Fig_17_16_no_Vos 1312 -112 R0
SYMATTR InstName U1
SYMBOL current 992 -144 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName I1
SYMATTR Value 500n
SYMBOL pmos4 1008 -416 M180
WINDOW 0 56 32 Invisible 0
WINDOW 3 56 72 Invisible 0
SYMATTR InstName M2
SYMATTR Value P_50n
SYMATTR Value2 l=50n w=1u
SYMBOL current 768 -528 R0
WINDOW 0 42 19 Left 0
WINDOW 3 43 49 Left 0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName Ibias
SYMATTR Value 1µ
SYMBOL pmos4 1072 -560 M180
WINDOW 0 56 32 Invisible 0
WINDOW 3 56 72 Invisible 0
SYMATTR InstName M4
SYMATTR Value P_50n
SYMATTR Value2 l=1u w=1u
SYMBOL pmos4 816 -560 R180
WINDOW 0 56 32 Invisible 0
WINDOW 3 56 72 Invisible 0
SYMATTR InstName M5
SYMATTR Value P_50n
SYMATTR Value2 l=1u w=1u
SYMBOL voltage 448 208 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 -83 163 Left 0
SYMATTR Value PULSE(0 1 100n 10p 10p 320n)
SYMATTR InstName Venable
SYMBOL DSM_counter_bit 2096 480 R0
SYMATTR InstName U2
SYMBOL DSM_counter_bit 2096 160 R0
SYMATTR InstName U3
SYMBOL DSM_counter_bit 2096 -160 R0
SYMATTR InstName U4
SYMBOL DSM_counter_bit 2096 -480 R0
SYMATTR InstName U5
SYMBOL DSM_counter_bit 2096 -800 R0
SYMATTR InstName U6
SYMBOL voltage 768 208 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 -83 163 Left 0
SYMATTR Value PULSE(0 1 50n 10p 10p 10n)
SYMATTR InstName Vstore
SYMBOL voltage 1072 208 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 -83 163 Left 0
SYMATTR Value PULSE(0 1 70n 10p 10p 10n)
SYMATTR InstName Vxfer
SYMBOL NAND_3 1536 320 R0
SYMATTR InstName U7
SYMBOL INV_20_10 1312 384 R0
SYMATTR InstName U8
TEXT 1280 -632 Left 0 !.lib cmosedu_models.txt\n.ic v(vbit)=0.5
TEXT 600 -280 Left 0 !.tran 0 500n 0 uic
TEXT 240 -144 Left 0 ;Models the current of a floating gate memory cell. Adjust\nbetween 0 and 1 uA. Note how increasing the simulation time\nwill increase the sense's SNR.
TEXT 640 -24 Left 0 !.measure mean(I(vdd))
TEXT 1256 -416 Left 0 ;Note that you need to let the DSM sensing circuit run for a little while \nbefore you enable the counter. This drives the bitline to VREF. Here\nI cheat by using the .ic statement to minimize the simulation time.
TEXT 1512 -944 Left 0 ;Store an initial value of 000000 to the counter
TEXT 1440 -880 Left 0 ;Transfer the value into the counter prior to sensing