Version 4 SHEET 1 2936 3384 WIRE -176 256 -176 224 WIRE -176 368 -176 336 WIRE -176 512 -176 480 WIRE -176 624 -176 592 WIRE -176 848 -176 800 WIRE -176 960 -176 928 WIRE -176 1136 -176 1104 WIRE -176 1248 -176 1216 WIRE -176 1824 -176 1792 WIRE -176 1952 -176 1904 WIRE -176 2048 -176 2016 WIRE -176 2176 -176 2128 WIRE -176 2384 -176 2336 WIRE -176 2496 -176 2464 WIRE -160 1472 -192 1472 WIRE -144 800 -176 800 WIRE -144 2608 -176 2608 WIRE -144 2656 -176 2656 WIRE -128 -64 -128 -96 WIRE -128 64 -128 16 WIRE -128 800 -144 800 WIRE -128 1104 -176 1104 WIRE -128 2336 -176 2336 WIRE -112 480 -176 480 WIRE -112 1472 -160 1472 WIRE -112 1536 -112 1472 WIRE -112 1648 -112 1584 WIRE -96 224 -176 224 WIRE -96 1792 -176 1792 WIRE -96 2016 -176 2016 WIRE -80 -96 -128 -96 WIRE -64 1520 -64 1472 WIRE -64 1648 -64 1600 WIRE 48 1472 -64 1472 WIRE 64 2608 16 2608 WIRE 128 1136 128 1104 WIRE 128 1248 128 1216 WIRE 176 1104 128 1104 WIRE 224 1472 128 1472 WIRE 224 1536 224 1472 WIRE 224 1648 224 1600 WIRE 256 2368 224 2368 WIRE 256 2416 224 2416 WIRE 256 2608 224 2608 WIRE 256 2656 224 2656 WIRE 272 1472 224 1472 WIRE 352 1824 352 1792 WIRE 352 1952 352 1904 WIRE 352 2048 352 2016 WIRE 352 2176 352 2128 WIRE 384 1472 352 1472 WIRE 384 1536 384 1472 WIRE 384 1648 384 1600 WIRE 432 1472 384 1472 WIRE 432 1792 352 1792 WIRE 432 2016 352 2016 WIRE 448 -64 448 -96 WIRE 448 64 448 16 WIRE 464 2368 416 2368 WIRE 464 2608 416 2608 WIRE 496 -96 448 -96 WIRE 512 304 496 304 WIRE 544 1472 512 1472 WIRE 544 1536 544 1472 WIRE 544 1648 544 1600 WIRE 576 304 512 304 WIRE 576 1136 576 1104 WIRE 576 1248 576 1216 WIRE 592 1472 544 1472 WIRE 656 2368 624 2368 WIRE 656 2416 624 2416 WIRE 656 2608 624 2608 WIRE 656 2656 624 2656 WIRE 688 304 656 304 WIRE 688 336 688 304 WIRE 688 432 688 400 WIRE 704 816 624 816 WIRE 704 1104 576 1104 WIRE 704 1472 672 1472 WIRE 704 1536 704 1472 WIRE 704 1648 704 1600 WIRE 752 1472 704 1472 WIRE 800 480 800 368 WIRE 800 576 800 560 WIRE 816 816 784 816 WIRE 816 848 816 816 WIRE 816 944 816 912 WIRE 848 304 688 304 WIRE 848 368 800 368 WIRE 864 1472 832 1472 WIRE 864 1536 864 1472 WIRE 864 1648 864 1600 WIRE 864 1824 864 1792 WIRE 864 1952 864 1904 WIRE 864 2368 816 2368 WIRE 864 2608 816 2608 WIRE 912 1472 864 1472 WIRE 928 992 928 880 WIRE 928 1088 928 1072 WIRE 944 1792 864 1792 WIRE 976 816 816 816 WIRE 976 880 928 880 WIRE 1024 1472 992 1472 WIRE 1024 1536 1024 1472 WIRE 1024 1648 1024 1600 WIRE 1072 352 1024 352 WIRE 1072 400 1072 352 WIRE 1072 496 1072 448 WIRE 1072 1984 1008 1984 WIRE 1072 2016 1008 2016 WIRE 1072 2048 1008 2048 WIRE 1072 2080 1008 2080 WIRE 1072 2112 1008 2112 WIRE 1072 2304 1008 2304 WIRE 1072 2400 1008 2400 WIRE 1072 2496 1008 2496 WIRE 1072 2592 1008 2592 WIRE 1072 2688 1008 2688 WIRE 1088 400 1072 400 WIRE 1088 448 1072 448 WIRE 1136 384 1136 352 WIRE 1136 496 1136 464 WIRE 1152 1472 1024 1472 WIRE 1152 1520 1152 1472 WIRE 1152 1648 1152 1600 WIRE 1200 352 1136 352 WIRE 1200 864 1152 864 WIRE 1216 1984 1152 1984 WIRE 1216 2016 1152 2016 WIRE 1216 2048 1152 2048 WIRE 1216 2080 1152 2080 WIRE 1216 2112 1152 2112 WIRE 1232 1472 1152 1472 WIRE 1232 2304 1152 2304 WIRE 1232 2400 1152 2400 WIRE 1232 2400 1232 2304 WIRE 1232 2496 1152 2496 WIRE 1232 2496 1232 2400 WIRE 1232 2592 1152 2592 WIRE 1232 2592 1232 2496 WIRE 1232 2688 1152 2688 WIRE 1232 2688 1232 2592 WIRE 1264 2496 1232 2496 FLAG -128 64 0 FLAG -176 960 0 FLAG -80 -96 fstart FLAG -144 800 sine0 FLAG -176 624 0 FLAG -112 480 phase IOPIN -112 480 Out FLAG 448 64 0 FLAG 496 -96 freq IOPIN 496 -96 Out FLAG -176 1952 0 FLAG -96 1792 bit0c FLAG 352 1952 0 FLAG 432 1792 bit1c FLAG 864 1952 0 FLAG 944 1792 bit2c FLAG -176 2176 0 FLAG -96 2016 bit3c FLAG 352 2176 0 FLAG 432 2016 bit4c FLAG 1264 2496 sintest IOPIN 1264 2496 Out FLAG 1008 2400 bit1 FLAG 1008 2496 bit2 FLAG 1008 2592 bit3 FLAG 1008 2688 bit4 FLAG 1008 2304 bit0 FLAG -176 1248 0 FLAG -128 1104 sine1 IOPIN -128 1104 Out FLAG -64 1648 0 FLAG 224 1648 0 FLAG 384 1648 0 FLAG 544 1648 0 FLAG 704 1648 0 FLAG 864 1648 0 FLAG 1024 1648 0 FLAG 1152 1648 0 FLAG 624 816 sine0 FLAG 464 2368 bit0 IOPIN 464 2368 Out FLAG -176 2496 0 FLAG 224 2368 bit0c FLAG 224 2416 clkout FLAG 464 2608 bit3 IOPIN 464 2608 Out FLAG 224 2608 bit3c FLAG 224 2656 clkout FLAG 864 2368 bit1 IOPIN 864 2368 Out FLAG 624 2368 bit1c FLAG 624 2416 clkout FLAG 864 2608 bit4 IOPIN 864 2608 Out FLAG 624 2608 bit4c FLAG 624 2656 clkout FLAG 64 2608 bit2 IOPIN 64 2608 Out FLAG -176 2608 bit2c FLAG -176 2656 clkout FLAG -128 2336 clkout IOPIN -128 2336 Out FLAG 704 1104 sine IOPIN 704 1104 Out FLAG 1008 1984 bit4 FLAG 1008 2016 bit3 FLAG 1008 2048 bit2 FLAG 1008 2080 bit1 FLAG 1008 2112 bit0 FLAG 1216 1984 bit4_ FLAG 1216 2016 bit3_ FLAG 1216 2048 bit2_ FLAG 1216 2080 bit1_ FLAG 1216 2112 bit0_ FLAG 128 1248 0 FLAG 176 1104 sine2 IOPIN 176 1104 Out FLAG -176 368 0 FLAG -96 224 phaseacc FLAG 1232 1472 filtSine IOPIN 1232 1472 Out FLAG -160 1472 sine1 FLAG -112 1648 0 FLAG 688 432 0 FLAG 800 576 0 FLAG 1200 352 phase0 FLAG 512 304 phaseacc FLAG 1072 496 0 FLAG 1136 496 0 FLAG 816 944 0 FLAG 928 1088 0 FLAG 576 1248 0 FLAG 1200 864 sine_ SYMBOL voltage -128 -80 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V1 SYMATTR Value PULSE(0 1 0 1p 1p 1 2) SYMBOL bv -176 832 R0 WINDOW 3 11 -8 Left 0 SYMATTR Value V=int(sin(2*pi*V(phase)/{ACCU})*({DAC}-1)/2+{DAC-1}/2+EPS) SYMATTR InstName B2 SYMBOL bv -176 496 R0 WINDOW 3 46 116 Left 0 WINDOW 39 49 80 Left 0 SYMATTR Value V=int(V(phase0)+0.5) SYMATTR InstName B3 SYMBOL bv 448 -80 R0 SYMATTR InstName B4 SYMATTR Value V=V(Fstart)*int(FREQ1+0.5) SYMBOL bv -176 1808 R0 SYMATTR InstName B6 SYMATTR Value V=if((V(sine)-2*int(V(sine)/2+{EPS}))>0.5,1,0) SYMBOL bv 352 1808 R0 SYMATTR InstName B7 SYMATTR Value V=if((V(sine)-4*int(V(sine)/4+{EPS}))>1.5,1,0) SYMBOL bv 864 1808 R0 SYMATTR InstName B8 SYMATTR Value V=if((V(sine)-8*int(V(sine)/8+{EPS}))>3.5,1,0) SYMBOL bv -176 2032 R0 SYMATTR InstName B9 SYMATTR Value V=if((V(sine)-16*int(V(sine)/16+{EPS}))>7.5,1,0) SYMBOL bv 352 2032 R0 SYMATTR InstName B10 SYMATTR Value V=if((V(sine)-32*int(V(sine)/32+{EPS}))>15.5,1,0) SYMBOL res 1056 2320 R270 WINDOW 0 32 56 VTop 0 WINDOW 3 0 56 VBottom 0 SYMATTR InstName R2 SYMATTR Value 16k SYMBOL res 1056 2416 R270 WINDOW 0 32 56 VTop 0 WINDOW 3 0 56 VBottom 0 SYMATTR InstName R3 SYMATTR Value 8k SYMBOL res 1056 2512 R270 WINDOW 0 32 56 VTop 0 WINDOW 3 0 56 VBottom 0 SYMATTR InstName R4 SYMATTR Value 4k SYMBOL res 1056 2608 R270 WINDOW 0 32 56 VTop 0 WINDOW 3 0 56 VBottom 0 SYMATTR InstName R5 SYMATTR Value 2k SYMBOL res 1056 2704 R270 WINDOW 0 32 56 VTop 0 WINDOW 3 0 56 VBottom 0 SYMATTR InstName R6 SYMATTR Value 1k SYMBOL bv -176 1120 R0 SYMATTR InstName B11 SYMATTR Value V=2*V(sine)/{DAC-1}-1 SYMBOL res 32 1488 R270 WINDOW 0 32 56 VTop 0 WINDOW 3 0 56 VBottom 0 SYMATTR InstName R7 SYMATTR Value 50 SYMBOL cap 208 1536 R0 SYMATTR InstName C1 SYMATTR Value 92.5p SYMBOL ind 256 1488 R270 WINDOW 0 32 56 VTop 0 WINDOW 3 5 56 VBottom 0 SYMATTR InstName L1 SYMATTR Value 405n SYMBOL cap 368 1536 R0 SYMATTR InstName C2 SYMATTR Value 205.4p SYMBOL ind 416 1488 R270 WINDOW 0 32 56 VTop 0 WINDOW 3 5 56 VBottom 0 SYMATTR InstName L2 SYMATTR Value 489.4n SYMBOL cap 528 1536 R0 SYMATTR InstName C3 SYMATTR Value 219.5p SYMBOL ind 576 1488 R270 WINDOW 0 32 56 VTop 0 WINDOW 3 5 56 VBottom 0 SYMATTR InstName L3 SYMATTR Value 501.1n SYMBOL cap 688 1536 R0 SYMATTR InstName C4 SYMATTR Value 219.5p SYMBOL ind 736 1488 R270 WINDOW 0 32 56 VTop 0 WINDOW 3 5 56 VBottom 0 SYMATTR InstName L4 SYMATTR Value 489.4n SYMBOL cap 848 1536 R0 SYMATTR InstName C5 SYMATTR Value 205.4p SYMBOL ind 896 1488 R270 WINDOW 0 32 56 VTop 0 WINDOW 3 5 56 VBottom 0 SYMATTR InstName L5 SYMATTR Value 405n SYMBOL cap 1008 1536 R0 SYMATTR InstName C6 SYMATTR Value 92.5p SYMBOL res 1136 1504 R0 SYMATTR InstName R8 SYMATTR Value 50 SYMBOL Digital\\dflop 336 2320 R0 WINDOW 3 51 -34 Left 0 SYMATTR Value td={TS/2} SYMATTR InstName A1 SYMBOL voltage -176 2368 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V6 SYMATTR Value PULSE(0 1 {TS/2} 1p 1p {TS/2} {TS}) SYMBOL Digital\\dflop 336 2560 R0 WINDOW 3 51 -34 Left 0 SYMATTR Value td={TS/2} SYMATTR InstName A2 SYMBOL Digital\\dflop 736 2320 R0 WINDOW 3 51 -34 Left 0 SYMATTR Value td={TS/2} SYMATTR InstName A3 SYMBOL Digital\\dflop 736 2560 R0 WINDOW 3 51 -34 Left 0 SYMATTR Value td={TS/2} SYMATTR InstName A4 SYMBOL Digital\\dflop -64 2560 R0 WINDOW 3 51 -34 Left 0 SYMATTR Value td={TS/2} SYMATTR InstName A5 SYMBOL dview5 1088 2128 R0 SYMATTR InstName U1 SYMATTR SpiceLine OFFSET=-7 GAIN=0.5 SYMBOL bv 128 1120 R0 SYMATTR InstName B13 SYMATTR Value V=V(sine)/{DAC-1} SYMBOL bv -176 240 R0 WINDOW 3 -50 173 Left 0 WINDOW 39 34 81 Left 0 SYMATTR Value V=int(V(freq)+V(phase)-{ACCU}*int((V(freq)+V(phase))/{ACCU})+0.5) SYMATTR InstName B14 SYMBOL e -64 1504 R0 SYMATTR InstName E4 SYMATTR Value 2 SYMBOL SpecialFunctions\\sample 928 336 R0 SYMATTR InstName A6 SYMATTR SpiceLine vhigh=1000 SYMATTR SpiceLine2 rout=1 SYMBOL res 560 320 R270 WINDOW 0 32 56 VTop 0 WINDOW 3 0 56 VBottom 0 SYMATTR InstName R1 SYMATTR Value 10 SYMBOL cap 672 336 R0 SYMATTR InstName C11 SYMATTR Value {CH} SYMBOL voltage 800 464 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V7 SYMATTR Value PULSE(0 1 0 1p 1p {0.2*TS} {TS}) SYMBOL e 1136 368 R0 SYMATTR InstName E5 SYMATTR Value 1 SYMBOL SpecialFunctions\\sample 1056 848 R0 SYMATTR InstName A7 SYMATTR SpiceLine vhigh=1000 SYMATTR SpiceLine2 rout=1 SYMBOL res 688 832 R270 WINDOW 0 32 56 VTop 0 WINDOW 3 0 56 VBottom 0 SYMATTR InstName R9 SYMATTR Value 10 SYMBOL cap 800 848 R0 SYMATTR InstName C7 SYMATTR Value {CH} SYMBOL voltage 928 976 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V2 SYMATTR Value PULSE(0 1 0 1p 1p {0.2*TS} {TS}) SYMBOL Misc\\Epoly 576 1120 R0 SYMATTR InstName E1 SYMATTR Value VALUE={IF((time<1p), V(sine0), V(sine_))} TEXT -192 -704 Left 0 !.tran 0 3u 0 {TS/100} TEXT -192 -408 Left 0 !.PARAM DAC=32 TEXT -192 -528 Left 0 !.PARAM ACCU=256 TEXT -192 -496 Left 0 !.PARAM FREQ1=FSIN/FS*ACCU TEXT -192 -560 Left 0 !.PARAM TS=1/FS TEXT -192 -592 Left 0 !.PARAM FS=100e6 TEXT -192 -624 Left 0 !.PARAM FSIN=5e6 TEXT -192 -968 Left 0 ;A DDS Generator With An Integer Accumulator and DAC\n=============================================\nVersion 2.0\n \nClock frequency: FS 100MHz\nAccumulator: ACCU 256 (8bit)\nFrequency resolution: FS / ACCU \nDAC steps: 32 (5bit) TEXT -224 -152 Left 0 ;fstart must be 0 at t=0 or a uramp() must be added. TEXT -200 168 Left 0 ;The Integer Phase Accumulator TEXT -216 720 Left 0 ;The Sine Function "ROM" With S/H\nIt converts the highest bits of the accumulator to the sine values. TEXT -224 1744 Left 0 ;The Optional Parallel Data Output Bits For A Sine DAC TEXT 936 2208 Left 0 ;A Test Circuit For The Parallel Sine Bits\n"sintest" must be equal to "sine2". TEXT -216 1032 Left 0 ;The normalized sine output from an idela DAC. \nAdjust gain and offset according to your needs. TEXT -192 -328 Left 0 !.model sw1 sw(Vt=0.5 Ron=1 Roff=1G) TEXT -224 2272 Left 0 ;The Deglitcher For The Data Bits TEXT 816 728 Left 0 ;The Sine "ROM" Deglitcher With Sample And Hold TEXT 16 448 Left 0 ;The Phase Wrapper Makes The Word Length. TEXT 624 168 Left 0 ;The Pace Maker With Sample And Hold\n It is a deglitcher too. TEXT 440 -152 Left 0 ;Round To The Nearest Integer TEXT 504 -432 Left 0 ;R\nE\nG TEXT 664 -432 Left 0 ;SINE\n \nROM TEXT 768 -432 Left 0 ;R\nE\nG TEXT 912 -432 Left 0 ;D\nA\nC TEXT 1000 -416 Left 0 ;LP-\nFLT TEXT 1072 -424 Left 0 ;SINE TEXT 424 -520 Left 0 ;D(7:0) TEXT 576 -432 Left 0 ;D(7:3) TEXT 312 -392 Left 0 ;FREQ TEXT 312 -320 Left 0 ;FS TEXT 528 -576 Left 0 ;The Basic DDS Generator TEXT 968 -520 Left 0 ;DIIGITAL SINE TEXT 408 -368 Left 0 ;ACC TEXT -136 1376 Left 0 ;The 30MHz Chebyshef Low Pass Filter TEXT -200 2864 Left 0 !.SUBCKT DVIEW5 in1 out1 in2 out2 in3 out3 in4 out4 in5 out5 offs1={offset} gain1={gain}\nVoffs1 base1 0 DC {offs1+4} \nVoffs2 base2 base1 DC -1\nVoffs3 base3 base2 DC -1\nVoffs4 base4 base3 DC -1\nVoffs5 base5 base4 DC -1\nE1 out1 base1 in1 0 {gain1}\nE2 out2 base2 in2 0 {gain1}\nE3 out3 base3 in3 0 {gain1}\nE4 out4 base4 in4 0 {gain1}\nE5 out5 base5 in5 0 {gain1}\nR1 in1 0 1e8\nR2 in2 0 1e8\nR3 in3 0 1e8\nR4 in4 0 1e8\nR5 in5 0 1e8\n.ENDS DVIEW5 TEXT -192 -368 Left 0 !.PARAM EPS=1e-3 TEXT -200 2816 Left 0 ;The Digital Signal Watcher TEXT 520 -680 Left 0 ;Helmut Sennewald V1.0 TEXT 824 2048 Left 0 ;Bit Viewer -> TEXT 824 624 Left 0 ;PULSE(0 1 {TS*0.5} 1p 1p {0.2*TS} {TS}) TEXT -192 -672 Left 0 !.options plotwinsize=0 TEXT -192 -456 Left 0 !.param CH=TS/(10*100) TEXT 552 1040 Left 0 ;Bypass the S/H at t=<1p LINE Normal 391 -375 310 -375 LINE Normal 432 -400 432 -425 LINE Normal 419 -413 444 -413 LINE Normal 472 -413 497 -413 LINE Normal 514 -339 511 -331 LINE Normal 517 -331 514 -339 LINE Normal 514 -299 514 -331 LINE Normal 648 -412 531 -412 LINE Normal 555 -498 555 -412 LINE Normal 366 -498 555 -498 LINE Normal 366 -439 366 -498 LINE Normal 391 -439 366 -439 LINE Normal 736 -413 761 -413 LINE Normal 778 -339 775 -331 LINE Normal 781 -331 778 -339 LINE Normal 778 -299 778 -331 LINE Normal 880 -412 795 -412 LINE Normal 984 -412 957 -412 LINE Normal 1061 -409 1127 -409 LINE Normal 314 -299 778 -299 LINE Normal 826 -504 826 -412 LINE Normal 1128 -504 826 -504 RECTANGLE Normal 1376 665 -248 131 RECTANGLE Normal 1381 1312 -250 695 RECTANGLE Normal 1382 2749 -255 1718 RECTANGLE Normal 1025 107 -250 -180 RECTANGLE Normal 472 -332 391 -475 RECTANGLE Normal 531 -331 497 -475 RECTANGLE Normal 735 -332 649 -475 RECTANGLE Normal 957 -331 880 -475 RECTANGLE Normal 795 -331 761 -475 RECTANGLE Normal 1061 -331 984 -475 RECTANGLE Normal 1384 1694 -256 1337