Version 4
SHEET 1 884 680
WIRE 192 64 48 64
WIRE 288 64 192 64
WIRE 432 64 288 64
WIRE 48 128 48 64
WIRE 192 128 192 64
WIRE 288 144 288 64
FLAG 48 208 0
FLAG 192 208 0
FLAG 432 64 out
FLAG 48 416 0
FLAG 48 336 in
FLAG 288 208 0
FLAG -128 416 0
FLAG -128 336 vd
SYMBOL bi 48 208 R180
WINDOW 0 24 88 Left 0
WINDOW 3 24 0 Left 0
SYMATTR InstName B1
SYMATTR Value I= delay(V(in),{Td })
SYMBOL res 176 112 R0
SYMATTR InstName R1
SYMATTR Value 1
SYMBOL voltage 48 320 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value PULSE(0 1 0 10n)
SYMBOL cap 272 144 R0
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL voltage -128 320 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 24 44 Left 0
SYMATTR Value {Td}
SYMATTR InstName V2
TEXT -312 -40 Left 0 !.tran 0 4 {4-3*0.01} 0.01
TEXT -320 48 Left 0 !.STEP param Td 0.5 4 0.1
TEXT -296 -112 Left 0 ;Plotting the result of a .TRAN analysis vs delay in B1.\nPlot V(out) versus V(vd) and set "Mark data points"
TEXT -40 -40 Left 0 ;LTspice needs at least 2 data points left over\nfor a correct display.
TEXT 144 256 Left 0 ;This would be\nthe circuit under test.
RECTANGLE Normal 384 304 144 32