Version 4
SHEET 1 880 680
WIRE 208 96 208 48
WIRE 176 112 -96 112
WIRE 384 128 240 128
WIRE 176 144 64 144
WIRE 208 192 208 160
WIRE -224 208 -224 192
WIRE -96 208 -96 112
WIRE 64 208 64 144
WIRE -224 320 -224 288
WIRE -96 320 -96 288
WIRE 64 320 64 288
FLAG 208 192 0
FLAG -224 320 0
FLAG 208 48 VCC
FLAG -224 192 VCC
FLAG 384 128 out
IOPIN 384 128 Out
FLAG 64 320 0
FLAG -96 320 0
SYMBOL voltage -224 192 R0
WINDOW 123 0 0 Left 0
WINDOW 39 24 132 Left 0
SYMATTR SpiceLine Rser=1
SYMATTR InstName V1
SYMATTR Value 3.3
SYMBOL voltage -96 192 R0
WINDOW 3 27 93 Left 0
WINDOW 123 0 0 Left 0
WINDOW 39 24 132 Left 0
SYMATTR Value 1
SYMATTR InstName V2
SYMBOL voltage 64 192 R0
WINDOW 3 24 160 Left 0
WINDOW 123 0 0 Left 0
WINDOW 39 24 132 Left 0
SYMATTR Value SINE(1 1 1k)
SYMATTR SpiceLine Rser=1k
SYMATTR InstName V3
SYMBOL Robertugo\\comp5_all 208 64 R0
WINDOW 0 -30 63 Left 0
SYMATTR InstName U1
SYMATTR SpiceModel MAX9119
TEXT -504 64 Left 0 !.tran 0 10m
TEXT -504 88 Left 0 !.options plotwinsize=0
TEXT -504 136 Left 0 !.options gminsteps=0
TEXT -504 184 Left 0 !.options cshunt=1e-17
TEXT -504 160 Left 0 !.options abstol=1e-11
TEXT -504 208 Left 0 ;.options reltol=1e-3
TEXT -504 240 Left 0 ;.options vntol=1e-6
TEXT -200 -24 Left 0 ;The key for successful simulation\nhas been the maximum time step \nvalue of 100n and an abstol of 10p.\n .tran 0 10m 0 .1u\n.options abstol=1e-11
TEXT -504 112 Left 0 !.options maxstep=100n