Version 4
SHEET 1 1480 988
WIRE 288 -320 288 -352
WIRE 48 -272 -240 -272
WIRE 208 -272 48 -272
WIRE 448 -272 368 -272
WIRE 48 -240 -16 -240
WIRE 208 -240 48 -240
WIRE 48 -208 -144 -208
WIRE 208 -208 48 -208
WIRE 448 -208 384 -208
WIRE -240 -160 -240 -272
WIRE -144 -160 -144 -208
WIRE -16 -160 -16 -240
WIRE 288 -128 288 -160
WIRE -240 -64 -240 -80
WIRE -144 -64 -144 -80
WIRE -16 -64 -16 -80
WIRE -224 16 -256 16
WIRE -112 16 -144 16
WIRE 16 16 -16 16
WIRE -256 48 -256 16
WIRE -144 48 -144 16
WIRE -16 48 -16 16
WIRE -256 144 -256 128
WIRE -144 144 -144 128
WIRE -16 144 -16 128
WIRE -48 368 -272 368
WIRE 256 416 256 384
WIRE -272 464 -272 368
WIRE -240 464 -272 464
WIRE 0 464 -80 464
WIRE 16 464 0 464
WIRE 176 464 144 464
WIRE 384 464 336 464
WIRE 416 464 384 464
WIRE -304 512 -320 512
WIRE -240 512 -304 512
WIRE -48 512 -48 368
WIRE -48 512 -64 512
WIRE 0 512 -48 512
WIRE 16 512 0 512
WIRE 96 512 80 512
WIRE 176 512 96 512
WIRE 384 512 352 512
WIRE 416 512 384 512
WIRE 256 592 256 560
FLAG -16 -64 0
FLAG -240 -64 0
FLAG -144 -64 0
FLAG 48 -272 J
FLAG 48 -208 K
FLAG 48 -240 CP
FLAG -304 512 CP
FLAG 96 512 CP
FLAG 448 -272 Q_X_JK
FLAG 0 464 Q_A_D
FLAG 384 464 Q_X_T
FLAG 144 464 hi
FLAG -256 144 0
FLAG -224 16 hi
FLAG -144 144 0
FLAG -112 16 lo
FLAG -16 144 0
FLAG 16 16 clr
FLAG 448 -208 _Q_X_JK
FLAG 256 592 lo
FLAG 256 384 lo
FLAG 0 512 _Q_A_D
FLAG 384 512 _Q_X_T
SYMBOL voltage -16 -176 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value PULSE(0 1 50n 10n 10n 50n 100n)
SYMBOL voltage -240 -176 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 1
SYMBOL voltage -144 -176 R0
SYMATTR InstName V3
SYMATTR Value 1
SYMBOL xtflop 256 416 R0
SYMATTR InstName U3
SYMBOL Digital\\dflop -160 416 R0
WINDOW 3 0 0 Invisible 0
SYMATTR Value Td=10n
SYMATTR InstName A2
SYMBOL XJKFLOP 288 -320 R0
SYMATTR InstName U1
SYMBOL voltage -256 32 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V6
SYMATTR Value 1
SYMBOL voltage -144 32 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V4
SYMATTR Value 0
SYMBOL voltage -16 32 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V7
SYMATTR Value PULSE(1 0 10n 1n 1n 1 1)
TEXT -264 -392 Left 0 !.tran 0 500n 0 1n
TEXT 688 -648 Left 0 !.SUBCKT XJKFLOP  J K C S R QN Q  0 \n* No support for floating ground.\n* Replace all "0" with FGND,\n* if floating ground is required.\n* \nRs S 0 1G\nRc R 0 1G\n*\n* J=1, K=0    Q=1\n* J=1, K=1    Q=toggle\n* J=0, K=0    Q=no change\n* J=0, K=1    Q=0  \nAKNF  K 0 0 0 0  Kn 0 0  BUF \nAJNF  J 0 0 0 0  Jn 0 0  BUF \nA11   J Kn 0   0 0  0 D1 0  AND \nA10   J K QN 0 0  0 D2 0  AND  \nA01   Jn Kn Q  0 0  0 D3 0  AND \nAOR3  D1 D2 D3  0 0  0 Di 0  OR  \nADFF  Di 0 C S R  QN Q 0  DFLOP   td={td} \n.ends
TEXT 688 -56 Left 0 !.SUBCKT XTFLOP  T 0 C S R QN Q  0 \n* Subcircuit for a T-Flipflop with T-enable\n* No support for floating ground.\n* Replace all "0" with FGND,\n* if floating ground is required.\n* \nRs S 0 1G\nRc R 0 1G\nRt  T vcc 1G\nVCC vcc 0 1\n*\nAXOR  T Q 0 0 0   0 TX 0  XOR\nADFF  TX 0 C S R  QN Q 0  DFLOP   td={td} tripdt=1n\n.ends
TEXT -264 392 Left 0 ;A-DFLOP
TEXT 152 384 Left 0 ;XTFLOP
TEXT -64 -352 Left 0 ;Divide by 2 with JKFLOP
TEXT -80 320 Left 0 ;Divide by 2 circuits with D- and T-flipflop
TEXT -264 -784 Left 0 ;JK-Flipflop And T-Flipflop                                   Helmut Sennewald, 12/10/2007\nDifferent circuits for a divider by 2 will be demonstrated.\n \nThis schematic uses the symbol "xjkflop.asy" and "xtflop.asy".\nThe subcircuits "XJKFLOP" and "XTFLOP" are in the schematic as text.\nEvery flipflop needs a delay to operate properly, e.g. td=10n.\n \nT(oggle)-Flipflop:\nIt ca be realized with a D-Flipflop with QN feeded back to the D input\nor a with a subcircuit named "XTFLOP". It has an enable T-input. \nThis T-input should be externally tied to Vhigh.\nThe circuit with the D-flipflop is recommended for a divider by two.
TEXT 264 -376 Left 0 ;XJKFLOP