Version 4 SHEET 1 1452 1212 WIRE -144 -256 -208 -256 WIRE 0 -256 -32 -256 WIRE -208 -160 -208 -256 WIRE -144 -160 -208 -160 WIRE 0 -160 -32 -160 WIRE -208 -144 -208 -160 WIRE 192 -128 144 -128 WIRE -656 -112 -656 -144 WIRE -512 -112 -512 -144 WIRE 144 -112 144 -128 WIRE -208 -48 -208 -64 WIRE -656 0 -656 -32 WIRE -512 0 -512 -32 WIRE 144 0 144 -32 WIRE 176 0 144 0 WIRE 208 0 176 0 WIRE 352 0 320 0 WIRE 144 16 144 0 WIRE 848 32 848 16 WIRE -720 48 -736 48 WIRE -576 48 -592 48 WIRE 352 64 272 64 WIRE -736 80 -736 48 WIRE -592 80 -592 48 WIRE -16 80 -80 80 WIRE 96 80 64 80 WIRE 992 80 912 80 WIRE 144 96 144 80 WIRE 656 96 624 96 WIRE 752 96 736 96 WIRE 640 128 576 128 WIRE 656 128 640 128 WIRE 768 128 736 128 WIRE 848 128 848 112 WIRE 912 128 912 80 WIRE 912 128 848 128 WIRE 928 128 912 128 WIRE -512 144 -512 96 WIRE -464 144 -512 144 WIRE -304 160 -352 160 WIRE -272 160 -304 160 WIRE 640 160 576 160 WIRE 656 160 640 160 WIRE 768 160 736 160 WIRE -656 176 -656 96 WIRE -464 176 -656 176 WIRE -80 176 -80 80 WIRE -48 176 -80 176 WIRE 96 176 96 80 WIRE 96 176 64 176 WIRE 128 176 96 176 WIRE 272 176 272 64 WIRE 272 176 128 176 WIRE 640 192 576 192 WIRE 656 192 640 192 WIRE 768 192 736 192 WIRE 992 192 976 192 WIRE -656 208 -656 176 WIRE -512 208 -512 144 WIRE -304 208 -304 160 WIRE -80 208 -80 176 WIRE 128 224 48 224 WIRE 320 224 240 224 WIRE 640 224 576 224 WIRE 656 224 640 224 WIRE 768 224 736 224 WIRE 992 224 912 224 WIRE 48 240 48 224 WIRE 240 240 240 224 WIRE 1248 240 1216 240 WIRE 608 256 576 256 WIRE 640 272 640 224 WIRE 912 272 912 224 WIRE 912 272 640 272 WIRE 608 288 576 288 WIRE -80 304 -80 272 WIRE 992 304 976 304 WIRE -656 320 -656 288 WIRE -656 320 -688 320 WIRE -512 320 -512 288 WIRE -512 320 -656 320 WIRE -304 320 -304 288 WIRE -304 320 -512 320 WIRE 608 320 576 320 WIRE 48 336 48 320 WIRE 240 336 240 320 FLAG -80 304 0 FLAG 48 336 0 FLAG 128 224 VDD FLAG 0 -160 out_14 FLAG -208 -48 0 FLAG -208 -160 in FLAG 768 128 q0_ FLAG 768 160 q1_ FLAG 768 192 q2_ FLAG 768 224 q3_ FLAG 640 128 q0 FLAG 640 160 q1 FLAG 640 192 q2 FLAG 640 224 q3 FLAG 976 192 0 FLAG 848 16 VDD FLAG 976 304 VDD FLAG 1216 176 q123 FLAG 624 96 q123 FLAG 752 96 q123_ FLAG 144 96 0 FLAG 192 -128 VDD FLAG 176 0 res FLAG 240 336 0 FLAG 320 224 VEE FLAG -592 80 0 FLAG -736 80 0 FLAG -688 320 VEE FLAG -656 -144 q0 FLAG -512 -144 q1 FLAG -272 160 q01_vee FLAG 128 176 osc FLAG 0 -256 out_0 SYMBOL res -32 96 R270 WINDOW 0 32 56 VTop 0 WINDOW 3 0 56 VBottom 0 SYMATTR InstName R1 SYMATTR Value 21k SYMBOL cap -96 208 R0 SYMATTR InstName C1 SYMATTR Value 220p SYMBOL voltage 48 224 R0 SYMATTR InstName V1 SYMATTR Value {VDD} SYMBOL voltage -208 -160 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V2 SYMATTR Value PULSE(0 {VDD} 0 5u 5u 0 10u) SYMBOL dview5 672 240 R0 SYMATTR InstName U4 SYMATTR SpiceLine OFFSET={VDD+1} GAIN=0.5/{VDD} SYMATTR ModelFile CD4000.Lib SYMBOL res 832 16 R0 WINDOW 0 33 49 Left 0 WINDOW 3 30 89 Left 0 SYMATTR InstName R3 SYMATTR Value 20k SYMBOL cap 928 144 R270 WINDOW 0 16 10 VTop 0 WINDOW 3 41 56 VBottom 0 SYMATTR InstName C2 SYMATTR Value 1n SYMBOL res 128 -128 R0 SYMATTR InstName R4 SYMATTR Value 10k SYMBOL cap 128 16 R0 SYMATTR InstName Cres SYMATTR Value 500p SYMBOL voltage 240 224 R0 SYMATTR InstName V4 SYMATTR Value -5.2V SYMBOL pnp -576 96 M180 SYMATTR InstName Q2 SYMBOL pnp -720 96 M180 SYMATTR InstName Q1 SYMBOL res -672 -128 R0 SYMATTR InstName R5 SYMATTR Value 10k SYMBOL res -528 -128 R0 SYMATTR InstName R6 SYMATTR Value 10k SYMBOL res -672 192 R0 SYMATTR InstName R7 SYMATTR Value 10k SYMBOL res -528 192 R0 SYMATTR InstName R8 SYMATTR Value 10k SYMBOL res -320 192 R0 SYMATTR InstName R9 SYMATTR Value 2k SYMBOL CD4024B 464 -64 R0 SYMATTR InstName U3 SYMATTR SpiceLine VDD={VDD} SPEED=1.0 TRIPDT=5e-9 SYMBOL CD40106B 0 128 R0 WINDOW 0 -63 13 Left 0 WINDOW 3 -21 14 Left 0 SYMATTR InstName U1 SYMATTR SpiceLine VDD={VDD} SPEED=1.0 TRIPDT=5e-9 SYMBOL CD40106B -96 -208 R0 SYMATTR InstName U2 SYMATTR SpiceLine VDD={VDD} SPEED=1.0 TRIPDT=5e-9 SYMBOL CD4049B -96 -320 R0 WINDOW 0 -74 93 Left 0 SYMATTR InstName U8 SYMATTR SpiceLine VDD={VDD} SPEED=1.0 TRIPDT=5e-9 SYMBOL CD40106B 256 -48 R0 SYMATTR InstName U6 SYMATTR SpiceLine VDD={VDD} SPEED=1.0 TRIPDT=5e-9 SYMBOL CD4011B -416 96 R0 SYMATTR InstName U7 SYMATTR SpiceLine VDD=5.2 SPEED=1.0 TRIPDT=5e-9 SYMATTR SpiceModel 0 VEE SYMBOL CD14538B 1104 16 R0 SYMATTR InstName U5 SYMATTR SpiceLine VDD={VDD} SPEED=1.0 TRIPDT=1e-9 TEXT -704 -248 Left 0 !.tran 0 100u 5n TEXT -416 -240 Left 0 !.IC V(res)=0 TEXT -704 -272 Left 0 ;Simulation TEXT -408 -272 Left 0 ;Initialization TEXT -448 88 Left 0 ;Gate supplied with 0,-5.2V TEXT 392 -88 Left 0 ;Counter supplied with +5V and 0(GND) TEXT -728 -200 Left 0 ;74HC00 supplied with -5.2V TEXT -208 -296 Left 0 ;Show threshhold voltage TEXT -416 -200 Left 0 !.param VDD=15 TEXT 136 -264 Left 0 ;----> Take a look how the voltage VDD and its value is passed to all subcircuits. TEXT 192 -216 Left 0 !.inclide dview.lib