Version 4
SHEET 1 3084 692
WIRE 112 -624 80 -624
WIRE 480 -624 112 -624
WIRE 960 -624 480 -624
WIRE 80 -528 80 -624
WIRE 480 -496 480 -624
WIRE 960 -496 960 -624
WIRE 432 -416 288 -416
WIRE 912 -416 768 -416
WIRE 80 -336 80 -448
WIRE 288 -288 288 -416
WIRE 352 -288 288 -288
WIRE 480 -288 480 -400
WIRE 480 -288 432 -288
WIRE 512 -288 480 -288
WIRE 576 -288 512 -288
WIRE 768 -288 768 -416
WIRE 832 -288 768 -288
WIRE 960 -288 960 -400
WIRE 960 -288 912 -288
WIRE 992 -288 960 -288
WIRE 1056 -288 992 -288
WIRE 288 -240 288 -288
WIRE 480 -240 480 -288
WIRE 576 -240 576 -288
WIRE 768 -240 768 -288
WIRE 960 -240 960 -288
WIRE 1056 -240 1056 -288
WIRE 288 -112 288 -160
WIRE 480 -112 480 -176
WIRE 576 -112 576 -160
WIRE 768 -112 768 -160
WIRE 960 -112 960 -176
WIRE 1056 -112 1056 -160
FLAG 80 -336 0
FLAG 512 -288 out1
FLAG 112 -624 in
FLAG 288 -112 0
FLAG 576 -112 0
FLAG 480 -112 0
FLAG 992 -288 out2
FLAG 768 -112 0
FLAG 1056 -112 0
FLAG 960 -112 0
SYMBOL voltage 80 -544 R0
WINDOW 123 0 0 Left 0
WINDOW 39 41 66 Left 0
SYMATTR SpiceLine Rser=1
SYMATTR InstName V1
SYMATTR Value PWL(0 0 1 10)
SYMBOL cap 464 -240 R0
SYMATTR InstName C1
SYMATTR Value 1µ
SYMATTR SpiceLine Rser=.1
SYMBOL res 560 -256 R0
SYMATTR InstName R5
SYMATTR Value 100
SYMBOL res 448 -304 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R1
SYMATTR Value 100
SYMBOL res 272 -256 R0
SYMATTR InstName R2
SYMATTR Value 100
SYMBOL nmos 432 -496 R0
SYMATTR InstName M1
SYMATTR Value BSP129_L0
SYMATTR Prefix X
SYMBOL cap 944 -240 R0
SYMATTR InstName C2
SYMATTR Value 1µ
SYMATTR SpiceLine Rser=.1
SYMBOL res 1040 -256 R0
SYMATTR InstName R3
SYMATTR Value 100
SYMBOL res 928 -304 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R4
SYMATTR Value 100
SYMBOL res 752 -256 R0
SYMATTR InstName R6
SYMATTR Value 100
SYMBOL nmos 912 -496 R0
SYMATTR InstName M2
SYMATTR Value BSS-129
SYMATTR Prefix X
TEXT 72 -760 Left 0 !.tran 1
TEXT 1952 -776 Left 0 ;.include small_signal_L0.lib
TEXT 1224 -880 Left 0 ;.include small_signal.lib\n* Requires a change in the pin-order as done below.\n.SUBCKT BSS-129 1 2 3 \n-> \n.SUBCKT BSS-129 3 1 2
TEXT 1216 -696 Left 0 !* Infineon small_signal.lib\n*Depl-MOS*240V 150mA 20 Ohm*Add_in_Line\n* G S D\n*.SUBCKT BSS-129 1 2 3\n* Pin-order changed for "nmos" symbol from LTspice\n* D G S\n.SUBCKT BSS-129 3 1 2  \nLS 5 2 7N\nLD 83 3 5N\nRG 4 11 5\nRS 5 76 1M\nDBSS129 76 83 DREV\n.MODEL DREV D CJO=30P RS=20M TT=50N IS=30P BV=240\nMBSS129 90 11 76 76 MBUZ\n.MODEL MBUZ NMOS VTO=-1.30 KP=0.165  \nM2 11 90 8 8 MSW\n.MODEL MSW NMOS VTO=5 KP=25\nM3 90 11 8 8 MSW\nCOX 11 8 66P\nDGD 8 90 DCGD\n.MODEL DCGD D CJO=13.57P M=0.475 VJ=1.062\nCGS 76 11 25P\nRDR 90 83 2\nLG 4 1 7N\n.ENDS
TEXT 368 -832 Left 0 ;How to make the "nmos" from a model symbol to a subcircuit symbol:\nPlace a "nmos" symbol on the the schematic.\nCtrl-RightMouseClick on this instance(symbol)\n-> Change Prefix:MN to Prefix:X
TEXT 1952 -736 Left 0 !.SUBCKT BSP129_L0  drain  gate  source\n \nLg     gate  g1    3n\nLd     drain d1    1n\nLs     source s1   3n\nRs      s1    s2   0.027\n \nRg     g1    g2     10\nM1      d2    g2    s2    s2    DMOS    L=1u   W=1u\n.MODEL DMOS NMOS ( KP= 0.486  VTO=-0.85  THETA=0  VMAX=1.5e5  ETA=0  LEVEL=3)\nRd     d2    d1a    3.15 TC=11m\n.MODEL MVDR NMOS (KP=1.05 VTO=-1.4   LAMBDA=0.15)\nMr d1 d2a d1a d1a MVDR W=1u L=1u\nRx d2a d1a 1m\n \nDbd     s2    d2    Dbt\n.MODEL     Dbt    D(BV=290   M=0.5  CJO=66.42p  VJ=0.5V)\nDbody   s2   21    DBODY\n.MODEL DBODY  D(IS=13.5p  N=1.2  RS=246u  EG=1.12  TT=60n)\nRdiode  d1  21    370.37m TC=1m\n \n.MODEL   sw    NMOS(VTO=0  KP=10   LEVEL=1)\nMaux      g2   c    a    a   sw\nMaux2     b    d    g2    g2   sw\nEaux      c    a    d2    g2   1\nEaux2     d    g2   d2    g2   -1\nCox       b    d2   180.9p\n.MODEL     DGD    D(M=0.66   CJO=180.9p   VJ=0.5)\nRpar      b    d2   1Meg\nDgd       a    d2   DGD\nRpar2     d2   a    10Meg\nCgs     g2    s2    75.06p\n \n.ENDS  BSP129_L0
TEXT 368 -912 Left 0 ;BSS129\nBoth models are from Infineon.