Version 4
SHEET 1 1672 680
WIRE -224 64 -224 16
WIRE -224 176 -224 144
WIRE -208 352 -208 320
WIRE -208 464 -208 432
WIRE -112 320 -208 320
WIRE -64 16 -224 16
WIRE -64 48 -64 16
WIRE -64 192 -64 128
WIRE -64 240 -64 192
WIRE -64 352 -64 336
WIRE -16 192 -64 192
FLAG -224 176 0
FLAG -64 352 0
FLAG -208 464 0
FLAG -16 192 rds
IOPIN -16 192 Out
SYMBOL voltage -224 48 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL voltage -208 336 R0
SYMATTR InstName V2
SYMATTR Value 10
SYMBOL res -80 32 R0
SYMATTR InstName R1
SYMATTR Value 5
SYMBOL nmos -112 240 R0
SYMATTR InstName M1
SYMATTR Value Si4410DY_TEMP
TEXT -272 -128 Left 0 ;.dc V2 0 5 0.01
TEXT -272 -200 Left 0 !.step param Tj 0 100 1
TEXT -272 -168 Left 0 !.op
TEXT -272 -80 Left 0 !.options TEMP={Tj}\n.param TKR=1+(Tj-25)*0.01
TEXT 56 -144 Left 0 !.model Si4410DY_TEMP VDMOS(Rg=3 Rd={3m*TKR} Rs={3m*TKR} \n+ Vto=2.6 Kp=60 Cgdmax=1.9n Cgdmin=50p Cgs=3.1n Cjo=1n  \n+ Is=5.5p Rb=5.7m )
TEXT 56 192 Left 0 ;rds=V(rds)/1A
TEXT -272 -248 Left 0 ;Plot   V(rds)/1A   for a nice curve of  Rds_on(Temp)
TEXT 64 -192 Left 0 ;Datasheet:  http://www.vishay.com/docs/71726/71726.pdf
TEXT 56 -40 Left 0 ;*Model from LTspice "standard.mos"-file\n.model Si4410DY VDMOS(Rg=3 Rd=3m Rs=3m Vto=2.6 Kp=60 \n+ Cgdmax=1.9n Cgdmin=50p Cgs=3.1n Cjo=1n \n+ Is=5.5p Rb=5.7m )