Version 4 SHEET 1 1608 1700 WIRE 464 -272 416 -272 WIRE 672 -272 544 -272 WIRE 800 -272 672 -272 WIRE 848 -272 800 -272 WIRE 672 -208 672 -272 WIRE 672 -208 592 -208 WIRE 672 -192 672 -208 WIRE 592 -160 592 -208 WIRE 640 -160 592 -160 WIRE 800 -144 800 -272 WIRE 672 0 672 -128 WIRE 800 0 800 -80 WIRE -144 128 -336 128 WIRE 64 128 -64 128 WIRE 208 128 64 128 WIRE 256 128 208 128 WIRE 464 128 416 128 WIRE 672 128 544 128 WIRE 800 128 672 128 WIRE 832 128 800 128 WIRE 64 192 64 128 WIRE 64 192 -16 192 WIRE 672 192 672 128 WIRE 672 192 592 192 WIRE 64 208 64 192 WIRE 672 208 672 192 WIRE 208 224 208 128 WIRE -336 240 -336 128 WIRE -16 240 -16 192 WIRE 32 240 -16 240 WIRE 592 240 592 192 WIRE 640 240 592 240 WIRE 800 240 800 128 WIRE 672 368 672 272 WIRE 800 368 800 304 WIRE 800 368 672 368 WIRE -336 400 -336 320 WIRE 64 400 64 272 WIRE 208 400 208 288 WIRE 672 400 672 368 FLAG 64 400 0 FLAG -336 400 0 FLAG 256 128 2v5_a IOPIN 256 128 Out FLAG 672 0 0 FLAG 848 -272 2v5 IOPIN 848 -272 Out FLAG -336 128 v1 FLAG 416 -272 v1 FLAG 672 400 0 FLAG 832 128 2v5a IOPIN 832 128 Out FLAG 416 128 v1 FLAG 800 0 0 FLAG 208 400 0 SYMBOL res -160 144 R270 WINDOW 0 32 56 VTop 0 WINDOW 3 0 56 VBottom 0 SYMATTR InstName R1 SYMATTR Value 1k SYMBOL voltage -336 224 R0 WINDOW 123 24 132 Left 0 WINDOW 39 0 0 Left 0 SYMATTR Value2 AC 1 SYMATTR InstName V1 SYMATTR Value PULSE(12.5 0 10u 1n 1n 5m 10m) SYMBOL res 448 -256 R270 WINDOW 0 32 56 VTop 0 WINDOW 3 0 56 VBottom 0 SYMATTR InstName R2 SYMATTR Value 1k SYMBOL res 448 144 R270 WINDOW 0 32 56 VTop 0 WINDOW 3 0 56 VBottom 0 SYMATTR InstName R17 SYMATTR Value 1k SYMBOL cap 784 240 R0 SYMATTR InstName C5 SYMATTR Value 100p SYMBOL cap 784 -144 R0 SYMATTR InstName C6 SYMATTR Value 100p SYMBOL cap 192 224 R0 SYMATTR InstName C7 SYMATTR Value 100p SYMBOL Robertugo\\xref3 48 208 R0 SYMATTR InstName U1 SYMATTR SpiceModel TL431 SYMBOL Robertugo\\xref3 656 208 R0 SYMATTR InstName U3 SYMATTR SpiceModel TL431_A SYMBOL Robertugo\\xref3 656 -192 R0 SYMATTR InstName U2 SYMATTR SpiceModel TL431A TEXT -344 -208 Left 0 !.op TEXT -344 -176 Left 0 ;.dc V1 -10 12.5 0.01 TEXT -344 -112 Left 0 !.tran 0 10m 0 1u TEXT -344 -48 Left 0 ;.noise v(2v5a) v1 dec 100 10 10k TEXT -344 -144 Left 0 ;.step TEMP 0 100 5 TEXT -344 -80 Left 0 ;.ac dec 100 1k 10MEG TEXT 592 80 Left 0 ;Transistor level model from Helmut TEXT 592 -328 Left 0 ;Behaviour model from TI TEXT -48 80 Left 0 ;Behaviour model from analog@ieee.org TEXT -344 -400 Left 0 ;TL431 Test Schematic\nHelmut Sennewald 5/26/2004 TEXT -8 -248 Left 0 !.option noopiter