Version 4
SHEET 1 2692 4800
WIRE 464 -80 -288 -80
WIRE 592 -80 464 -80
WIRE 464 -48 464 -80
WIRE 592 16 592 0
WIRE 192 64 -160 64
WIRE 272 64 192 64
WIRE 288 64 272 64
WIRE 464 64 464 32
WIRE 464 64 368 64
WIRE 528 64 464 64
WIRE -160 128 -160 64
WIRE -112 128 -160 128
WIRE 272 128 272 64
WIRE 272 128 224 128
WIRE 592 144 592 112
WIRE 624 144 592 144
WIRE 656 144 624 144
WIRE 864 144 736 144
WIRE 992 144 864 144
WIRE 1136 144 992 144
WIRE -288 160 -288 -80
WIRE -192 160 -288 160
WIRE 992 176 992 144
WIRE -288 192 -288 160
WIRE 592 192 592 144
WIRE -192 208 -192 160
WIRE -112 208 -192 208
WIRE 336 208 224 208
WIRE 864 224 864 144
WIRE 336 240 336 208
WIRE 992 272 992 240
WIRE -384 288 -480 288
WIRE -288 288 -288 272
WIRE -288 288 -384 288
WIRE -224 288 -288 288
WIRE -112 288 -224 288
WIRE 288 288 224 288
WIRE 336 288 288 288
WIRE 432 288 400 288
WIRE 592 304 592 256
WIRE 432 320 432 288
WIRE -480 336 -480 288
WIRE -288 352 -288 288
WIRE -112 368 -160 368
WIRE 448 368 224 368
WIRE 992 368 992 336
WIRE 864 384 864 288
WIRE 992 384 992 368
WIRE 992 384 864 384
WIRE 992 400 992 384
WIRE 864 432 864 384
WIRE 864 432 768 432
WIRE 448 448 448 368
WIRE 496 448 448 448
WIRE 576 448 496 448
WIRE 704 448 576 448
WIRE -480 464 -480 416
WIRE -288 464 -288 416
WIRE -160 464 -160 368
WIRE 816 464 768 464
WIRE 992 496 992 480
WIRE 576 544 576 528
WIRE 816 544 816 464
WIRE 816 544 576 544
WIRE 576 560 576 544
WIRE 576 656 576 640
WIRE -224 720 -224 288
WIRE 736 720 736 480
WIRE 736 720 -224 720
FLAG -480 464 0
FLAG -288 464 0
FLAG 432 320 0
FLAG 592 304 0
FLAG 1136 144 Vo
FLAG 992 496 0
FLAG -160 464 0
FLAG 336 240 0
FLAG 192 64 base_drive
FLAG 624 144 collector
FLAG 496 448 feedback
FLAG 736 416 0
FLAG 288 288 clock
FLAG -384 288 Vin
FLAG 992 368 current_sense
FLAG 576 656 0
SYMBOL voltage -480 320 R0
WINDOW 123 0 0 Left 0
WINDOW 39 24 132 Left 0
SYMATTR SpiceLine Rser=0.001
SYMATTR InstName V1
SYMATTR Value 4.7
SYMBOL res -272 288 R180
WINDOW 0 -39 87 Left 0
WINDOW 3 -52 44 Left 0
SYMATTR InstName R1
SYMATTR Value 0.3
SYMBOL cap 336 304 R270
WINDOW 0 32 32 VTop 0
WINDOW 3 0 32 VBottom 0
SYMATTR InstName C2
SYMATTR Value 330p
SYMBOL schottky 608 256 R180
WINDOW 0 -34 67 Left 0
WINDOW 3 -111 -7 Left 0
SYMATTR InstName D1
SYMATTR Value MBRS340
SYMATTR Description Diode
SYMATTR Type diode
SYMBOL ind2 640 160 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 4 56 VBottom 0
SYMATTR InstName L1
SYMATTR Value 330µ
SYMATTR SpiceLine Ipk=1.1 Rser=0.349 Rpar=34880 Cpar=6.98p mfg="Wurth Elektronik" pn="744771233 WE-PD L"
SYMATTR Type ind
SYMBOL polcap -304 352 R0
WINDOW 39 24 86 Left 0
WINDOW 40 24 85 Left 0
SYMATTR SpiceLine Rser=0.1
SYMATTR InstName C1
SYMATTR Value 470µ
SYMBOL res 384 48 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R5
SYMATTR Value 100
SYMBOL res 448 -64 R0
SYMATTR InstName R6
SYMATTR Value 100
SYMBOL pnp 528 112 M180
SYMATTR InstName Q1
SYMATTR Value 2N3906
SYMBOL mc34063a 128 224 R0
SYMATTR InstName U1
SYMBOL res 976 384 R0
SYMATTR InstName R4
SYMATTR Value 5.1
SYMBOL res 560 432 R0
SYMATTR InstName R3
SYMATTR Value 2.40k
SYMBOL Opamps\\opamp2 736 512 R180
SYMATTR InstName U2
SYMATTR Value lm6142A/NS
SYMBOL res 576 -96 R0
SYMATTR InstName R9
SYMATTR Value .01
SYMBOL diode 976 272 R0
SYMATTR InstName D2
SYMATTR Value MURS120
SYMBOL diode 976 176 R0
SYMATTR InstName D3
SYMATTR Value MURS120
SYMBOL polcap 848 224 R0
WINDOW 3 24 64 Left 0
SYMATTR Value 1000µ
SYMATTR InstName C3
SYMATTR Description Capacitor
SYMATTR Type cap
SYMATTR SpiceLine V=4 Irms=5.3 Rser=0.01 MTBF=0 Lser=0 mfg="KEMET" pn="T510E108K004AS4115" type="Tantalum" ppPkg=1
SYMBOL res 560 544 R0
SYMATTR InstName R2
SYMATTR Value 10k
TEXT -472 -320 Left 0 !.tran 0 10m 9.5m 100n uic
TEXT -472 -248 Left 0 ;.options Gmin=1e-9 method=Gear
TEXT -472 -216 Left 0 ;.options plotwinsize=0
TEXT -472 -600 Left 0 ;MC34063A WIth An External PNP-Transistor\n===================================\n \nWatch the higher ripple current through inductor L1 if Iload=0.5A.\n \nThe external PNP transistor must be a special switching transistor.\n \nThe option "load" has to be used for the load current sink I1.
TEXT -472 -288 Left 0 ;.IC V(Vo)=1.68
TEXT -304 -288 Left 0 ;Preset Vo for shorter simulation time
TEXT 1160 944 Left 0 !* Models adapted to LTSPICE syntax by Helmut Sennewald.  03/14/2004\n* Don't remove this copyright notice.\n* The used models are property of ONSEMI and/or Intusoft(www.intusoft.com).\n* They are from ONsemi's webpage and also from the Intusoft's SPICE (ICAP/4 demo 8.3.10).\n* The links are www.onsemi.com and www.intusoft.com .\n \n* All SPICE command lines starting with a comment "*" have been changed \n* to be compatible with LTSPICE. \n \n\n* This model is part of a ICAP/4 demo circuit from the ONsemi webpage.\n* The ground pin must be always at net 0 in the schematic!\n.SUBCKT mc34063a 1 2 3 4 5 6 7 8\n*exempt 20030227 20395 -30736294\n*BY KEHINDE OMOLAYO 2-20-03\n*TERMINAL ID\n*SWITCH COLLECTOR=1 SWITCH EMITTER=2 TIMING CAPACITOR=3 GND=4\n*COMPARATOR INVERTING INPUT=5 VCC=6 IPK SENSE=7 DRIVER COLLECTOR=8\n.MODEL DMC34063 D (CJO=2P N=0.05)\n.MODEL QSWITCH NPN BF=75 CJC=2P IS=3E-9 RB=1 RC=0.45 RE=0\n+ VJC=.75 VJE=.75 VJS=.75\nE1 10 0 5 4 1\nR1 4 5 10MEG\nV1 20 0 PULSE 0 2\nE2 11 0 3 4 1\n*B1 13 0 V=1M/(ABS((27.475-195M*V(12))+(36.002+244M*V(12))*V(9)-(302.302+651M*V(12))*V(9)^2)+1F)\nB1 13 0 V=1M/(ABS((27.475-195M*V(12))+(36.002+244M*V(12))*V(9)-(302.302+651M*V(12))*V(9)**2)+1F)\nE3 12 0 6 4 1\nE4 9 0 6 7 1\nR2 6 7 10MEG\n*B2 14 0 V=1M*((-10.765-151M*V(12))+(45.344+864M*V(12))*V(9)-+(35.99+1.378*V(12))*V(9)^2+(8.341+839M*V(12))*V(9)^3)\nB2 14 0 V=1M*((-10.765-151M*V(12))+(45.344+864M*V(12))*V(9)-+(35.99+1.378*V(12))*V(9)**2+(8.341+839M*V(12))*V(9)**3)\n*B4 15 0 V=V(9)>0.32 ? V(14) : V(13)\nB4 15 0 V=IF( V(9)>0.32, V(14), V(13) )\nC1 19 0 10P\n*B5 16 0 V= V(20)<1 ? 2 :  V(24)>1 ? 2 : V(19)>1 ? 0 : 2\nB5 16 0 V= IF( V(20)<1, 2, IF(V(24)>1, 2, IF( V(19)>1, 0, 2 ) ) )\nR3 16 17 150\nC2 17 0 10P\n*B6 18 0 V=V(20)<1 ? 0 : V(24)>1 ? 0 : V(11)<(1.083-1.239*V(29)) ? 2 : V(17)>1 ? 0 : 2\nB6 18 0 V= IF( V(20)<1, 0, IF( V(24)>1, 0, IF( V(11)<(1.083-1.239*V(29)), 2, IF(V(17)>1, 0, 2 ) ) ) )\nR4 18 19 150\nD1 4 3 DMC34063\nD2 3 6 DMC34063\nC3 11 31 1N\n*B7 4 36 I=V(17)>1 ? -(224.4U+2.359U*V(12))*0.77 : V(15)*0.77\nB7 4 36 I=IF( V(17)>1, -(224.4U+2.359U*V(12))*0.77, V(15)*0.77 )\nC5 23 0 10P\n*B9 21 0 V= V(20)<1 ? 2 : V(17)>1 ? 2 : V(26)>1 ? 0 : 2\nB9 21 0 V= IF( V(20)<1, 2, IF( V(17)>1, 2, IF( V(26)>1, 0, 2 ) ) )\nR5 27 26 150\nC6 26 0 10P\n*B10 27 0 V=V(20)<1 ? 0 : V(17)>1 ? 0 : V(10)<1.25 ? 2 : V(23)>1 ? 0 : 2\nB10 27 0 V=IF( V(20)<1, 0, IF(V(17)>1, 0, IF(V(10)<1.25, 2, IF(V(23)>1, 0, 2 ) ) ) )\nR6 21 23 150\n*B12 33 0 V=V(11)>(1.148+184.6M*V(29)) ? 2 : 0\nB12 33 0 V=IF( V(11)>(1.148+184.6M*V(29)), 2, 0 )\nR13 33 24 10K\nC8 24 0 10P\nQ1 8 30 25 QSWITCH\nQ2 1 25 2 QSWITCH\nR15 25 2 100\nD5 2 30 DMC34063\nG1 2 30 26 23 5M\nR16 2 4 10MEG\nR23 31 28 1M\n*V6 28 0 \nV6 28 0 0\n*V7 36 3 \nV7 36 3 0\nB13 29 0 V=I(V6)/(I(V7)+866.8M*I(V6))\n.ENDS
TEXT 224 960 Left 0 !*//////////////////////////////////////////////////////////////////////\n* (C) National Semiconductor, Inc.\n* Models developed and under copyright by:\n* National Semiconductor, Inc.  \n \n*/////////////////////////////////////////////////////////////////////\n* Legal Notice: This material is intended for free software support.\n* The file may be copied, and distributed; however, reselling the \n*  material is illegal\n \n*////////////////////////////////////////////////////////////////////\n* For ordering or technical information on these models, contact:\n* National Semiconductor's Customer Response Center\n*                 7:00 A.M.--7:00 P.M.  U.S. Central Time\n*                                (800) 272-9959\n* For Applications support, contact the Internet address:\n*  amps-apps@galaxy.nsc.com\n \n*//////////////////////////////////////////////////////////\n*LM158 DUAL OPERATIONAL AMPLIFIER MACRO-MODEL\n*//////////////////////////////////////////////////////////\n*\n* connections:      non-inverting input\n*                   |   inverting input\n*                   |   |   positive power supply\n*                   |   |   |   negative power supply\n*                   |   |   |   |   output\n*                   |   |   |   |   |\n*                   |   |   |   |   |\n.SUBCKT LM158/NS    1   2  99  50  28\n*\n*Features:\n*Eliminates need for dual supplies\n*Large DC voltage gain =             100dB\n*High bandwidth =                     1MHz\n*Low input offset voltage =            2mV\n*Wide supply range =       +-1.5V to +-16V\n*\n*NOTE: Model is for single device only and simulated\n*      supply current is 1/2 of total device current.\n*      Output crossover distortion with dual supplies\n*      is not modeled.\n*\n****************INPUT STAGE**************\n*\nIOS 2 1 5N\n*^Input offset current\nR1 1 3 500K\nR2 3 2 500K\nI1 99 4 100U\nR3 5 50 517\nR4 6 50 517\nQ1 5 2 4 QX\nQ2 6 7 4 QX\n*Fp2=1.2 MHz\nC4 5 6 128.27P\n*\n***********COMMON MODE EFFECT***********\n*\nI2 99 50 75U\n*^Quiescent supply current\nEOS 7 1 POLY(1) 16 49 2E-3 1\n*Input offset voltage.^\nR8 99 49 60K\nR9 49 50 60K\n*\n*********OUTPUT VOLTAGE LIMITING********\nV2 99 8 1.63\nD1 9 8 DX\nD2 10 9 DX\nV3 10 50 .635\n*\n**************SECOND STAGE**************\n*\nEH 99 98 99 49 1\nG1 98 9 POLY(1) 5 6 0 9.8772E-4 0 .3459\n*Fp1=7.86 Hz\nR5 98 9 101.2433MEG\nC3 98 9 200P\n*\n***************POLE STAGE***************\n*\n*Fp=2 MHz\nG3 98 15 9 49 1E-6\nR12 98 15 1MEG\nC5 98 15 7.9577E-14\n*\n*********COMMON-MODE ZERO STAGE*********\n*\n*Fpcm=10 KHz\nG4 98 16 3 49 5.6234E-8               \nL2 98 17 15.9M\nR13 17 16 1K\n*\n**************OUTPUT STAGE**************\n*\nF6 50 99 POLY(1) V6 300U 1\nE1 99 23 99 15 1\nR16 24 23 17.5\nD5 26 24 DX\nV6 26 22 .63V\nR17 23 25 17.5\nD6 25 27 DX\nV7 22 27 .63V\nV5 22 21 0.27V\nD4 21 15 DX\nV4 20 22 0.27V\nD3 15 20 DX\nL3 22 28 500P\nRL3 22 28 100K\n*\n***************MODELS USED**************\n*\n.MODEL DX D(IS=1E-15)\n.MODEL QX PNP(BF=1.111E3)\n*\n.ENDS\n*$
TEXT -976 976 Left 0 !*//////////////////////////////////////////////////////////////////////\n* (C) National Semiconductor, Inc.\n* Models developed and under copyright by:\n* National Semiconductor, Inc.  \n \n*/////////////////////////////////////////////////////////////////////\n* Legal Notice: This material is intended for free software support.\n* The file may be copied, and distributed; however, reselling the \n*  material is illegal\n \n*////////////////////////////////////////////////////////////////////\n* For ordering or technical information on these models, contact:\n* National Semiconductor's Customer Response Center\n*                 7:00 A.M.--7:00 P.M.  U.S. Central Time\n*                                (800) 272-9959\n* For Applications support, contact the Internet address:\n*  Appshelp@galaxy.nsc.com\n \n*//////////////////////////////////////////////////////////\n*LM6142A OP-AMP MACRO-MODEL\n*//////////////////////////////////////////////////////////\n*\n* Connections:      Non-inverting input\n*                   |   Inverting input\n*                   |   |   Positive power supply\n*                   |   |   |   Negative power supply\n*                   |   |   |   |   Output\n*                   |   |   |   |   |\n*                   |   |   |   |   |\n.SUBCKT LM6142A/NS  1   2  99  50  28\n* CAUTION:  SET .OPTIONS GMIN=1E-16 TO CORRECTLY MODEL INPUT BIAS CURRENT.\n* Features:\n* Operates from single supply\n* Rail-to-rail output swing\n* Low offset voltage (max) = 1mV           \n* Input current = 170nA            \n* Slew rate = 27V/uS                       \n* Gain-bandwidth product = 17MHZ          \n* Low supply current = 600uA               \n*\n* NOTE: - This model is for a single device only and the simulated\n*         supply current is for one op amp only.\n*       - Noise is not modeled.\n*       - Asymmetrical gain is not modeled.\n*       - In the next revision, the following will be modelled\n*       - Voltage dependent (Vin or Vcc) slew rate\n*       - Gain/phase variation vs output Z\n*\nCI1 1  50 2P\nCI2 2  50 2P\n*\n* 53Hz pole capacitor\nC3  98 9  0.30N\n*\nC4  6  5  .493P\nC7  98 11 3.54F\n*\nDP1 1  99 DA\nDP2 50 1  DX\nDP3 2  99 DB\nDP4 50 2  DX\nD1  9  8  DX\nD2  10 9  DX\nD3  15 20 DX\nD4  21 15 DX\nD5  26 24 DX\nD6  25 27 DX\nD7  22 99 DX\nD8  50 22 DX\nD9  0  14 DX\nD10 12 0  DX\nD11 11 33 DX\nD12 34 11 DX\nD14 31 32 DX \nEH  97 98 99    49 1.0\nEN  0  96 0     50 1.0\n* Input offset voltage -|\nEOS 7  1  POLY(1) 16 49 1M 1\nEP  97 0  99    0  1.0\nE1  97 19 99    15 1.0\nE2  18 7  32    99 1E-3 \n* Sourcing load +Vs current\nF1  99 0  VA2   1\n* Sinking load -Vs current\nF2  0  50 VA3   1\nF3  13 0  VA1   1\nG1  98 9  5     6  0.1\nG2  98 11 9     49 1U\nG3  98 15 11    49 1U\n; DC CMRR\nG4  98 16 POLY(2) 1 49 2 49 0 3.54E-8 3.54E-8\nI1  99 4  23U\nI2  99 50 627U\n* Load dependent pole\nL1 22 28 300N\n*\n* CMR lead\nL2  16 17 7.95M\nM1  5  2  4     99 MX\nM2  6  18 4     99 MX\nR3  5  50 3.60K\nR4  6  50 3.60K\nR5  98 9  1E7\nR8  99 49 133.3K\nR9  49 50 133.3K\nR12 98 11 1E6\nR13 98 17 1K\n* -Rout\nR16 23 24 10\n* +Rout\nR17 23 25 18\n* +Isc slope control\nR18 20 29 12K\n* -Isc slope control\nR19 21 30 12K\nR21 98 15 1E6\nR22 22 28 900\nR23 32 97 100K    \nVA1 19 23 0V\nVA2 14 13 0V\nVA3 13 12 0V\nV2  97 8  0.625V\nV3  10 96 0.625V\nV4  29 22 -.186V\nV5  22 30 -.186V\nV6  26 22 0.63V\nV7  22 27 0.63V\nV8 31 50 4V\nV9 34 96 .346\nV10 97 33 .346\n*\n.MODEL  DA D    (IS=170E-9)\n.MODEL  DB D    (IS=173E-9)\n.MODEL  DX D    (IS=1.0E-14)\n.MODEL  MX PMOS (VTO=-.6 KP=4.2E-4 GAMMA=1.1)\n.ENDS\n*$
TEXT -456 -160 Left 0 !.lib opamp.sub