Version 4 SHEET 1 2020 1976 WIRE -2112 480 -2112 448 WIRE -2112 576 -2112 560 WIRE -2048 448 -2112 448 WIRE -1744 448 -1776 448 WIRE -1744 544 -1744 496 WIRE -1744 704 -1792 704 WIRE -1520 544 -1744 544 WIRE -1520 608 -1520 544 WIRE -1520 784 -1520 752 WIRE -1504 368 -1520 368 WIRE -1504 672 -1520 672 WIRE -1472 416 -1520 416 WIRE -1472 448 -1520 448 WIRE -1472 480 -1520 480 WIRE -1472 512 -1520 512 WIRE -1472 544 -1520 544 WIRE -1392 672 -1392 640 WIRE -1392 784 -1392 752 WIRE -1232 512 -1280 512 WIRE -1136 960 -1168 960 WIRE -1104 512 -1152 512 WIRE -1104 544 -1104 512 WIRE -1104 656 -1104 624 WIRE -992 512 -1104 512 WIRE -992 544 -992 512 WIRE -992 656 -1104 656 WIRE -992 656 -992 608 WIRE -992 688 -992 656 WIRE -992 784 -992 752 WIRE -992 960 -1056 960 WIRE -992 976 -992 960 WIRE -992 1072 -992 1056 WIRE -944 512 -992 512 FLAG -2112 576 0 FLAG -2048 448 fref FLAG -1392 784 0 FLAG -1392 640 vcc FLAG -992 784 0 FLAG -1280 512 pc2 FLAG -944 512 vco_in FLAG -1792 704 vco_in FLAG -1472 416 pc1 FLAG -1472 448 pc2 FLAG -1472 480 pcp FLAG -1472 512 v7 FLAG -1776 448 fref IOPIN -1776 448 In FLAG -1520 784 0 FLAG -1504 368 vcc FLAG -992 1072 0 FLAG -1168 960 v7 FLAG -1504 672 vdem FLAG -1472 544 fvco IOPIN -1472 544 Out SYMBOL voltage -2112 464 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V1 SYMATTR Value PULSE(0 5 0 50n 50n 2.5u 5u) SYMBOL voltage -1392 656 R0 SYMATTR InstName V3 SYMATTR Value 5 SYMBOL res -1248 528 R270 WINDOW 0 32 56 VTop 0 WINDOW 3 0 56 VBottom 0 SYMATTR InstName R3 SYMATTR Value 100k SYMBOL cap -1008 688 R0 SYMATTR InstName C2 SYMATTR Value 10n SYMBOL res -1120 528 R0 SYMATTR InstName R4 SYMATTR Value 21k SYMBOL cap -1008 544 R0 SYMATTR InstName C3 SYMATTR Value 2.2n SYMBOL res -1040 976 M270 WINDOW 0 32 56 VTop 0 WINDOW 3 0 56 VBottom 0 SYMATTR InstName R1 SYMATTR Value 1.8k SYMBOL voltage -992 960 R0 SYMATTR InstName V2 SYMATTR Value 9 SYMBOL cd4046b_h -1632 320 R0 WINDOW 39 -328 519 Left 0 SYMATTR InstName X1 SYMATTR SpiceLine VCC1=5 FMIN=0.1e6 FMAX=0.3e6 SPEED=1.0 TDEL1=20n TRIPDT1=8n TEXT -2128 368 Left 0 !.tran 0 2500u 0 500n TEXT -2128 400 Left 0 !.options plotwinsize=0 TEXT -1968 896 Left 0 ;The visible parameters are from the CD4046 model. \nThey can be made invisible in the symbol's dialog.\nTherefore RightMouseClick on the symbol and uncheck it.\n \nFMAX = max. VCO frequency\nFMIN = min. VCO frequency\nTDEL1=20n internal gate delay; don't change it\nTRIPDT1=8n change it to 8n for Fvco>=2.5e5, 8n*2.5e5/Fvco_max\nExample: Fvco_max=1kHz -> TRIPDT=2u TEXT -2128 -112 Left 0 ;The CD4046 PLL\nHelmut Sennewald, V0.8\nPlease refer to TI, Fairchild, Onsemi and Philips datasheets.\nhttp://focus.ti.com/lit/ds/symlink/cd4046b.pdf\nhttp://www.fairchildsemi.com/ds/CD/CD4046BC.pdf\nhttp://www.onsemi.com/pub/Collateral/MC14046B-D.PDF\nhttp://www.semiconductors.philips.com/acrobat_download/datasheets/HEF4046B_CNV_3.pdf\nCheck carefully the datasheets, because there may be differences.\n \nThis is a hierarchical design. You can RightMouseClick \non the instance(symbol) and probe down the hierarchy. \nTo probe signals down the hierarchy requires\nControl Panel -> Save Defaults \n...Save Subcircuit Voltages\n...Save Subcircuit Currents TEXT -1296 376 Left 0 ;Loop Filter\nReference designators according to \nPLL-design program pll.zip from Philips. TEXT -1264 928 Left 0 ;Zener diode RECTANGLE Normal -1168 864 -1968 816