Version 4
SHEET 1 2020 1976
WIRE -1504 368 -1520 368
WIRE -1472 416 -1520 416
WIRE -1744 448 -1776 448
WIRE -1472 448 -1520 448
WIRE -1472 480 -1520 480
WIRE -1472 512 -1520 512
WIRE -1232 512 -1280 512
WIRE -1104 512 -1152 512
WIRE -992 512 -1104 512
WIRE -944 512 -992 512
WIRE -1744 544 -1744 496
WIRE -1520 544 -1744 544
WIRE -1472 544 -1520 544
WIRE -1104 544 -1104 512
WIRE -992 544 -992 512
WIRE -1744 576 -1760 576
WIRE -1744 608 -1760 608
WIRE -1520 608 -1520 544
WIRE -2112 640 -2176 640
WIRE -1744 640 -1760 640
WIRE -1104 656 -1104 624
WIRE -992 656 -992 608
WIRE -992 656 -1104 656
WIRE -2176 672 -2176 640
WIRE -1744 672 -1760 672
WIRE -1472 672 -1520 672
WIRE -1392 672 -1392 640
WIRE -992 688 -992 656
WIRE -1744 704 -1776 704
WIRE -1744 736 -1760 736
WIRE -2176 768 -2176 752
WIRE -1520 784 -1520 752
WIRE -1392 784 -1392 752
WIRE -992 784 -992 752
FLAG -2176 768 0
FLAG -2112 640 fref
FLAG -1392 784 0
FLAG -1392 640 vcc
FLAG -992 784 0
FLAG -1280 512 pc2
FLAG -944 512 vco_in
FLAG -1776 704 vco_in
FLAG -1472 416 pc1
FLAG -1472 448 pc2
FLAG -1472 480 pcp
FLAG -1472 512 pc3
FLAG -1776 448 fref
IOPIN -1776 448 In
FLAG -1520 784 0
FLAG -1504 368 vcc
FLAG -1472 544 fvco
IOPIN -1472 544 Out
SYMBOL voltage -2176 656 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value PULSE(0 5 0 5n 5n .5u 1u)
SYMBOL voltage -1392 656 R0
SYMATTR InstName V3
SYMATTR Value 5
SYMBOL res -1248 528 R270
WINDOW 0 16 -6 VTop 0
WINDOW 3 44 113 VBottom 0
SYMATTR InstName R3
SYMATTR Value 21k
SYMBOL cap -1008 688 R0
SYMATTR InstName C2
SYMATTR Value 10n
SYMBOL res -1120 528 R0
SYMATTR InstName R4
SYMATTR Value 4.7k
SYMBOL cap -1008 544 R0
SYMATTR InstName C3
SYMATTR Value 2.2n
SYMBOL 74HC4046 -1632 320 R0
SYMATTR InstName X2
TEXT -2192 560 Left 0 !.tran 0 500u 0 100n
TEXT -2192 592 Left 0 !.options plotwinsize=0
TEXT -2232 88 Left 0 ;The (MC)74HC4046 PLL\nHelmut Sennewald, V0.9\nPlease refer to the Onsemi and Philips datasheets.\nhttp://www.onsemi.com/pub/Collateral/MC74HC4046A-D.PDF\nhttp://www.semiconductors.philips.com/acrobat/datasheets/74HC_HCT4046A_CNV_2.pdf\nThe datasheets from Fairchild and National Semiconductor show a different phase detector-2. \n \nThis is a hierarchical design. You can RightMouseClick \non the instance(symbol) and probe down the hierarchy. \nTo probe signals down the hierarchy requires\nControl Panel -> Save Defaults \n...Save Subcircuit Voltages\n...Save Subcircuit Currents
TEXT -1328 408 Left 0 ;Loop Filter\nReference designators according to \nPLL-design program PLL from Philips.
TEXT -1440 264 Left 0 ;FMAX = max. VCO frequency\nFMIN = min. VCO frequency\nTDEL1=5n  internal gate delay; don't change it\nTRIPDT1=3n  change it to 2n for Fvco>=1e6, 2n*1e6/Fvco_max\nExample: Fvco_max=1kHz -> TRIPDT=2u