Version 4
SHEET 1 956 804
WIRE 144 -16 128 -16
WIRE 144 16 128 16
WIRE 144 48 128 48
WIRE 128 128 96 128
WIRE 336 128 256 128
WIRE 288 160 192 160
WIRE 416 160 288 160
WIRE -384 192 -560 192
WIRE 96 192 -256 192
WIRE 112 192 96 192
WIRE 272 192 256 192
WIRE 96 240 -256 240
WIRE 112 240 96 240
WIRE 272 240 256 240
WIRE -560 272 -560 192
WIRE -384 288 -464 288
WIRE 96 288 -256 288
WIRE 112 288 96 288
WIRE 272 288 256 288
WIRE -560 320 -560 272
WIRE -464 320 -464 288
WIRE -560 416 -560 400
WIRE -464 416 -464 400
WIRE -320 448 -320 320
WIRE 416 448 416 160
WIRE 416 448 -320 448
FLAG 288 160 Gamma
FLAG 272 288 RPS
IOPIN 272 288 Out
FLAG 128 -16 H1
IOPIN 128 -16 Out
FLAG 128 16 H2
IOPIN 128 16 Out
FLAG 128 48 H3
IOPIN 128 48 Out
FLAG -464 416 0
FLAG 336 128 Tout
IOPIN 336 128 Out
FLAG -560 272 VHV
FLAG -560 416 0
FLAG 96 192 A
FLAG 96 240 B
FLAG 96 288 C
FLAG 96 128 Tin
IOPIN 96 128 In
FLAG 272 192 Jload
IOPIN 272 192 In
FLAG 272 240 Dload
IOPIN 272 240 In
SYMBOL voltage -560 304 R0
SYMATTR InstName V1
SYMATTR Value 24
SYMBOL voltage -464 304 R0
SYMATTR InstName V2
SYMATTR Value {Dir}
SYMBOL 3fcsin -304 240 R0
SYMATTR InstName U1
SYMBOL BLDC 192 240 R0
SYMATTR SpiceLine Ph=0
SYMATTR InstName U2
TEXT -560 -64 Left 0 ;Brushless DC Motor Model Test with Sinusoidal Analog Drive\n(c) Peter KAPAS Nov. 24. 2006 - Sept. 07.2009\npkapas@sbcglobal.net
TEXT -304 416 Left 0 !.tran 50m
TEXT -304 384 Left 0 !.param Dir=1
TEXT 96 384 Left 0 ;Dir=+1 - Positive  Rotation
TEXT 96 416 Left 0 ;Dir= -1 - Negative Rotation
TEXT 120 320 Left 0 !.param Npp=4
TEXT -560 40 Left 0 ;For optimal Performance end Efficiency of ANALsin \nDrive the right Set-Up of [Dev] and [Offs] Parameters\nare Required. (see SpiceLine2 in ANALsin)