Version 4
SHEET 1 880 680
WIRE -272 208 -272 128
WIRE -272 352 -272 288
WIRE -144 240 -144 192
WIRE -144 352 -272 352
WIRE -144 352 -144 320
WIRE -128 192 -144 192
WIRE -48 256 -48 240
WIRE -48 352 -144 352
WIRE -48 352 -48 336
WIRE -32 240 -48 240
WIRE 0 240 -32 240
WIRE 0 288 0 240
WIRE 16 192 -128 192
WIRE 16 288 0 288
WIRE 112 128 -272 128
WIRE 112 144 112 128
WIRE 112 352 -48 352
WIRE 112 352 112 336
WIRE 112 368 112 352
WIRE 256 192 208 192
WIRE 256 192 256 144
WIRE 256 224 256 192
WIRE 256 256 256 224
WIRE 256 288 208 288
WIRE 288 128 112 128
WIRE 288 160 288 128
WIRE 320 144 256 144
WIRE 320 144 320 128
WIRE 320 160 288 160
WIRE 320 224 256 224
WIRE 320 256 256 256
WIRE 560 256 544 256
WIRE 560 288 544 288
WIRE 560 320 544 320
WIRE 560 352 544 352
WIRE 560 384 544 384
WIRE 560 416 544 416
WIRE 560 448 544 448
WIRE 560 480 544 480
FLAG 112 368 0
FLAG -128 192 Sigin
FLAG -32 240 Comp
SYMBOL x46DetFase 112 240 R0
SYMATTR InstName X1
SYMBOL voltage -272 192 R0
WINDOW 3 -29 58 Left 0
SYMATTR Value {Vdd}
SYMATTR InstName Vcc
SYMBOL voltage -144 224 R0
WINDOW 0 -23 60 Left 0
WINDOW 3 -55 -21 Invisible 0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName Vsig
SYMATTR Value SINE({Vdd/2} {Vdd/2} 2e6 0 0 {fase})
SYMBOL voltage -48 240 M0
WINDOW 0 -25 60 Left 0
WINDOW 3 -93 -7 Invisible 0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName Vref
SYMATTR Value SINE({Vdd/2} {Vdd/2} 2e6 0 0)
SYMBOL Dig_Add\\TTL\\HCT\\74hct164 432 48 R0
SYMATTR InstName U1
TEXT -272 376 Left 0 !.Param Vdd 5\n.step param fase 0 315 45
TEXT -264 104 Left 0 !.tran 0 10u 0