* AD645A SPICE Macro-model 4/92, Rev. B * JCB / PMI * * Revision History: * Rev. B: Converted model to include noise analysis. * * This version of the AD645 model simulates the worst case * parameters of the 'A' grade. The worst case parameters * used correspond to those in the data sheet. * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD645A 1 2 99 50 30 * * INPUT STAGE & POLE AT 40 MHZ * R3 5 50 1.049 R4 6 50 1.049 CIN 1 2 1E-12 C2 5 6 1.90E-9 I1 99 4 100E-3 IOS 1 2 0.5E-12 EOS 65 1 POLY(1) 17 24 500E-6 1 J1 5 2 4 JX J2 6 7 4 JX EN 7 65 43 0 1 GN1 0 1 47 0 1E-6 GN2 0 2 61 0 1E-6 GB1 2 50 POLY(3) 4,2 5,2 50,2 0 1E-12 1E-12 1E-12 GB2 7 50 POLY(3) 4,7 6,7 50,7 0 1E-12 1E-12 1E-12 * EREF 98 0 24 0 1 * * VOLTAGE NOISE GENERATOR * VN1 41 0 DC 2 RS1 41 42 11.8E3 RS2 42 43 1.2E9 CS1 42 43 79.8E-11 RS3 43 44 1.2E9 CS2 43 44 79.8E-11 RS4 44 45 11.8E3 VN2 0 45 DC 2 * * CURRENT NOISE GENERATOR * VN3 46 0 DC 2 RN5 46 47 144 RN6 47 48 144 VN4 0 48 DC 2 * * CURRENT NOISE GENERATOR * VN5 60 0 DC 2 RN7 60 61 144 RN8 61 62 144 VN6 0 62 DC 2 * * SECOND STAGE & POLE AT 3 HZ * R5 9 98 5.26E5 C3 9 98 1.00E-7 G1 98 9 5 6 9.53E-1 V2 99 8 4.7 V3 10 50 4.7 D1 9 8 DX D2 10 9 DX * * NEGATIVE ZERO AT 15 MHZ * R6 11 12 1E6 C4 11 12 -10.6E-15 R7 12 98 1 E2 11 98 9 24 1E6 * * POLE AT 40 MHZ * R8 13 98 1E3 C5 13 98 3.98E-12 G2 98 13 12 24 1E-3 * * POLE AT 40 MHZ * R9 14 98 1E3 C6 14 98 3.98E-12 G3 98 14 13 24 1E-3 * * POLE AT 40 MHZ * R10 15 98 1E3 C7 15 98 3.98E-12 G4 98 15 14 24 1E-3 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 600 HZ * R11 16 17 1E6 C8 16 17 2.65E-10 R12 17 98 1 E3 16 98 POLY(2) 1 98 2 98 0 15.8 15.8 * * POLE AT 40 MHZ * R13 18 98 1E3 C9 18 98 3.98E-12 G5 98 18 15 24 1E-3 * * OUTPUT STAGE * R14 24 99 2000E3 R15 24 50 2000E3 ISY 99 50 -96.5E-3 R16 29 99 360 R17 29 50 360 L1 29 30 1E-8 G6 27 50 18 29 2.78E-3 G7 28 50 29 18 2.78E-3 G8 29 99 99 18 2.78E-3 G9 50 29 18 50 2.78E-3 V4 25 29 2.0 V5 29 26 2.0 D3 18 25 DX D4 26 18 DX D5 99 27 DX D6 99 28 DX D7 50 27 DY D8 50 28 DY F1 29 0 V4 1 F2 0 29 V5 1 * * MODELS USED * .MODEL JX PJF(BETA=4.54 VTO=-2.000 IS=2.5E-12 RD=0.1 + RS=0.1 CGD=1E-15 CGS=1E-15) .MODEL DX D(IS=1E-15 RS=10 CJO=1E-15) .MODEL DY D(IS=1E-15 BV=50 RS=10 CJO=1E-15) .MODEL DEN D(IS=1E-12 RS=7409.6 KF=2.051E-15 AF=1) .MODEL DIN D(IS=1E-12 RS=41.5 KF=0 AF=1) .ENDS AD645A * AD645B SPICE Macro-model 4/92, Rev. B * JCB / PMI * * Revision History: * Rev. B: Converted model to include noise analysis. * * This version of the AD645 model simulates the worst case * parameters of the 'B' grade. The worst case parameters * used correspond to those in the data sheet. * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD645B 1 2 99 50 30 * * INPUT STAGE & POLE AT 40 MHZ * R3 5 50 1.049 R4 6 50 1.049 CIN 1 2 1E-12 C2 5 6 1.90E-9 I1 99 4 100E-3 IOS 1 2 0.25E-12 EOS 65 1 POLY(1) 17 24 250E-6 1 J1 5 2 4 JX J2 6 7 4 JX EN 7 65 43 0 1 GN1 0 1 47 0 1E-6 GN2 0 2 61 0 1E-6 GB1 2 50 POLY(3) 4,2 5,2 50,2 0 1E-12 1E-12 1E-12 GB2 7 50 POLY(3) 4,7 6,7 50,7 0 1E-12 1E-12 1E-12 * EREF 98 0 24 0 1 * * VOLTAGE NOISE GENERATOR * VN1 41 0 DC 2 RS1 41 42 11.8E3 RS2 42 43 1.2E9 CS1 42 43 100E-11 RS3 43 44 1.2E9 CS2 43 44 100E-11 RS4 44 45 11.8E3 VN2 0 45 DC 2 * * CURRENT NOISE GENERATOR * VN3 46 0 DC 2 RN5 46 47 75.4 RN6 47 48 75.4 VN4 0 48 DC 2 * * CURRENT NOISE GENERATOR * VN5 60 0 DC 2 RN7 60 61 75.4 RN8 61 62 75.4 VN6 0 62 DC 2 * * SECOND STAGE & POLE AT 1.5 HZ * R5 9 98 1.05E6 C3 9 98 1.00E-7 G1 98 9 5 6 9.53E-1 V2 99 8 4.7 V3 10 50 4.7 D1 9 8 DX D2 10 9 DX * * NEGATIVE ZERO AT 15 MHZ * R6 11 12 1E6 C4 11 12 -10.6E-15 R7 12 98 1 E2 11 98 9 24 1E6 * * POLE AT 40 MHZ * R8 13 98 1E3 C5 13 98 3.98E-12 G2 98 13 12 24 1E-3 * * POLE AT 40 MHZ * R9 14 98 1E3 C6 14 98 3.98E-12 G3 98 14 13 24 1E-3 * * POLE AT 40 MHZ * R10 15 98 1E3 C7 15 98 3.98E-12 G4 98 15 14 24 1E-3 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 380 HZ * R11 16 17 1E6 C8 16 17 4.198E-10 R12 17 98 1 E3 16 98 POLY(2) 1 98 2 98 0 10 10 * * POLE AT 40 MHZ * R13 18 98 1E3 C9 18 98 3.98E-12 G5 98 18 15 24 1E-3 * * OUTPUT STAGE * R14 24 99 2000E3 R15 24 50 2000E3 ISY 99 50 -96.5E-3 R16 29 99 360 R17 29 50 360 L1 29 30 1E-8 G6 27 50 18 29 2.78E-3 G7 28 50 29 18 2.78E-3 G8 29 99 99 18 2.78E-3 G9 50 29 18 50 2.78E-3 V4 25 29 2.0 V5 29 26 2.0 D3 18 25 DX D4 26 18 DX D5 99 27 DX D6 99 28 DX D7 50 27 DY D8 50 28 DY F1 29 0 V4 1 F2 0 29 V5 1 * * MODELS USED * .MODEL JX PJF(BETA=4.54 VTO=-2.000 IS=1.5E-12 RD=0.1 + RS=0.1 CGD=1E-15 CGS=1E-15) .MODEL DX D(IS=1E-15 RS=10 CJO=1E-15) .MODEL DY D(IS=1E-15 BV=50 RS=10 CJO=1E-15) .MODEL DEN D(IS=1E-12 RS=7409.6 KF=2.051E-15 AF=1) .MODEL DIN D(IS=1E-12 RS=41.5 KF=0 AF=1) .ENDS AD645B * AD645J SPICE Macro-model 4/92, Rev. B * JCB / PMI * * Revision History: * Rev. B: Converted model to include noise analysis. * * This version of the AD645 model simulates the worst case * parameters of the 'J' grade. The worst case parameters * used correspond to those in the data sheet. * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD645J 1 2 99 50 30 * * INPUT STAGE & POLE AT 40 MHZ * R3 5 50 1.049 R4 6 50 1.049 CIN 1 2 1E-12 C2 5 6 1.90E-9 I1 99 4 100E-3 IOS 1 2 0.5E-12 EOS 65 1 POLY(1) 17 24 500E-6 1 J1 5 2 4 JX J2 6 7 4 JX EN 7 65 43 0 1 GN1 0 1 47 0 1E-6 GN2 0 2 61 0 1E-6 GB1 2 50 POLY(3) 4,2 5,2 50,2 0 1E-12 1E-12 1E-12 GB2 7 50 POLY(3) 4,7 6,7 50,7 0 1E-12 1E-12 1E-12 * EREF 98 0 24 0 1 * * VOLTAGE NOISE GENERATOR * VN1 41 0 DC 2 RS1 41 42 11.8E3 RS2 42 43 1.2E9 CS1 42 43 79.8E-11 RS3 43 44 1.2E9 CS2 43 44 79.8E-11 RS4 44 45 11.8E3 VN2 0 45 DC 2 * * CURRENT NOISE GENERATOR * VN3 46 0 DC 2 RN5 46 47 144 RN6 47 48 144 VN4 0 48 DC 2 * * CURRENT NOISE GENERATOR * VN5 60 0 DC 2 RN7 60 61 144 RN8 61 62 144 VN6 0 62 DC 2 * * SECOND STAGE & POLE AT 3 HZ * R5 9 98 5.26E5 C3 9 98 1.00E-7 G1 98 9 5 6 9.53E-1 V2 99 8 4.7 V3 10 50 4.7 D1 9 8 DX D2 10 9 DX * * NEGATIVE ZERO AT 15 MHZ * R6 11 12 1E6 C4 11 12 -10.6E-15 R7 12 98 1 E2 11 98 9 24 1E6 * * POLE AT 40 MHZ * R8 13 98 1E3 C5 13 98 3.98E-12 G2 98 13 12 24 1E-3 * * POLE AT 40 MHZ * R9 14 98 1E3 C6 14 98 3.98E-12 G3 98 14 13 24 1E-3 * * POLE AT 40 MHZ * R10 15 98 1E3 C7 15 98 3.98E-12 G4 98 15 14 24 1E-3 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 600 HZ * R11 16 17 1E6 C8 16 17 2.65E-10 R12 17 98 1 E3 16 98 POLY(2) 1 98 2 98 0 15.8 15.8 * * POLE AT 40 MHZ * R13 18 98 1E3 C9 18 98 3.98E-12 G5 98 18 15 24 1E-3 * * OUTPUT STAGE * R14 24 99 2000E3 R15 24 50 2000E3 ISY 99 50 -96.5E-3 R16 29 99 360 R17 29 50 360 L1 29 30 1E-8 G6 27 50 18 29 2.78E-3 G7 28 50 29 18 2.78E-3 G8 29 99 99 18 2.78E-3 G9 50 29 18 50 2.78E-3 V4 25 29 2.0 V5 29 26 2.0 D3 18 25 DX D4 26 18 DX D5 99 27 DX D6 99 28 DX D7 50 27 DY D8 50 28 DY F1 29 0 V4 1 F2 0 29 V5 1 * * MODELS USED * .MODEL JX PJF(BETA=4.54 VTO=-2.000 IS=1.5E-12 RD=0.1 + RS=0.1 CGD=1E-15 CGS=1E-15) .MODEL DX D(IS=1E-15 RS=10 CJO=1E-15) .MODEL DY D(IS=1E-15 BV=50 RS=10 CJO=1E-15) .MODEL DEN D(IS=1E-12 RS=7409.6 KF=2.051E-15 AF=1) .MODEL DIN D(IS=1E-12 RS=41.5 KF=0 AF=1) .ENDS AD645J * AD645K SPICE Macro-model 4/92, Rev. B * JCB / PMI * * Revision History: * Rev. B: Converted model to include noise analysis. * * This version of the AD645 model simulates the worst case * parameters of the 'K' grade. The worst case parameters * used correspond to those in the data sheet. * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD645K 1 2 99 50 30 * * INPUT STAGE & POLE AT 40 MHZ * R3 5 50 1.049 R4 6 50 1.049 CIN 1 2 1E-12 C2 5 6 1.90E-9 I1 99 4 100E-3 IOS 1 2 0.25E-12 EOS 65 1 POLY(1) 17 24 250E-6 1 J1 5 2 4 JX J2 6 7 4 JX EN 7 65 43 0 1 GN1 0 1 47 0 1E-6 GN2 0 2 61 0 1E-6 GB1 2 50 POLY(3) 4,2 5,2 50,2 0 1E-12 1E-12 1E-12 GB2 7 50 POLY(3) 4,7 6,7 50,7 0 1E-12 1E-12 1E-12 * EREF 98 0 24 0 1 * * VOLTAGE NOISE GENERATOR * VN1 41 0 DC 2 RS1 41 42 11.8E3 RS2 42 43 1.2E9 CS1 42 43 100E-11 RS3 43 44 1.2E9 CS2 43 44 100E-11 RS4 44 45 11.8E3 VN2 0 45 DC 2 * * CURRENT NOISE GENERATOR * VN3 46 0 DC 2 RN5 46 47 75.4 RN6 47 48 75.4 VN4 0 48 DC 2 * * CURRENT NOISE GENERATOR * VN5 60 0 DC 2 RN7 60 61 75.4 RN8 61 62 75.4 VN6 0 62 DC 2 * * SECOND STAGE & POLE AT 1.5 HZ * R5 9 98 1.05E6 C3 9 98 1.00E-7 G1 98 9 5 6 9.53E-1 V2 99 8 4.7 V3 10 50 4.7 D1 9 8 DX D2 10 9 DX * * NEGATIVE ZERO AT 15 MHZ * R6 11 12 1E6 C4 11 12 -10.6E-15 R7 12 98 1 E2 11 98 9 24 1E6 * * POLE AT 40 MHZ * R8 13 98 1E3 C5 13 98 3.98E-12 G2 98 13 12 24 1E-3 * * POLE AT 40 MHZ * R9 14 98 1E3 C6 14 98 3.98E-12 G3 98 14 13 24 1E-3 * * POLE AT 40 MHZ * R10 15 98 1E3 C7 15 98 3.98E-12 G4 98 15 14 24 1E-3 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 380 HZ * R11 16 17 1E6 C8 16 17 4.198E-10 R12 17 98 1 E3 16 98 POLY(2) 1 98 2 98 0 10 10 * * POLE AT 40 MHZ * R13 18 98 1E3 C9 18 98 3.98E-12 G5 98 18 15 24 1E-3 * * OUTPUT STAGE * R14 24 99 2000E3 R15 24 50 2000E3 ISY 99 50 -96.5E-3 R16 29 99 360 R17 29 50 360 L1 29 30 1E-8 G6 27 50 18 29 2.78E-3 G7 28 50 29 18 2.78E-3 G8 29 99 99 18 2.78E-3 G9 50 29 18 50 2.78E-3 V4 25 29 2.0 V5 29 26 2.0 D3 18 25 DX D4 26 18 DX D5 99 27 DX D6 99 28 DX D7 50 27 DY D8 50 28 DY F1 29 0 V4 1 F2 0 29 V5 1 * * MODELS USED * .MODEL JX PJF(BETA=4.54 VTO=-2.000 IS=0.75E-12 RD=0.1 + RS=0.1 CGD=1E-15 CGS=1E-15) .MODEL DX D(IS=1E-15 RS=10 CJO=1E-15) .MODEL DY D(IS=1E-15 BV=50 RS=10 CJO=1E-15) .MODEL DEN D(IS=1E-12 RS=7409.6 KF=2.051E-15 AF=1) .MODEL DIN D(IS=1E-12 RS=41.5 KF=0 AF=1) .ENDS AD645K * AD645S SPICE Macro-model 4/92, Rev. B * JCB / PMI * * Revision History: * Rev. B: Converted model to include noise analysis. * * This version of the AD645 model simulates the worst case * parameters of the 'S' grade. The worst case parameters * used correspond to those in the data sheet. * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD645S 1 2 99 50 30 * * INPUT STAGE & POLE AT 40 MHZ * R3 5 50 1.049 R4 6 50 1.049 CIN 1 2 1E-12 C2 5 6 1.90E-9 I1 99 4 100E-3 IOS 1 2 0.5E-12 EOS 65 1 POLY(1) 17 24 500E-6 1 J1 5 2 4 JX J2 6 7 4 JX EN 7 65 43 0 1 GN1 0 1 47 0 1E-6 GN2 0 2 61 0 1E-6 GB1 2 50 POLY(3) 4,2 5,2 50,2 0 1E-12 1E-12 1E-12 GB2 7 50 POLY(3) 4,7 6,7 50,7 0 1E-12 1E-12 1E-12 * EREF 98 0 24 0 1 * * VOLTAGE NOISE GENERATOR * VN1 41 0 DC 2 RS1 41 42 11.8E3 RS2 42 43 1.2E9 CS1 42 43 79.8E-11 RS3 43 44 1.2E9 CS2 43 44 79.8E-11 RS4 44 45 11.8E3 VN2 0 45 DC 2 * * CURRENT NOISE GENERATOR * VN3 46 0 DC 2 RN5 46 47 144 RN6 47 48 144 VN4 0 48 DC 2 * * CURRENT NOISE GENERATOR * VN5 60 0 DC 2 RN7 60 61 144 RN8 61 62 144 VN6 0 62 DC 2 * * SECOND STAGE & POLE AT 3 HZ * R5 9 98 5.26E5 C3 9 98 1.00E-7 G1 98 9 5 6 9.53E-1 V2 99 8 4.7 V3 10 50 4.7 D1 9 8 DX D2 10 9 DX * * NEGATIVE ZERO AT 15 MHZ * R6 11 12 1E6 C4 11 12 -10.6E-15 R7 12 98 1 E2 11 98 9 24 1E6 * * POLE AT 40 MHZ * R8 13 98 1E3 C5 13 98 3.98E-12 G2 98 13 12 24 1E-3 * * POLE AT 40 MHZ * R9 14 98 1E3 C6 14 98 3.98E-12 G3 98 14 13 24 1E-3 * * POLE AT 40 MHZ * R10 15 98 1E3 C7 15 98 3.98E-12 G4 98 15 14 24 1E-3 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 600 HZ * R11 16 17 1E6 C8 16 17 2.65E-10 R12 17 98 1 E3 16 98 POLY(2) 1 98 2 98 0 15.8 15.8 * * POLE AT 40 MHZ * R13 18 98 1E3 C9 18 98 3.98E-12 G5 98 18 15 24 1E-3 * * OUTPUT STAGE * R14 24 99 2000E3 R15 24 50 2000E3 ISY 99 50 -96.5E-3 R16 29 99 360 R17 29 50 360 L1 29 30 1E-8 G6 27 50 18 29 2.78E-3 G7 28 50 29 18 2.78E-3 G8 29 99 99 18 2.78E-3 G9 50 29 18 50 2.78E-3 V4 25 29 2.0 V5 29 26 2.0 D3 18 25 DX D4 26 18 DX D5 99 27 DX D6 99 28 DX D7 50 27 DY D8 50 28 DY F1 29 0 V4 1 F2 0 29 V5 1 * * MODELS USED * .MODEL JX PJF(BETA=4.54 VTO=-2.000 IS=2.5E-12 RD=0.1 + RS=0.1 CGD=1E-15 CGS=1E-15) .MODEL DX D(IS=1E-15 RS=10 CJO=1E-15) .MODEL DY D(IS=1E-15 BV=50 RS=10 CJO=1E-15) .MODEL DEN D(IS=1E-12 RS=7409.6 KF=2.051E-15 AF=1) .MODEL DIN D(IS=1E-12 RS=41.5 KF=0 AF=1) .ENDS AD645S * AD704 SPICE Macro-model 9/91, Rev. B * AAG / PMI * * Revision History: * REV B * Updated op amp architecture implemented. * * Copyright 1991 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD704 1 2 99 50 28 * * INPUT STAGE & POLE AT 3 MHz * IOS 1 2 DC 15E-12 CIN 1 2 2E-12 R1 2 3 3.3157E8 R2 1 3 3.3157E8 EOS 9 1 POLY(1) 16 22 30E-6 1 D1 2 9 DX D2 9 2 DX Q1 5 2 10 QX Q2 6 9 11 QX R3 99 5 530.51 R4 99 6 530.51 C2 5 6 50E-12 R5 10 4 13.314 R6 11 4 13.314 I1 4 50 100E-6 * * GAIN STAGE & DOMINANT POLE AT 0.45 HZ * EREF 98 0 22 0 1 G1 98 12 5 6 1.885E-3 R7 12 98 530.51E6 C3 12 98 666.67E-12 V1 99 13 DC 1.3375 D3 12 13 DX V2 14 50 DC 1.3375 D4 14 12 DX * * COMMON-MODE GAIN NETWORK WITH ZERO AT 500 HZ * ECM 15 98 3 22 251.19E-3 RCM1 15 16 1E6 CCM 15 16 318.31E-12 RCM2 16 98 1 * * ZERO-POLE PAIR AT 165 kHz / 430 kHz * GZP1 98 17 12 22 1E-6 RZP1 17 18 1E6 RZP2 18 98 1.6061E6 LZP 18 98 594.45E-3 * * NEGATIVE ZERO AT -3 MHz * ENZ 19 98 17 22 1E6 RNZ1 19 20 1 CNZ 19 20 -53.052E-9 RNZ2 20 98 1E-6 * * POLE AT 10 MHz * G2 98 21 20 22 1E-6 R10 21 98 1E6 C5 21 98 15.915E-15 * * OUTPUT STAGE * IDC 99 50 DC 260E-6 RDC1 99 22 1E6 RDC2 22 50 1E6 DO1 99 23 DX GO1 23 50 27 21 2E-3 DO2 50 23 DY DO3 99 24 DX GO2 24 50 21 27 2E-3 DO4 50 24 DY VSC1 25 27 3.15 DSC1 21 25 DX VSC2 27 26 3.15 DSC2 26 21 DX GO3 27 99 99 21 2E-3 GO4 50 27 21 50 2E-3 RO1 99 27 500 RO2 27 50 500 LO 27 28 265E-9 * * MODELS USED * .MODEL QX NPN(BF=6.25E5) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS AD704 * AD704A SPICE Macro-model 9/91, Rev. B * AAG / PMI * * This version of the AD704 model simulates the worst case * parameters of the 'A' grade. The worst case parameters * used correspond to those in the data sheet. * * Revision History: * REV B * Updated op amp architecture implemented. * * Copyright 1991 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD704A 1 2 99 50 28 * * INPUT STAGE & POLE AT 3 MHz * IOS 1 2 DC 125E-12 CIN 1 2 2E-12 R1 2 3 9.8243E7 R2 1 3 9.8243E7 EOS 9 1 POLY(1) 16 22 150E-6 1 D1 2 9 DX D2 9 2 DX Q1 5 2 10 QX Q2 6 9 11 QX R3 99 5 530.51 R4 99 6 530.51 C2 5 6 50E-12 R5 10 4 13.314 R6 11 4 13.314 I1 4 50 100E-6 * * GAIN STAGE & DOMINANT POLE AT 2.25 HZ * EREF 98 0 22 0 1 G1 98 12 5 6 1.885E-3 R7 12 98 106.1E6 C3 12 98 666.67E-12 V1 99 13 DC 2.3625 D3 12 13 DX V2 14 50 DC 2.3625 D4 14 12 DX * * COMMON-MODE GAIN NETWORK WITH ZERO AT 20 kHZ * ECM 15 98 3 22 10 RCM1 15 16 1E6 CCM 15 16 7.9577E-12 RCM2 16 98 1 * * ZERO-POLE PAIR AT 165 kHz / 430 kHz * GZP1 98 17 12 22 1E-6 RZP1 17 18 1E6 RZP2 18 98 1.6061E6 LZP 18 98 594.45E-3 * * NEGATIVE ZERO AT -3 MHz * ENZ 19 98 17 22 1E6 RNZ1 19 20 1 CNZ 19 20 -53.052E-9 RNZ2 20 98 1E-6 * * POLE AT 10 MHz * G2 98 21 20 22 1E-6 R10 21 98 1E6 C5 21 98 15.915E-15 * * OUTPUT STAGE * IDC 99 50 DC 485E-6 RDC1 99 22 1E6 RDC2 22 50 1E6 DO1 99 23 DX GO1 23 50 27 21 2E-3 DO2 50 23 DY DO3 99 24 DX GO2 24 50 21 27 2E-3 DO4 50 24 DY VSC1 25 27 3.15 DSC1 21 25 DX VSC2 27 26 3.15 DSC2 26 21 DX GO3 27 99 99 21 2E-3 GO4 50 27 21 50 2E-3 RO1 99 27 500 RO2 27 50 500 LO 27 28 265E-9 * * MODELS USED * .MODEL QX NPN(BF=1.8519E5) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS AD704A * AD704B SPICE Macro-model 9/91, Rev. B * AAG / PMI * * This version of the AD704 model simulates the worst case * parameters of the 'B' grade. The worst case parameters * used correspond to those in the data sheet. * * Revision History: * REV B * Updated op amp architecture implemented. * * Copyright 1991 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD704B 1 2 99 50 28 * * INPUT STAGE & POLE AT 3 MHz * IOS 1 2 DC 50E-12 CIN 1 2 2E-12 R1 2 3 1.7684E8 R2 1 3 1.7684E8 EOS 9 1 POLY(1) 16 22 75E-6 1 D1 2 9 DX D2 9 2 DX Q1 5 2 10 QX Q2 6 9 11 QX R3 99 5 530.51 R4 99 6 530.51 C2 5 6 50E-12 R5 10 4 13.314 R6 11 4 13.314 I1 4 50 100E-6 * * GAIN STAGE & DOMINANT POLE AT 1.5 HZ * EREF 98 0 22 0 1 G1 98 12 5 6 1.885E-3 R7 12 98 159.15E6 C3 12 98 666.67E-12 V1 99 13 DC 2.3625 D3 12 13 DX V2 14 50 DC 2.3625 D4 14 12 DX * * COMMON-MODE GAIN NETWORK WITH ZERO AT 4 kHZ * ECM 15 98 3 22 1.9953 RCM1 15 16 1E6 CCM 15 16 39.883E-12 RCM2 16 98 1 * * ZERO-POLE PAIR AT 165 kHz / 430 kHz * GZP1 98 17 12 22 1E-6 RZP1 17 18 1E6 RZP2 18 98 1.6061E6 LZP 18 98 594.45E-3 * * NEGATIVE ZERO AT -3 MHz * ENZ 19 98 17 22 1E6 RNZ1 19 20 1 CNZ 19 20 -53.052E-9 RNZ2 20 98 1E-6 * * POLE AT 10 MHz * G2 98 21 20 22 1E-6 R10 21 98 1E6 C5 21 98 15.915E-15 * * OUTPUT STAGE * IDC 99 50 DC 485E-6 RDC1 99 22 1E6 RDC2 22 50 1E6 DO1 99 23 DX GO1 23 50 27 21 2E-3 DO2 50 23 DY DO3 99 24 DX GO2 24 50 21 27 2E-3 DO4 50 24 DY VSC1 25 27 3.15 DSC1 21 25 DX VSC2 27 26 3.15 DSC2 26 21 DX GO3 27 99 99 21 2E-3 GO4 50 27 21 50 2E-3 RO1 99 27 500 RO2 27 50 500 LO 27 28 265E-9 * * MODELS USED * .MODEL QX NPN(BF=3.3333E5) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS AD704B * AD704J SPICE Macro-model 9/91, Rev. B * AAG / PMI * * This version of the AD704 model simulates the worst case * parameters of the 'J' grade. The worst case parameters * used correspond to those in the data sheet. * * Revision History: * REV B * Updated op amp architecture implemented. * * Copyright 1991 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD704J 1 2 99 50 28 * * INPUT STAGE & POLE AT 3 MHz * IOS 1 2 DC 125E-12 CIN 1 2 2E-12 R1 2 3 9.8243E7 R2 1 3 9.8243E7 EOS 9 1 POLY(1) 16 22 150E-6 1 D1 2 9 DX D2 9 2 DX Q1 5 2 10 QX Q2 6 9 11 QX R3 99 5 530.51 R4 99 6 530.51 C2 5 6 50E-12 R5 10 4 13.314 R6 11 4 13.314 I1 4 50 100E-6 * * GAIN STAGE & DOMINANT POLE AT 2.25 HZ * EREF 98 0 22 0 1 G1 98 12 5 6 1.885E-3 R7 12 98 106.1E6 C3 12 98 666.67E-12 V1 99 13 DC 2.3625 D3 12 13 DX V2 14 50 DC 2.3625 D4 14 12 DX * * COMMON-MODE GAIN NETWORK WITH ZERO AT 20 kHZ * ECM 15 98 3 22 10 RCM1 15 16 1E6 CCM 15 16 7.9577E-12 RCM2 16 98 1 * * ZERO-POLE PAIR AT 165 kHz / 430 kHz * GZP1 98 17 12 22 1E-6 RZP1 17 18 1E6 RZP2 18 98 1.6061E6 LZP 18 98 594.45E-3 * * NEGATIVE ZERO AT -3 MHz * ENZ 19 98 17 22 1E6 RNZ1 19 20 1 CNZ 19 20 -53.052E-9 RNZ2 20 98 1E-6 * * POLE AT 10 MHz * G2 98 21 20 22 1E-6 R10 21 98 1E6 C5 21 98 15.915E-15 * * OUTPUT STAGE * IDC 99 50 DC 485E-6 RDC1 99 22 1E6 RDC2 22 50 1E6 DO1 99 23 DX GO1 23 50 27 21 2E-3 DO2 50 23 DY DO3 99 24 DX GO2 24 50 21 27 2E-3 DO4 50 24 DY VSC1 25 27 3.15 DSC1 21 25 DX VSC2 27 26 3.15 DSC2 26 21 DX GO3 27 99 99 21 2E-3 GO4 50 27 21 50 2E-3 RO1 99 27 500 RO2 27 50 500 LO 27 28 265E-9 * * MODELS USED * .MODEL QX NPN(BF=1.8519E5) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS AD704J * AD704K SPICE Macro-model 9/91, Rev. B * AAG / PMI * * This version of the AD704 model simulates the worst case * parameters of the 'K' grade. The worst case parameters * used correspond to those in the data sheet. * * Revision History: * REV B * Updated op amp architecture implemented. * * Copyright 1991 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD704K 1 2 99 50 28 * * INPUT STAGE & POLE AT 3 MHz * IOS 1 2 DC 50E-12 CIN 1 2 2E-12 R1 2 3 1.7684E8 R2 1 3 1.7684E8 EOS 9 1 POLY(1) 16 22 75E-6 1 D1 2 9 DX D2 9 2 DX Q1 5 2 10 QX Q2 6 9 11 QX R3 99 5 530.51 R4 99 6 530.51 C2 5 6 50E-12 R5 10 4 13.314 R6 11 4 13.314 I1 4 50 100E-6 * * GAIN STAGE & DOMINANT POLE AT 1.5 HZ * EREF 98 0 22 0 1 G1 98 12 5 6 1.885E-3 R7 12 98 159.15E6 C3 12 98 666.67E-12 V1 99 13 DC 2.3625 D3 12 13 DX V2 14 50 DC 2.3625 D4 14 12 DX * * COMMON-MODE GAIN NETWORK WITH ZERO AT 4 kHZ * ECM 15 98 3 22 1.9953 RCM1 15 16 1E6 CCM 15 16 39.883E-12 RCM2 16 98 1 * * ZERO-POLE PAIR AT 165 kHz / 430 kHz * GZP1 98 17 12 22 1E-6 RZP1 17 18 1E6 RZP2 18 98 1.6061E6 LZP 18 98 594.45E-3 * * NEGATIVE ZERO AT -3 MHz * ENZ 19 98 17 22 1E6 RNZ1 19 20 1 CNZ 19 20 -53.052E-9 RNZ2 20 98 1E-6 * * POLE AT 10 MHz * G2 98 21 20 22 1E-6 R10 21 98 1E6 C5 21 98 15.915E-15 * * OUTPUT STAGE * IDC 99 50 DC 485E-6 RDC1 99 22 1E6 RDC2 22 50 1E6 DO1 99 23 DX GO1 23 50 27 21 2E-3 DO2 50 23 DY DO3 99 24 DX GO2 24 50 21 27 2E-3 DO4 50 24 DY VSC1 25 27 3.15 DSC1 21 25 DX VSC2 27 26 3.15 DSC2 26 21 DX GO3 27 99 99 21 2E-3 GO4 50 27 21 50 2E-3 RO1 99 27 500 RO2 27 50 500 LO 27 28 265E-9 * * MODELS USED * .MODEL QX NPN(BF=3.3333E5) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS AD704K * AD704T SPICE Macro-model 9/91, Rev. B * AAG / PMI * * This version of the AD704 model simulates the worst case * parameters of the 'T' grade. The worst case parameters * used correspond to those in the data sheet. * * Revision History: * REV B * Updated op amp architecture implemented. * * Copyright 1991 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD704T 1 2 99 50 28 * * INPUT STAGE & POLE AT 3 MHz * IOS 1 2 DC 75E-12 CIN 1 2 2E-12 R1 2 3 1.3263E8 R2 1 3 1.3263E8 EOS 9 1 POLY(1) 16 22 100E-6 1 D1 2 9 DX D2 9 2 DX Q1 5 2 10 QX Q2 6 9 11 QX R3 99 5 530.51 R4 99 6 530.51 C2 5 6 50E-12 R5 10 4 13.314 R6 11 4 13.314 I1 4 50 100E-6 * * GAIN STAGE & DOMINANT POLE AT 2.25 HZ * EREF 98 0 22 0 1 G1 98 12 5 6 1.885E-3 R7 12 98 106.1E6 C3 12 98 666.67E-12 V1 99 13 DC 2.3625 D3 12 13 DX V2 14 50 DC 2.3625 D4 14 12 DX * * COMMON-MODE GAIN NETWORK WITH ZERO AT 6.3 kHZ * ECM 15 98 3 22 3.1623 RCM1 15 16 1E6 CCM 15 16 25.165E-12 RCM2 16 98 1 * * ZERO-POLE PAIR AT 165 kHz / 430 kHz * GZP1 98 17 12 22 1E-6 RZP1 17 18 1E6 RZP2 18 98 1.6061E6 LZP 18 98 594.45E-3 * * NEGATIVE ZERO AT -3 MHz * ENZ 19 98 17 22 1E6 RNZ1 19 20 1 CNZ 19 20 -53.052E-9 RNZ2 20 98 1E-6 * * POLE AT 10 MHz * G2 98 21 20 22 1E-6 R10 21 98 1E6 C5 21 98 15.915E-15 * * OUTPUT STAGE * IDC 99 50 DC 485E-6 RDC1 99 22 1E6 RDC2 22 50 1E6 DO1 99 23 DX GO1 23 50 27 21 2E-3 DO2 50 23 DY DO3 99 24 DX GO2 24 50 21 27 2E-3 DO4 50 24 DY VSC1 25 27 3.15 DSC1 21 25 DX VSC2 27 26 3.15 DSC2 26 21 DX GO3 27 99 99 21 2E-3 GO4 50 27 21 50 2E-3 RO1 99 27 500 RO2 27 50 500 LO 27 28 265E-9 * * MODELS USED * .MODEL QX NPN(BF=2.5E5) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS AD704T * AD706A SPICE Macro-model 9/91, Rev. A * AAG / PMI * * This version of the AD706 model simulates the worst case * parameters of the 'A' grade. The worst case parameters * used correspond to those in the data sheet. * * Copyright 1991 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD706A 1 2 99 50 28 * * INPUT STAGE & POLE AT 3 MHz * IOS 1 2 DC 75E-12 CIN 1 2 2E-12 R1 2 3 1.3263E8 R2 1 3 1.3263E8 EOS 9 1 POLY(1) 16 22 100E-6 1 D1 2 9 DX D2 9 2 DX Q1 5 2 10 QX Q2 6 9 11 QX R3 99 5 530.51 R4 99 6 530.51 C2 5 6 50E-12 R5 10 4 13.314 R6 11 4 13.314 I1 4 50 100E-6 * * GAIN STAGE & DOMINANT POLE AT 2.25 HZ * EREF 98 0 22 0 1 G1 98 12 5 6 1.885E-3 R7 12 98 106.1E6 C3 12 98 666.67E-12 V1 99 13 DC 2.3635 D3 12 13 DX V2 14 50 DC 2.3625 D4 14 12 DX * * COMMON-MODE GAIN NETWORK WITH ZERO AT 6.32 kHZ * ECM 15 98 3 22 3.1623 RCM1 15 16 1E6 CCM 15 16 25.165E-12 RCM2 16 98 1 * * ZERO-POLE PAIR AT 165 kHz / 430 kHz * GZP1 98 17 12 22 1E-6 RZP1 17 18 1E6 RZP2 18 98 1.6061E6 LZP 18 98 594.45E-3 * * NEGATIVE ZERO AT -3 MHz * ENZ 19 98 17 22 1E6 RNZ1 19 20 1 CNZ 19 20 -53.052E-9 RNZ2 20 98 1E-6 * * POLE AT 10 MHz * G2 98 21 20 22 1E-6 R10 21 98 1E6 C5 21 98 15.915E-15 * * OUTPUT STAGE * IDC 99 50 DC 485E-6 RDC1 99 22 1E6 RDC2 22 50 1E6 DO1 99 23 DX GO1 23 50 27 21 2E-3 DO2 50 23 DY DO3 99 24 DX GO2 24 50 21 27 2E-3 DO4 50 24 DY VSC1 25 27 3.15 DSC1 21 25 DX VSC2 27 26 3.15 DSC2 26 21 DX GO3 27 99 99 21 2E-3 GO4 50 27 21 50 2E-3 RO1 99 27 500 RO2 27 50 500 LO 27 28 265E-9 * * MODELS USED * .MODEL QX NPN(BF=250E3) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS AD706A * AD706B SPICE Macro-model 9/91, Rev. A * AAG / PMI * * This version of the AD706 model simulates the worst case * parameters of the 'B' grade. The worst case parameters * used correspond to those in the data sheet. * * Copyright 1991 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD706B 1 2 99 50 28 * * INPUT STAGE & POLE AT 3 MHz * IOS 1 2 DC 50E-12 CIN 1 2 2E-12 R1 2 3 2.4114E8 R2 1 3 2.4114E8 EOS 9 1 POLY(1) 16 22 50E-6 1 D1 2 9 DX D2 9 2 DX Q1 5 2 10 QX Q2 6 9 11 QX R3 99 5 530.51 R4 99 6 530.51 C2 5 6 50E-12 R5 10 4 13.314 R6 11 4 13.314 I1 4 50 100E-6 * * GAIN STAGE & DOMINANT POLE AT 1.5 HZ * EREF 98 0 22 0 1 G1 98 12 5 6 1.885E-3 R7 12 98 159.15E6 C3 12 98 666.67E-12 V1 99 13 DC 2.3635 D3 12 13 DX V2 14 50 DC 2.3625 D4 14 12 DX * * COMMON-MODE GAIN NETWORK WITH ZERO AT 4 kHZ * ECM 15 98 3 22 1.9953 RCM1 15 16 1E6 CCM 15 16 39.88E-12 RCM2 16 98 1 * * ZERO-POLE PAIR AT 165 kHz / 430 kHz * GZP1 98 17 12 22 1E-6 RZP1 17 18 1E6 RZP2 18 98 1.6061E6 LZP 18 98 594.45E-3 * * NEGATIVE ZERO AT -3 MHz * ENZ 19 98 17 22 1E6 RNZ1 19 20 1 CNZ 19 20 -53.052E-9 RNZ2 20 98 1E-6 * * POLE AT 10 MHz * G2 98 21 20 22 1E-6 R10 21 98 1E6 C5 21 98 15.915E-15 * * OUTPUT STAGE * IDC 99 50 DC 485E-6 RDC1 99 22 1E6 RDC2 22 50 1E6 DO1 99 23 DX GO1 23 50 27 21 2E-3 DO2 50 23 DY DO3 99 24 DX GO2 24 50 21 27 2E-3 DO4 50 24 DY VSC1 25 27 3.15 DSC1 21 25 DX VSC2 27 26 3.15 DSC2 26 21 DX GO3 27 99 99 21 2E-3 GO4 50 27 21 50 2E-3 RO1 99 27 500 RO2 27 50 500 LO 27 28 265E-9 * * MODELS USED * .MODEL QX NPN(BF=454.55E3) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS AD706B * AD706J SPICE Macro-model 9/91, Rev. A * AAG / PMI * * This version of the AD706 model simulates the worst case * parameters of the 'J' grade. The worst case parameters * used correspond to those in the data sheet. * * Copyright 1991 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD706J 1 2 99 50 28 * * INPUT STAGE & POLE AT 3 MHz * IOS 1 2 DC 75E-12 CIN 1 2 2E-12 R1 2 3 1.3263E8 R2 1 3 1.3263E8 EOS 9 1 POLY(1) 16 22 100E-6 1 D1 2 9 DX D2 9 2 DX Q1 5 2 10 QX Q2 6 9 11 QX R3 99 5 530.51 R4 99 6 530.51 C2 5 6 50E-12 R5 10 4 13.314 R6 11 4 13.314 I1 4 50 100E-6 * * GAIN STAGE & DOMINANT POLE AT 2.25 HZ * EREF 98 0 22 0 1 G1 98 12 5 6 1.885E-3 R7 12 98 106.1E6 C3 12 98 666.67E-12 V1 99 13 DC 2.3635 D3 12 13 DX V2 14 50 DC 2.3625 D4 14 12 DX * * COMMON-MODE GAIN NETWORK WITH ZERO AT 6.32 kHZ * ECM 15 98 3 22 3.1623 RCM1 15 16 1E6 CCM 15 16 25.165E-12 RCM2 16 98 1 * * ZERO-POLE PAIR AT 165 kHz / 430 kHz * GZP1 98 17 12 22 1E-6 RZP1 17 18 1E6 RZP2 18 98 1.6061E6 LZP 18 98 594.45E-3 * * NEGATIVE ZERO AT -3 MHz * ENZ 19 98 17 22 1E6 RNZ1 19 20 1 CNZ 19 20 -53.052E-9 RNZ2 20 98 1E-6 * * POLE AT 10 MHz * G2 98 21 20 22 1E-6 R10 21 98 1E6 C5 21 98 15.915E-15 * * OUTPUT STAGE * IDC 99 50 DC 485E-6 RDC1 99 22 1E6 RDC2 22 50 1E6 DO1 99 23 DX GO1 23 50 27 21 2E-3 DO2 50 23 DY DO3 99 24 DX GO2 24 50 21 27 2E-3 DO4 50 24 DY VSC1 25 27 3.15 DSC1 21 25 DX VSC2 27 26 3.15 DSC2 26 21 DX GO3 27 99 99 21 2E-3 GO4 50 27 21 50 2E-3 RO1 99 27 500 RO2 27 50 500 LO 27 28 265E-9 * * MODELS USED * .MODEL QX NPN(BF=250E3) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS AD706J * AD706K SPICE Macro-model 9/91, Rev. A * AAG / PMI * * This version of the AD706 model simulates the worst case * parameters of the 'K' grade. The worst case parameters * used correspond to those in the data sheet. * * Copyright 1991 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD706K 1 2 99 50 28 * * INPUT STAGE & POLE AT 3 MHz * IOS 1 2 DC 50E-12 CIN 1 2 2E-12 R1 2 3 2.4114E8 R2 1 3 2.4114E8 EOS 9 1 POLY(1) 16 22 50E-6 1 D1 2 9 DX D2 9 2 DX Q1 5 2 10 QX Q2 6 9 11 QX R3 99 5 530.51 R4 99 6 530.51 C2 5 6 50E-12 R5 10 4 13.314 R6 11 4 13.314 I1 4 50 100E-6 * * GAIN STAGE & DOMINANT POLE AT 1.5 HZ * EREF 98 0 22 0 1 G1 98 12 5 6 1.885E-3 R7 12 98 159.15E6 C3 12 98 666.67E-12 V1 99 13 DC 2.3635 D3 12 13 DX V2 14 50 DC 2.3625 D4 14 12 DX * * COMMON-MODE GAIN NETWORK WITH ZERO AT 4 kHZ * ECM 15 98 3 22 1.9953 RCM1 15 16 1E6 CCM 15 16 39.88E-12 RCM2 16 98 1 * * ZERO-POLE PAIR AT 165 kHz / 430 kHz * GZP1 98 17 12 22 1E-6 RZP1 17 18 1E6 RZP2 18 98 1.6061E6 LZP 18 98 594.45E-3 * * NEGATIVE ZERO AT -3 MHz * ENZ 19 98 17 22 1E6 RNZ1 19 20 1 CNZ 19 20 -53.052E-9 RNZ2 20 98 1E-6 * * POLE AT 10 MHz * G2 98 21 20 22 1E-6 R10 21 98 1E6 C5 21 98 15.915E-15 * * OUTPUT STAGE * IDC 99 50 DC 485E-6 RDC1 99 22 1E6 RDC2 22 50 1E6 DO1 99 23 DX GO1 23 50 27 21 2E-3 DO2 50 23 DY DO3 99 24 DX GO2 24 50 21 27 2E-3 DO4 50 24 DY VSC1 25 27 3.15 DSC1 21 25 DX VSC2 27 26 3.15 DSC2 26 21 DX GO3 27 99 99 21 2E-3 GO4 50 27 21 50 2E-3 RO1 99 27 500 RO2 27 50 500 LO 27 28 265E-9 * * MODELS USED * .MODEL QX NPN(BF=454.55E3) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS AD706K * AD706T SPICE Macro-model 9/91, Rev. A * AAG / PMI * * This version of the AD706 model simulates the worst case * parameters of the 'T' grade. The worst case parameters * used correspond to those in the data sheet. * * Copyright 1991 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD706T 1 2 99 50 28 * * INPUT STAGE & POLE AT 3 MHz * IOS 1 2 DC 50E-12 CIN 1 2 2E-12 R1 2 3 2.2105E8 R2 1 3 2.2105E8 EOS 9 1 POLY(1) 16 22 50E-6 1 D1 2 9 DX D2 9 2 DX Q1 5 2 10 QX Q2 6 9 11 QX R3 99 5 530.51 R4 99 6 530.51 C2 5 6 50E-12 R5 10 4 13.314 R6 11 4 13.314 I1 4 50 100E-6 * * GAIN STAGE & DOMINANT POLE AT 2.25 HZ * EREF 98 0 22 0 1 G1 98 12 5 6 1.885E-3 R7 12 98 106.1E6 C3 12 98 666.67E-12 V1 99 13 DC 2.3635 D3 12 13 DX V2 14 50 DC 2.3625 D4 14 12 DX * * COMMON-MODE GAIN NETWORK WITH ZERO AT 4 kHZ * ECM 15 98 3 22 1.9953 RCM1 15 16 1E6 CCM 15 16 39.88E-12 RCM2 16 98 1 * * ZERO-POLE PAIR AT 165 kHz / 430 kHz * GZP1 98 17 12 22 1E-6 RZP1 17 18 1E6 RZP2 18 98 1.6061E6 LZP 18 98 594.45E-3 * * NEGATIVE ZERO AT -3 MHz * ENZ 19 98 17 22 1E6 RNZ1 19 20 1 CNZ 19 20 -53.052E-9 RNZ2 20 98 1E-6 * * POLE AT 10 MHz * G2 98 21 20 22 1E-6 R10 21 98 1E6 C5 21 98 15.915E-15 * * OUTPUT STAGE * IDC 99 50 DC 485E-6 RDC1 99 22 1E6 RDC2 22 50 1E6 DO1 99 23 DX GO1 23 50 27 21 2E-3 DO2 50 23 DY DO3 99 24 DX GO2 24 50 21 27 2E-3 DO4 50 24 DY VSC1 25 27 3.15 DSC1 21 25 DX VSC2 27 26 3.15 DSC2 26 21 DX GO3 27 99 99 21 2E-3 GO4 50 27 21 50 2E-3 RO1 99 27 500 RO2 27 50 500 LO 27 28 265E-9 * * MODELS USED * .MODEL QX NPN(BF=416.67E3) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS AD706T * AD711A SPICE Macro-model 1/91, Rev. A * JLW / PMI * * This version of the AD711 model simulates the worst case * parameters of the 'A' grade. The worst case parameters * used correspond to those in the data book. * * * Copyright 1991 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * connections: non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD711A 13 15 12 16 14 * VOS 15 8 DC 1E-3 EC 9 0 14 0 1 C1 6 7 .5E-12 RP 16 12 9.09E3 GB 11 0 3 0 1.67E3 RD1 6 16 16E3 RD2 7 16 16E3 ISS 12 1 DC 100E-6 CCI 3 11 45E-12 GCM 0 3 0 1 1.76E-9 GA 3 0 7 6 630E-6 RE 1 0 2.5E6 RGM 3 0 2.4E3 VC 12 2 DC 2.6 VE 10 16 DC 3.1 RO1 11 14 25 CE 1 0 2E-12 RO2 0 11 30 RS1 1 4 5.77E3 RS2 1 5 5.77E3 J1 6 13 4 FET J2 7 8 5 FET DC 14 2 DIODE DE 10 14 DIODE DP 16 12 DIODE D1 9 11 DIODE D2 11 9 DIODE IOS 15 13 12.5E-12 .MODEL DIODE D() .MODEL FET PJF(VTO=-1 BETA=1E-3 IS=50E-12) .ENDS * AD711B SPICE Macro-model 1/91, Rev. A * JLW / PMI * * This version of the AD711 model simulates the worst case * parameters of the 'B' grade. The worst case parameters * used correspond to those in the data book. * * * Copyright 1991 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * connections: non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD711B 13 15 12 16 14 * VOS 15 8 DC 0.5E-3 EC 9 0 14 0 1 C1 6 7 .5E-12 RP 16 12 10.35E3 GB 11 0 3 0 1.67E3 RD1 6 16 16E3 RD2 7 16 16E3 ISS 12 1 DC 100E-6 CCI 3 11 45E-12 GCM 0 3 0 1 1.76E-9 GA 3 0 7 6 780E-6 RE 1 0 2.5E6 RGM 3 0 2.6E3 VC 12 2 DC 2.8 VE 10 16 DC 3.1 RO1 11 14 25 CE 1 0 2E-12 RO2 0 11 30 RS1 1 4 5.77E3 RS2 1 5 5.77E3 J1 6 13 4 FET J2 7 8 5 FET DC 14 2 DIODE DE 10 14 DIODE DP 16 12 DIODE D1 9 11 DIODE D2 11 9 DIODE IOS 15 13 12.5E-12 .MODEL DIODE D() .MODEL FET PJF(VTO=-1 BETA=1E-3 IS=50E-12) .ENDS * AD711C SPICE Macro-model 1/91, Rev. A * JLW / PMI * * This version of the AD711 model simulates the worst case * parameters of the 'C' grade. The worst case parameters * used correspond to those in the data book. * * * Copyright 1991 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * connections: non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD711C 13 15 12 16 14 * VOS 15 8 DC 0.25E-3 EC 9 0 14 0 1 C1 6 7 .5E-12 RP 16 12 11.11E3 GB 11 0 3 0 1.67E3 RD1 6 16 16E3 RD2 7 16 16E3 ISS 12 1 DC 100E-6 CCI 3 11 45E-12 GCM 0 3 0 1 1.76E-9 GA 3 0 7 6 780E-6 RE 1 0 2.5E6 RGM 3 0 2.6E3 VC 12 2 DC 2.8 VE 10 16 DC 3.1 RO1 11 14 25 CE 1 0 2E-12 RO2 0 11 30 RS1 1 4 5.77E3 RS2 1 5 5.77E3 J1 6 13 4 FET J2 7 8 5 FET DC 14 2 DIODE DE 10 14 DIODE DP 16 12 DIODE D1 9 11 DIODE D2 11 9 DIODE IOS 15 13 5E-12 .MODEL DIODE D() .MODEL FET PJF(VTO=-1 BETA=1E-3 IS=25E-12) .ENDS * AD711J SPICE Macro-model 1/91, Rev. A * JLW / PMI * * This version of the AD711 model simulates the worst case * parameters of the 'J' grade. The worst case parameters * used correspond to those in the data book. * * * Copyright 1991 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * connections: non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD711J 13 15 12 16 14 * VOS 15 8 DC 2E-3 EC 9 0 14 0 1 C1 6 7 .5E-12 RP 16 12 9.09E3 GB 11 0 3 0 1.67E3 RD1 6 16 16E3 RD2 7 16 16E3 ISS 12 1 DC 100E-6 CCI 3 11 45E-12 GCM 0 3 0 1 1.76E-9 GA 3 0 7 6 630E-6 RE 1 0 2.5E6 RGM 3 0 2.4E3 VC 12 2 DC 2.6 VE 10 16 DC 3.1 RO1 11 14 25 CE 1 0 2E-12 RO2 0 11 30 RS1 1 4 5.77E3 RS2 1 5 5.77E3 J1 6 13 4 FET J2 7 8 5 FET DC 14 2 DIODE DE 10 14 DIODE DP 16 12 DIODE D1 9 11 DIODE D2 11 9 DIODE IOS 15 13 12.5E-12 .MODEL DIODE D() .MODEL FET PJF(VTO=-1 BETA=1E-3 IS=50E-12) .ENDS * AD711K SPICE Macro-model 1/91, Rev. A * JLW / PMI * * This version of the AD711 model simulates the worst case * parameters of the 'K' grade. The worst case parameters * used correspond to those in the data book. * * * Copyright 1991 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * connections: non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD711K 13 15 12 16 14 * VOS 15 8 DC 0.5E-3 EC 9 0 14 0 1 C1 6 7 .5E-12 RP 16 12 10.35E3 GB 11 0 3 0 1.67E3 RD1 6 16 16E3 RD2 7 16 16E3 ISS 12 1 DC 100E-6 CCI 3 11 45E-12 GCM 0 3 0 1 1.76E-9 GA 3 0 7 6 780E-6 RE 1 0 2.5E6 RGM 3 0 2.6E3 VC 12 2 DC 2.8 VE 10 16 DC 3.1 RO1 11 14 25 CE 1 0 2E-12 RO2 0 11 30 RS1 1 4 5.77E3 RS2 1 5 5.77E3 J1 6 13 4 FET J2 7 8 5 FET DC 14 2 DIODE DE 10 14 DIODE DP 16 12 DIODE D1 9 11 DIODE D2 11 9 DIODE IOS 15 13 12.5E-12 .MODEL DIODE D() .MODEL FET PJF(VTO=-1 BETA=1E-3 IS=50E-12) .ENDS * AD711S SPICE Macro-model 1/91, Rev. A * JLW / PMI * * This version of the AD711 model simulates the worst case * parameters of the 'S' grade. The worst case parameters * used correspond to those in the data book. * * * Copyright 1991 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * connections: non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD711S 13 15 12 16 14 * VOS 15 8 DC 1E-3 EC 9 0 14 0 1 C1 6 7 .5E-12 RP 16 12 9.09E3 GB 11 0 3 0 1.67E3 RD1 6 16 16E3 RD2 7 16 16E3 ISS 12 1 DC 100E-6 CCI 3 11 45E-12 GCM 0 3 0 1 1.76E-9 GA 3 0 7 6 630E-6 RE 1 0 2.5E6 RGM 3 0 2.4E3 VC 12 2 DC 2.6 VE 10 16 DC 3.1 RO1 11 14 25 CE 1 0 2E-12 RO2 0 11 30 RS1 1 4 5.77E3 RS2 1 5 5.77E3 J1 6 13 4 FET J2 7 8 5 FET DC 14 2 DIODE DE 10 14 DIODE DP 16 12 DIODE D1 9 11 DIODE D2 11 9 DIODE IOS 15 13 12.5E-12 .MODEL DIODE D() .MODEL FET PJF(VTO=-1 BETA=1E-3 IS=50E-12) .ENDS * AD711T SPICE Macro-model 1/91, Rev. A * JLW / PMI * * This version of the AD711 model simulates the worst case * parameters of the 'T' grade. The worst case parameters * used correspond to those in the data book. * * * Copyright 1991 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * connections: non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD711T 13 15 12 16 14 * VOS 15 8 DC 0.5E-3 EC 9 0 14 0 1 C1 6 7 .5E-12 RP 16 12 10.35E3 GB 11 0 3 0 1.67E3 RD1 6 16 16E3 RD2 7 16 16E3 ISS 12 1 DC 100E-6 CCI 3 11 45E-12 GCM 0 3 0 1 1.76E-9 GA 3 0 7 6 780E-6 RE 1 0 2.5E6 RGM 3 0 2.6E3 VC 12 2 DC 2.8 VE 10 16 DC 3.1 RO1 11 14 25 CE 1 0 2E-12 RO2 0 11 30 RS1 1 4 5.77E3 RS2 1 5 5.77E3 J1 6 13 4 FET J2 7 8 5 FET DC 14 2 DIODE DE 10 14 DIODE DP 16 12 DIODE D1 9 11 DIODE D2 11 9 DIODE IOS 15 13 12.5E-12 .MODEL DIODE D() .MODEL FET PJF(VTO=-1 BETA=1E-3 IS=50E-12) .ENDS * AD712A SPICE Macro-model 4/92, Rev. B * JCB/JW/PMI * * This version of the AD712 model simulates the worst case * parameters of the 'A' grade. The worst case parameters * used correspond to those in the data sheet. * * Revision History: * Rev B: Convert model into ADSpice format * Add noise generators * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD712A 1 2 99 50 30 * * INPUT STAGE * R3 5 50 5.305 R4 6 50 5.305 CIN 1 2 5.5E-12 I1 99 4 100E-3 IOS 1 2 12.5E-12 EOS 60 1 POLY(1) 17 24 1E-3 1 EN 7 60 42 0 1 GN1 0 1 45 0 1E-6 GN2 0 2 48 0 1E-6 J1 5 2 4 JX J2 6 7 4 JX GB1 2 50 POLY(3) 4,2 5,2 50,2 0 1E-12 1E-12 1E-12 GB2 7 50 POLY(3) 4,7 6,7 50,7 0 1E-12 1E-12 1E-12 * EREF 98 0 24 0 1 * * VOLTAGE NOISE GENERATOR * VN1 41 0 DC 2 DN1 41 42 DEN DN2 42 43 DEN VN2 0 43 DC 2 * * CURRENT NOISE GENERATOR * VN3 44 0 DC 2 DN3 44 45 DIN DN4 45 46 DIN VN4 0 46 DC 2 * * CURRENT NOISE GENERATOR * VN5 47 0 DC 2 DN5 47 48 DIN DN6 48 49 DIN VN6 0 49 DC 2 * * SECOND STAGE & POLE AT 32 HZ * R5 9 98 7.96E5 C3 9 98 6.25E-9 G1 98 9 5 6 1.88E-1 V2 99 8 2.2 V3 10 50 2.8 D1 9 8 DX D2 10 9 DX * * COMMON-MODE GAIN NETWORK WITH ZERO AT 2.4kHZ * R11 16 17 1E6 C8 16 17 6.695E-11 R12 17 98 1 E3 16 98 POLY(2) 1 98 2 98 0 79.24 79.24 * * POLE AT 15 MHZ * R13 18 98 1E3 C9 18 98 10.61E-12 G5 98 18 9 24 1E-3 * * OUTPUT STAGE * R14 24 99 500E3 R15 24 50 500E3 CF 24 0 1E-6 ISY 99 50 -93.2E-3 R16 29 99 110 R17 29 50 110 L1 29 30 1E-8 G6 27 50 18 29 9.09E-3 G7 28 50 29 18 9.09E-3 G8 29 99 99 18 9.09E-3 G9 50 29 18 50 9.09E-3 V4 25 29 0.675 V5 29 26 0.675 D3 18 25 DX D4 26 18 DX D5 99 27 DX D6 99 28 DX D7 50 27 DY D8 50 28 DY F1 29 0 V4 1 F2 0 29 V5 1 * * MODELS USED * .MODEL JX PJF(BETA=1.78E-1 VTO=-2.000 IS=75E-12 RD=0 + RS=0 CGD=1E-12 CGS=1E-12) .MODEL DX D(IS=1E-15 RS=0 CJO=1E-12) .MODEL DY D(IS=1E-15 BV=50 RS=10 CJO=1E-12) .MODEL DEN D(IS=1E-12 RS=30909 KF=2.651E-15 AF=1) .MODEL DIN D(IS=1E-12 RS=12090 KF=0 AF=1) .ENDS AD712A * AD712B SPICE Macro-model 4/92, Rev. B * JCB/JW/PMI * * This version of the AD712 model simulates the worst case * parameters of the 'B' grade. The worst case parameters * used correspond to those in the data sheet. * * Revision History: * Rev B: Convert model into ADSpice format * Add noise generators * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD712B 1 2 99 50 30 * * INPUT STAGE * R3 5 50 5.968 R4 6 50 5.968 CIN 1 2 5.5E-12 I1 99 4 100E-3 IOS 1 2 12.5E-12 EOS 60 1 POLY(1) 17 24 0.7E-3 1 EN 7 60 42 0 1 GN1 0 1 45 0 1E-6 GN2 0 2 48 0 1E-6 J1 5 2 4 JX J2 6 7 4 JX GB1 2 50 POLY(3) 4,2 5,2 50,2 0 1E-12 1E-12 1E-12 GB2 7 50 POLY(3) 4,7 6,7 50,7 0 1E-12 1E-12 1E-12 * EREF 98 0 24 0 1 * * VOLTAGE NOISE GENERATOR * VN1 41 0 DC 2 DN1 41 42 DEN DN2 42 43 DEN VN2 0 43 DC 2 * * CURRENT NOISE GENERATOR * VN3 44 0 DC 2 DN3 44 45 DIN DN4 45 46 DIN VN4 0 46 DC 2 * * CURRENT NOISE GENERATOR * VN5 47 0 DC 2 DN5 47 48 DIN DN6 48 49 DIN VN6 0 49 DC 2 * * SECOND STAGE & POLE AT 24 HZ * R5 9 98 1.19E6 C3 9 98 5.56E-9 G1 98 9 5 6 1.68E-1 V2 99 8 2.2 V3 10 50 2.8 D1 9 8 DX D2 10 9 DX * * COMMON-MODE GAIN NETWORK WITH ZERO AT 1500 HZ * R11 16 17 1E6 C8 16 17 1.061E-10 R12 17 98 1 E3 16 98 POLY(2) 1 98 2 98 0 50 50 * * POLE AT 15 MHZ * R13 18 98 1E3 C9 18 98 10.61E-12 G5 98 18 9 24 1E-3 * * OUTPUT STAGE * R14 24 99 500E3 R15 24 50 500E3 CF 24 0 1E-6 ISY 99 50 -94.4E-3 R16 29 99 110 R17 29 50 110 L1 29 30 1E-8 G6 27 50 18 29 9.09E-3 G7 28 50 29 18 9.09E-3 G8 29 99 99 18 9.09E-3 G9 50 29 18 50 9.09E-3 V4 25 29 0.675 V5 29 26 0.675 D3 18 25 DX D4 26 18 DX D5 99 27 DX D6 99 28 DX D7 50 27 DY D8 50 28 DY F1 29 0 V4 1 F2 0 29 V5 1 * * MODELS USED * .MODEL JX PJF(BETA=1.4E-1 VTO=-2.000 IS=75E-12 RD=0 + RS=0 CGD=1E-12 CGS=1E-12) .MODEL DX D(IS=1E-15 RS=0 CJO=1E-12) .MODEL DY D(IS=1E-15 BV=50 RS=10 CJO=1E-12) .MODEL DEN D(IS=1E-12 RS=30909 KF=2.651E-15 AF=1) .MODEL DIN D(IS=1E-12 RS=12090 KF=0 AF=1) .ENDS AD712B * AD712C SPICE Macro-model 4/92, Rev. B * JCB/JW/PMI * * This version of the AD712 model simulates the worst case * parameters of the 'C' grade. The worst case parameters * used correspond to those in the data sheet. * * Revision History: * Rev B: Convert model into ADSpice format * Add noise generators * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD712C 1 2 99 50 30 * * INPUT STAGE * R3 5 50 5.968 R4 6 50 5.968 CIN 1 2 5.5E-12 I1 99 4 100E-3 IOS 1 2 5E-12 EOS 60 1 POLY(1) 17 24 300E-6 1 EN 7 60 42 0 1 GN1 0 1 45 0 1E-6 GN2 0 2 48 0 1E-6 J1 5 2 4 JX J2 6 7 4 JX GB1 2 50 POLY(3) 4,2 5,2 50,2 0 1E-12 1E-12 1E-12 GB2 7 50 POLY(3) 4,7 6,7 50,7 0 1E-12 1E-12 1E-12 * EREF 98 0 24 0 1 * * VOLTAGE NOISE GENERATOR * VN1 41 0 DC 2 DN1 41 42 DEN DN2 42 43 DEN VN2 0 43 DC 2 * * CURRENT NOISE GENERATOR * VN3 44 0 DC 2 DN3 44 45 DIN DN4 45 46 DIN VN4 0 46 DC 2 * * CURRENT NOISE GENERATOR * VN5 47 0 DC 2 DN5 47 48 DIN DN6 48 49 DIN VN6 0 49 DC 2 * * SECOND STAGE & POLE AT 24 HZ * R5 9 98 1.19E6 C3 9 98 5.56E-9 G1 98 9 5 6 1.68E-1 V2 99 8 2.2 V3 10 50 2.8 D1 9 8 DX D2 10 9 DX * * COMMON-MODE GAIN NETWORK WITH ZERO AT 750 HZ * R11 16 17 1E6 C8 16 17 2.117E-10 R12 17 98 1 E3 16 98 POLY(2) 1 98 2 98 0 25 25 * * POLE AT 15 MHZ * R13 18 98 1E3 C9 18 98 10.61E-12 G5 98 18 9 24 1E-3 * * OUTPUT STAGE * R14 24 99 500E3 R15 24 50 500E3 CF 24 0 1E-6 ISY 99 50 -94.4E-3 R16 29 99 110 R17 29 50 110 L1 29 30 1E-8 G6 27 50 18 29 9.09E-3 G7 28 50 29 18 9.09E-3 G8 29 99 99 18 9.09E-3 G9 50 29 18 50 9.09E-3 V4 25 29 0.675 V5 29 26 0.675 D3 18 25 DX D4 26 18 DX D5 99 27 DX D6 99 28 DX D7 50 27 DY D8 50 28 DY F1 29 0 V4 1 F2 0 29 V5 1 * * MODELS USED * .MODEL JX PJF(BETA=1.4E-1 VTO=-2.000 IS=50E-12 RD=0 + RS=0 CGD=1E-12 CGS=1E-12) .MODEL DX D(IS=1E-15 RS=0 CJO=1E-12) .MODEL DY D(IS=1E-15 BV=50 RS=10 CJO=1E-12) .MODEL DEN D(IS=1E-12 RS=30909 KF=2.651E-15 AF=1) .MODEL DIN D(IS=1E-12 RS=12090 KF=0 AF=1) .ENDS AD712C * AD712J SPICE Macro-model 4/92, Rev. B * JCB/JW/PMI * * This version of the AD712 model simulates the worst case * parameters of the 'J' grade. The worst case parameters * used correspond to those in the data sheet. * * Revision History: * Rev B: Convert model into ADSpice format * Add noise generators * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD712J 1 2 99 50 30 * * INPUT STAGE * R3 5 50 5.305 R4 6 50 5.305 CIN 1 2 5.5E-12 I1 99 4 100E-3 IOS 1 2 12.5E-12 EOS 60 1 POLY(1) 17 24 3E-3 1 EN 7 60 42 0 1 GN1 0 1 45 0 1E-6 GN2 0 2 48 0 1E-6 J1 5 2 4 JX J2 6 7 4 JX GB1 2 50 POLY(3) 4,2 5,2 50,2 0 1E-12 1E-12 1E-12 GB2 7 50 POLY(3) 4,7 6,7 50,7 0 1E-12 1E-12 1E-12 * EREF 98 0 24 0 1 * * VOLTAGE NOISE GENERATOR * VN1 41 0 DC 2 DN1 41 42 DEN DN2 42 43 DEN VN2 0 43 DC 2 * * CURRENT NOISE GENERATOR * VN3 44 0 DC 2 DN3 44 45 DIN DN4 45 46 DIN VN4 0 46 DC 2 * * CURRENT NOISE GENERATOR * VN5 47 0 DC 2 DN5 47 48 DIN DN6 48 49 DIN VN6 0 49 DC 2 * * SECOND STAGE & POLE AT 32 HZ * R5 9 98 7.96E5 C3 9 98 6.25E-9 G1 98 9 5 6 1.88E-1 V2 99 8 2.2 V3 10 50 2.8 D1 9 8 DX D2 10 9 DX * * COMMON-MODE GAIN NETWORK WITH ZERO AT 2.4kHZ * R11 16 17 1E6 C8 16 17 6.695E-11 R12 17 98 1 E3 16 98 POLY(2) 1 98 2 98 0 79.24 79.24 * * POLE AT 15 MHZ * R13 18 98 1E3 C9 18 98 10.61E-12 G5 98 18 9 24 1E-3 * * OUTPUT STAGE * R14 24 99 500E3 R15 24 50 500E3 CF 24 0 1E-6 ISY 99 50 -93.2E-3 R16 29 99 110 R17 29 50 110 L1 29 30 1E-8 G6 27 50 18 29 9.09E-3 G7 28 50 29 18 9.09E-3 G8 29 99 99 18 9.09E-3 G9 50 29 18 50 9.09E-3 V4 25 29 0.675 V5 29 26 0.675 D3 18 25 DX D4 26 18 DX D5 99 27 DX D6 99 28 DX D7 50 27 DY D8 50 28 DY F1 29 0 V4 1 F2 0 29 V5 1 * * MODELS USED * .MODEL JX PJF(BETA=1.78E-1 VTO=-2.000 IS=75E-12 RD=0 + RS=0 CGD=1E-12 CGS=1E-12) .MODEL DX D(IS=1E-15 RS=0 CJO=1E-12) .MODEL DY D(IS=1E-15 BV=50 RS=10 CJO=1E-12) .MODEL DEN D(IS=1E-12 RS=30909 KF=2.651E-15 AF=1) .MODEL DIN D(IS=1E-12 RS=12090 KF=0 AF=1) .ENDS AD712J * AD712K SPICE Macro-model 4/92, Rev. B * JCB/JW/PMI * * This version of the AD712 model simulates the worst case * parameters of the 'K' grade. The worst case parameters * used correspond to those in the data sheet. * * Revision History: * Rev B: Convert model into ADSpice format * Add noise generators * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD712K 1 2 99 50 30 * * INPUT STAGE * R3 5 50 5.968 R4 6 50 5.968 CIN 1 2 5.5E-12 I1 99 4 100E-3 IOS 1 2 12.5E-12 EOS 60 1 POLY(1) 17 24 1E-3 1 EN 7 60 42 0 1 GN1 0 1 45 0 1E-6 GN2 0 2 48 0 1E-6 J1 5 2 4 JX J2 6 7 4 JX GB1 2 50 POLY(3) 4,2 5,2 50,2 0 1E-12 1E-12 1E-12 GB2 7 50 POLY(3) 4,7 6,7 50,7 0 1E-12 1E-12 1E-12 * EREF 98 0 24 0 1 * * VOLTAGE NOISE GENERATOR * VN1 41 0 DC 2 DN1 41 42 DEN DN2 42 43 DEN VN2 0 43 DC 2 * * CURRENT NOISE GENERATOR * VN3 44 0 DC 2 DN3 44 45 DIN DN4 45 46 DIN VN4 0 46 DC 2 * * CURRENT NOISE GENERATOR * VN5 47 0 DC 2 DN5 47 48 DIN DN6 48 49 DIN VN6 0 49 DC 2 * * SECOND STAGE & POLE AT 24 HZ * R5 9 98 1.19E6 C3 9 98 5.56E-9 G1 98 9 5 6 1.68E-1 V2 99 8 2.2 V3 10 50 2.8 D1 9 8 DX D2 10 9 DX * * COMMON-MODE GAIN NETWORK WITH ZERO AT 1500 HZ * R11 16 17 1E6 C8 16 17 1.061E-10 R12 17 98 1 E3 16 98 POLY(2) 1 98 2 98 0 50 50 * * POLE AT 15 MHZ * R13 18 98 1E3 C9 18 98 10.61E-12 G5 98 18 9 24 1E-3 * * OUTPUT STAGE * R14 24 99 500E3 R15 24 50 500E3 CF 24 0 1E-6 ISY 99 50 -94.4E-3 R16 29 99 110 R17 29 50 110 L1 29 30 1E-8 G6 27 50 18 29 9.09E-3 G7 28 50 29 18 9.09E-3 G8 29 99 99 18 9.09E-3 G9 50 29 18 50 9.09E-3 V4 25 29 0.675 V5 29 26 0.675 D3 18 25 DX D4 26 18 DX D5 99 27 DX D6 99 28 DX D7 50 27 DY D8 50 28 DY F1 29 0 V4 1 F2 0 29 V5 1 * * MODELS USED * .MODEL JX PJF(BETA=1.4E-1 VTO=-2.000 IS=75E-12 RD=0 + RS=0 CGD=1E-12 CGS=1E-12) .MODEL DX D(IS=1E-15 RS=0 CJO=1E-12) .MODEL DY D(IS=1E-15 BV=50 RS=10 CJO=1E-12) .MODEL DEN D(IS=1E-12 RS=30909 KF=2.651E-15 AF=1) .MODEL DIN D(IS=1E-12 RS=12090 KF=0 AF=1) .ENDS AD712K * AD712S SPICE Macro-model 4/92, Rev. B * JCB/JW/PMI * * This version of the AD712 model simulates the worst case * parameters of the 'A' grade. The worst case parameters * used correspond to those in the data sheet. * * Revision History: * Rev B: Convert model into ADSpice format * Add noise generators * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD712S 1 2 99 50 30 * * INPUT STAGE * R3 5 50 5.305 R4 6 50 5.305 CIN 1 2 5.5E-12 I1 99 4 100E-3 IOS 1 2 12.5E-12 EOS 60 1 POLY(1) 17 24 1E-3 1 EN 7 60 42 0 1 GN1 0 1 45 0 1E-6 GN2 0 2 48 0 1E-6 J1 5 2 4 JX J2 6 7 4 JX GB1 2 50 POLY(3) 4,2 5,2 50,2 0 1E-12 1E-12 1E-12 GB2 7 50 POLY(3) 4,7 6,7 50,7 0 1E-12 1E-12 1E-12 * EREF 98 0 24 0 1 * * VOLTAGE NOISE GENERATOR * VN1 41 0 DC 2 DN1 41 42 DEN DN2 42 43 DEN VN2 0 43 DC 2 * * CURRENT NOISE GENERATOR * VN3 44 0 DC 2 DN3 44 45 DIN DN4 45 46 DIN VN4 0 46 DC 2 * * CURRENT NOISE GENERATOR * VN5 47 0 DC 2 DN5 47 48 DIN DN6 48 49 DIN VN6 0 49 DC 2 * * SECOND STAGE & POLE AT 32 HZ * R5 9 98 7.96E5 C3 9 98 6.25E-9 G1 98 9 5 6 1.88E-1 V2 99 8 2.2 V3 10 50 2.8 D1 9 8 DX D2 10 9 DX * * COMMON-MODE GAIN NETWORK WITH ZERO AT 2.4kHZ * R11 16 17 1E6 C8 16 17 6.695E-11 R12 17 98 1 E3 16 98 POLY(2) 1 98 2 98 0 79.24 79.24 * * POLE AT 15 MHZ * R13 18 98 1E3 C9 18 98 10.61E-12 G5 98 18 9 24 1E-3 * * OUTPUT STAGE * R14 24 99 500E3 R15 24 50 500E3 CF 24 0 1E-6 ISY 99 50 -93.2E-3 R16 29 99 110 R17 29 50 110 L1 29 30 1E-8 G6 27 50 18 29 9.09E-3 G7 28 50 29 18 9.09E-3 G8 29 99 99 18 9.09E-3 G9 50 29 18 50 9.09E-3 V4 25 29 0.675 V5 29 26 0.675 D3 18 25 DX D4 26 18 DX D5 99 27 DX D6 99 28 DX D7 50 27 DY D8 50 28 DY F1 29 0 V4 1 F2 0 29 V5 1 * * MODELS USED * .MODEL JX PJF(BETA=1.78E-1 VTO=-2.000 IS=75E-12 RD=0 + RS=0 CGD=1E-12 CGS=1E-12) .MODEL DX D(IS=1E-15 RS=0 CJO=1E-12) .MODEL DY D(IS=1E-15 BV=50 RS=10 CJO=1E-12) .MODEL DEN D(IS=1E-12 RS=30909 KF=2.651E-15 AF=1) .MODEL DIN D(IS=1E-12 RS=12090 KF=0 AF=1) .ENDS AD712S * AD712T SPICE Macro-model 4/92, Rev. B * JCB/JW/PMI * * This version of the AD712 model simulates the worst case * parameters of the 'B' grade. The worst case parameters * used correspond to those in the data sheet. * * Revision History: * Rev B: Convert model into ADSpice format * Add noise generators * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD712T 1 2 99 50 30 * * INPUT STAGE * R3 5 50 5.968 R4 6 50 5.968 CIN 1 2 5.5E-12 I1 99 4 100E-3 IOS 1 2 12.5E-12 EOS 60 1 POLY(1) 17 24 0.7E-3 1 EN 7 60 42 0 1 GN1 0 1 45 0 1E-6 GN2 0 2 48 0 1E-6 J1 5 2 4 JX J2 6 7 4 JX GB1 2 50 POLY(3) 4,2 5,2 50,2 0 1E-12 1E-12 1E-12 GB2 7 50 POLY(3) 4,7 6,7 50,7 0 1E-12 1E-12 1E-12 * EREF 98 0 24 0 1 * * VOLTAGE NOISE GENERATOR * VN1 41 0 DC 2 DN1 41 42 DEN DN2 42 43 DEN VN2 0 43 DC 2 * * CURRENT NOISE GENERATOR * VN3 44 0 DC 2 DN3 44 45 DIN DN4 45 46 DIN VN4 0 46 DC 2 * * CURRENT NOISE GENERATOR * VN5 47 0 DC 2 DN5 47 48 DIN DN6 48 49 DIN VN6 0 49 DC 2 * * SECOND STAGE & POLE AT 24 HZ * R5 9 98 1.19E6 C3 9 98 5.56E-9 G1 98 9 5 6 1.68E-1 V2 99 8 2.2 V3 10 50 2.8 D1 9 8 DX D2 10 9 DX * * COMMON-MODE GAIN NETWORK WITH ZERO AT 1500 HZ * R11 16 17 1E6 C8 16 17 1.061E-10 R12 17 98 1 E3 16 98 POLY(2) 1 98 2 98 0 50 50 * * POLE AT 15 MHZ * R13 18 98 1E3 C9 18 98 10.61E-12 G5 98 18 9 24 1E-3 * * OUTPUT STAGE * R14 24 99 500E3 R15 24 50 500E3 CF 24 0 1E-6 ISY 99 50 -94.4E-3 R16 29 99 110 R17 29 50 110 L1 29 30 1E-8 G6 27 50 18 29 9.09E-3 G7 28 50 29 18 9.09E-3 G8 29 99 99 18 9.09E-3 G9 50 29 18 50 9.09E-3 V4 25 29 0.675 V5 29 26 0.675 D3 18 25 DX D4 26 18 DX D5 99 27 DX D6 99 28 DX D7 50 27 DY D8 50 28 DY F1 29 0 V4 1 F2 0 29 V5 1 * * MODELS USED * .MODEL JX PJF(BETA=1.4E-1 VTO=-2.000 IS=75E-12 RD=0 + RS=0 CGD=1E-12 CGS=1E-12) .MODEL DX D(IS=1E-15 RS=0 CJO=1E-12) .MODEL DY D(IS=1E-15 BV=50 RS=10 CJO=1E-12) .MODEL DEN D(IS=1E-12 RS=30909 KF=2.651E-15 AF=1) .MODEL DIN D(IS=1E-12 RS=12090 KF=0 AF=1) .ENDS AD712T * AD713A SPICE Macro-model 1/91, Rev. A * JLW / PMI * * This version of the AD713 model simulates the worst case * parameters of the 'A' grade. The worst case parameters * used correspond to those in the device data sheet. * * * Copyright 1991 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * connections: non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD713A 13 15 12 16 14 * VOS 15 8 DC 1.5E-3 EC 9 0 14 0 1 C1 6 7 .5E-12 RP 16 12 9.16E3 GB 11 0 3 0 1.67E3 RD1 6 16 16E3 RD2 7 16 16E3 ISS 12 1 DC 100E-6 CCI 3 11 45E-12 GCM 0 3 0 1 1.76E-9 GA 3 0 7 6 630E-6 RE 1 0 2.5E6 RGM 3 0 2.4E3 VC 12 2 DC 2.6 VE 10 16 DC 3.1 RO1 11 14 25 CE 1 0 2E-12 RO2 0 11 30 RS1 1 4 5.77E3 RS2 1 5 5.77E3 J1 6 13 4 FET J2 7 8 5 FET DC 14 2 DIODE DE 10 14 DIODE DP 16 12 DIODE D1 9 11 DIODE D2 11 9 DIODE IOS 15 13 37.5E-12 .MODEL DIODE D() .MODEL FET PJF(VTO=-1 BETA=1E-3 IS=150E-12) .ENDS * AD713B SPICE Macro-model 1/91, Rev. A * JLW / PMI * * This version of the AD713 model simulates the worst case * parameters of the 'B' grade. The worst case parameters * used correspond to those in the device data sheet. * * * Copyright 1991 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * connections: non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD713B 13 15 12 16 14 * VOS 15 8 DC 0.5E-3 EC 9 0 14 0 1 C1 6 7 .5E-12 RP 16 12 10.35E3 GB 11 0 3 0 1.67E3 RD1 6 16 16E3 RD2 7 16 16E3 ISS 12 1 DC 100E-6 CCI 3 11 45E-12 GCM 0 3 0 1 1.76E-9 GA 3 0 7 6 780E-6 RE 1 0 2.5E6 RGM 3 0 2.6E3 VC 12 2 DC 2.8 VE 10 16 DC 3.1 RO1 11 14 25 CE 1 0 2E-12 RO2 0 11 30 RS1 1 4 5.77E3 RS2 1 5 5.77E3 J1 6 13 4 FET J2 7 8 5 FET DC 14 2 DIODE DE 10 14 DIODE DP 16 12 DIODE D1 9 11 DIODE D2 11 9 DIODE IOS 15 13 17.5E-12 .MODEL DIODE D() .MODEL FET PJF(VTO=-1 BETA=1E-3 IS=75E-12) .ENDS * AD713J SPICE Macro-model 1/91, Rev. A * JLW / PMI * * This version of the AD713 model simulates the worst case * parameters of the 'J' grade. The worst case parameters * used correspond to those in the device data sheet. * * * Copyright 1991 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * connections: non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD713J 13 15 12 16 14 * VOS 15 8 DC 1.5E-3 EC 9 0 14 0 1 C1 6 7 .5E-12 RP 16 12 9.16E3 GB 11 0 3 0 1.67E3 RD1 6 16 16E3 RD2 7 16 16E3 ISS 12 1 DC 100E-6 CCI 3 11 45E-12 GCM 0 3 0 1 1.76E-9 GA 3 0 7 6 630E-6 RE 1 0 2.5E6 RGM 3 0 2.4E3 VC 12 2 DC 2.6 VE 10 16 DC 3.1 RO1 11 14 25 CE 1 0 2E-12 RO2 0 11 30 RS1 1 4 5.77E3 RS2 1 5 5.77E3 J1 6 13 4 FET J2 7 8 5 FET DC 14 2 DIODE DE 10 14 DIODE DP 16 12 DIODE D1 9 11 DIODE D2 11 9 DIODE IOS 15 13 37.5E-12 .MODEL DIODE D() .MODEL FET PJF(VTO=-1 BETA=1E-3 IS=150E-12) .ENDS * AD713K SPICE Macro-model 1/91, Rev. A * JLW / PMI * * This version of the AD713 model simulates the worst case * parameters of the 'K' grade. The worst case parameters * used correspond to those in the device data sheet. * * * Copyright 1991 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * connections: non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD713K 13 15 12 16 14 * VOS 15 8 DC 0.5E-3 EC 9 0 14 0 1 C1 6 7 .5E-12 RP 16 12 10.35E3 GB 11 0 3 0 1.67E3 RD1 6 16 16E3 RD2 7 16 16E3 ISS 12 1 DC 100E-6 CCI 3 11 45E-12 GCM 0 3 0 1 1.76E-9 GA 3 0 7 6 780E-6 RE 1 0 2.5E6 RGM 3 0 2.6E3 VC 12 2 DC 2.8 VE 10 16 DC 3.1 RO1 11 14 25 CE 1 0 2E-12 RO2 0 11 30 RS1 1 4 5.77E3 RS2 1 5 5.77E3 J1 6 13 4 FET J2 7 8 5 FET DC 14 2 DIODE DE 10 14 DIODE DP 16 12 DIODE D1 9 11 DIODE D2 11 9 DIODE IOS 15 13 17.5E-12 .MODEL DIODE D() .MODEL FET PJF(VTO=-1 BETA=1E-3 IS=75E-12) .ENDS * AD713S SPICE Macro-model 1/91, Rev. A * JLW / PMI * * This version of the AD713 model simulates the worst case * parameters of the 'S' grade. The worst case parameters * used correspond to those in the device data sheet. * * * Copyright 1991 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * connections: non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD713S 13 15 12 16 14 * VOS 15 8 DC 1.5E-3 EC 9 0 14 0 1 C1 6 7 .5E-12 RP 16 12 9.16E3 GB 11 0 3 0 1.67E3 RD1 6 16 16E3 RD2 7 16 16E3 ISS 12 1 DC 100E-6 CCI 3 11 45E-12 GCM 0 3 0 1 1.76E-9 GA 3 0 7 6 630E-6 RE 1 0 2.5E6 RGM 3 0 2.4E3 VC 12 2 DC 2.6 VE 10 16 DC 3.1 RO1 11 14 25 CE 1 0 2E-12 RO2 0 11 30 RS1 1 4 5.77E3 RS2 1 5 5.77E3 J1 6 13 4 FET J2 7 8 5 FET DC 14 2 DIODE DE 10 14 DIODE DP 16 12 DIODE D1 9 11 DIODE D2 11 9 DIODE IOS 15 13 37.5E-12 .MODEL DIODE D() .MODEL FET PJF(VTO=-1 BETA=1E-3 IS=150E-12) .ENDS * AD713T SPICE Macro-model 1/91, Rev. A * JLW / PMI * * This version of the AD713 model simulates the worst case * parameters of the 'T' grade. The worst case parameters * used correspond to those in the device data sheet. * * * Copyright 1991 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * connections: non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD713T 13 15 12 16 14 * VOS 15 8 DC 0.5E-3 EC 9 0 14 0 1 C1 6 7 .5E-12 RP 16 12 10.35E3 GB 11 0 3 0 1.67E3 RD1 6 16 16E3 RD2 7 16 16E3 ISS 12 1 DC 100E-6 CCI 3 11 45E-12 GCM 0 3 0 1 1.76E-9 GA 3 0 7 6 780E-6 RE 1 0 2.5E6 RGM 3 0 2.6E3 VC 12 2 DC 2.8 VE 10 16 DC 3.1 RO1 11 14 25 CE 1 0 2E-12 RO2 0 11 30 RS1 1 4 5.77E3 RS2 1 5 5.77E3 J1 6 13 4 FET J2 7 8 5 FET DC 14 2 DIODE DE 10 14 DIODE DP 16 12 DIODE D1 9 11 DIODE D2 11 9 DIODE IOS 15 13 17.5E-12 .MODEL DIODE D() .MODEL FET PJF(VTO=-1 BETA=1E-3 IS=75E-12) .ENDS * AD743A SPICE Macro-model 4/92, Rev. A * AAG / PMI * * This version of the AD743 multiplier model simulates the worst case * parameters of the 'A' grade. The worst case parameters used * correspond to those in the data sheet. * * Copyright 1992 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD743A 1 2 99 50 37 * * INPUT STAGE & POLE AT 65 MHz * IOS 1 2 DC 75E-12 CIN 1 2 20E-12 EOS 9 3 POLY(1) 16 31 800E-6 1 EN 3 1 41 0 1 J1 5 2 4 PJX J2 6 9 4 PJX R3 5 51 0.9323 R4 6 51 0.9323 C2 5 6 1.3132E-9 I1 97 4 100E-3 EPOS 97 0 99 0 1 ENEG 51 0 50 0 1 GN1 0 1 44 0 1E-6 GN2 0 2 47 0 1E-6 * * INPUT NOISE VOLTAGE GENERATOR * VN1 40 0 DC 2 DN1 40 41 DEN DN2 41 42 DEN VN2 0 42 DC 2 * * INPUT NOISE CURRENT GENERATOR FOR IN+ * VN3 43 0 DC 2 DN3 43 44 DIN DN4 44 45 DIN VN4 0 45 DC 2 * * INPUT NOISE CURRENT GENERATOR FOR IN- * VN5 46 0 DC 2 DN5 46 47 DIN DN6 47 48 DIN VN6 0 48 DC 2 * * GAIN STAGE & DOMINANT POLE AT 4.78 Hz * EREF 98 0 31 0 1 G1 98 12 5 6 1.0726 R5 12 98 9.32314E5 C3 12 98 35.714E-9 V1 99 13 DC 0.8 D1 12 13 DX V2 14 50 DC 2 D4 14 12 DX * * CMR Network with Zero at 7.554 kHz * ECM 15 98 POLY(2) 1 31 2 31 (0,50,50) RCM1 15 16 1 CCM 15 16 2.107E-5 RCM2 16 98 1E-6 * * NEGATIVE ZERO AT -19.5 MHz * ENZ 17 98 12 31 1E6 RNZ1 17 18 1 CNZ 17 18 -8.1618E-9 RNZ2 18 98 1E-6 * * POLE-ZERO PAIR AT 330 kHz/690 kHz * GPZ 98 19 18 31 1 RPZ1 19 98 1 RPZ2 19 20 0.91667 CPZ 20 98 251.63E-9 * * POLE AT 65 MHz * G2 98 21 19 31 1 R10 21 98 1 C5 21 98 2.4485E-9 * * OUTPUT STAGE * VWIRE 21 30 0 * IDC 99 50 DC 9.7E-3 RDC1 99 31 50E3 CDC 31 0 1E-12 RDC2 31 50 50E3 DO1 99 32 DX GO1 32 50 36 30 5.5556E-3 DO2 50 32 DY DO3 99 33 DX GO2 33 50 30 36 5.5556E-3 DO4 50 33 DY VSC1 34 36 3.1 DSC1 30 34 DX VSC2 36 35 2.66 DSC2 35 30 DX GO3 36 99 99 30 5.5556E-3 GO4 50 36 30 50 5.5556E-3 FO1 36 0 VSC1 1 FO2 0 36 VSC2 1 RO1 99 36 180 RO2 36 50 180 LO 36 37 250E-9 * * MODELS USED * .MODEL PJX PJF(VTO=-2 BETA=5.7526 IS=400E-12) .MODEL DEN D(IS=1E-12 RS=1.237E3 AF=1 KF=1.3772E-15) .MODEL DIN D(IS=1E-12 RS=5.7483E3 AF=1 KF=7.7505E-15) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS AD743A * AD743B SPICE Macro-model 4/92, Rev. A * AAG / PMI * * This version of the AD743 multiplier model simulates the worst case * parameters of the 'B' grade. The worst case parameters used * correspond to those in the data sheet. * * Copyright 1992 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD743B 1 2 99 50 37 * * INPUT STAGE & POLE AT 65 MHz * IOS 1 2 DC 37.5E-12 CIN 1 2 20E-12 EOS 9 3 POLY(1) 16 31 250E-6 1 EN 3 1 41 0 1 J1 5 2 4 PJX J2 6 9 4 PJX R3 5 51 0.9323 R4 6 51 0.9323 C2 5 6 1.3132E-9 I1 97 4 100E-3 EPOS 97 0 99 0 1 ENEG 51 0 50 0 1 GN1 0 1 44 0 1E-6 GN2 0 2 47 0 1E-6 * * INPUT NOISE VOLTAGE GENERATOR * VN1 40 0 DC 2 DN1 40 41 DEN DN2 41 42 DEN VN2 0 42 DC 2 * * INPUT NOISE CURRENT GENERATOR FOR IN+ * VN3 43 0 DC 2 DN3 43 44 DIN DN4 44 45 DIN VN4 0 45 DC 2 * * INPUT NOISE CURRENT GENERATOR FOR IN- * VN5 46 0 DC 2 DN5 46 47 DIN DN6 47 48 DIN VN6 0 48 DC 2 * * GAIN STAGE & DOMINANT POLE AT 2.39 Hz * EREF 98 0 31 0 1 G1 98 12 5 6 1.0726 R5 12 98 1.8646E6 C3 12 98 35.714E-9 V1 99 13 DC 0.8 D1 12 13 DX V2 14 50 DC 2 D4 14 12 DX * * CMR Network with Zero at 2.388 kHz * ECM 15 98 POLY(2) 1 31 2 31 (0,15.812,15.812) RCM1 15 16 1 CCM 15 16 6.663E-5 RCM2 16 98 1E-6 * * NEGATIVE ZERO AT -19.5 MHz * ENZ 17 98 12 31 1E6 RNZ1 17 18 1 CNZ 17 18 -8.1618E-9 RNZ2 18 98 1E-6 * * POLE-ZERO PAIR AT 330 kHz/690 kHz * GPZ 98 19 18 31 1 RPZ1 19 98 1 RPZ2 19 20 0.91667 CPZ 20 98 251.63E-9 * * POLE AT 65 MHz * G2 98 21 19 31 1 R10 21 98 1 C5 21 98 2.4485E-9 * * OUTPUT STAGE * VWIRE 21 30 0 * IDC 99 50 DC 9.7E-3 RDC1 99 31 50E3 CDC 31 0 1E-12 RDC2 31 50 50E3 DO1 99 32 DX GO1 32 50 36 30 5.5556E-3 DO2 50 32 DY DO3 99 33 DX GO2 33 50 30 36 5.5556E-3 DO4 50 33 DY VSC1 34 36 3.1 DSC1 30 34 DX VSC2 36 35 2.66 DSC2 35 30 DX GO3 36 99 99 30 5.5556E-3 GO4 50 36 30 50 5.5556E-3 FO1 36 0 VSC1 1 FO2 0 36 VSC2 1 RO1 99 36 180 RO2 36 50 180 LO 36 37 250E-9 * * MODELS USED * .MODEL PJX PJF(VTO=-2 BETA=5.7526 IS=250E-12) .MODEL DEN D(IS=1E-12 RS=1.237E3 AF=1 KF=1.3772E-15) .MODEL DIN D(IS=1E-12 RS=5.7483E3 AF=1 KF=7.7505E-15) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS AD743B * AD743J SPICE Macro-model 4/92, Rev. A * AAG / PMI * * This version of the AD743 multiplier model simulates the worst case * parameters of the 'J' grade. The worst case parameters used * correspond to those in the data sheet. * * Copyright 1992 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD743J 1 2 99 50 37 * * INPUT STAGE & POLE AT 65 MHz * IOS 1 2 DC 75E-12 CIN 1 2 20E-12 EOS 9 3 POLY(1) 16 31 1E-3 1 EN 3 1 41 0 1 J1 5 2 4 PJX J2 6 9 4 PJX R3 5 51 0.9323 R4 6 51 0.9323 C2 5 6 1.3132E-9 I1 97 4 100E-3 EPOS 97 0 99 0 1 ENEG 51 0 50 0 1 GN1 0 1 44 0 1E-6 GN2 0 2 47 0 1E-6 * * INPUT NOISE VOLTAGE GENERATOR * VN1 40 0 DC 2 DN1 40 41 DEN DN2 41 42 DEN VN2 0 42 DC 2 * * INPUT NOISE CURRENT GENERATOR FOR IN+ * VN3 43 0 DC 2 DN3 43 44 DIN DN4 44 45 DIN VN4 0 45 DC 2 * * INPUT NOISE CURRENT GENERATOR FOR IN- * VN5 46 0 DC 2 DN5 46 47 DIN DN6 47 48 DIN VN6 0 48 DC 2 * * GAIN STAGE & DOMINANT POLE AT 4.78 Hz * EREF 98 0 31 0 1 G1 98 12 5 6 1.0726 R5 12 98 9.32314E5 C3 12 98 35.714E-9 V1 99 13 DC 0.8 D1 12 13 DX V2 14 50 DC 2 D4 14 12 DX * * CMR Network with Zero at 7.554 kHz * ECM 15 98 POLY(2) 1 31 2 31 (0,50,50) RCM1 15 16 1 CCM 15 16 2.107E-5 RCM2 16 98 1E-6 * * NEGATIVE ZERO AT -19.5 MHz * ENZ 17 98 12 31 1E6 RNZ1 17 18 1 CNZ 17 18 -8.1618E-9 RNZ2 18 98 1E-6 * * POLE-ZERO PAIR AT 330 kHz/690 kHz * GPZ 98 19 18 31 1 RPZ1 19 98 1 RPZ2 19 20 0.91667 CPZ 20 98 251.63E-9 * * POLE AT 65 MHz * G2 98 21 19 31 1 R10 21 98 1 C5 21 98 2.4485E-9 * * OUTPUT STAGE * VWIRE 21 30 0 * IDC 99 50 DC 9.7E-3 RDC1 99 31 50E3 CDC 31 0 1E-12 RDC2 31 50 50E3 DO1 99 32 DX GO1 32 50 36 30 5.5556E-3 DO2 50 32 DY DO3 99 33 DX GO2 33 50 30 36 5.5556E-3 DO4 50 33 DY VSC1 34 36 3.1 DSC1 30 34 DX VSC2 36 35 2.66 DSC2 35 30 DX GO3 36 99 99 30 5.5556E-3 GO4 50 36 30 50 5.5556E-3 FO1 36 0 VSC1 1 FO2 0 36 VSC2 1 RO1 99 36 180 RO2 36 50 180 LO 36 37 250E-9 * * MODELS USED * .MODEL PJX PJF(VTO=-2 BETA=5.7526 IS=400E-12) .MODEL DEN D(IS=1E-12 RS=1.237E3 AF=1 KF=1.3772E-15) .MODEL DIN D(IS=1E-12 RS=5.7483E3 AF=1 KF=7.7505E-15) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS AD743J * AD743K SPICE Macro-model 4/92, Rev. A * AAG / PMI * * This version of the AD743 multiplier model simulates the worst case * parameters of the 'K' grade. The worst case parameters used * correspond to those in the data sheet. * * Copyright 1992 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD743K 1 2 99 50 37 * * INPUT STAGE & POLE AT 65 MHz * IOS 1 2 DC 37.5E-12 CIN 1 2 20E-12 EOS 9 3 POLY(1) 16 31 500E-6 1 EN 3 1 41 0 1 J1 5 2 4 PJX J2 6 9 4 PJX R3 5 51 0.9323 R4 6 51 0.9323 C2 5 6 1.3132E-9 I1 97 4 100E-3 EPOS 97 0 99 0 1 ENEG 51 0 50 0 1 GN1 0 1 44 0 1E-6 GN2 0 2 47 0 1E-6 * * INPUT NOISE VOLTAGE GENERATOR * VN1 40 0 DC 2 DN1 40 41 DEN DN2 41 42 DEN VN2 0 42 DC 2 * * INPUT NOISE CURRENT GENERATOR FOR IN+ * VN3 43 0 DC 2 DN3 43 44 DIN DN4 44 45 DIN VN4 0 45 DC 2 * * INPUT NOISE CURRENT GENERATOR FOR IN- * VN5 46 0 DC 2 DN5 46 47 DIN DN6 47 48 DIN VN6 0 48 DC 2 * * GAIN STAGE & DOMINANT POLE AT 2.39 Hz * EREF 98 0 31 0 1 G1 98 12 5 6 1.0726 R5 12 98 1.8646E6 C3 12 98 35.714E-9 V1 99 13 DC 0.8 D1 12 13 DX V2 14 50 DC 2 D4 14 12 DX * * CMR Network with Zero at 2.388 kHz * ECM 15 98 POLY(2) 1 31 2 31 (0,15.812,15.812) RCM1 15 16 1 CCM 15 16 6.663E-5 RCM2 16 98 1E-6 * * NEGATIVE ZERO AT -19.5 MHz * ENZ 17 98 12 31 1E6 RNZ1 17 18 1 CNZ 17 18 -8.1618E-9 RNZ2 18 98 1E-6 * * POLE-ZERO PAIR AT 330 kHz/690 kHz * GPZ 98 19 18 31 1 RPZ1 19 98 1 RPZ2 19 20 0.91667 CPZ 20 98 251.63E-9 * * POLE AT 65 MHz * G2 98 21 19 31 1 R10 21 98 1 C5 21 98 2.4485E-9 * * OUTPUT STAGE * VWIRE 21 30 0 * IDC 99 50 DC 9.7E-3 RDC1 99 31 50E3 CDC 31 0 1E-12 RDC2 31 50 50E3 DO1 99 32 DX GO1 32 50 36 30 5.5556E-3 DO2 50 32 DY DO3 99 33 DX GO2 33 50 30 36 5.5556E-3 DO4 50 33 DY VSC1 34 36 3.1 DSC1 30 34 DX VSC2 36 35 2.66 DSC2 35 30 DX GO3 36 99 99 30 5.5556E-3 GO4 50 36 30 50 5.5556E-3 FO1 36 0 VSC1 1 FO2 0 36 VSC2 1 RO1 99 36 180 RO2 36 50 180 LO 36 37 250E-9 * * MODELS USED * .MODEL PJX PJF(VTO=-2 BETA=5.7526 IS=250E-12) .MODEL DEN D(IS=1E-12 RS=1.237E3 AF=1 KF=1.3772E-15) .MODEL DIN D(IS=1E-12 RS=5.7483E3 AF=1 KF=7.7505E-15) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS AD743K * AD743S SPICE Macro-model 4/92, Rev. A * AAG / PMI * * This version of the AD743 multiplier model simulates the worst case * parameters of the 'S' grade. The worst case parameters used * correspond to those in the data sheet. * * Copyright 1992 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD743S 1 2 99 50 37 * * INPUT STAGE & POLE AT 65 MHz * IOS 1 2 DC 75E-12 CIN 1 2 20E-12 EOS 9 3 POLY(1) 16 31 1E-3 1 EN 3 1 41 0 1 J1 5 2 4 PJX J2 6 9 4 PJX R3 5 51 0.9323 R4 6 51 0.9323 C2 5 6 1.3132E-9 I1 97 4 100E-3 EPOS 97 0 99 0 1 ENEG 51 0 50 0 1 GN1 0 1 44 0 1E-6 GN2 0 2 47 0 1E-6 * * INPUT NOISE VOLTAGE GENERATOR * VN1 40 0 DC 2 DN1 40 41 DEN DN2 41 42 DEN VN2 0 42 DC 2 * * INPUT NOISE CURRENT GENERATOR FOR IN+ * VN3 43 0 DC 2 DN3 43 44 DIN DN4 44 45 DIN VN4 0 45 DC 2 * * INPUT NOISE CURRENT GENERATOR FOR IN- * VN5 46 0 DC 2 DN5 46 47 DIN DN6 47 48 DIN VN6 0 48 DC 2 * * GAIN STAGE & DOMINANT POLE AT 4.78 Hz * EREF 98 0 31 0 1 G1 98 12 5 6 1.0726 R5 12 98 9.32314E5 C3 12 98 35.714E-9 V1 99 13 DC 0.8 D1 12 13 DX V2 14 50 DC 2 D4 14 12 DX * * CMR Network with Zero at 7.554 kHz * ECM 15 98 POLY(2) 1 31 2 31 (0,50,50) RCM1 15 16 1 CCM 15 16 2.107E-5 RCM2 16 98 1E-6 * * NEGATIVE ZERO AT -19.5 MHz * ENZ 17 98 12 31 1E6 RNZ1 17 18 1 CNZ 17 18 -8.1618E-9 RNZ2 18 98 1E-6 * * POLE-ZERO PAIR AT 330 kHz/690 kHz * GPZ 98 19 18 31 1 RPZ1 19 98 1 RPZ2 19 20 0.91667 CPZ 20 98 251.63E-9 * * POLE AT 65 MHz * G2 98 21 19 31 1 R10 21 98 1 C5 21 98 2.4485E-9 * * OUTPUT STAGE * VWIRE 21 30 0 * IDC 99 50 DC 9.7E-3 RDC1 99 31 50E3 CDC 31 0 1E-12 RDC2 31 50 50E3 DO1 99 32 DX GO1 32 50 36 30 5.5556E-3 DO2 50 32 DY DO3 99 33 DX GO2 33 50 30 36 5.5556E-3 DO4 50 33 DY VSC1 34 36 3.1 DSC1 30 34 DX VSC2 36 35 2.66 DSC2 35 30 DX GO3 36 99 99 30 5.5556E-3 GO4 50 36 30 50 5.5556E-3 FO1 36 0 VSC1 1 FO2 0 36 VSC2 1 RO1 99 36 180 RO2 36 50 180 LO 36 37 250E-9 * * MODELS USED * .MODEL PJX PJF(VTO=-2 BETA=5.7526 IS=400E-12) .MODEL DEN D(IS=1E-12 RS=1.237E3 AF=1 KF=1.3772E-15) .MODEL DIN D(IS=1E-12 RS=5.7483E3 AF=1 KF=7.7505E-15) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS AD743S * AD745A SPICE Macro-model 10/95, Rev. B * ARG / ADSC * * This version of the AD745 model simulates the worst-case * parameters of the 'A' grade. The worst-case parameters * used correspond to those in the data sheet. * * * Revision History: * Rev. B * Changed the negative zero circuit to correspond to the new design * which eliminates the negative capacitor value. * * * Copyright 1992 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License * Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD745A 3 2 99 50 37 * * INPUT STAGE AND POLE AT 54MHZ * I1 97 1 1 J1 5 2 1 JX J2 6 4 1 JX CIN 2 3 20E-12 IOS 3 2 75E-12 EN 7 3 9 0 1 GN1 0 2 12 0 1E-6 GN2 0 3 15 0 1E-6 EOS 4 7 POLY(1) 31 52 800E-6 1 R1 5 51 86.842E-3 R2 6 51 86.842E-3 C1 5 6 16.969E-9 EPOS 97 0 99 0 1 ENEG 51 0 50 0 1 EREF 98 0 52 0 1 * * VOLTAGE NOISE SOURCE WITH FLICKER NOISE * VN1 8 0 DC 2 VN2 0 10 DC 2 DN1 8 9 DEN DN2 9 10 DEN * * CURRENT NOISE SOURCE WITH FLICKER NOISE * VN3 11 0 DC 10 VN4 0 13 DC 10 DN3 11 12 DIN DN4 12 13 DIN * * CURRENT NOISE SOURCE WITH FLICKER NOISE * VN5 14 0 DC 10 VN6 0 16 DC 10 DN5 14 15 DIN DN6 15 16 DIN * * GAIN STAGE AND DOMINANT POLE AT 22.9HZ * R3 17 98 86.842E3 C2 17 98 80E-9 G1 98 17 5 6 11.515 V1 97 18 .727 V2 19 51 1.893 D1 17 18 DX D2 19 17 DX * * POLE AT 30MHZ * R4 23 98 1 C3 23 98 5.305E-9 G2 98 23 17 52 1 * * POLE AT 30MHZ * R5 24 98 1 C4 24 98 5.305E-9 G3 98 24 23 52 1 * * NEGATIVE ZERO AT -54MHZ * R6 25 26 1 R7 26 98 1E-6 E1 25 98 24 52 1E6 VX1 84 0 DC 0 EX1 83 0 25 26 1 FX1 25 26 VX1 -1 CX1 83 84 2.947E-9 * * POLE / ZERO AT 2MHZ / 2.25MHZ * R8 27 98 1 R9 27 28 8 C6 28 98 8.842E-9 G4 98 27 26 52 1 * * COMMON MODE GAIN STAGE WITH ZERO AT 126KHZ * E2 29 30 2 52 0.5 E3 30 98 3 52 0.5 R10 29 31 1 R11 31 98 100E-6 C7 29 31 1.264E-6 * * REFERENCE NODE AND OUTPUT STAGE * RMP1 97 52 1 RMP2 52 51 1 GSY 99 50 POLY(1) 99 50 9.625E-3 12.5E-6 R13 99 36 200 R14 36 50 200 L1 36 37 1E-10 G5 34 50 27 36 5E-3 G6 35 50 36 27 5E-3 G7 36 99 99 27 5E-3 G8 50 36 27 50 5E-3 V3 32 36 1.55 V4 36 33 1.55 D3 27 32 DX D4 33 27 DX D5 99 34 DX D6 99 35 DX D7 50 34 DY D8 50 35 DY F1 36 0 V3 1 F2 0 36 V4 1 * * MODELS USED * .MODEL JX PJF(BETA=66.299, VTO=-1.5 IS=400E-12) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15, BV=50) .MODEL DEN D(RS=1.931E3, KF=2.278E-15, AF=1) .MODEL DIN D(RS=5.277E3, KF=42.593E-15, AF=1) .ENDS AD745A * AD745B SPICE Macro-model 10/95, Rev. B * ARG / ADSC * * This version of the AD745 model simulates the worst-case * parameters of the 'B' grade. The worst-case parameters * used correspond to those in the data sheet. * * * Revision History: * Rev. B * Changed the negative zero circuit to correspond to the new design * which eliminates the negative capacitor value. * * * Copyright 1992 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License * Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD745B 3 2 99 50 37 * * INPUT STAGE AND POLE AT 54MHZ * I1 97 1 1 J1 5 2 1 JX J2 6 4 1 JX CIN 2 3 20E-12 IOS 3 2 37.5E-12 EN 7 3 9 0 1 GN1 0 2 12 0 1E-6 GN2 0 3 15 0 1E-6 EOS 4 7 POLY(1) 31 52 250E-6 1 R1 5 51 86.842E-3 R2 6 51 86.842E-3 C1 5 6 16.969E-9 EPOS 97 0 99 0 1 ENEG 51 0 50 0 1 EREF 98 0 52 0 1 * * VOLTAGE NOISE SOURCE WITH FLICKER NOISE * VN1 8 0 DC 2 VN2 0 10 DC 2 DN1 8 9 DEN DN2 9 10 DEN * * CURRENT NOISE SOURCE WITH FLICKER NOISE * VN3 11 0 DC 10 VN4 0 13 DC 10 DN3 11 12 DIN DN4 12 13 DIN * * CURRENT NOISE SOURCE WITH FLICKER NOISE * VN5 14 0 DC 10 VN6 0 16 DC 10 DN5 14 15 DIN DN6 15 16 DIN * * GAIN STAGE AND DOMINANT POLE AT 11.45HZ * R3 17 98 173.684E3 C2 17 98 80E-9 G1 98 17 5 6 11.515 V1 97 18 .727 V2 19 51 1.893 D1 17 18 DX D2 19 17 DX * * POLE AT 30MHZ * R4 23 98 1 C3 23 98 5.305E-9 G2 98 23 17 52 1 * * POLE AT 30MHZ * R5 24 98 1 C4 24 98 5.305E-9 G3 98 24 23 52 1 * * NEGATIVE ZERO AT -54MHZ * R6 25 26 1 R7 26 98 1E-6 E1 25 98 24 52 1E6 VX1 84 0 DC 0 EX1 83 0 25 26 1 FX1 25 26 VX1 -1 CX1 83 84 2.947E-9 * * POLE / ZERO AT 2MHZ / 2.25MHZ * R8 27 98 1 R9 27 28 8 C6 28 98 8.842E-9 G4 98 27 26 52 1 * * COMMON MODE GAIN STAGE WITH ZERO AT 39.8KHZ * E2 29 30 2 52 0.5 E3 30 98 3 52 0.5 R10 29 31 1 R11 31 98 31.623E-6 C7 29 31 3.998E-6 * * REFERENCE NODE AND OUTPUT STAGE * RMP1 97 52 1 RMP2 52 51 1 GSY 99 50 POLY(1) 99 50 9.625E-3 12.5E-6 R13 99 36 200 R14 36 50 200 L1 36 37 1E-10 G5 34 50 27 36 5E-3 G6 35 50 36 27 5E-3 G7 36 99 99 27 5E-3 G8 50 36 27 50 5E-3 V3 32 36 1.55 V4 36 33 1.55 D3 27 32 DX D4 33 27 DX D5 99 34 DX D6 99 35 DX D7 50 34 DY D8 50 35 DY F1 36 0 V3 1 F2 0 36 V4 1 * * MODELS USED * .MODEL JX PJF(BETA=66.299, VTO=-1.5 IS=250E-12) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15, BV=50) .MODEL DEN D(RS=1.931E3, KF=2.278E-15, AF=1) .MODEL DIN D(RS=5.277E3, KF=42.593E-15, AF=1) .ENDS AD745B * AD745J SPICE Macro-model 10/95, Rev. B * ARG / ADSC * * This version of the AD745 model simulates the worst-case * parameters of the 'J' grade. The worst-case parameters * used correspond to those in the data sheet. * * * Revision History: * Rev. B * Changed the negative zero circuit to correspond to the new design * which eliminates the negative capacitor value. * * * Copyright 1992 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License * Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD745J 3 2 99 50 37 * * INPUT STAGE AND POLE AT 54MHZ * I1 97 1 1 J1 5 2 1 JX J2 6 4 1 JX CIN 2 3 20E-12 IOS 3 2 75E-12 EN 7 3 9 0 1 GN1 0 2 12 0 1E-6 GN2 0 3 15 0 1E-6 EOS 4 7 POLY(1) 31 52 1E-3 1 R1 5 51 86.842E-3 R2 6 51 86.842E-3 C1 5 6 16.969E-9 EPOS 97 0 99 0 1 ENEG 51 0 50 0 1 EREF 98 0 52 0 1 * * VOLTAGE NOISE SOURCE WITH FLICKER NOISE * VN1 8 0 DC 2 VN2 0 10 DC 2 DN1 8 9 DEN DN2 9 10 DEN * * CURRENT NOISE SOURCE WITH FLICKER NOISE * VN3 11 0 DC 10 VN4 0 13 DC 10 DN3 11 12 DIN DN4 12 13 DIN * * CURRENT NOISE SOURCE WITH FLICKER NOISE * VN5 14 0 DC 10 VN6 0 16 DC 10 DN5 14 15 DIN DN6 15 16 DIN * * GAIN STAGE AND DOMINANT POLE AT 22.9HZ * R3 17 98 86.842E3 C2 17 98 80E-9 G1 98 17 5 6 11.515 V1 97 18 .727 V2 19 51 1.893 D1 17 18 DX D2 19 17 DX * * POLE AT 30MHZ * R4 23 98 1 C3 23 98 5.305E-9 G2 98 23 17 52 1 * * POLE AT 30MHZ * R5 24 98 1 C4 24 98 5.305E-9 G3 98 24 23 52 1 * * NEGATIVE ZERO AT -54MHZ * R6 25 26 1 R7 26 98 1E-6 E1 25 98 24 52 1E6 VX1 84 0 DC 0 EX1 83 0 25 26 1 FX1 25 26 VX1 -1 CX1 83 84 2.947E-9 * * POLE / ZERO AT 2MHZ / 2.25MHZ * R8 27 98 1 R9 27 28 8 C6 28 98 8.842E-9 G4 98 27 26 52 1 * * COMMON MODE GAIN STAGE WITH ZERO AT 126KHZ * E2 29 30 2 52 0.5 E3 30 98 3 52 0.5 R10 29 31 1 R11 31 98 100E-6 C7 29 31 1.264E-6 * * REFERENCE NODE AND OUTPUT STAGE * RMP1 97 52 1 RMP2 52 51 1 GSY 99 50 POLY(1) 99 50 9.625E-3 12.5E-6 R13 99 36 200 R14 36 50 200 L1 36 37 1E-10 G5 34 50 27 36 5E-3 G6 35 50 36 27 5E-3 G7 36 99 99 27 5E-3 G8 50 36 27 50 5E-3 V3 32 36 1.55 V4 36 33 1.55 D3 27 32 DX D4 33 27 DX D5 99 34 DX D6 99 35 DX D7 50 34 DY D8 50 35 DY F1 36 0 V3 1 F2 0 36 V4 1 * * MODELS USED * .MODEL JX PJF(BETA=66.299, VTO=-1.5 IS=400E-12) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15, BV=50) .MODEL DEN D(RS=1.931E3, KF=2.278E-15, AF=1) .MODEL DIN D(RS=5.277E3, KF=42.593E-15, AF=1) .ENDS AD745J * AD745K SPICE Macro-model 10/95, Rev. B * ARG / ADSC * * This version of the AD745 model simulates the worst-case * parameters of the 'K' grade. The worst-case parameters * used correspond to those in the data sheet. * * * Revision History: * Rev. B * Changed the negative zero circuit to correspond to the new design * which eliminates the negative capacitor value. * * * Copyright 1992 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License * Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD745K 3 2 99 50 37 * * INPUT STAGE AND POLE AT 54MHZ * I1 97 1 1 J1 5 2 1 JX J2 6 4 1 JX CIN 2 3 20E-12 IOS 3 2 37.5E-12 EN 7 3 9 0 1 GN1 0 2 12 0 1E-6 GN2 0 3 15 0 1E-6 EOS 4 7 POLY(1) 31 52 500E-6 1 R1 5 51 86.842E-3 R2 6 51 86.842E-3 C1 5 6 16.969E-9 EPOS 97 0 99 0 1 ENEG 51 0 50 0 1 EREF 98 0 52 0 1 * * VOLTAGE NOISE SOURCE WITH FLICKER NOISE * VN1 8 0 DC 2 VN2 0 10 DC 2 DN1 8 9 DEN DN2 9 10 DEN * * CURRENT NOISE SOURCE WITH FLICKER NOISE * VN3 11 0 DC 10 VN4 0 13 DC 10 DN3 11 12 DIN DN4 12 13 DIN * * CURRENT NOISE SOURCE WITH FLICKER NOISE * VN5 14 0 DC 10 VN6 0 16 DC 10 DN5 14 15 DIN DN6 15 16 DIN * * GAIN STAGE AND DOMINANT POLE AT 11.45HZ * R3 17 98 173.684E3 C2 17 98 80E-9 G1 98 17 5 6 11.515 V1 97 18 .727 V2 19 51 1.893 D1 17 18 DX D2 19 17 DX * * POLE AT 30MHZ * R4 23 98 1 C3 23 98 5.305E-9 G2 98 23 17 52 1 * * POLE AT 30MHZ * R5 24 98 1 C4 24 98 5.305E-9 G3 98 24 23 52 1 * * NEGATIVE ZERO AT -54MHZ * R6 25 26 1 R7 26 98 1E-6 E1 25 98 24 52 1E6 VX1 84 0 DC 0 EX1 83 0 25 26 1 FX1 25 26 VX1 -1 CX1 83 84 2.947E-9 * * POLE / ZERO AT 2MHZ / 2.25MHZ * R8 27 98 1 R9 27 28 8 C6 28 98 8.842E-9 G4 98 27 26 52 1 * * COMMON MODE GAIN STAGE WITH ZERO AT 39.8KHZ * E2 29 30 2 52 0.5 E3 30 98 3 52 0.5 R10 29 31 1 R11 31 98 31.623E-6 C7 29 31 3.998E-6 * * REFERENCE NODE AND OUTPUT STAGE * RMP1 97 52 1 RMP2 52 51 1 GSY 99 50 POLY(1) 99 50 9.625E-3 12.5E-6 R13 99 36 200 R14 36 50 200 L1 36 37 1E-10 G5 34 50 27 36 5E-3 G6 35 50 36 27 5E-3 G7 36 99 99 27 5E-3 G8 50 36 27 50 5E-3 V3 32 36 1.55 V4 36 33 1.55 D3 27 32 DX D4 33 27 DX D5 99 34 DX D6 99 35 DX D7 50 34 DY D8 50 35 DY F1 36 0 V3 1 F2 0 36 V4 1 * * MODELS USED * .MODEL JX PJF(BETA=66.299, VTO=-1.5 IS=250E-12) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15, BV=50) .MODEL DEN D(RS=1.931E3, KF=2.278E-15, AF=1) .MODEL DIN D(RS=5.277E3, KF=42.593E-15, AF=1) .ENDS AD745K * AD745S SPICE Macro-model 10/95, Rev. B * ARG / ADSC * * This version of the AD745 model simulates the worst-case * parameters of the 'S' grade. The worst-case parameters * used correspond to those in the data sheet. * * * Revision History: * Rev. B * Changed the negative zero circuit to correspond to the new design * which eliminates the negative capacitor value. * * * Copyright 1992 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License * Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD745S 3 2 99 50 37 * * INPUT STAGE AND POLE AT 54MHZ * I1 97 1 1 J1 5 2 1 JX J2 6 4 1 JX CIN 2 3 20E-12 IOS 3 2 75E-12 EN 7 3 9 0 1 GN1 0 2 12 0 1E-6 GN2 0 3 15 0 1E-6 EOS 4 7 POLY(1) 31 52 1E-3 1 R1 5 51 86.842E-3 R2 6 51 86.842E-3 C1 5 6 16.969E-9 EPOS 97 0 99 0 1 ENEG 51 0 50 0 1 EREF 98 0 52 0 1 * * VOLTAGE NOISE SOURCE WITH FLICKER NOISE * VN1 8 0 DC 2 VN2 0 10 DC 2 DN1 8 9 DEN DN2 9 10 DEN * * CURRENT NOISE SOURCE WITH FLICKER NOISE * VN3 11 0 DC 10 VN4 0 13 DC 10 DN3 11 12 DIN DN4 12 13 DIN * * CURRENT NOISE SOURCE WITH FLICKER NOISE * VN5 14 0 DC 10 VN6 0 16 DC 10 DN5 14 15 DIN DN6 15 16 DIN * * GAIN STAGE AND DOMINANT POLE AT 22.9HZ * R3 17 98 86.842E3 C2 17 98 80E-9 G1 98 17 5 6 11.515 V1 97 18 .727 V2 19 51 1.893 D1 17 18 DX D2 19 17 DX * * POLE AT 30MHZ * R4 23 98 1 C3 23 98 5.305E-9 G2 98 23 17 52 1 * * POLE AT 30MHZ * R5 24 98 1 C4 24 98 5.305E-9 G3 98 24 23 52 1 * * NEGATIVE ZERO AT -54MHZ * R6 25 26 1 R7 26 98 1E-6 E1 25 98 24 52 1E6 VX1 84 0 DC 0 EX1 83 0 25 26 1 FX1 25 26 VX1 -1 CX1 83 84 2.947E-9 * * POLE / ZERO AT 2MHZ / 2.25MHZ * R8 27 98 1 R9 27 28 8 C6 28 98 8.842E-9 G4 98 27 26 52 1 * * COMMON MODE GAIN STAGE WITH ZERO AT 126KHZ * E2 29 30 2 52 0.5 E3 30 98 3 52 0.5 R10 29 31 1 R11 31 98 100E-6 C7 29 31 1.264E-6 * * REFERENCE NODE AND OUTPUT STAGE * RMP1 97 52 1 RMP2 52 51 1 GSY 99 50 POLY(1) 99 50 9.625E-3 12.5E-6 R13 99 36 200 R14 36 50 200 L1 36 37 1E-10 G5 34 50 27 36 5E-3 G6 35 50 36 27 5E-3 G7 36 99 99 27 5E-3 G8 50 36 27 50 5E-3 V3 32 36 1.55 V4 36 33 1.55 D3 27 32 DX D4 33 27 DX D5 99 34 DX D6 99 35 DX D7 50 34 DY D8 50 35 DY F1 36 0 V3 1 F2 0 36 V4 1 * * MODELS USED * .MODEL JX PJF(BETA=66.299, VTO=-1.5 IS=400E-12) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15, BV=50) .MODEL DEN D(RS=1.931E3, KF=2.278E-15, AF=1) .MODEL DIN D(RS=5.277E3, KF=42.593E-15, AF=1) .ENDS AD745S * AD746A SPICE Macro-model 1/91, Rev. A * JLW / PMI * * This version of the AD746 model simulates the worst case * parameters of the 'A' grade. The worst case parameters * used correspond to those in the device data sheet. * * * Copyright 1991 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | .subckt AD746A 11 14 10 16 13 * VOS 14 7 DC 1.5E-3 EC 8 0 13 0 1 C1 5 6 0.33E-12 GB 12 0 15 0 1.67E3 RD1 5 16 16E3 RD2 6 16 16E3 ISS 10 1 DC 100E-6 GCM 0 15 0 1 1.76E-9 GA 15 0 6 5 1.4E-3 RE 1 0 2.5E6 RGM 15 0 1.1E3 VC 10 2 DC 2.8 VE 9 16 DC 3.1 RO1 12 13 25 CE 1 0 1E-12 RO2 0 12 30 RS1 1 3 5.77E3 RS2 1 4 5.77E3 CCI 15 12 40E-12 RP 16 10 6.13E3 J1 5 11 3 FET J2 6 7 4 FET DC 13 2 DIODE DE 9 13 DIODE DP 16 10 DIODE D1 8 12 DIODE D2 12 8 DIODE IOS 14 11 62.5E-12 .MODEL DIODE D() .MODEL FET PJF(VTO=-1 BETA=1E-3 IS=250E-12) .ENDS * AD746B SPICE Macro-model 1/91, Rev. A * JLW / PMI * * This version of the AD746 model simulates the worst case * parameters of the 'B' grade. The worst case parameters * used correspond to those in the device data sheet. * * * Copyright 1991 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | .subckt AD746B 11 14 10 16 13 * VOS 14 7 DC 0.5E-3 EC 8 0 13 0 1 C1 5 6 0.33E-12 GB 12 0 15 0 1.67E3 RD1 5 16 16E3 RD2 6 16 16E3 ISS 10 1 DC 100E-6 GCM 0 15 0 1 1.76E-9 GA 15 0 6 5 1.63E-3 RE 1 0 2.5E6 RGM 15 0 1.1E3 VC 10 2 DC 2.8 VE 9 16 DC 3.1 RO1 12 13 25 CE 1 0 1E-12 RO2 0 12 30 RS1 1 3 5.77E3 RS2 1 4 5.77E3 CCI 15 12 40E-12 RP 16 10 7.69E3 J1 5 11 3 FET J2 6 7 4 FET DC 13 2 DIODE DE 9 13 DIODE DP 16 10 DIODE D1 8 12 DIODE D2 12 8 DIODE IOS 14 11 37.5E-12 .MODEL DIODE D() .MODEL FET PJF(VTO=-1 BETA=1E-3 IS=150E-12) .ENDS * AD746J SPICE Macro-model 1/91, Rev. A * JLW / PMI * * This version of the AD746 model simulates the worst case * parameters of the 'J' grade. The worst case parameters * used correspond to those in the device data sheet. * * * Copyright 1991 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | .subckt AD746J 11 14 10 16 13 * VOS 14 7 DC 1.5E-3 EC 8 0 13 0 1 C1 5 6 0.33E-12 GB 12 0 15 0 1.67E3 RD1 5 16 16E3 RD2 6 16 16E3 ISS 10 1 DC 100E-6 GCM 0 15 0 1 1.76E-9 GA 15 0 6 5 1.4E-3 RE 1 0 2.5E6 RGM 15 0 1.1E3 VC 10 2 DC 2.8 VE 9 16 DC 3.1 RO1 12 13 25 CE 1 0 1E-12 RO2 0 12 30 RS1 1 3 5.77E3 RS2 1 4 5.77E3 CCI 15 12 40E-12 RP 16 10 6.13E3 J1 5 11 3 FET J2 6 7 4 FET DC 13 2 DIODE DE 9 13 DIODE DP 16 10 DIODE D1 8 12 DIODE D2 12 8 DIODE IOS 14 11 62.5E-12 .MODEL DIODE D() .MODEL FET PJF(VTO=-1 BETA=1E-3 IS=250E-12) .ENDS * AD746S SPICE Macro-model 1/91, Rev. A * JLW / PMI * * This version of the AD746 model simulates the worst case * parameters of the 'S' grade. The worst case parameters * used correspond to those in the device data sheet. * * * Copyright 1991 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | .subckt AD746S 11 14 10 16 13 * VOS 14 7 DC 1E-3 EC 8 0 13 0 1 C1 5 6 0.33E-12 GB 12 0 15 0 1.67E3 RD1 5 16 16E3 RD2 6 16 16E3 ISS 10 1 DC 100E-6 GCM 0 15 0 1 1.76E-9 GA 15 0 6 5 1.4E-3 RE 1 0 2.5E6 RGM 15 0 1.1E3 VC 10 2 DC 2.8 VE 9 16 DC 3.1 RO1 12 13 25 CE 1 0 1E-12 RO2 0 12 30 RS1 1 3 5.77E3 RS2 1 4 5.77E3 CCI 15 12 40E-12 RP 16 10 6.13E3 J1 5 11 3 FET J2 6 7 4 FET DC 13 2 DIODE DE 9 13 DIODE DP 16 10 DIODE D1 8 12 DIODE D2 12 8 DIODE IOS 14 11 62.5E-12 .MODEL DIODE D() .MODEL FET PJF(VTO=-1 BETA=1E-3 IS=250E-12) .ENDS * AD795J SPICE Macro-model 11/94, Rev. A * JOM / ADSC * * Revision History: * none * * This version of the AD795 model simulates the worst case * parameters of the 'J' grade. The worst case parameters * used correspond to those in the data sheet. * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD795J 1 2 99 50 30 * * INPUT STAGE & POLE AT 40 MHZ * R3 5 50 .719 R4 6 50 .719 CIN 1 2 2E-12 C2 5 6 1.3835E-9 I1 99 4 100E-3 IOS 1 2 1.00E-12 EOS 65 1 POLY(1) 17 24 500E-6 1 J1 5 2 4 JX J2 6 7 4 JX EN 7 65 43 0 1 GN1 0 1 47 0 1E-6 GN2 0 2 61 0 1E-6 GB1 2 50 POLY(3) 4,2 5,2 50,2 0 1E-12 1E-12 1E-12 GB2 7 50 POLY(3) 4,7 6,7 50,7 0 1E-12 1E-12 1E-12 * EREF 98 0 24 0 1 * * VOLTAGE NOISE GENERATOR * VN1 41 0 DC 2 RS1 41 42 11.8E3 RS2 42 43 1.2E9 CS1 42 43 79.8E-11 RS3 43 44 1.2E9 CS2 43 44 79.8E-11 RS4 44 45 11.8E3 VN2 0 45 DC 2 * * CURRENT NOISE GENERATOR * VN3 46 0 DC 2 RN5 46 47 144 RN6 47 48 144 VN4 0 48 DC 2 * * CURRENT NOISE GENERATOR * VN5 60 0 DC 2 RN7 60 61 144 RN8 61 62 144 VN6 0 62 DC 2 * * SECOND STAGE & POLE AT 7 HZ * R5 9 98 2.2737E5 C3 9 98 1.00E-7 G1 98 9 5 6 1.39 V2 99 8 4.525 V3 10 50 4.525 D1 9 8 DX D2 10 9 DX * * NEGATIVE ZERO AT 15 MHZ * R6 11 12 1E6 R7 12 98 1 E2 11 98 9 24 1E6 VX1 84 0 0 EX1 83 0 11 12 1 FX1 11 12 VX1 -1 CX1 83 84 10.6E-15 * * POLE AT 20 MHZ * R8 13 98 1E3 C5 13 98 7.96E-12 G2 98 13 12 24 1E-3 * * POLE AT 20 MHZ * R9 14 98 1E3 C6 14 98 7.96E-12 G3 98 14 13 24 1E-3 * * POLE AT 20 MHZ * R10 15 98 1E3 C7 15 98 7.96E-12 G4 98 15 14 24 1E-3 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 3000 HZ * R11 16 17 1E6 C8 16 17 5.3E-11 R12 17 98 1 E3 16 98 POLY(2) 1 98 2 98 0 15.848 15.848 * * POLE AT 20 MHZ * R13 18 98 1E3 C9 18 98 7.96E-12 G5 98 18 15 24 1E-3 * * OUTPUT STAGE * R14 24 99 2000E3 R15 24 50 2000E3 FSY 99 50 POLY(2) V7 V8 -98.5E-3 1 1 R16 29 99 360 R17 29 50 360 L1 29 30 1E-8 G8 29 99 99 18 2.78E-3 G9 50 29 18 50 2.78E-3 V4 25 29 2.0 V5 29 26 2.0 D3 18 25 DX D4 26 18 DX F1 29 0 V4 1 F2 0 29 V5 1 G6 98 70 29 18 2.78E-3 D5 70 71 DX D6 72 70 DX V7 71 98 DC 0 V8 98 72 DC 0 * * MODELS USED * .MODEL JX PJF(BETA=9.6605 VTO=-2.000 IS=1.5E-12 RD=0.1 + RS=0.1 CGD=1E-15 CGS=1E-15) .MODEL DX D(IS=1E-15 RS=10 CJO=1E-15) .ENDS AD795J * AD795K SPICE Macro-model 11/94, Rev. A * JOM / ADSC * * Revision History: * NONE * * This version of the AD795 model simulates the worst case * parameters of the 'K' grade. The worst case parameters * used correspond to those in the data sheet. * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD795K 1 2 99 50 30 * * INPUT STAGE & POLE AT 40 MHZ * R3 5 50 .719 R4 6 50 .719 CIN 1 2 2E-12 C2 5 6 1.3835E-9 I1 99 4 100E-3 IOS 1 2 0.5E-12 EOS 65 1 POLY(1) 17 24 250E-6 1 J1 5 2 4 JX J2 6 7 4 JX EN 7 65 43 0 1 GN1 0 1 47 0 1E-6 GN2 0 2 61 0 1E-6 GB1 2 50 POLY(3) 4,2 5,2 50,2 0 1E-12 1E-12 1E-12 GB2 7 50 POLY(3) 4,7 6,7 50,7 0 1E-12 1E-12 1E-12 * EREF 98 0 24 0 1 * * VOLTAGE NOISE GENERATOR * VN1 41 0 DC 2 RS1 41 42 11.8E3 RS2 42 43 1.2E9 CS1 42 43 100E-11 RS3 43 44 1.2E9 CS2 43 44 100E-11 RS4 44 45 11.8E3 VN2 0 45 DC 2 * * CURRENT NOISE GENERATOR * VN3 46 0 DC 2 RN5 46 47 75.4 RN6 47 48 75.4 VN4 0 48 DC 2 * * CURRENT NOISE GENERATOR * VN5 60 0 DC 2 RN7 60 61 75.4 RN8 61 62 75.4 VN6 0 62 DC 2 * * SECOND STAGE & POLE AT 7 HZ * R5 9 98 2.2737e5 C3 9 98 1.00E-7 G1 98 9 5 6 1.39 V2 99 8 4.525 V3 10 50 4.525 D1 9 8 DX D2 10 9 DX * * NEGATIVE ZERO AT 15 MHZ * R6 11 12 1E6 R7 12 98 1 E2 11 98 9 24 1E6 VX1 84 0 0 EX1 83 0 11 12 1 FX1 11 12 VX1 -1 CX1 83 84 10.6E-15 * * POLE AT 20 MHZ * R8 13 98 1E3 C5 13 98 7.96E-12 G2 98 13 12 24 1E-3 * * POLE AT 20 MHZ * R9 14 98 1E3 C6 14 98 7.96E-12 G3 98 14 13 24 1E-3 * * POLE AT 20 MHZ * R10 15 98 1E3 C7 15 98 7.96E-12 G4 98 15 14 24 1E-3 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 1900 HZ * R11 16 17 1E6 C8 16 17 8.37E-11 R12 17 98 1 E3 16 98 POLY(2) 1 98 2 98 0 10 10 * * POLE AT 20 MHZ * R13 18 98 1E3 C9 18 98 7.96E-12 G5 98 18 15 24 1E-3 * * OUTPUT STAGE * R14 24 99 2000E3 R15 24 50 2000E3 FSY 99 50 POLY(2) V7 V8 -98.7E-3 1 1 R16 29 99 360 R17 29 50 360 L1 29 30 1E-8 G8 29 99 99 18 2.78E-3 G9 50 29 18 50 2.78E-3 V4 25 29 2.0 V5 29 26 2.0 D3 18 25 DX D4 26 18 DX F1 29 0 V4 1 F2 0 29 V5 1 G6 98 70 29 18 2.78E-3 D5 70 71 DX D6 72 70 DX V7 71 98 DC 0 V8 98 72 DC 0 * * MODELS USED * .MODEL JX PJF(BETA=9.6605 VTO=-2.000 IS=0.50E-12 RD=0.1 + RS=0.1 CGD=1E-15 CGS=1E-15) .MODEL DX D(IS=1E-15 RS=10 CJO=1E-15) .ENDS AD795K *AD8001A SPICE Macro Model 9/94, Rev. A * AAG/ADSC * * Copyright 1994 by Analog Devices, Inc. * * Refer to the "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License * Statement * * Node assignments * Non-inverting input * | Inverting input * | | Positive supply * | | | Negative supply * | | | | Output * | | | | | .SUBCKT AD8001A 3 2 7 4 6 * * INPUT STAGE * CIN 3 4 1.5E-12 GB1 7 3 POLY(1) 3 100 (3E-6,0.2E-6) EOS 9 3 POLY(1) 23 100 (2E-3,1) Q1 7 9 10 QN I1 10 4 DC 2.568E-4 I2 7 11 DC 2.568E-4 Q2 4 9 11 QP R1 7 14 1E3 V1 7 17 DC 6.96561E-2 D1 17 14 DX Q3 14 11 15 QN Q4 16 10 15 QP R2 16 4 1E3 D2 16 18 DX V2 18 4 DC 6.96561E-2 LIN- 15 2 0.1E-9 GB2 7 2 POLY(1) 3 100 (5E-6,0.3E-6) CS1 7 2 0.03E-12 CS2 2 4 0.03E-12 * * GAIN STAGE AND DOMINANT POLE AT 230 kHz * EREF 100 0 POLY(2) (7,0) (4,0) (0,0.5,0.5) G1 100 19 7 14 1E-3 G2 19 100 16 4 1E-3 R3 19 100 1.24E6 C1 19 100 5.580468E-13 V3 7 20 DC 2.3747 D3 19 20 DX D4 21 19 DX V4 21 4 DC 2.3747 * * COMMON-MODE REJECTION NETWORK WITH ZERO AT 22 MHz * ECM 100 22 3 100 19.95 RCM1 22 23 1E4 CCM 22 23 7.2343E-13 RCM2 23 100 1 * * POLE AT 800 MHz * G4 100 24 19 100 1E-6 R5 24 100 1E6 C3 24 100 1.9894368E-16 * * POLE AT 4 GHz * G5 100 25 24 100 1E-6 R6 25 100 1E6 C4 25 100 3.9788736E-17 * * OUTPUT STAGE * VW 25 30 DC 0 * FSY 7 4 POLY(2) VSY1 VSY2 (4.2326E-3,1,1) GSY 100 35 33 30 4.6728972E-2 DSY1 35 36 DX VSY1 36 100 DC 0 DSY2 37 35 DX VSY2 100 37 DC 0 DSC1 30 31 DX VSC1 31 33 DC 0.62526 DSC2 32 30 DX VSC2 33 32 DC 0.62526 GO1 33 7 7 30 4.6728972E-2 RO1 7 33 21.4 GO2 4 33 30 4 4.6728972E-2 RO2 33 4 21.4 LO 33 6 7E-9 * .MODEL QN NPN(BF=100 IS=1E-15) .MODEL QP PNP(BF=100 IS=1E-15) .MODEL DX D(IS=1E-15) * .ENDS AD8001A *AD8001AN SPICE Macro Model 9/94, Rev. A * AAG/ADSC * * This version of the AD8001 model simulates the worst case * parameters of the 'A' grade in the N package (PDIP). The worst case * parameters used correspond to those in the data sheet. * This model was developed using the +-5V specifications. * * Copyright 1994 by Analog Devices, Inc. * * Refer to the "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License * Statement * * Node assignments * Non-inverting input * | Inverting input * | | Positive supply * | | | Negative supply * | | | | Output * | | | | | .SUBCKT AD8001AN 3 2 7 4 6 * * INPUT STAGE * CIN 3 4 1.5E-12 GB1 7 3 POLY(1) 3 100 (6E-6,0.3E-6) EOS 9 3 POLY(1) 23 100 (5E-3,1) Q1 7 9 10 QN I1 10 4 DC 2.568E-4 I2 7 11 DC 2.568E-4 Q2 4 9 11 QP R1 7 14 1E3 V1 7 17 DC -6.34541E-2 D1 17 14 DX Q3 14 11 15 QN Q4 16 10 15 QP R2 16 4 1E3 D2 16 18 DX V2 18 4 DC -6.34541E-2 LIN- 15 2 0.1E-9 GB2 7 2 POLY(1) 3 100 (25E-6,1E-6) CS1 7 2 0.03E-12 CS2 2 4 0.03E-12 * * GAIN STAGE AND DOMINANT POLE AT 891 kHz * EREF 100 0 POLY(2) (7,0) (4,0) (0,0.5,0.5) G1 100 19 7 14 1E-3 G2 19 100 16 4 1E-3 R3 19 100 3.196E5 C1 19 100 5.58902E-13 V3 7 20 DC 2.8108 D3 19 20 DX D4 21 19 DX V4 21 4 DC 2.8108 * * COMMON-MODE REJECTION NETWORK WITH ZERO AT 34.87 MHz * ECM 100 22 3 100 31.668 RCM1 22 23 1E4 CCM 22 23 4.56424E-13 RCM2 23 100 1 * * POLE AT 800 MHz * G4 100 24 19 100 1E-6 R5 24 100 1E6 C3 24 100 1.9894368E-16 * * POLE AT 4 GHz * G5 100 25 24 100 1E-6 R6 25 100 1E6 C4 25 100 3.9788736E-17 * * OUTPUT STAGE * VW 25 30 DC 0 * FSY 7 4 POLY(2) VSY1 VSY2 (4.7326E-3,1,1) GSY 100 35 33 30 4.6728972E-2 DSY1 35 36 DX VSY1 36 100 DC 0 DSY2 37 35 DX VSY2 100 37 DC 0 DSC1 30 31 DX VSC1 31 33 DC 0.3615 DSC2 32 30 DX VSC2 33 32 DC 0.3615 GO1 33 7 7 30 4.6728972E-2 RO1 7 33 21.4 GO2 4 33 30 4 4.6728972E-2 RO2 33 4 21.4 LO 33 6 7E-9 * .MODEL QN NPN(BF=100 IS=1E-15) .MODEL QP PNP(BF=100 IS=1E-15) .MODEL DX D(IS=1E-15) * .ENDS AD8001AN *AD8001AR SPICE Macro Model 9/94, Rev. A * AAG/ADSC * * This version of the AD8001 model simulates the worst case * parameters of the 'A' grade in the R package (SOIC). The worst case * parameters used correspond to those in the data sheet. * This model was developed using the +-5V specifications. * * Copyright 1994 by Analog Devices, Inc. * * Refer to the "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License * Statement * * Node assignments * Non-inverting input * | Inverting input * | | Positive supply * | | | Negative supply * | | | | Output * | | | | | .SUBCKT AD8001AR 3 2 7 4 6 * * INPUT STAGE * CIN 3 4 1.5E-12 GB1 7 3 POLY(1) 3 100 (6E-6,0.3E-6) EOS 9 3 POLY(1) 23 100 (5E-3,1) Q1 7 9 10 QN I1 10 4 DC 2.568E-4 I2 7 11 DC 2.568E-4 Q2 4 9 11 QP R1 7 14 1E3 V1 7 17 DC -4.41135E-2 D1 17 14 DX Q3 14 11 15 QN Q4 16 10 15 QP R2 16 4 1E3 D2 16 18 DX V2 18 4 DC -4.41135E-2 LIN- 15 2 0.1E-9 GB2 7 2 POLY(1) 3 100 (25E-6,1E-6) CS1 7 2 0.03E-12 CS2 2 4 0.03E-12 * * GAIN STAGE AND DOMINANT POLE AT 860 kHz * EREF 100 0 POLY(2) (7,0) (4,0) (0,0.5,0.5) G1 100 19 7 14 1E-3 G2 19 100 16 4 1E-3 R3 19 100 3.196E5 C1 19 100 5.79048E-13 V3 7 20 DC 2.8108 D3 19 20 DX D4 21 19 DX V4 21 4 DC 2.8108 * * COMMON-MODE REJECTION NETWORK WITH ZERO AT 34.87 MHz * ECM 100 22 3 100 31.668 RCM1 22 23 1E4 CCM 22 23 4.56424E-13 RCM2 23 100 1 * * POLE AT 800 MHz * G4 100 24 19 100 1E-6 R5 24 100 1E6 C3 24 100 1.9894368E-16 * * POLE AT 4 GHz * G5 100 25 24 100 1E-6 R6 25 100 1E6 C4 25 100 3.9788736E-17 * * OUTPUT STAGE * VW 25 30 DC 0 * FSY 7 4 POLY(2) VSY1 VSY2 (4.7326E-3,1,1) GSY 100 35 33 30 4.6728972E-2 DSY1 35 36 DX VSY1 36 100 DC 0 DSY2 37 35 DX VSY2 100 37 DC 0 DSC1 30 31 DX VSC1 31 33 DC 0.3615 DSC2 32 30 DX VSC2 33 32 DC 0.3615 GO1 33 7 7 30 4.6728972E-2 RO1 7 33 21.4 GO2 4 33 30 4 4.6728972E-2 RO2 33 4 21.4 LO 33 6 7E-9 * .MODEL QN NPN(BF=100 IS=1E-15) .MODEL QP PNP(BF=100 IS=1E-15) .MODEL DX D(IS=1E-15) * .ENDS AD8001AR *AD8002AN SPICE Macro Model 11/95, Rev. A * RFD/ADS * * This version of the AD8002 model simulates the worst case * parameters of the 'A' grade in the 'N ' package (PDIP). The Worst case * parameters used correspond to those in the data sheet. * This model was developed using the +/-5V specifications. * * Copyright 1995 by Analog Devices, Inc. * * Refer to the "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License * Statement. * * Node assignments * Non-inverting input * | Inverting input * | | Positive supply * | | | Negative supply * | | | | Output * | | | | | .SUBCKT AD8002AN 3 2 7 4 6 * ****** INPUT STAGE ****** * Q1 7 9 10 QN Q2 4 9 11 QP Q3 14 11 15 QN Q4 16 10 15 QP I1 10 4 DC 2.568e-4 I2 7 11 DC 2.568e-4 D1 17 14 DX D2 16 18 DX V2 18 4 DC -4.41135e-2 V1 7 17 DC -4.41135e-2 R1 14 7 1E3 R2 4 16 1E3 CS1 7 2 .25e-12 CS2 2 4 .25e-12 CIN 3 4 1.5E-12 LIN- 15 2 .9e-9 GB1 7 3 POLY(1) 3 100 (6e-6,0.9e-6) GB2 7 2 POLY(1) 3 100 (25e-6,1e-6) EOS 3 9 POLY(1) 100 23 (6E-3,1) * ****** GAINST ******** * V3 7 20 DC 2.8108 V4 21 4 DC 2.8108 R3 100 19 3.1e5 C1 19 100 6.05E-13 D3 19 20 DX D4 21 19 DX G1 100 19 POLY(1) 7 14 (0.0,1E-3) G2 19 100 POLY(1) 16 4 (0.0,1E-3) EREF 100 0 POLY(2) (7,0) (4,0) (0,0.5,0.5) * ****** CMRR ****** * CCM 22 23 4.56424e-13 RCM2 100 23 1 RCM1 23 22 1e4 ECM 22 100 POLY(1) 100 3 (0.0,31.668) * ****** POLE 1 ****** * C3 100 24 2.273642e-16 R5 24 100 1e6 G4 100 24 POLY(1) 19 100 (0.0,1E-6) * ****** POLE 2 ****** * C4 25 100 3.978877e-17 R6 25 100 1e6 G5 100 25 POLY(1) 24 100 (0.0,1E-6) * ****** OUTPUT ****** * RO1 33 7 21.4 RO2 4 33 21.4 VW 25 30 DC 0 VSC1 31 33 DC .325 VSC2 33 32 DC .325 LO 33 6 2e-9 DSC2 32 30 DX DSC1 30 31 DX GO1 33 7 POLY(1) 7 30 (0.0,4.6728972e-2) GO2 4 33 POLY(1) 30 4 (0.0,4.6728972e-2) * VSY1 36 100 DC 0 VSY2 100 37 DC 0 DSY1 35 36 DX DSY2 37 35 DX FSY 7 4 POLY(2) VSY1 VSY2 (4.7326E-3,1,1) GSY 100 35 33 30 4.6728972E-2 * .MODEL QN NPN(BF=100 IS=1E-15) .MODEL QP PNP(BF=100 IS=1E-15) .MODEL DX D(IS=1E-15) .ENDS AD8002AN *AD8002AR SPICE Macro Model 11/95, Rev. A * RFD/ADS * * This version of the AD8002 model simulates the worst case * parameters of the 'A' grade in the 'R ' package (SOIC). The Worst case * parameters used correspond to those in the data sheet. * This model was developed using the +/-5V specifications. * * Copyright 1995 by Analog Devices, Inc. * * Refer to the "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License * Statement. * * Node assignments * Non-inverting input * | Inverting input * | | Positive supply * | | | Negative supply * | | | | Output * | | | | | .SUBCKT AD8002AR 3 2 7 4 6 * ****** INPUT STAGE ******** * Q1 7 9 10 QN Q2 4 9 11 QP Q3 14 11 15 QN Q4 16 10 15 QP I1 10 4 DC 2.568e-4 I2 7 11 DC 2.568e-4 D1 17 14 DX D2 16 18 DX V2 18 4 DC -4.41135e-2 V1 7 17 DC -4.41135e-2 R1 14 7 1E3 R2 4 16 1E3 CS1 7 2 .25e-12 CS2 2 4 .25e-12 CIN 3 4 1.5E-12 LIN- 15 2 .9e-9 GB1 7 3 POLY(1) 3 100 (6e-6,0.9e-6) GB2 7 2 POLY(1) 3 100 (25e-6,1e-6) EOS 3 9 POLY(1) 100 23 (6E-3,1) * ****** gainst ******* * V3 7 20 DC 2.8108 V4 21 4 DC 2.8108 R3 100 19 3.1e5 C1 19 100 6.4987781e-13 D3 19 20 DX D4 21 19 DX G1 100 19 POLY(1) 7 14 (0,1E-3) G2 19 100 POLY(1) 16 4 (0,1E-3) EREF 100 0 POLY(2) (7,0) (4,0) (0,0.5,0.5) * ****** CMRR ********* * CCM 22 23 4.56424e-13 RCM2 100 23 1 RCM1 23 22 1e4 ECM 22 100 100 3 31.668 * ******* POLE1 *********** * C3 100 24 2.273644e-16 R5 24 100 1e6 G4 100 24 19 100 1E-6 * ******** POLE2 *********** * C4 25 100 3.978877e-17 R6 25 100 1e6 G5 100 25 24 100 1E-6 * ****** OUTPUT ******** * RO1 33 7 21.4 RO2 4 33 21.4 VW 25 30 DC 0 VSC1 31 33 DC .325 VSC2 33 32 DC .325 LO 33 6 2e-9 DSC2 32 30 DX DSC1 30 31 DX GO1 33 7 POLY(1) 7 30 (0.0, 4.6728972e-2) GO2 4 33 POLY(1) 30 4 (0.0, 4.6728972e-2) * VSY1 36 100 DC 0 VSY2 100 37 DC 0 DSY1 35 36 DX DSY2 37 35 DX FSY 7 4 POLY(2) VSY1 VSY2 (4.7326E-3,1,1) GSY 100 35 33 30 4.6728972E-2 * .MODEL QN NPN(BF=100 IS=1E-15) .MODEL QP PNP(BF=100 IS=1E-15) .MODEL DX D(IS=1E-15) .ENDS AD8002AR * AD8004a SPICE Macro-model 12/96, revA * SMR/ADI * * Copyright 1996 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * This model was written with the specs as they apply to running from a * dual supply, +/-5v. This means that the model will give a slew rate of * 3000v/us, whether or not the model is run from +/-5v, or single supply * of 5v. The user should keep in mind that the actual slew rate is much * slower in the real device when running from single supply 5v. Refer to * the data sheet for the actual specs. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD8004a 1 2 99 50 24 * * INPUT STAGE * r1 99 8 1 r2 10 50 1 i1 99 5 100e-6 i2 4 50 100e-6 q1 50 3 5 qp1 q2 99 3 4 qn1 q3 8 6 2 qn2 q4 10 7 2 qp2 r3 5 6 1 r4 4 7 1 r3a 99 6 40k r4a 50 7 40k * * input error sources * ib1 99 2 90e-6 ib2 99 3 110e-6 vos 3 1 3.5e-3 cs1 99 2 0.75e-12 cs2 50 2 0.75e-12 cs3 99 3 0.75e-12 cs4 50 3 0.75e-12 * * first gain stage and dominant pole * r5 12 99 280k r6 12 50 280k c3 12 99 1e-12 c4 12 50 1e-12 g1 99 12 99 8 1 g2 12 50 10 50 1 gsl1 99 12 poly(1) 99 8 0 0 300 gsl2 12 50 poly(1) 10 50 0 0 300 v3 99 13 1.6 v4 14 50 1.6 d3 12 13 dx d4 14 12 dx * * secondary pole * r7 15 99 1k r8 15 50 1k c5 15 99 0.9pf c6 15 50 0.9pf g3 99 15 12 18 1e-3 g4 15 50 18 12 1e-3 * * buffer stage * g13 98 17 15 98 1e-4 rbuf 17 98 10k * * reference stage * r13 18 99 1e5 r14 18 50 1e5 eref 98 0 18 0 1 rref 98 0 1e6 * * current mirroring on supplies * fo1 98 300 vcd 1 vi1 311 98 0 vi2 98 312 0 dm1 300 311 dx dm2 312 300 dx fsy 99 50 poly(2) vi1 vi2 0 1 1 iq 99 50 10.9e-3 * * output stage * r15 23 99 2 r16 23 50 2 vcd 23 25 0 l1 25 24 1.5e-12 rl 24 98 1e6 g11 99 23 17 99 0.5 g12 23 50 50 17 0.5 v5 19 23 0.59 v6 23 20 0.59 d5 19 17 dx d6 17 20 dx * * models * .model qn1 npn(bf=1e3 is=1e-15) .model qp1 pnp(bf=1e3 is=1e-15) .model qn2 npn(bf=1e3 is=1e-15) .model qp2 pnp(bf=1e3 is=1e-15) .model dx d(is=1e-15) .ends ad8004a ***** AD8004 SPICE model Rev B SMR/ADI 8-18-97 * Copyright 1997 by Analog Devices, Inc. * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License * Statement. * rev B was developed to add the correct noise characteristics, and * to create an improved solution for slew rate. * This model will give typical performance characteristics * for the following parameters; * closed loop gain and phase vs bandwidth * output current and voltage limiting * offset voltage (is static, will not vary with vcm) * ibias (again, is static, will not vary with vcm) * slew rate and step response performance * (slew rate is based on 10-90% of step response) * current on output will be reflected to the supplies * vnoise, referred to the input * inoise, referred to the input * distortion is not characterized * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD8004an 1 2 99 50 28 * input stage * q1 50 3 5 qp1 q2 99 5 4 qn1 q3 99 3 6 qn1 q4 50 6 4 qp1 i1 99 5 2.6e-4 i2 6 50 2.6e-4 cin1 1 98 1.5e-12 cin2 2 98 1.5e-12 v1 4 2 0 * input error sources * eos 3 1 poly(1) 20 98 1e-3 1 fbn 2 98 poly(1) vnoise3 35e-6 1e-3 fbp 1 98 poly(1) vnoise3 40e-6 1e-3 * gain stage * f1 98 7 poly(1) v1 0 1 0 1500 rgain 7 98 2.9e5 cgain 7 98 2e-12 dcl1 7 8 d1 dcl2 9 7 d1 vcl1 99 8 1.75 vcl2 9 50 1.75 * second pole * epole 14 98 7 98 1 rpole 14 15 1 cpole 15 98 0.6e-9 * reference stage * eref 98 0 poly(2) 99 0 50 0 0 0.5 0.5 ecmref 30 0 poly(2) 1 0 2 0 0 0.5 0.5 * vnoise stage * rnoise1 19 98 7.35e-3 vnoise1 19 98 0 vnoise2 21 98 0.4 dnoise1 21 19 dn fnoise1 20 98 vnoise1 1 rnoise2 20 98 1 * inoise stage * rnoise3 22 98 11.5e-6 vnoise3 22 98 0 vnoise4 24 98 0.585 dnoise2 24 22 dn fnoise2 23 98 vnoise3 1 rnoise4 23 98 1 * buffer stage * gbuf 98 13 15 98 1e-2 rbuf 98 13 1e2 * output current reflected to supplies * fcurr 98 40 voc 1 vcur1 26 98 0 vcur2 98 27 0 dcur1 40 26 d1 dcur2 27 40 d1 * output stage * vo1 99 90 0 vo2 91 50 0 fout1 0 99 poly(2) vo1 vcur1 -13.27e-3 1 -1 fout2 50 0 poly(2) vo2 vcur2 -13.27e-3 1 -1 gout1 90 10 13 99 0.5 gout2 91 10 13 50 0.5 rout1 10 90 2 rout2 10 91 2 voc 10 28 0 rout3 28 98 1e6 dcl3 13 11 d1 dcl4 12 13 d1 vcl3 11 10 -0.69 vcl4 10 12 -0.69 .model qp1 pnp() .model qn1 npn() .model d1 d() .model dn d(af=1 kf=1e-8) .ends ***** AD8011 SPICE model Rev A SMR/ADI 9-30-97 * Copyright 1997 by Analog Devices, Inc. * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * This model will give typical performance characteristics * for the following parameters; * closed loop gain and phase vs bandwidth * output current and voltage limiting * offset voltage (is static, will not vary with vcm) * ibias (again, is static, will not vary with vcm) * slew rate and step response performance * (slew rate is based on 10-90% of step response) * current on output will be reflected to the supplies * vnoise, referred to the input * inoise, referred to the input * distortion is not characterized * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD8011an 1 2 99 50 28 * input stage * q1 50 3 5 qp1 q2 99 5 4 qn1 q3 99 3 6 qn1 q4 50 6 4 qp1 i1 99 5 0.26e-3 i2 6 50 0.26e-3 cin1 1 98 1e-12 cin2 2 98 2.3e-12 v1 4 2 0 * input error sources * eos 3 1 poly(1) 20 98 2e-3 1 fbn 2 98 poly(1) vnoise3 5e-6 1e-3 fbp 1 98 poly(1) vnoise3 5e-6 1e-3 * gain stage * f1 98 7 poly(1) v1 0 1 0 100 rgain 7 98 1.3e6 cgain 7 98 1.5e-12 dcl1 7 8 d1 dcl2 9 7 d1 vcl1 99 8 1.54 vcl2 9 50 1.54 gcm 98 7 poly(2) 98 0 30 0 0 1e-5 1e-5 * second pole * epole 14 98 7 98 1 rpole 14 15 1 cpole 15 98 0.4e-9 * reference stage * eref 98 0 poly(2) 99 0 50 0 0 0.5 0.5 ecmref 30 0 poly(2) 1 0 2 0 0 0.5 0.5 * vnoise stage * rnoise1 19 98 10.6e-3 vnoise1 19 98 0 vnoise2 21 98 0.53 dnoise1 21 19 dn fnoise1 20 98 vnoise1 1 rnoise2 20 98 1 * inoise stage * rnoise3 22 98 0.46e-3 vnoise3 22 98 0 vnoise4 24 98 0.6 dnoise2 24 22 dn fnoise2 23 98 vnoise3 1 rnoise4 23 98 1 * buffer stage * gbuf 98 13 15 98 1e-2 rbuf 98 13 1e2 * output current reflected to supplies * fcurr 98 40 voc 1 vcur1 26 98 0 vcur2 98 27 0 dcur1 40 26 d1 dcur2 27 40 d1 * output stage * vo1 99 90 0 vo2 91 50 0 fout1 0 99 poly(2) vo1 vcur1 -9.27e-3 1 -1 fout2 50 0 poly(2) vo2 vcur2 -9.27e-3 1 -1 gout1 90 10 13 99 0.1 gout2 91 10 13 50 0.1 rout1 10 90 10 rout2 10 91 10 voc 10 28 0 rout3 28 98 1e6 dcl3 13 11 d1 dcl4 12 13 d1 vcl3 11 10 -0.64 vcl4 10 12 -0.64 .model qp1 pnp(kf=1e-30) .model qn1 npn(kf=1e-30) .model d1 d(af=0 kf=1e-30) .model dn d(af=1 kf=1e-8) .ends ad8011an * AD8031a Spice Macro-model ADI/SMR 8/96, Rev A * * Copyright 1996 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. * Use of this model indicates your acceptance with * the terms and provisions in the License Statement. * * The following parameters are accurately modeled; * * open loop gain and phase vs frequency * output clamping voltage and current * input common mode range * CMRR vs freq * I bias vs Vcm in * Slew rate * Output currents are reflected to V supplies * * Vos is static and will not vary with Vcm in * Step response is modeled at unity gain w/1k load * * Distortion and noise are not characterized * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD8031a 1 2 99 50 61 ***** Input bias current source ecm 20 0 3 97 1 d1 20 21 dx d2 23 20 dx v3 21 22 -0.9 v4 24 23 -0.9 r20 22 0 100 r21 24 0 100 f1 0 25 v3 1 f2 25 0 v4 1 r22 25 0 1k d3 25 26 dx d4 27 25 dx v5 26 0 0.2 v6 0 27 0.3 g1 1 0 25 0 400e-9 g2 2 0 25 0 400e-9 ***** Input Stage R1 1 3 140k R2 3 2 140k C1 1 2 1.6pf R3 1 98 40e6 R4 2 98 40e6 r9 15 7 1015 r10 16 7 1015 q1 5 1 15 qn1 q2 6 4 16 qn1 r5 99 5 1515 r6 99 6 1515 cp 5 6 0.657p ib3 7 50 1e-4 eos 2 4 poly(1) (105,98) 0.55e-3 1 ***** dummy first stage (pnp) for correct bias current ib4 81 99 1e-4 r11 82 81 1015 r12 83 81 1015 q3 84 1 82 qp1 q4 85 4 83 qp1 r13 50 84 1515 r14 50 85 1515 ***** gain stage/pole at 2530hz/clamp circuitry g3 99 31 6 5 0.692 g4 31 50 5 6 0.692 r7 99 31 19072 r8 31 50 19072 c3 99 31 3.3n c4 31 50 3.3n vc1 99 45 0.66 vc2 46 50 1.11 dc1 31 45 dx dc2 46 31 dx ***** internal reference rdiv1 99 97 100k rdiv2 97 50 100k Eref 98 0 97 0 1 rref 98 0 1e6 ***** Common mode gain network gacm1 99 100 3 98 7.94e-13 gacm2 100 50 98 3 7.94e-13 racm1 99 100 1e4 racm2 100 50 1e4 ***** Common mode gain network/zero at 2530hz ecm1 101 98 100 98 1e6 racm3 101 102 1e6 racm4 102 103 1 lacm1 103 98 62.9u ***** Common mode gain network/zero at 450hz/pole at 1mhz ecm2 104 98 102 98 6000 racm5 104 105 6000 racm6 105 106 1 lacm2 106 98 354u ***** buffer to output stage gbuf 98 32 31 98 1e-4 re1 32 98 10k ***** output stage fo1 98 110 vcd 1 do1 110 111 dx do2 112 110 dx vi1 111 98 0 vi2 98 112 0 fsy 99 50 poly(2) vi1 vi2 5.61e-4 1 1 go3 60 99 99 32 0.5 go4 50 60 32 50 0.5 r03 60 99 2 r04 60 50 2 vcd 60 62 0 lo1 62 61 2u ro2 61 98 1e9 do5 32 70 dx do6 71 32 dx vo1 70 60 -0.642 vo2 60 71 -0.628 .model dx d(is=1e-15) .model qn1 npn(bf=2500 vaf=100) .model qp1 pnp(bf=2500 vaf=60) .ends ad8031a ***** AD8036an SPICE model Rev A SMR/ADI 8-26-97 * Copyright 1997 by Analog Devices, Inc. * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License * Statement. * This model will give typical performance characteristics * for the following parameters; * pos and neg clamp voltages * closed loop gain and phase vs bandwidth * output current and voltage limiting * offset voltage (is static, will not vary with vcm) * ibias (again, is static, will not vary with vcm) * slew rate and step response performance * (slew rate is based on 10-90% of step response) * current on output will be reflected to the supplies * vnoise, referred to the input * inoise, referred to the input * distortion is not characterized * Node assignments * non-inverting input * | inverting input * | | positive supply * | | VH VL | negative supply * | | | | | | output * | | | | | | | .SUBCKT AD8036an 1 2 3 4 99 50 21 * input stage * eos 1 13 poly(2) 29 98 34 98 -2e-3 1 50e-9 rnon 13 98 500e3 ibnon 13 98 4e-6 ibinv 2 98 3.5e-6 cinnon 1 98 1.2e-12 cininv 2 98 1.2e-12 rinh 3 99 1e6 rinl 4 50 1e6 cinh 3 99 1e-12 cinl 4 50 1e-12 gincl 98 5 13 98 1e-2 rincl 98 5 1e2 dcl1 5 6 d1 dcl2 7 5 d1 eclH 6 98 poly(1) 3 98 -0.675 1 eclL 7 98 poly(1) 4 98 0.675 1 q1 11 2 8 qn1 q2 12 5 9 qn1 i1 10 50 0.1 i2 50 99 0.1 r3 99 11 12.8 r4 99 12 12.8 cpole 11 12 26.47e-12 r5 8 10 12.28 r6 9 10 12.28 * gain/bw stage ggain1 99 14 11 12 0.078 ggain2 50 14 11 12 0.078 cgain1 99 14 67e-12 cgain2 50 14 67e-12 rgain1 99 14 10163 rgain2 50 14 10163 vclgn1 99 17 1.75 vclgn2 18 50 1.75 dclgn1 14 17 d1 dclgn2 18 14 d1 * reference stage eref1 98 0 poly(2) 99 0 50 0 0 0.5 0.5 eref2 97 0 poly(2) 1 0 2 0 0 0.5 0.5 * common mode rejection ecm1 30 98 97 98 4255 rcm1 30 31 4255 rcm2 31 32 1 lcm1 32 98 0.68e-6 ecm2 33 98 31 98 20k rcm3 33 34 20k rcm4 34 35 1 lcm2 35 98 3.18e-6 * vnoise rnoise1 27 98 0.37e-3 vnoise1 27 98 0 vnoise2 28 98 0.475 dnoise1 28 27 dn fnoise1 29 98 vnoise1 1 rnoise2 29 98 1 * buffer stage gbuf 98 15 14 98 1e-2 rbuf 98 15 100 * output current reflected to supplies * fcurr 98 24 vout 1 vcur1 25 98 0 vcur2 98 26 0 dcur1 24 25 d1 dcur2 26 24 d1 * output stage vo1 99 19 0 vo2 20 50 0 fout1 0 99 poly(2) vo1 vcur1 -20.5e-3 1 -1 fout2 50 0 poly(2) vo2 vcur2 -20.5e-3 1 -1 gout1 19 16 15 99 1 gout2 20 16 15 50 1 rout1 19 16 1 rout2 16 20 1 vout 16 21 0 rload 21 98 1e6 viclmp1 15 22 0.645 viclmp2 23 15 0.645 diclmp1 16 22 d1 diclmp2 23 16 d1 .model qn1 npn(bf=1e5) .model d1 d() .model dn d(af=1 kf=1e-8) .ends ad8036an * AD8041a Spice Macro-model 9/96, Rev A * * Copyright 1996 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. * Use of this model indicates your acceptance with * the terms and provisions in the License Statement. * * The following parameters are accurately modeled; * * open loop gain and phase vs frequency * output clamping voltage and current * input common mode range * CMRR vs freq * I bias vs Vcm in * Slew rate * Output currents are reflected to V supplies * * Vos is static and will not vary with Vcm in * Step response is modeled at unity gain w/1k load * * Distortion and noise are not characterized * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD8041a 1 2 99 50 61 ***** Input bias current source ecm 20 0 99 3 1 d1 20 21 dx v3 21 22 0.2 r20 22 0 100 f1 0 25 v3 1 r22 25 0 1k r23 26 28 8 d3 25 26 dx v5 28 0 .3 g1 1 0 0 25 400e-9 g2 2 0 0 25 400e-9 ***** Input Stage R1 1 3 80k R2 3 2 80k C1 1 2 1.8pf rcm1 1 0 5e6 rcm2 2 0 5e6 R3 1 98 40e6 R4 2 98 40e6 r9 15 7 764 r10 16 7 764 q1 5 1 15 qp1 q2 6 4 16 qp1 r5 99 5 1254 r6 99 6 1254 ib3 7 50 1e-4 eos 2 4 poly(1) (108,98) 2e-3 1 ***** gain stage/pole at 3200hz/clamp circuitry g3 99 31 5 6 7.97e-4 g4 31 50 6 5 7.97e-4 r7 99 31 63e6 r8 31 50 63e6 c3 99 31 0.635e-12 c4 31 50 0.635e-12 vc1 99 45 0.72 vc2 46 50 0.72 dc1 31 45 dx dc2 46 31 dx ***** pole at 200mhz e1 32 98 31 98 1 rflt 32 33 1k cflt 33 98 0.796e-12 ***** internal reference rdiv1 99 97 100k rdiv2 97 50 100k Eref 98 0 97 0 1 rref 98 0 1e6 ***** Common mode gain network gacm1 99 100 3 98 2e-13 gacm2 100 50 98 3 2e-13 racm1 99 100 1e4 racm2 100 50 1e4 ***** Common mode gain network/zero at 3200hz ecm1 101 98 100 98 1e6 racm3 101 102 1e6 racm4 102 103 1 lacm1 103 98 40u ***** Common mode gain network/zero at 100khz/pole at 60mhz ecm2 104 98 102 98 300 racm5 104 105 300 racm6 105 106 1 lacm2 106 98 .78u ***** Common mode gain network/pole at 60mhz ecm3 107 98 105 98 1 racm7 107 108 10k cacm1 108 98 0.265e-12 ***** buffer to output stage gbuf 98 34 33 98 1e-4 re1 34 98 10k ***** output stage fo1 98 110 vcd 1 do1 110 111 dx do2 112 110 dx vi1 111 98 0 vi2 98 112 0 fsy 99 50 poly(2) vi1 vi2 4.73e-3 1 1 go3 60 99 99 34 0.1 go4 50 60 34 50 0.1 r03 60 99 10 r04 60 50 10 vcd 60 62 0 lo1 62 61 2n ro2 61 98 1e9 do5 34 70 dx do6 71 34 dx vo1 70 60 -0.31 vo2 60 71 -0.05 .model dx d(is=1e-15) .model qn1 npn(bf=500 vaf=100) .model qp1 pnp(bf=500 vaf=60) .ends ad8041a * AD8047 SPICE Macro-model * JCH / ADI * * Copyright 1997 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of * this model indicates your acceptance of the terms and pro- * visions in the License Statement. * * CAUTION: NOISE PERFORMANCE IS NOT INCLUDED IN THIS MODEL. NOISE * MODELING WILL BE INCLUDED IN A LATER REVISION. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD8047 3 1 99 50 44 * * INPUT STAGE AND POLE AT 800MHZ * I1 8 50 1E-3 Q1 4 1 6 QN Q2 5 2 7 QN R1 99 4 862 R2 99 5 862 C1 4 5 0.116p R3 6 8 810.5 R4 7 8 810.5 RCM1 1 20 5G RCM2 3 20 5G IOS 1 3 3u EOS 3 2 POLY(1) (16,98) 1E-3 1 CIN1 1 99 1.5PF CIN2 2 99 1.5PF * * GAIN STAGE AND DOMINANT POLE AT 110KHZ * EREF 98 0 POLY(2) (99,0) (50,0) 0 0.5 0.5 G1 98 9 4 5 1.16E-3 R5 9 98 1.085E6 C2 9 98 1.333E-12 D1 9 10 DX D2 11 9 DX H1 99 10 POLY(1) Vout 1.87 37.9 -3.94E2 2.44E3 H2 11 50 POLY(1) Vout 1.93 -40.3 -4.51E2 -2.70E3 * *POLE AT 1.1GHZ * GP1 98 12 9 98 1 RP1 98 12 1 CP1 98 12 0.14N * *POLE AT 1.1GHZ * GP2 98 13 12 98 1 RP2 98 13 1 CP2 98 13 0.14N * *POLE AT 1.1GHZ * GP3 98 14 13 98 1 RP3 98 14 1 CP3 98 14 0.14N * *POLE AT 1.3GHZ * GP4 98 17 14 98 1 RP4 98 17 1 CP4 98 17 0.12N * *COMMON-MODE ZERO AT 113KHZ * GCM1 98 15 20 98 1E-10 RCM3 15 16 1MEG LCM1 16 98 1.4 * * BUFFER TO OUTPUT STAGE * GB11 98 40 14 98 200m RB11 98 40 5 * * OUTPUT STAGE * RO1 99 45 0.4 RO2 45 50 0.4 G7 45 99 99 40 2.5 G8 50 45 40 50 2.5 G9 98 60 45 40 2.5 D7 60 61 DX D8 62 60 DX V7 61 98 DC 0 V8 98 62 DC 0 FSY 99 50 POLY(2) V7 V8 4E-3 1 1 D9 41 45 DX D10 45 42 DX V5 40 41 0.68 V6 42 40 0.68 Vout 45 46 0 LO 46 44 .06E-9 * * MODELS USED * .MODEL DX D .MODEL QN NPN(BF=500) .ENDS AD8047 ***** AD8055an SPICE model Rev A SMR/ADI 8-26-97 * Copyright 1997 by Analog Devices, Inc. * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License * Statement. * This model will give typical performance characteristics * for the following parameters; * closed loop gain and phase vs bandwidth * output current and voltage limiting * offset voltage (is static, will not vary with vcm) * ibias (again, is static, will not vary with vcm) * slew rate and step response performance * (slew rate is based on 10-90% of step response) * current on output will be reflected to the supplies * vnoise, referred to the input * inoise, referred to the input * distortion is not characterized * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD8055an 1 2 99 50 17 * input stage * q1 4 15 13 qn1 q2 5 2 14 qn1 i1 3 50 0.1 i2 50 99 0.1 r3 99 4 14.96 r4 99 5 14.96 r5 13 3 14.44 r6 14 3 14.44 cpole 4 5 26.61pf cin1 1 98 2pf cin2 2 98 2pf * error stage eos 1 15 poly(2) 30 98 92 0 3e-3 1 25e-9 gnoise1 98 1 33 98 1e-4 gnoise2 98 2 33 98 1e-4 * gain/bw stage g1 99 9 poly(1) 5 4 0 0.067 0 0.022 g2 50 9 poly(1) 5 4 0 0.067 0 0.022 rgain1 99 9 53078 rgain2 50 9 53078 cgain1 99 9 71.42pf cgain2 50 9 71.42pf vlim1 99 18 2.46 vlim2 19 50 2.46 dlim1 9 18 d1 dlim2 19 9 d1 * vnoise stage * rnoise1 39 98 0.46e-3 vnoise1 39 98 0 vnoise2 31 98 0.56 dnoise1 31 39 dn fnoise1 30 98 vnoise1 1 rnoise2 30 98 1 * inoise stage * rnoise3 32 98 0.166e-3 vnoise3 32 98 0 vnoise4 34 98 0.545 dnoise2 34 32 dn fnoise2 33 98 vnoise3 1 rnoise4 33 98 1 * buffer stage gbuf 98 12 9 98 1e-2 rbuf 98 12 100 * reference stage eref1 98 0 poly(2) 99 0 50 0 0 0.5 0.5 eref2 97 0 poly(2) 1 0 2 0 0 0.5 0.5 * common mode rejection* ecm1 96 0 98 97 23809 rcm2 96 95 23809 rcm1 95 94 1 lcm1 94 0 3.79e-6 ecm2 93 0 95 0 3332 rcm3 93 92 3332 rcm4 92 89 1 lcm2 89 0 0.53e-6 * output current reflected to supplies * fcurr 98 40 vout 1 vcur1 26 98 0 vcur2 98 27 0 dcur1 40 26 d1 dcur2 27 40 d1 * output stage vo1 99 90 0 vo2 91 50 0 fout1 0 99 poly(2) vo1 vcur1 -5.4e-3 1 -1 fout2 50 0 poly(2) vo2 vcur2 -5.4e-3 1 -1 gout1 90 16 12 99 1 gout2 91 16 12 50 1 rout1 16 90 1 rout2 16 91 1 vout 16 17 0 viclmp1 12 20 0.703 viclmp2 21 12 0.703 diclmp1 16 20 d1 diclmp2 21 16 d1 .model qn1 npn(bf=1e5) .model d1 d() .model dn d(af=1 kf=1e-8) .ends ad8055an * AD8072jn SPICE Macro-model rev B; 6/6/97,SMR,ADI * Copyright 1997 by Analog Devices, Inc. * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * This model will give typical performance characteristics * for the following parameters; * closed loop gain and phase vs bandwidth * output current and voltage limiting * offset voltage (is static, will not vary with vcm) * ibias (again, is static, will not vary with vcm) * slew rate and step response performance * (slew rate is based on 10-90% of step response) * current on output will be reflected to the supplies * vnoise, referred to the input * inoise, referred to the input * distortion is not characterized * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD8072jn 1 2 99 50 24 * INPUT STAGE v1 8 2 0 i1 99 5 108e-6 i2 4 50 108e-6 q1 50 3 5 qp1 q2 99 3 4 qn1 q3 99 5 8 qn2 q4 50 4 8 qp2 * input error sources fn 99 2 vn4 1e-3 ib1 99 2 2.87e-6 ib2 99 3 4e-6 eos 3 1 poly(1) (32,98) 2e-3 1 cs3 98 2 1.6e-12 cs4 98 3 1.6e-12 * slew rate limiting stage fl1 98 70 v1 1 dl1 70 98 dx dl2 98 70 dx dl3 70 72 dx dl4 72 70 dx vl1 72 73 0 rl1 73 98 27 * first gain stage and dominant pole fgain 98 12 vl1 2 r5 12 98 300k c4 12 98 1.7e-12 v3 99 13 2.54 v4 14 50 2.84 d3 12 13 dx d4 14 12 dx * v noise generator vn1 30 98 0.555 dn1 30 31 dn1 rn1 31 98 1.84e-3 vn2 31 98 0 fn1 32 98 vn2 1 rn2 32 98 1 * i noise generation vn3 33 98 0.595 dn2 33 34 dn1 rn3 34 98 0.46e-3 vn4 34 98 0 fn2 35 98 vn4 1 rn4 35 98 1 * buffer stage g13 98 17 12 98 1e-2 rbuf 17 98 100 * reference stage eref1 98 0 poly(2) 99 0 50 0 0 0.5 0.5 * current mirroring on supplies fo3 98 300 vo1 1 vi1 311 98 0 vi2 98 312 0 dm1 300 311 dx dm2 312 300 dx * output stage r15 23 90 2 r16 23 91 2 vo1 23 24 0 vo2 99 90 0 vo3 91 50 0 fo1 0 99 poly(2) vo2 vi1 -6.67e-3 1 -1 fo2 50 0 poly(2) vo3 vi2 -6.67e-3 1 -1 rl 24 98 1e6 g11 23 90 99 17 0.5 g12 23 91 50 17 0.5 v5 23 19 -0.666 v6 20 23 -0.668 d5 19 17 dx d6 17 20 dx * models .model qn1 npn(bf=1e3) .model qp1 pnp(bf=1e3) .model qn2 npn(bf=1e3) .model qp2 pnp(bf=1e3) .model dx d() .model dn1 d(af=1 kf=1e-10) .ends ad8072jn * AD811 SPICE Macro-model 7/91, Rev. A * JCB / PMI * * * Copyright 1991 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD811 1 2 99 50 28 * * INPUT STAGE * R1 99 8 1E3 R2 10 50 1E3 V1 99 9 11 D1 9 8 DX V2 11 50 11 D2 10 11 DX I1 99 5 920E-6 I2 4 50 920E-6 Q1 5 5 3 QN Q2 4 4 3 QP Q3 8 5 30 QN Q4 10 4 30 QP * * INPUT ERROR SOURCES * GB1 99 1 POLY(1) 1 22 2E-6 1E-6 GB2 99 30 POLY(1) 1 22 2E-6 1E-6 VOS 3 1 500E-6 LS1 30 2 4E-8 CS1 99 2 0.5E-12 CS2 50 2 0.5E-12 CIN 1 50 2E-12 * EREF 97 0 22 0 1 * * GAIN STAGE & DOMINANT POLE * R5 12 97 1.5E6 C3 12 97 3.9E-12 G1 97 12 99 8 1E-3 G2 12 97 10 50 1E-3 V3 99 13 2.9 V4 14 50 2.9 D3 12 13 DX D4 14 12 DX * * POLE AT 400 MHZ * R8 17 97 1E6 C4 17 97 0.530E-15 G4 97 17 12 22 1E-6 * * ZERO AT 150 MHZ * R20 18 19 1E6 R21 19 97 1 C20 18 19 -.530E-15 E20 18 97 17 22 1E6 * * POLE AT 200 MHZ * R12 21 97 1E6 C8 21 97 0.395E-15 G8 97 21 19 22 1E-6 * * OUTPUT STAGE * ISY 99 50 14.7E-3 R13 22 99 16.7E3 R14 22 50 16.7E3 R15 27 99 22 R16 27 50 22 L2 27 28 1E-8 G9 25 50 21 27 45.45E-3 G10 26 50 27 21 45.45E-3 G11 27 99 99 21 45.45E-3 G12 50 27 21 50 45.45E-3 V5 23 27 1.3 V6 27 24 1.3 D5 21 23 DX D6 24 21 DX D7 99 25 DX D8 99 26 DX D9 50 25 DY D10 50 26 DY * * MODELS USED * .MODEL QN NPN(BF=1E9 IS=1E-15) .MODEL QP PNP(BF=1E9 IS=1E-15) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS AD811 * AD812A SPICE Macro-model 12/93, Rev. A * JCB / PMI * * This version of the AD812 model simulates the worst case * parameters of the 'A' grade. The worst case parameters * used correspond to those in the data sheet. This model was * developed using the +-5V specifications. * * Copyright 1993 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. * Use of this model indicates your acceptance with * the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD812A 1 2 99 50 28 * * INPUT STAGE * R1 99 8 1E3 R2 10 50 1E3 V1 99 9 0.9 D1 9 8 DX V2 11 50 0.9 D2 10 11 DX I1 99 5 140E-6 I2 4 50 140E-6 Q1 5 5 3 QN Q2 4 4 3 QP Q3 8 5 2 QN Q4 10 4 2 QP * * INPUT ERROR SOURCES * GB1 99 1 POLY(1) 1 22 1E-6 0.15E-6 GB2 99 2 POLY(1) 1 22 20E-6 3E-6 EOS 3 1 POLY(1) 16 22 5E-3 1 CS2 50 2 1.7E-12 CIN 1 50 1.7E-12 * EREF 98 0 22 0 1 * * GAIN STAGE & DOMINANT POLE * R5 12 98 750E3 C3 12 98 4.8E-12 G1 98 12 99 8 1E-3 G2 12 98 10 50 1E-3 V3 99 13 1.5 V4 14 50 1.5 D3 12 13 DX D4 14 12 DX * * POLE AT 200 MHZ * R6 17 98 1E6 C4 17 98 0.795E-15 G3 98 17 12 22 1E-6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 19 KHZ * R7 15 16 1E4 R8 16 98 1 C5 15 16 30E-12 E3 98 15 1 22 10.0 * * POLE AT 150 MHZ * R9 21 98 1E6 C6 21 98 1.06E-15 G4 98 21 17 22 1E-6 * * OUTPUT STAGE * R10 22 99 8E3 R11 22 50 8E3 R12 27 99 60 R13 27 50 60 L2 27 28 1E-8 G5 27 99 99 21 16.67E-3 G6 50 27 21 50 16.67E-3 V5 23 27 1.75 V6 27 24 1.75 D5 21 23 DX D6 24 21 DX G7 98 35 27 21 16.67E-3 D7 35 36 DX D8 37 35 DX V7 36 98 DC 0 V8 98 37 DC 0 F1 99 50 POLY(2) V7 V8 3.104E-3 1 1 * * MODELS USED * .MODEL QN NPN(BF=1E3 IS=1E-15) .MODEL QP PNP(BF=1E3 IS=1E-15) .MODEL DX D(IS=1E-15) .ENDS * AD817A SPICE Macro-model Rev. A, 11/92 * ARG / ADI * * This version of the AD817 model simulates the worst case * parameters of the 'A' grade. The worst case parameters * used correspond to those in the data sheet. * * Copyright 1993 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of * this model indicates your acceptance of the terms and pro- * visions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD817A 2 1 99 50 46 * * INPUT STAGE AND POLE AT 160MHZ * I1 8 50 1E-3 Q1 4 1 6 QN Q2 5 3 7 QN CIN 1 2 1.5PF R1 99 4 1.085K R2 99 5 1.085K C1 4 5 4.187E-13 R3 6 8 1.033K R4 7 8 1.033K IOS 1 2 100E-9 EOS 3 2 POLY(1) (15,98) 2E-3 50.119 * * GAIN STAGE AND DOMINANT POLE AT 8.8KHZ * EREF 98 0 POLY(2) (99,0) (50,0) 0 0.5 0.5 G1 98 9 4 5 .922E-3 R5 9 98 4.341E6 C2 9 98 3.333E-12 D1 9 10 DX D2 11 9 DX V1 99 10 2.43 V2 11 50 2.43 * * COMMON MODE STAGE WITH ZERO AT 15.849KHZ * ECM 14 98 POLY(2) 1 98 2 98 0 0.5 0.5 R7 14 15 1E6 C4 14 15 10.042E-12 R8 15 98 1 * *POLE AT 120MHZ * GP2 98 31 9 98 1E-6 RP2 31 98 1E6 CP2 31 98 1.326E-15 * *ZERO AT 60MHZ * EZ1 32 98 31 98 1E6 RZ1 32 33 1E6 RZ2 33 98 1 CZ1 32 33 2.65E-15 * *ZERO AT 100MHZ * EZ2 34 98 33 98 1E6 RZ3 34 35 1E6 RZ4 35 98 1 CZ2 34 35 1.59E-15 * *POLE AT 120MHZ * GP3 98 36 35 98 1E-6 RP3 36 98 1E6 CP3 36 98 1.326E-15 * *POLE AT 160MHZ * GP10 98 40 36 98 1E-6 RP10 40 98 1E6 CP10 40 98 .995E-15 * * OUTPUT STAGE * RO1 99 45 16 RO2 45 50 16 G7 45 99 99 40 62.5E-3 G8 50 45 40 50 62.5E-3 G9 98 60 45 40 62.5E-3 D7 60 61 DX D8 62 60 DX V7 61 98 DC 0 V8 98 62 DC 0 GSY 99 50 99 50 7.692E-6 FSY 99 50 POLY(2) V7 V8 6.27E-3 1 1 D9 41 45 DX D10 45 42 DX V5 40 41 0.04 V6 42 40 0.04 LO 45 46 .06E-9 * * MODELS USED * .MODEL DX D .MODEL QN NPN(BF=75.758) .ENDS AD817A * AD818A SPICE Model Rev. A, 8/94 * ARG / PMI * * Revision History: * * - Changed EOS multiplier from 5 to 0.1; changed R9 from 10 ohms to * 500 ohms; changed C3 from 31.381E-9 to 31.381E-12, all in order * to fix common mode rejection stage (and thereby, fix open-loop gain * near 0dB crossing). * * * This version of the AD818 model simulates the worst case * parameters of the 'A' grade. The worst case parameters * used correspond to those in the data sheet. * * Copyright 1993 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of * this model indicates your acceptance of the terms and pro- * visions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD818A 2 1 99 50 45 * * INPUT STAGE AND POLE AT 400MHZ * I1 4 50 1E-3 CIN 1 2 1.5E-12 IOS 2 1 100E-9 Q1 5 1 7 QN Q2 6 3 8 QN R3 99 5 750 R4 99 6 750 R5 7 4 698 R6 8 4 698 C1 5 6 239E-15 EOS 3 2 POLY(1) (13,98) 2E-3 0.1 * * GAIN STAGE AND DOMINANT POLE AT 15.9KHZ * EREF 98 0 39 0 1 G1 98 9 5 6 1.333E-3 R7 9 98 4.5E6 C2 9 98 2.222E-12 D1 9 10 DX D2 11 9 DX V1 99 10 2.2 V2 11 50 2.2 * * COMMON MODE GAIN STAGE WITH ZERO AT 5KHZ * ECM 12 98 POLY(2) (1,39) (2,39) 0 0.5 0.5 R8 12 13 1E6 R9 13 98 500 C3 12 13 31.831E-12 * * NEGATIVE ZERO AT 150MHZ * E1 14 98 9 39 1E6 R11 14 15 1 R12 15 98 1E-6 FNZ 14 15 VNZ -1 ENZ 16 98 14 15 1 VNZ 17 98 DC 0 CNZ 16 17 1.061E-9 * * ZERO/POLE AT 20MHZ/25MHZ * E2 18 98 15 39 1.25 R13 18 19 1 R14 19 98 4 C5 18 19 7.958E-9 * * POLE AT 400MHZ * G2 98 40 19 39 1E-6 R10 40 98 1E6 C4 40 98 .398E-15 * * OUTPUT STAGE * RS1 99 39 65E3 RS2 39 50 65E3 RO1 99 45 16 RO2 45 50 16 G7 45 99 99 40 62.5E-3 G8 50 45 40 50 62.5E-3 G9 98 60 45 40 62.5E-3 D7 60 61 DX D8 62 60 DX V7 61 98 DC 0 V8 98 62 DC 0 FSY 99 50 POLY(2) V7 V8 6.27E-3 1 1 D9 41 45 DX D10 45 42 DX V5 40 41 0.18 V6 42 40 0.18 .MODEL QN NPN(BF=75.758) .MODEL DX D() .ENDS AD818A * AD820A SPICE Macro-model 2/95, Rev. A * ARG / ADSC * * This version of the AD820 model simulates the worst-case * parameters of the 'A' grade. The worst-case parameters * used correspond to those in the data sheet. * * Copyright 1995 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. * Use of this model indicates your acceptance with * the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD820A 1 2 99 50 25 * * INPUT STAGE & POLE AT 5MHZ * R3 5 99 2456 R4 6 99 2456 CIN 1 2 5E-12 C2 5 6 6.48E-12 I1 4 50 108E-6 IOS 1 2 1E-11 EOS 7 1 POLY(1) (12,98) 800E-6 2.41 J1 5 2 4 JX J2 6 7 4 JX GB1 50 2 POLY(3) (2,4) (2,5) (2,50) 0 1E-12 1E-12 1E-12 GB2 50 7 POLY(3) (7,4) (7,5) (7,50) 0 1E-12 1E-12 1E-12 * EREF 98 0 30 0 1 * * GAIN STAGE & POLE AT 25 HZ * R5 9 98 1.234E6 C3 9 25 32E-12 G1 98 9 6 5 4.07E-4 V1 8 98 0 V2 98 10 -1 D1 9 10 DX D2 8 9 DX * * COMMON-MODE GAIN NETWORK WITH ZERO AT 5 KHZ * R21 11 12 1E6 R22 12 98 200 C14 11 12 32.25E-12 E13 11 98 POLY(2) (2,98) (1,98) 0 0.5 0.5 * * POLE AT 10 MHZ * R23 18 98 1E6 C15 18 98 15.9E-15 G15 98 18 9 98 1E-6 * * OUTPUT STAGE * ES 26 51 POLY(1) (18,98) 1.72 1 RS 26 22 500 V3 23 51 1.03951 V4 21 23 1.36 C16 20 25 2E-12 C17 24 25 2E-12 RG1 20 97 1E8 RG2 24 97 1E8 Q1 20 20 97 PNP Q2 20 21 22 NPN Q3 24 23 22 PNP Q4 24 24 51 NPN Q5 25 20 97 PNP 20 Q6 25 24 51 NPN 20 VP 96 97 0 VN 51 52 0 EP 96 0 POLY(1) (99,0) 0.01 1 EN 52 0 POLY(1) (50,0) -0.015 1 R25 30 99 275E3 R26 30 50 275E3 FSY1 99 0 POLY(1) VP 210.5E-6 1 FSY2 0 50 POLY(1) VN 210.5E-6 1 * * MODELS USED * .MODEL JX NJF(BETA=7.67E-4 VTO=-2.000 IS=12.5E-12) .MODEL NPN NPN(BF=120 VAF=150 VAR=15 RB=2E3 RE=4 RC=200) .MODEL PNP PNP(BF=120 VAF=150 VAR=15 RB=2E3 RE=4 RC=900) .MODEL DX D(IS=1E-15) .ENDS AD820A * AD820B SPICE Macro-model 2/95, Rev. A * ARG / ADSC * * This version of the AD820 model simulates the worst-case * parameters of the 'B' grade. The worst-case parameters * used correspond to those in the data sheet. * * Copyright 1995 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. * Use of this model indicates your acceptance with * the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD820B 1 2 99 50 25 * * INPUT STAGE & POLE AT 5MHZ * R3 5 99 2456 R4 6 99 2456 CIN 1 2 5E-12 C2 5 6 6.48E-12 I1 4 50 108E-6 IOS 1 2 5E-12 EOS 7 1 POLY(1) (12,98) 400E-6 2.41 J1 5 2 4 JX J2 6 7 4 JX GB1 50 2 POLY(3) (2,4) (2,5) (2,50) 0 1E-12 1E-12 1E-12 GB2 50 7 POLY(3) (7,4) (7,5) (7,50) 0 1E-12 1E-12 1E-12 * EREF 98 0 30 0 1 * * GAIN STAGE & POLE AT 25 HZ * R5 9 98 1.234E6 C3 9 25 32E-12 G1 98 9 6 5 4.07E-4 V1 8 98 0 V2 98 10 -1 D1 9 10 DX D2 8 9 DX * * COMMON-MODE GAIN NETWORK WITH ZERO AT 2.47 KHZ * R21 11 12 1E6 R22 12 98 100 C14 11 12 64.5E-12 E13 11 98 POLY(2) (2,98) (1,98) 0 0.5 0.5 * * POLE AT 10 MHZ * R23 18 98 1E6 C15 18 98 15.9E-15 G15 98 18 9 98 1E-6 * * OUTPUT STAGE * ES 26 51 POLY(1) (18,98) 1.72 1 RS 26 22 500 V3 23 51 1.03951 V4 21 23 1.36 C16 20 25 2E-12 C17 24 25 2E-12 RG1 20 97 1E8 RG2 24 97 1E8 Q1 20 20 97 PNP Q2 20 21 22 NPN Q3 24 23 22 PNP Q4 24 24 51 NPN Q5 25 20 97 PNP 20 Q6 25 24 51 NPN 20 VP 96 97 0 VN 51 52 0 EP 96 0 POLY(1) (99,0) 0.01 1 EN 52 0 POLY(1) (50,0) -0.015 1 R25 30 99 275E3 R26 30 50 275E3 FSY1 99 0 POLY(1) VP 210.5E-6 1 FSY2 0 50 POLY(1) VN 210.5E-6 1 * * MODELS USED * .MODEL JX NJF(BETA=7.67E-4 VTO=-2.000 IS=5E-12) .MODEL NPN NPN(BF=120 VAF=150 VAR=15 RB=2E3 RE=4 RC=200) .MODEL PNP PNP(BF=120 VAF=150 VAR=15 RB=2E3 RE=4 RC=900) .MODEL DX D(IS=1E-15) .ENDS AD820B * AD822A SPICE Macro-model 2/95, Rev. A * ARG / ADSC * * This version of the AD822 model simulates the worst-case * parameters of the 'A' grade. The worst-case parameters * used correspond to those in the data sheet. * * Copyright 1995 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. * Use of this model indicates your acceptance with * the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD822A 1 2 99 50 25 * * INPUT STAGE & POLE AT 5MHZ * R3 5 99 2456 R4 6 99 2456 CIN 1 2 5E-12 C2 5 6 6.48E-12 I1 4 50 108E-6 IOS 1 2 1E-11 EOS 7 1 POLY(1) (12,98) 800E-6 2.41 J1 5 2 4 JX J2 6 7 4 JX GB1 50 2 POLY(3) (2,4) (2,5) (2,50) 0 1E-12 1E-12 1E-12 GB2 50 7 POLY(3) (7,4) (7,5) (7,50) 0 1E-12 1E-12 1E-12 * EREF 98 0 30 0 1 * * GAIN STAGE & POLE AT 25 HZ * R5 9 98 1.234E6 C3 9 25 32E-12 G1 98 9 6 5 4.07E-4 V1 8 98 0 V2 98 10 -1 D1 9 10 DX D2 8 9 DX * * COMMON-MODE GAIN NETWORK WITH ZERO AT 5 KHZ * R21 11 12 1E6 R22 12 98 200 C14 11 12 32.25E-12 E13 11 98 POLY(2) (2,98) (1,98) 0 0.5 0.5 * * POLE AT 10 MHZ * R23 18 98 1E6 C15 18 98 15.9E-15 G15 98 18 9 98 1E-6 * * OUTPUT STAGE * ES 26 51 POLY(1) (18,98) 1.72 1 RS 26 22 500 V3 23 51 1.03951 V4 21 23 1.36 C16 20 25 2E-12 C17 24 25 2E-12 RG1 20 97 1E8 RG2 24 97 1E8 Q1 20 20 97 PNP Q2 20 21 22 NPN Q3 24 23 22 PNP Q4 24 24 51 NPN Q5 25 20 97 PNP 20 Q6 25 24 51 NPN 20 VP 96 97 0 VN 51 52 0 EP 96 0 POLY(1) (99,0) 0.01 1 EN 52 0 POLY(1) (50,0) -0.015 1 R25 30 99 275E3 R26 30 50 275E3 FSY1 99 0 POLY(1) VP 210.5E-6 1 FSY2 0 50 POLY(1) VN 210.5E-6 1 * * MODELS USED * .MODEL JX NJF(BETA=7.67E-4 VTO=-2.000 IS=12.5E-12) .MODEL NPN NPN(BF=120 VAF=150 VAR=15 RB=2E3 RE=4 RC=200) .MODEL PNP PNP(BF=120 VAF=150 VAR=15 RB=2E3 RE=4 RC=900) .MODEL DX D(IS=1E-15) .ENDS AD822A * AD822B SPICE Macro-model 2/95, Rev. A * ARG / ADSC * * This version of the AD822 model simulates the worst-case * parameters of the 'B' grade. The worst-case parameters * used correspond to those in the data sheet. * * Copyright 1995 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. * Use of this model indicates your acceptance with * the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD822B 1 2 99 50 25 * * INPUT STAGE & POLE AT 5MHZ * R3 5 99 2456 R4 6 99 2456 CIN 1 2 5E-12 C2 5 6 6.48E-12 I1 4 50 108E-6 IOS 1 2 5E-12 EOS 7 1 POLY(1) (12,98) 400E-6 2.41 J1 5 2 4 JX J2 6 7 4 JX GB1 50 2 POLY(3) (2,4) (2,5) (2,50) 0 1E-12 1E-12 1E-12 GB2 50 7 POLY(3) (7,4) (7,5) (7,50) 0 1E-12 1E-12 1E-12 * EREF 98 0 30 0 1 * * GAIN STAGE & POLE AT 25 HZ * R5 9 98 1.234E6 C3 9 25 32E-12 G1 98 9 6 5 4.07E-4 V1 8 98 0 V2 98 10 -1 D1 9 10 DX D2 8 9 DX * * COMMON-MODE GAIN NETWORK WITH ZERO AT 3.5 KHZ * R21 11 12 1E6 R22 12 98 141 C14 11 12 45.6E-12 E13 11 98 POLY(2) (2,98) (1,98) 0 0.5 0.5 * * POLE AT 10 MHZ * R23 18 98 1E6 C15 18 98 15.9E-15 G15 98 18 9 98 1E-6 * * OUTPUT STAGE * ES 26 51 POLY(1) (18,98) 1.72 1 RS 26 22 500 V3 23 51 1.03951 V4 21 23 1.36 C16 20 25 2E-12 C17 24 25 2E-12 RG1 20 97 1E8 RG2 24 97 1E8 Q1 20 20 97 PNP Q2 20 21 22 NPN Q3 24 23 22 PNP Q4 24 24 51 NPN Q5 25 20 97 PNP 20 Q6 25 24 51 NPN 20 VP 96 97 0 VN 51 52 0 EP 96 0 POLY(1) (99,0) 0.01 1 EN 52 0 POLY(1) (50,0) -0.015 1 R25 30 99 275E3 R26 30 50 275E3 FSY1 99 0 POLY(1) VP 210.5E-6 1 FSY2 0 50 POLY(1) VN 210.5E-6 1 * * MODELS USED * .MODEL JX NJF(BETA=7.67E-4 VTO=-2.000 IS=5E-12) .MODEL NPN NPN(BF=120 VAF=150 VAR=15 RB=2E3 RE=4 RC=200) .MODEL PNP PNP(BF=120 VAF=150 VAR=15 RB=2E3 RE=4 RC=900) .MODEL DX D(IS=1E-15) .ENDS AD822B * AD823an Spice Macro-model 4/16/97, Rev C, SMR * * Copyright 1996 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. * Use of this model indicates your acceptance with * the terms and provisions in the License Statement. * * The following parameters are accurately modeled; * * open loop gain and phase vs frequency * output clamping voltage and current * input common mode range * CMRR vs freq * I bias vs Vcm in * Slew rate * Output currents are reflected to V supplies * Voltage and current noise density are accurate * for the entire bandwidth of the AD823 * * Vos is static and will not vary with Vcm input * * Step response is modeled at unity gain w/1k load * * Distortion is not characterized * * This model of the AD823 works at 3.3v * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD823an 1 2 99 50 11 ***** Input Stage/pole at 50mhz R1 1 13 5e12 R2 13 2 5e12 fn1 98 1 vn2 1 fn2 98 2 vn2 1 cin1 1 98 1.8e-12 cin2 2 98 1.8e-12 J1 24 1 25 jx J2 24 14 26 jx R3 99 25 708 R4 99 26 708 Cp 25 26 0.65pf Ibt 24 50 0.62ma Ib1 1 98 5p Ib2 2 98 5p Eos 2 12 poly(1) 34 98 0.2e-3 1 Enoise 12 14 36 98 1 ***** Input V noise source dn1 35 98 dn1 rn1 35 98 6.5e-5 vn1 35 98 0 hn1 36 98 vn1 1 rn2 36 98 1 ***** Input I noise source rn3 37 98 1.6e10 vn2 37 98 0 hn2 38 98 vn2 1 rn4 38 98 1 ***** Gain Stage & Pole @ 300Hz Vd1 99 3 0.91 Vd2 4 50 0.91 Gg1 99 5 26 25 1.413e-3 Gg2 5 50 25 26 1.413e-3 D1 5 3 dx D2 4 5 dx Rg1 99 5 21.23e6 Rg2 50 5 21.23e6 Cdp1 99 5 25pf Cdp2 50 5 25pf ***** Internal Reference Eref1 98 0 poly(2) (99,0) (50,0) 0 0.5 0.5 Eref2 97 0 poly(2) (1,0) (2,0) 0 0.5 0.5 ***** Common Mode Gain Network/Pole at 10khz Gacm1 15 98 98 97 1.4 Lacm2 15 29 10e-9 Racm2 29 98 1e-3 ***** Common Mode Gain Network/Zero at 300hz Ecm1 30 98 15 98 70e-3 Racm3 30 31 1.67e3 Racm4 31 32 100e-3 Lacm3 32 98 53e-6 ***** Common Mode Gain Network/Pole at 5mhz Ecm2 33 98 31 98 1 Lacm4 33 34 31.8u Racm 34 98 1k ***** Zero/Pole Stages (20MHz/50MHz)) ezp 16 98 5 98 2.5 rzp1 16 17 188 rzp2 17 18 126 lzp 18 98 1u ***** Buffer to output stage gbuf 98 19 17 98 1e-4 Rbuf 19 98 10k ***** Output Stage fo1 98 90 vcd 1 Do1 90 91 dx Do2 92 90 dx vi1 91 98 0 vi2 98 92 0 fsy 99 50 poly(2) vi1 vi2 5.7e-3 1 1 Go3 10 99 99 19 50m Go4 50 10 19 50 50m Ro3 99 10 20 Ro4 10 50 20 vcd 10 95 0 lo1 95 11 1e-10 ro 11 98 1e6 Do5 19 20 dx Do6 21 19 dx Vo1 20 10 -0.3 Vo2 10 21 -0.4 .model dx d(IS=1e-15) .model dn1 d(is=1e-15 af=0 kf=1e-12) .model jx njf(beta=3e-3 vto=-1 Is=1e-12) .ends ad823an * AD824B SPICE Macro-model 9/94, Rev. A * ARG / PMI * * This version of the AD824 model simulates the worst-case * parameters of the 'B' grade. The worst-case parameters * used correspond to those in the data sheet. * * Copyright 1993 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. * Use of this model indicates your acceptance with * the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD824B 1 2 99 50 25 * * INPUT STAGE & POLE AT 3.1MHZ * R3 5 99 1.193E3 R4 6 99 1.193E3 CIN 1 2 4E-12 C2 5 6 19.229E-12 I1 4 50 108E-6 IOS 1 2 10E-12 EOS 7 1 POLY(1) (12,98) 0.5E-3 1 J1 4 2 5 JX J2 4 7 6 JX * * GAIN STAGE & DOMINANT POLE * EREF 98 0 30 0 1 R5 9 98 2.205E6 C3 9 25 54E-12 G1 98 9 6 5 0.838E-3 V1 8 98 -1 V2 98 10 -1 D1 9 10 DX D2 8 9 DX * * COMMON-MODE GAIN NETWORK WITH ZERO AT 1KHZ * R21 11 12 1E6 R22 12 98 100 C14 11 12 159E-12 E13 11 98 POLY(2) (2,98) (1,98) 0 0.5 0.5 * * POLE AT 10MHZ * R23 18 98 1E6 C15 18 98 15.9E-15 G15 98 18 9 98 1E-6 * * OUTPUT STAGE * ES 26 98 18 98 1 RS 26 22 2.4E3 IB1 98 21 2.404E-3 IB2 23 98 2.404E-3 D10 21 98 DY D11 98 23 DY C16 20 25 2E-12 C17 24 25 2E-12 DQ1 97 20 DQ Q2 20 21 22 NPN Q3 24 23 22 PNP DQ2 24 51 DQ Q5 25 20 97 PNP 20 Q6 25 24 51 NPN 20 VP 96 97 0 VN 51 52 0 EP 96 0 99 0 1 EN 52 0 50 0 1 R25 30 99 25E3 R26 30 50 25E3 FSY1 99 0 VP 1 FSY2 0 50 VN 1 DC1 25 99 DX DC2 50 25 DX * * MODELS USED * .MODEL JX NJF(BETA=3.2526E-3 VTO=-2.000 IS=25E-12) .MODEL NPN NPN(BF=120 VAF=150 VAR=15 RB=2E3 + RE=4 RC=650 IS=1E-16) .MODEL PNP PNP(BF=120 VAF=150 VAR=15 RB=2E3 + RE=4 RC=1E3 IS=1E-16) .MODEL DX D(IS=1E-15) .MODEL DY D() .MODEL DQ D(IS=1E-16) .ENDS AD824B * AD826A SPICE Macro-model Rev. A, 11/92 * ARG / ADI * * This version of the AD826 model simulates the worst-case * parameters of the 'A' grade. The worst-case parameters * used correspond to those in the data sheet. * * * Copyright 1993 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of * this model indicates your acceptance of the terms and pro- * visions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD826A 2 1 99 50 46 * * INPUT STAGE AND POLE AT 160MHZ * I1 8 50 1E-3 Q1 4 1 6 QN Q2 5 3 7 QN CD 1 2 1.5E-12 CC1 1 0 2.4E-12 CC2 2 0 2.4E-12 R1 99 4 955 R2 99 5 955 C1 4 5 .521E-12 R3 6 8 903 R4 7 8 903 IOS 1 2 150E-9 EOS 3 2 POLY(1) (15,39) 2E-3 5 * * GAIN STAGE AND DOMINANT POLE AT 12.5KHZ * EREF 98 0 39 0 1 G1 98 9 4 5 1.047E-3 R5 9 98 3.820E6 C2 9 98 3.333E-12 D1 9 10 DX D2 11 9 DX V1 99 10 2.25 V2 11 50 2.25 * * COMMON MODE STAGE WITH ZERO AT 15.811KHZ * ECM 14 98 POLY(2) (1,39) (2,39) 0 0.5 0.5 R7 14 15 1E6 C4 14 15 10.066E-12 R8 15 98 10 * *POLE AT 120MHZ * GP2 98 31 9 39 1E-6 RP2 31 98 1E6 CP2 31 98 1.326E-15 * *ZERO AT 75MHZ * EZ1 32 98 31 39 1E6 RZ1 32 33 1E6 RZ2 33 98 1 CZ1 32 33 2.12E-15 * *ZERO AT 100MHZ * EZ2 34 98 33 39 1E6 RZ3 34 35 1E6 RZ4 35 98 1 CZ2 34 35 1.59E-15 * *POLE AT 160MHZ * GP3 98 36 35 39 1E-6 RP3 36 98 1E6 CP3 36 98 .995E-15 * *POLE AT 160MHZ * GP10 98 40 36 39 1E-6 RP10 40 98 1E6 CP10 40 98 .995E-15 * * OUTPUT STAGE * RS1 99 39 20.548E3 RS2 39 50 20.548E3 RO1 99 45 16 RO2 45 50 16 G7 45 99 99 40 62.5E-3 G8 50 45 40 50 62.5E-3 G9 98 60 45 40 62.5E-3 D7 60 61 DX D8 62 60 DX V7 61 98 DC 0 V8 98 62 DC 0 FSY 99 50 POLY(2) V7 V8 5.77E-3 1 1 D9 41 45 DX D10 45 42 DX V5 40 41 0.4 V6 42 40 0.4 LO 45 46 .06E-9 * * MODELS USED * .MODEL DX D(IS=1E-12) .MODEL QN NPN(BF=74.76) .ENDS AD826A* AD828A SPICE Model Rev. A, 4/93 * ARG / PMI * * This version of the AD828 model simulates the worst-case * parameters of the 'A' grade. The worst-case parameters * used correspond to those in the data sheet. * * * Copyright 1993 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of * this model indicates your acceptance of the terms and pro- * visions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD828A 2 1 99 50 46 * * INPUT STAGE AND POLE AT 500MHZ * I1 4 50 1E-3 CIN 1 2 1.5E-12 CC1 1 0 .5E-12 CC2 2 0 .5E-12 IOS 2 1 150E-9 Q1 5 1 7 QN Q2 6 3 8 QN R3 99 5 796 R4 99 6 796 R5 7 4 744 R6 8 4 744 C1 5 6 200E-15 EOS 3 2 POLY(1) (21,98) 2E-3 0.5 * * GAIN STAGE AND DOMINANT POLE AT 15KHZ * EREF 98 0 39 0 1 G1 98 9 5 6 1.257E-3 R7 9 98 4.775E6 C2 9 98 2.222E-12 D1 9 10 DX D2 11 9 DX V1 99 10 2.4 V2 11 50 2.4 * * NEGATIVE ZERO AT 150MHZ * E1 14 98 9 39 1E6 R11 14 15 1 R12 15 98 1E-6 FNZ 14 15 VNZ -1 ENZ 16 98 14 15 1 VNZ 17 98 DC 0 CNZ 16 17 1.061E-9 * * ZERO/POLE AT 60MHZ/75MHZ * E2 18 98 15 39 1.25 R13 18 19 1 R14 19 98 4 C5 18 19 2.653E-9 * * COMMON MODE GAIN STAGE WITH ZERO AT 5KHZ * ECM 20 98 POLY(2) (1,39) (2,39) 0 0.5 0.5 R8 20 21 1E6 R9 21 98 100 C3 20 21 31.831E-12 * * POLE AT 400MHZ * G2 98 40 19 39 1E-6 R10 40 98 1E6 C4 40 98 .398E-15 * * OUTPUT STAGE * RS1 99 39 20.548E3 RS2 39 50 20.548E3 RO1 99 45 16 RO2 45 50 16 G7 45 99 99 40 62.5E-3 G8 50 45 40 50 62.5E-3 G9 98 60 45 40 62.5E-3 D7 60 61 DX D8 62 60 DX V7 61 98 DC 0 V8 98 62 DC 0 FSY 99 50 POLY(2) V7 V8 5.77E-3 1 1 D9 41 45 DX D10 45 42 DX V5 40 41 0.4 V6 42 40 0.4 LO 45 46 5E-8 .MODEL QN NPN(BF=74.76) .MODEL DX D(IS=1E-12) .ENDS AD828A* AD829A SPICE Macro-model 9/90, Rev. A * JCB / PMI * * This version of the AD829 model simulates the worst case * parameters of the 'A' grade. The worst case parameters * used correspond to those in the data sheet. * * Copyright 1990 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | compensation node * | | | | | | .SUBCKT AD829A 1 2 99 50 30 12 * * INPUT STAGE & POLE AT 200 MHZ * R1 2 3 17.8E3 R2 1 3 17.8E3 R3 5 99 56.4 R4 6 99 56.4 CIN 1 2 5E-12 C2 5 6 7.18E-12 I1 4 50 1.2E-3 IOS 1 2 250E-9 EOS 9 1 POLY(1) 19 23 0.5E-3 1 Q1 5 2 10 QX Q2 6 9 11 QX R5 10 4 13.4 R6 11 4 13.4 * EREF 98 0 23 0 1 * * GAIN STAGE & DOMINANT POLE AT 2.7 KHZ * R7 12 98 2.82E6 C3 12 98 5.2E-12 G1 98 12 5 6 17.73E-3 V2 99 13 3.4 V3 14 50 3.4 D3 12 13 DX D4 14 12 DX * * ZERO/POLE PAIR AT 50MHz/100MHz * R8 15 16 1E6 R9 16 98 1E6 L1 16 98 1.59E-3 G2 98 15 12 23 1E-6 * * POLE AT 400 MHZ * R41 41 98 1E6 C41 41 98 398E-18 G41 98 41 15 23 1E-6 * * POLE AT 400 MHZ * R42 42 98 1E6 C42 42 98 398E-18 G42 98 42 41 23 1E-6 * * POLE AT 200 MHZ * R43 43 98 1E6 C43 43 98 796E-18 G43 98 43 42 23 1E-6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 30 KHZ * R11 18 19 1E6 C6 18 19 5.31E-12 R12 19 98 1 E2 18 98 3 23 10 * * POLE AT 400 MHZ * R15 22 98 1E6 C8 22 98 398E-18 G3 98 22 43 23 1E-6 * * OUTPUT STAGE * RF 25 60 500 CF 60 12 12.5E-12 R16 23 99 100E3 R17 23 50 100E3 ISY 99 50 5.45E-3 R18 25 99 30 R19 25 50 30 L2 25 30 1E-8 G4 28 50 22 25 33.33E-3 G5 29 50 25 22 33.33E-3 G6 25 99 99 22 33.33E-3 G7 50 25 22 50 33.33E-3 V4 26 25 -0.2 V5 25 27 -0.2 D5 22 26 DX D6 27 22 DX D7 99 28 DX D8 99 29 DX D9 50 28 DY D10 50 29 DY * * MODELS USED * .MODEL QX NPN(BF=85.7) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * AD829J SPICE Macro-model 9/90, Rev. A * JCB / PMI * * This version of the AD829 model simulates the worst case * parameters of the 'J' grade. The worst case parameters * used correspond to those in the data sheet. * * Copyright 1990 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | compensation node * | | | | | | .SUBCKT AD829J 1 2 99 50 30 12 * * INPUT STAGE & POLE AT 200 MHZ * R1 2 3 17.8E3 R2 1 3 17.8E3 R3 5 99 56.4 R4 6 99 56.4 CIN 1 2 5E-12 C2 5 6 7.18E-12 I1 4 50 1.2E-3 IOS 1 2 250E-9 EOS 9 1 POLY(1) 19 23 1.0E-3 1 Q1 5 2 10 QX Q2 6 9 11 QX R5 10 4 13.4 R6 11 4 13.4 * EREF 98 0 23 0 1 * * GAIN STAGE & DOMINANT POLE AT 2.7 KHZ * R7 12 98 2.82E6 C3 12 98 5.2E-12 G1 98 12 5 6 17.73E-3 V2 99 13 3.4 V3 14 50 3.4 D3 12 13 DX D4 14 12 DX * * ZERO/POLE PAIR AT 50MHz/100MHz * R8 15 16 1E6 R9 16 98 1E6 L1 16 98 1.59E-3 G2 98 15 12 23 1E-6 * * POLE AT 400 MHZ * R41 41 98 1E6 C41 41 98 398E-18 G41 98 41 15 23 1E-6 * * POLE AT 400 MHZ * R42 42 98 1E6 C42 42 98 398E-18 G42 98 42 41 23 1E-6 * * POLE AT 200 MHZ * R43 43 98 1E6 C43 43 98 796E-18 G43 98 43 42 23 1E-6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 30 KHZ * R11 18 19 1E6 C6 18 19 5.31E-12 R12 19 98 1 E2 18 98 3 23 10 * * POLE AT 400 MHZ * R15 22 98 1E6 C8 22 98 398E-18 G3 98 22 43 23 1E-6 * * OUTPUT STAGE * RF 25 60 500 CF 60 12 12.5E-12 R16 23 99 100E3 R17 23 50 100E3 ISY 99 50 5.45E-3 R18 25 99 30 R19 25 50 30 L2 25 30 1E-8 G4 28 50 22 25 33.33E-3 G5 29 50 25 22 33.33E-3 G6 25 99 99 22 33.33E-3 G7 50 25 22 50 33.33E-3 V4 26 25 -0.2 V5 25 27 -0.2 D5 22 26 DX D6 27 22 DX D7 99 28 DX D8 99 29 DX D9 50 28 DY D10 50 29 DY * * MODELS USED * .MODEL QX NPN(BF=85.7) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * AD829S SPICE Macro-model 9/90, Rev. A * JCB / PMI * * This version of the AD829 model simulates the worst case * parameters of the 'S' grade. The worst case parameters * used correspond to those in the data sheet. * * Copyright 1990 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | compensation node * | | | | | | .SUBCKT AD829S 1 2 99 50 30 12 * * INPUT STAGE & POLE AT 200 MHZ * R1 2 3 17.8E3 R2 1 3 17.8E3 R3 5 99 56.4 R4 6 99 56.4 CIN 1 2 5E-12 C2 5 6 7.18E-12 I1 4 50 1.2E-3 IOS 1 2 250E-9 EOS 9 1 POLY(1) 19 23 0.5E-3 1 Q1 5 2 10 QX Q2 6 9 11 QX R5 10 4 13.4 R6 11 4 13.4 * EREF 98 0 23 0 1 * * GAIN STAGE & DOMINANT POLE AT 2.7 KHZ * R7 12 98 2.82E6 C3 12 98 5.2E-12 G1 98 12 5 6 17.73E-3 V2 99 13 3.4 V3 14 50 3.4 D3 12 13 DX D4 14 12 DX * * ZERO/POLE PAIR AT 50MHz/100MHz * R8 15 16 1E6 R9 16 98 1E6 L1 16 98 1.59E-3 G2 98 15 12 23 1E-6 * * POLE AT 400 MHZ * R41 41 98 1E6 C41 41 98 398E-18 G41 98 41 15 23 1E-6 * * POLE AT 400 MHZ * R42 42 98 1E6 C42 42 98 398E-18 G42 98 42 41 23 1E-6 * * POLE AT 200 MHZ * R43 43 98 1E6 C43 43 98 796E-18 G43 98 43 42 23 1E-6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 30 KHZ * R11 18 19 1E6 C6 18 19 5.31E-12 R12 19 98 1 E2 18 98 3 23 10 * * POLE AT 400 MHZ * R15 22 98 1E6 C8 22 98 398E-18 G3 98 22 43 23 1E-6 * * OUTPUT STAGE * RF 25 60 500 CF 60 12 12.5E-12 R16 23 99 100E3 R17 23 50 100E3 ISY 99 50 5.45E-3 R18 25 99 30 R19 25 50 30 L2 25 30 1E-8 G4 28 50 22 25 33.33E-3 G5 29 50 25 22 33.33E-3 G6 25 99 99 22 33.33E-3 G7 50 25 22 50 33.33E-3 V4 26 25 -0.2 V5 25 27 -0.2 D5 22 26 DX D6 27 22 DX D7 99 28 DX D8 99 29 DX D9 50 28 DY D10 50 29 DY * * MODELS USED * .MODEL QX NPN(BF=85.7) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * AD840J SPICE Macro-model 1/91, Rev. A * AAG / PMI * * This version of the AD-840 model simulates the worst case * parameters of the 'J' grade. The worst case parameters * used correspond to those in the data sheet. * * Copyright 1991 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD840J 1 2 100 101 36 * * INPUT STAGE & POLE AT 120 MHz * IOS 1 2 DC 0.2E-6 CIN 1 2 2E-12 R1 1 3 3.2325E3 R2 2 3 3.2325E3 EOS 9 1 POLY(1) 16 11 1E-3 1 R3 100 5 195.45 R4 100 6 195.45 C2 5 6 3.3929E-12 R5 7 4 143.73 R6 8 4 143.73 Q1 5 2 7 QX Q2 6 9 8 QX I1 4 101 DC 1E-3 * * VIRTUAL NODE * RVN1 100 10 25E3 RVN2 10 101 25E3 * * GAIN STAGE & DOMINANT POLE AT 3.8 KHz * EREF 11 0 10 0 1 G1 11 12 5 6 5.1163E-3 R7 12 11 14.659E6 C3 12 11 2.857E-12 V1 100 13 DC 5.0875 D1 12 13 DX V2 14 101 DC 5.0875 D2 14 12 DX * * COMMON-MODE GAIN NETWORK WITH ZERO AT 200 KHz * ECM 15 11 3 11 31.623 RCM1 15 16 1E6 CCM 15 16 795.77E-15 RCM2 16 11 1 * * NEGATIVE ZERO STAGE AT 290 MHz * EZ1 17 11 12 11 1E6 RZ1 17 18 1 CZ1 17 18 -548.81E-12 RZ2 18 11 1E-6 * * POLE STAGE AT 500 MHz * GP1 11 19 18 11 1E-6 RP1 19 11 1E6 CP1 19 11 318.31E-18 * * OUTPUT STAGE * IDC 100 101 DC 10.4E-3 VX 19 30 0 V3 32 35 DC 2.725 D3 30 32 DX V4 35 33 DC 2.575 D4 33 30 DX D5 100 31 DX GO1 31 101 30 35 16.667E-3 D6 101 31 DY D7 100 34 DX GO2 34 101 35 30 16.667E-3 D8 101 34 DY RO1 100 35 60 GO3 35 100 100 30 16.667E-3 RO2 35 101 60 GO4 101 35 30 101 16.667E-3 LO 35 36 0.04E-6 * * MODELS USED * .MODEL QX NPN(BF=62.5) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * AD840K SPICE Macro-model 1/91, Rev. A * AAG / PMI * * This version of the AD-840 model simulates the worst case * parameters of the 'K' grade. The worst case parameters * used correspond to those in the data sheet. * * Copyright 1991 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD840K 1 2 100 101 36 * * INPUT STAGE & POLE AT 120 MHz * IOS 1 2 DC 0.1E-6 CIN 1 2 2E-12 R1 1 3 5.172E3 R2 2 3 5.172E3 EOS 9 1 POLY(1) 16 11 300E-6 1 R3 100 5 195.46 R4 100 6 195.46 C2 5 6 3.3927E-12 R5 7 4 143.74 R6 8 4 143.74 Q1 5 2 7 QX Q2 6 9 8 QX I1 4 101 DC 1E-3 * * VIRTUAL NODE * RVN1 100 10 25E3 RVN2 10 101 25E3 * * GAIN STAGE & DOMINANT POLE AT 2.85 KHz * EREF 11 0 10 0 1 G1 11 12 5 6 5.1161E-3 R7 12 11 19.546E6 C3 12 11 2.857E-12 V1 100 13 DC 5.0875 D1 12 13 DX V2 14 101 DC 5.0875 D2 14 12 DX * * COMMON-MODE GAIN NETWORK WITH ZERO AT 31.7 KHz * ECM 15 11 3 11 5.0119 RCM1 15 16 1E6 CCM 15 16 5.0207E-12 RCM2 16 11 1 * * NEGATIVE ZERO STAGE AT 290 MHz * EZ1 17 11 12 11 1E6 RZ1 17 18 1 CZ1 17 18 -548.81E-12 RZ2 18 11 1E-6 * * POLE STAGE AT 500 MHz * GP1 11 19 18 11 1E-6 RP1 19 11 1E6 CP1 19 11 318.31E-18 * * OUTPUT STAGE * IDC 100 101 DC 10.4E-3 VX 19 30 0 V3 32 35 DC 2.725 D3 30 32 DX V4 35 33 DC 2.575 D4 33 30 DX D5 100 31 DX GO1 31 101 30 35 16.667E-3 D6 101 31 DY D7 100 34 DX GO2 34 101 35 30 16.667E-3 D8 101 34 DY RO1 100 35 60 GO3 35 100 100 30 16.667E-3 RO2 35 101 60 GO4 101 35 30 101 16.667E-3 LO 35 36 0.04E-6 * * MODELS USED * .MODEL QX NPN(BF=100) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * AD840S SPICE Macro-model 1/91, Rev. A * AAG / PMI * * This version of the AD-840 model simulates the worst case * parameters of the 'S' grade. The worst case parameters * used correspond to those in the data sheet. * * Copyright 1991 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD840S 1 2 100 101 36 * * INPUT STAGE & POLE AT 120 MHz * IOS 1 2 DC 0.2E-6 CIN 1 2 2E-12 R1 1 3 3.2325E3 R2 2 3 3.2325E3 EOS 9 1 POLY(1) 16 11 1E-3 1 R3 100 5 195.45 R4 100 6 195.45 C2 5 6 3.3929E-12 R5 7 4 143.73 R6 8 4 143.73 Q1 5 2 7 QX Q2 6 9 8 QX I1 4 101 DC 1E-3 * * VIRTUAL NODE * RVN1 100 10 25E3 RVN2 10 101 25E3 * * GAIN STAGE & DOMINANT POLE AT 3.8 KHz * EREF 11 0 10 0 1 G1 11 12 5 6 5.1163E-3 R7 12 11 14.659E6 C3 12 11 2.857E-12 V1 100 13 DC 5.0875 D1 12 13 DX V2 14 101 DC 5.0875 D2 14 12 DX * * COMMON-MODE GAIN NETWORK WITH ZERO AT 200 KHz * ECM 15 11 3 11 31.623 RCM1 15 16 1E6 CCM 15 16 795.77E-15 RCM2 16 11 1 * * NEGATIVE ZERO STAGE AT 290 MHz * EZ1 17 11 12 11 1E6 RZ1 17 18 1 CZ1 17 18 -548.81E-12 RZ2 18 11 1E-6 * * POLE STAGE AT 500 MHz * GP1 11 19 18 11 1E-6 RP1 19 11 1E6 CP1 19 11 318.31E-18 * * OUTPUT STAGE * IDC 100 101 DC 10.4E-3 VX 19 30 0 V3 32 35 DC 2.725 D3 30 32 DX V4 35 33 DC 2.575 D4 33 30 DX D5 100 31 DX GO1 31 101 30 35 16.667E-3 D6 101 31 DY D7 100 34 DX GO2 34 101 35 30 16.667E-3 D8 101 34 DY RO1 100 35 60 GO3 35 100 100 30 16.667E-3 RO2 35 101 60 GO4 101 35 30 101 16.667E-3 LO 35 36 0.04E-6 * * MODELS USED * .MODEL QX NPN(BF=62.5) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * AD843A SPICE Macro-model 1/92, Rev. A * JCB / PMI * * This version of the AD843 model simulates the worst case * parameters of the 'A' grade. The worst case parameters * used correspond to those in the data sheet. * * Copyright 1991 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD843A 1 2 99 50 30 * * INPUT STAGE & POLE AT 150 MHZ * R1 1 3 5E11 R2 2 3 5E11 R3 5 50 693.9 R4 6 50 693.9 CIN 1 2 4E-12 C2 5 6 0.765E-12 I1 99 4 1.0E-3 IOS 1 2 5E-10 EOS 7 1 POLY(1) 16 24 2E-3 1 J1 5 2 4 JX J2 6 7 4 JX * EREF 98 0 24 0 1 * * GAIN STAGE & POLE AT 2.45 KHZ * R5 9 98 1.04E7 C3 9 98 6.25E-12 G1 98 9 5 6 1.44E-3 V2 99 8 5.2 V3 10 50 5.2 D1 9 8 DX D2 10 9 DX * * POLE AT 200 MHZ * R6 11 98 1E6 C4 11 98 0.796E-15 G2 98 11 9 24 1E-6 * * NEGATIVE ZERO AT 100 MHZ * R8 13 14 1E6 R9 14 98 1 C6 13 14 -1.59E-15 E2 13 98 11 24 1000001 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 120 KHZ * R10 15 16 1E6 R11 16 98 1 C7 15 16 1.326E-12 E3 98 15 3 24 1000 * * POLE AT 200 MHZ * R12 23 98 1E6 C8 23 98 0.796E-15 G4 98 23 14 24 1E-6 * * OUTPUT STAGE * R13 24 99 50E3 R14 24 50 50E3 ISY 99 50 11.7E-3 R15 29 99 40 R16 29 50 40 L1 29 30 6E-8 G5 27 50 23 29 2.5E-2 G6 28 50 29 23 2.5E-2 G7 29 99 99 23 2.5E-2 G8 50 29 23 50 2.5E-2 V4 25 29 0.3 V5 29 26 0.3 D3 23 25 DX D4 26 23 DX D5 99 27 DX D6 99 28 DX D7 50 27 DY D8 50 28 DY * * MODELS USED * .MODEL JX PJF(BETA=1.04E-3 VTO=-2.000 IS=2.5E-9) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * AD843B SPICE Macro-model 1/92, Rev. A * JCB / PMI * * This version of the AD843 model simulates the worst case * parameters of the 'B' grade. The worst case parameters * used correspond to those in the data sheet. * * Copyright 1991 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD843B 1 2 99 50 30 * * INPUT STAGE & POLE AT 150 MHZ * R1 1 3 5E11 R2 2 3 5E11 R3 5 50 693.9 R4 6 50 693.9 CIN 1 2 4E-12 C2 5 6 0.765E-12 I1 99 4 1.0E-3 IOS 1 2 2E-10 EOS 7 1 POLY(1) 16 24 1E-3 1 J1 5 2 4 JX J2 6 7 4 JX * EREF 98 0 24 0 1 * * GAIN STAGE & POLE AT 1.83 KHZ * R5 9 98 1.39E7 C3 9 98 6.25E-12 G1 98 9 5 6 1.44E-3 V2 99 8 5.2 V3 10 50 5.2 D1 9 8 DX D2 10 9 DX * * POLE AT 200 MHZ * R6 11 98 1E6 C4 11 98 0.796E-15 G2 98 11 9 24 1E-6 * * NEGATIVE ZERO AT 100 MHZ * R8 13 14 1E6 R9 14 98 1 C6 13 14 -1.59E-15 E2 13 98 11 24 1000001 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 38 KHZ * R10 15 16 1E6 R11 16 98 1 C7 15 16 4.194E-12 E3 98 15 3 24 316.2 * * POLE AT 200 MHZ * R12 23 98 1E6 C8 23 98 0.796E-15 G4 98 23 14 24 1E-6 * * OUTPUT STAGE * R13 24 99 50E3 R14 24 50 50E3 ISY 99 50 11.7E-3 R15 29 99 40 R16 29 50 40 L1 29 30 6E-8 G5 27 50 23 29 2.5E-2 G6 28 50 29 23 2.5E-2 G7 29 99 99 23 2.5E-2 G8 50 29 23 50 2.5E-2 V4 25 29 0.3 V5 29 26 0.3 D3 23 25 DX D4 26 23 DX D5 99 27 DX D6 99 28 DX D7 50 27 DY D8 50 28 DY * * MODELS USED * .MODEL JX PJF(BETA=1.04E-3 VTO=-2.000 IS=1E-9) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * AD843J SPICE Macro-model 1/92, Rev. A * JCB / PMI * * This version of the AD843 model simulates the worst case * parameters of the 'J' grade. The worst case parameters * used correspond to those in the data sheet. * * Copyright 1991 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD843J 1 2 99 50 30 * * INPUT STAGE & POLE AT 150 MHZ * R1 1 3 5E11 R2 2 3 5E11 R3 5 50 693.9 R4 6 50 693.9 CIN 1 2 4E-12 C2 5 6 0.765E-12 I1 99 4 1.0E-3 IOS 1 2 5E-10 EOS 7 1 POLY(1) 16 24 2E-3 1 J1 5 2 4 JX J2 6 7 4 JX * EREF 98 0 24 0 1 * * GAIN STAGE & POLE AT 2.45 KHZ * R5 9 98 1.04E7 C3 9 98 6.25E-12 G1 98 9 5 6 1.44E-3 V2 99 8 5.2 V3 10 50 5.2 D1 9 8 DX D2 10 9 DX * * POLE AT 200 MHZ * R6 11 98 1E6 C4 11 98 0.796E-15 G2 98 11 9 24 1E-6 * * NEGATIVE ZERO AT 100 MHZ * R8 13 14 1E6 R9 14 98 1 C6 13 14 -1.59E-15 E2 13 98 11 24 1000001 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 120 KHZ * R10 15 16 1E6 R11 16 98 1 C7 15 16 1.326E-12 E3 98 15 3 24 1000 * * POLE AT 200 MHZ * R12 23 98 1E6 C8 23 98 0.796E-15 G4 98 23 14 24 1E-6 * * OUTPUT STAGE * R13 24 99 50E3 R14 24 50 50E3 ISY 99 50 11.7E-3 R15 29 99 40 R16 29 50 40 L1 29 30 6E-8 G5 27 50 23 29 2.5E-2 G6 28 50 29 23 2.5E-2 G7 29 99 99 23 2.5E-2 G8 50 29 23 50 2.5E-2 V4 25 29 0.3 V5 29 26 0.3 D3 23 25 DX D4 26 23 DX D5 99 27 DX D6 99 28 DX D7 50 27 DY D8 50 28 DY * * MODELS USED * .MODEL JX PJF(BETA=1.04E-3 VTO=-2.000 IS=2.5E-9) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * AD843K SPICE Macro-model 1/92, Rev. A * JCB / PMI * * This version of the AD843 model simulates the worst case * parameters of the 'K' grade. The worst case parameters * used correspond to those in the data sheet. * * Copyright 1991 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD843K 1 2 99 50 30 * * INPUT STAGE & POLE AT 150 MHZ * R1 1 3 5E11 R2 2 3 5E11 R3 5 50 693.9 R4 6 50 693.9 CIN 1 2 4E-12 C2 5 6 0.765E-12 I1 99 4 1.0E-3 IOS 1 2 2E-10 EOS 7 1 POLY(1) 16 24 1E-3 1 J1 5 2 4 JX J2 6 7 4 JX * EREF 98 0 24 0 1 * * GAIN STAGE & POLE AT 1.83 KHZ * R5 9 98 1.39E7 C3 9 98 6.25E-12 G1 98 9 5 6 1.44E-3 V2 99 8 5.2 V3 10 50 5.2 D1 9 8 DX D2 10 9 DX * * POLE AT 200 MHZ * R6 11 98 1E6 C4 11 98 0.796E-15 G2 98 11 9 24 1E-6 * * NEGATIVE ZERO AT 100 MHZ * R8 13 14 1E6 R9 14 98 1 C6 13 14 -1.59E-15 E2 13 98 11 24 1000001 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 38 KHZ * R10 15 16 1E6 R11 16 98 1 C7 15 16 4.194E-12 E3 98 15 3 24 316.2 * * POLE AT 200 MHZ * R12 23 98 1E6 C8 23 98 0.796E-15 G4 98 23 14 24 1E-6 * * OUTPUT STAGE * R13 24 99 50E3 R14 24 50 50E3 ISY 99 50 11.7E-3 R15 29 99 40 R16 29 50 40 L1 29 30 6E-8 G5 27 50 23 29 2.5E-2 G6 28 50 29 23 2.5E-2 G7 29 99 99 23 2.5E-2 G8 50 29 23 50 2.5E-2 V4 25 29 0.3 V5 29 26 0.3 D3 23 25 DX D4 26 23 DX D5 99 27 DX D6 99 28 DX D7 50 27 DY D8 50 28 DY * * MODELS USED * .MODEL JX PJF(BETA=1.04E-3 VTO=-2.000 IS=1E-9) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * AD843S SPICE Macro-model 1/92, Rev. A * JCB / PMI * * This version of the AD843 model simulates the worst case * parameters of the 'S' grade. The worst case parameters * used correspond to those in the data sheet. * * Copyright 1991 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD843S 1 2 99 50 30 * * INPUT STAGE & POLE AT 150 MHZ * R1 1 3 5E11 R2 2 3 5E11 R3 5 50 693.9 R4 6 50 693.9 CIN 1 2 4E-12 C2 5 6 0.765E-12 I1 99 4 1.0E-3 IOS 1 2 5E-10 EOS 7 1 POLY(1) 16 24 2E-3 1 J1 5 2 4 JX J2 6 7 4 JX * EREF 98 0 24 0 1 * * GAIN STAGE & POLE AT 2.45 KHZ * R5 9 98 1.04E7 C3 9 98 6.25E-12 G1 98 9 5 6 1.44E-3 V2 99 8 5.2 V3 10 50 5.2 D1 9 8 DX D2 10 9 DX * * POLE AT 200 MHZ * R6 11 98 1E6 C4 11 98 0.796E-15 G2 98 11 9 24 1E-6 * * NEGATIVE ZERO AT 100 MHZ * R8 13 14 1E6 R9 14 98 1 C6 13 14 -1.59E-15 E2 13 98 11 24 1000001 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 120 KHZ * R10 15 16 1E6 R11 16 98 1 C7 15 16 1.326E-12 E3 98 15 3 24 1000 * * POLE AT 200 MHZ * R12 23 98 1E6 C8 23 98 0.796E-15 G4 98 23 14 24 1E-6 * * OUTPUT STAGE * R13 24 99 50E3 R14 24 50 50E3 ISY 99 50 11.7E-3 R15 29 99 40 R16 29 50 40 L1 29 30 6E-8 G5 27 50 23 29 2.5E-2 G6 28 50 29 23 2.5E-2 G7 29 99 99 23 2.5E-2 G8 50 29 23 50 2.5E-2 V4 25 29 0.3 V5 29 26 0.3 D3 23 25 DX D4 26 23 DX D5 99 27 DX D6 99 28 DX D7 50 27 DY D8 50 28 DY * * MODELS USED * .MODEL JX PJF(BETA=1.04E-3 VTO=-2.000 IS=2.5E-9) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * AD845A SPICE Macro-model 12/90, Rev. A * AAG / PMI * * This version of the AD-845 model simulates the worst case * parameters of the 'A' grade. The worst case parameters * used correspond to those in the data sheet. * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD845A 1 2 100 101 36 * * INPUT STAGE & POLE AT 170 MHz * R1 1 3 5E10 R2 2 3 5E10 R3 100 5 656.31 R4 100 6 656.31 CIN 1 2 4E-12 C2 5 6 713.23E-15 I1 4 101 1E-3 IOS 1 2 DC 150E-12 EOS 7 1 POLY(1) 13 14 1.5E-3 1 J1 5 2 4 JX J2 6 7 4 JX * * GAIN STAGE & DOMINANT POLE AT 194 Hz * EREF 8 0 14 0 1 G1 8 9 5 6 1.5237E-3 R5 9 8 65.631E6 C3 9 8 12.5E-12 V1 100 10 DC 2.8125 D1 9 10 DX V2 11 101 DC 2.8125 D2 11 9 DX * * COMMON-MODE GAIN NETWORK WITH ZERO AT 158.49 KHz * ECM 12 8 3 14 50.119 RCM1 12 13 1E6 RCM2 13 8 1 CCM 12 13 1.0042E-12 * * VIRTUAL NODE * RVN1 100 14 17.33E3 RVN2 14 101 17.33E3 * * POLE STAGE AT 170 MHz * GP1 8 15 9 14 1E-6 RP1 15 8 1E6 CP1 15 8 0.93621E-15 * * NEGATIVE ZERO STAGE AT 46 MHz * EZ1 16 8 15 14 1E6 RZ1 16 17 1 RZ2 17 8 1E-6 CZ1 16 17 -3.4599E-9 * * POLE STAGE AT 170 MHz * GP2 8 18 17 14 1E-6 RP2 18 8 1E6 CP2 18 8 0.93621E-15 * * OUTPUT STAGE * IDC 100 101 DC 10.135E-3 VX 18 30 0 V3 32 35 DC 0.15 D3 30 32 DX V4 35 33 DC 0.15 D4 33 30 DX D5 100 31 DX GO1 31 101 30 35 33.33E-3 D6 101 31 DY D7 100 34 DX GO2 34 101 35 30 33.33E-3 D8 101 34 DY RO1 100 35 30 GO3 35 100 100 30 33.33E-3 RO2 35 101 30 GO4 101 35 30 101 33.33E-3 LO 35 36 45E-9 * * MODELS USED * .MODEL JX NJF(VTO=-2 BETA=1.1608E-3 IS=1E-9) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * AD845B SPICE Macro-model 12/90, Rev. A * AAG / PMI * * This version of the AD-845 model simulates the worst case * parameters of the 'B' grade. The worst case parameters * used correspond to those in the data sheet. * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD845B 1 2 100 101 36 * * INPUT STAGE & POLE AT 170 MHz * R1 1 3 5E10 R2 2 3 5E10 R3 100 5 771.16 R4 100 6 771.16 CIN 1 2 4E-12 C2 5 6 607.01E-15 I1 4 101 1E-3 IOS 1 2 DC 50E-12 EOS 7 1 POLY(1) 13 14 250E-6 1 J1 5 2 4 JX J2 6 7 4 JX * * GAIN STAGE & DOMINANT POLE AT 155.2 Hz * EREF 8 0 14 0 1 G1 8 9 5 6 1.2967E-3 R5 9 8 96.395E6 C3 9 8 10.638E-12 V1 100 10 DC 2.8125 D1 9 10 DX V2 11 101 DC 2.8125 D2 11 9 DX * * COMMON-MODE GAIN NETWORK WITH ZERO AT 63.096 KHz * ECM 12 8 3 14 19.953 RCM1 12 13 1E6 RCM2 13 8 1 CCM 12 13 2.522E-12 * * VIRTUAL NODE * RVN1 100 14 17.33E3 RVN2 14 101 17.33E3 * * POLE STAGE AT 170 MHz * GP1 8 15 9 14 1E-6 RP1 15 8 1E6 CP1 15 8 0.93621E-15 * * NEGATIVE ZERO STAGE AT 46 MHz * EZ1 16 8 15 14 1E6 RZ1 16 17 1 RZ2 17 8 1E-6 CZ1 16 17 -3.4599E-9 * * POLE STAGE AT 170 MHz * GP2 8 18 17 14 1E-6 RP2 18 8 1E6 CP2 18 8 0.93621E-15 * * OUTPUT STAGE * IDC 100 101 DC 10.135E-3 VX 18 30 0 V3 32 35 DC 0.15 D3 30 32 DX V4 35 33 DC 0.15 D4 33 30 DX D5 100 31 DX GO1 31 101 30 35 33.33E-3 D6 101 31 DY D7 100 34 DX GO2 34 101 35 30 33.33E-3 D8 101 34 DY RO1 100 35 30 GO3 35 100 100 30 33.33E-3 RO2 35 101 30 GO4 101 35 30 101 33.33E-3 LO 35 36 45E-9 * * MODELS USED * .MODEL JX NJF(VTO=-2 BETA=840.77E-6 IS=5E-10) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * AD845J SPICE Macro-model 12/90, Rev. A * AAG / PMI * * This version of the AD-845 model simulates the worst case * parameters of the 'J' grade. The worst case parameters * used correspond to those in the data sheet. * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD845J 1 2 100 101 36 * * INPUT STAGE & POLE AT 170 MHz * R1 1 3 5E10 R2 2 3 5E10 R3 100 5 656.31 R4 100 6 656.31 CIN 1 2 4E-12 C2 5 6 713.23E-15 I1 4 101 1E-3 IOS 1 2 DC 150E-12 EOS 7 1 POLY(1) 13 14 1.5E-3 1 J1 5 2 4 JX J2 6 7 4 JX * * GAIN STAGE & DOMINANT POLE AT 194 Hz * EREF 8 0 14 0 1 G1 8 9 5 6 1.5237E-3 R5 9 8 65.631E6 C3 9 8 12.5E-12 V1 100 10 DC 2.8125 D1 9 10 DX V2 11 101 DC 2.8125 D2 11 9 DX * * COMMON-MODE GAIN NETWORK WITH ZERO AT 158.49 KHz * ECM 12 8 3 14 50.119 RCM1 12 13 1E6 RCM2 13 8 1 CCM 12 13 1.0042E-12 * * VIRTUAL NODE * RVN1 100 14 17.33E3 RVN2 14 101 17.33E3 * * POLE STAGE AT 170 MHz * GP1 8 15 9 14 1E-6 RP1 15 8 1E6 CP1 15 8 0.93621E-15 * * NEGATIVE ZERO STAGE AT 46 MHz * EZ1 16 8 15 14 1E6 RZ1 16 17 1 RZ2 17 8 1E-6 CZ1 16 17 -3.4599E-9 * * POLE STAGE AT 170 MHz * GP2 8 18 17 14 1E-6 RP2 18 8 1E6 CP2 18 8 0.93621E-15 * * OUTPUT STAGE * IDC 100 101 DC 10.135E-3 VX 18 30 0 V3 32 35 DC 0.15 D3 30 32 DX V4 35 33 DC 0.15 D4 33 30 DX D5 100 31 DX GO1 31 101 30 35 33.33E-3 D6 101 31 DY D7 100 34 DX GO2 34 101 35 30 33.33E-3 D8 101 34 DY RO1 100 35 30 GO3 35 100 100 30 33.33E-3 RO2 35 101 30 GO4 101 35 30 101 33.33E-3 LO 35 36 45E-9 * * MODELS USED * .MODEL JX NJF(VTO=-2 BETA=1.1608E-3 IS=1E-9) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * AD845K SPICE Macro-model 12/90, Rev. A * AAG / PMI * * This version of the AD-845 model simulates the worst case * parameters of the 'K' grade. The worst case parameters * used correspond to those in the data sheet. * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD845K 1 2 100 101 36 * * INPUT STAGE & POLE AT 170 MHz * R1 1 3 5E10 R2 2 3 5E10 R3 100 5 771.16 R4 100 6 771.16 CIN 1 2 4E-12 C2 5 6 607.01E-15 I1 4 101 1E-3 IOS 1 2 DC 50E-12 EOS 7 1 POLY(1) 13 14 250E-6 1 J1 5 2 4 JX J2 6 7 4 JX * * GAIN STAGE & DOMINANT POLE AT 155.2 Hz * EREF 8 0 14 0 1 G1 8 9 5 6 1.2967E-3 R5 9 8 96.395E6 C3 9 8 10.638E-12 V1 100 10 DC 2.8125 D1 9 10 DX V2 11 101 DC 2.8125 D2 11 9 DX * * COMMON-MODE GAIN NETWORK WITH ZERO AT 63.096 KHz * ECM 12 8 3 14 19.953 RCM1 12 13 1E6 RCM2 13 8 1 CCM 12 13 2.522E-12 * * VIRTUAL NODE * RVN1 100 14 17.33E3 RVN2 14 101 17.33E3 * * POLE STAGE AT 170 MHz * GP1 8 15 9 14 1E-6 RP1 15 8 1E6 CP1 15 8 0.93621E-15 * * NEGATIVE ZERO STAGE AT 46 MHz * EZ1 16 8 15 14 1E6 RZ1 16 17 1 RZ2 17 8 1E-6 CZ1 16 17 -3.4599E-9 * * POLE STAGE AT 170 MHz * GP2 8 18 17 14 1E-6 RP2 18 8 1E6 CP2 18 8 0.93621E-15 * * OUTPUT STAGE * IDC 100 101 DC 10.135E-3 VX 18 30 0 V3 32 35 DC 0.15 D3 30 32 DX V4 35 33 DC 0.15 D4 33 30 DX D5 100 31 DX GO1 31 101 30 35 33.33E-3 D6 101 31 DY D7 100 34 DX GO2 34 101 35 30 33.33E-3 D8 101 34 DY RO1 100 35 30 GO3 35 100 100 30 33.33E-3 RO2 35 101 30 GO4 101 35 30 101 33.33E-3 LO 35 36 45E-9 * * MODELS USED * .MODEL JX NJF(VTO=-2 BETA=840.77E-6 IS=5E-10) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * AD845S SPICE Macro-model 12/90, Rev. A * AAG / PMI * * This version of the AD-845 model simulates the worst case * parameters of the 'S' grade. The worst case parameters * used correspond to those in the data sheet. * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD845S 1 2 100 101 36 * * INPUT STAGE & POLE AT 170 MHz * R1 1 3 5E10 R2 2 3 5E10 R3 100 5 771.16 R4 100 6 771.16 CIN 1 2 4E-12 C2 5 6 607.01E-15 I1 4 101 1E-3 IOS 1 2 DC 150E-12 EOS 7 1 POLY(1) 13 14 1E-3 1 J1 5 2 4 JX J2 6 7 4 JX * * GAIN STAGE & DOMINANT POLE AT 194 Hz * EREF 8 0 14 0 1 G1 8 9 5 6 1.2967E-3 R5 9 8 77.116E6 C3 9 8 10.638E-12 V1 100 10 DC 2.8125 D1 9 10 DX V2 11 101 DC 2.8125 D2 11 9 DX * * COMMON-MODE GAIN NETWORK WITH ZERO AT 158.49 KHz * ECM 12 8 3 14 50.119 RCM1 12 13 1E6 RCM2 13 8 1 CCM 12 13 1.0042E-12 * * VIRTUAL NODE * RVN1 100 14 17.33E3 RVN2 14 101 17.33E3 * * POLE STAGE AT 170 MHz * GP1 8 15 9 14 1E-6 RP1 15 8 1E6 CP1 15 8 0.93621E-15 * * NEGATIVE ZERO STAGE AT 46 MHz * EZ1 16 8 15 14 1E6 RZ1 16 17 1 RZ2 17 8 1E-6 CZ1 16 17 -3.4599E-9 * * POLE STAGE AT 170 MHz * GP2 8 18 17 14 1E-6 RP2 18 8 1E6 CP2 18 8 0.93621E-15 * * OUTPUT STAGE * IDC 100 101 DC 10.135E-3 VX 18 30 0 V3 32 35 DC 0.15 D3 30 32 DX V4 35 33 DC 0.15 D4 33 30 DX D5 100 31 DX GO1 31 101 30 35 33.33E-3 D6 101 31 DY D7 100 34 DX GO2 34 101 35 30 33.33E-3 D8 101 34 DY RO1 100 35 30 GO3 35 100 100 30 33.33E-3 RO2 35 101 30 GO4 101 35 30 101 33.33E-3 LO 35 36 45E-9 * * MODELS USED * .MODEL JX NJF(VTO=-2 BETA=840.77E-6 IS=1E-9) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * AD847A SPICE Macro-model 12/90, Rev. A * JCB / PMI * * This version of the AD847 model simulates the worst case * parameters of the 'A' grade. The worst case parameters * used correspond to those in the data sheet. * * Copyright 1990 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | * | | | | | .SUBCKT AD847A 1 2 99 50 30 * * INPUT STAGE & POLE AT 300 MHZ * R1 2 3 5E11 R2 1 3 5E11 R3 5 99 813 R4 6 99 813 CIN 1 2 1.5E-12 C2 5 6 326E-15 I1 4 50 908E-6 IOS 1 2 150E-9 EOS 9 1 POLY(1) 19 23 1.0E-3 1 Q1 5 2 10 QX Q2 6 9 11 QX R5 10 4 756 R6 11 4 756 * EREF 98 0 23 0 1 * * GAIN STAGE & DOMINANT POLE AT 16.2 KHZ * R7 12 98 2.44E6 C3 12 98 4.036E-12 G1 98 12 5 6 1.230E-3 V2 99 13 3.1 V3 14 50 3.1 D3 12 13 DX D4 14 12 DX * * ZERO/POLE PAIR AT 70MHz/200MHz * R8 15 16 1E6 R9 16 98 1.86E6 L1 16 98 1.48E-3 G2 98 15 12 23 1E-6 * * POLE AT 300 MHZ * R41 41 98 1E6 C41 41 98 531E-18 G41 98 41 15 23 1E-6 * * POLE AT 300 MHZ * R42 42 98 1E6 C42 42 98 531E-18 G42 98 42 41 23 1E-6 * * POLE AT 400 MHZ * R43 43 98 1E6 C43 43 98 398E-18 G43 98 43 42 23 1E-6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 224 kHZ * R11 18 19 1E6 C6 18 19 708E-15 R12 19 98 1 E2 18 98 3 23 100 * * POLE AT 400 MHZ * R15 22 98 1E6 C8 22 98 398E-18 G3 98 22 43 23 1E-6 * * OUTPUT STAGE * RF 30 60 500 CF 60 12 12.5E-12 R16 23 99 100E3 R17 23 50 100E3 ISY 99 50 5.24E-3 R18 25 99 90 R19 25 50 90 L2 25 30 3E-8 G4 28 50 22 25 11.11E-3 G5 29 50 25 22 11.11E-3 G6 25 99 99 22 11.11E-3 G7 50 25 22 50 11.11E-3 V4 26 25 0.8 V5 25 27 0.8 D5 22 26 DX D6 27 22 DX D7 99 28 DX D8 99 29 DX D9 50 28 DY D10 50 29 DY * * MODELS USED * .MODEL QX NPN(BF=90.8) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * AD847J SPICE Macro-model 12/90, Rev. A * JCB / PMI * * This version of the AD847 model simulates the worst case * parameters of the 'J' grade. The worst case parameters * used correspond to those in the data sheet. * * Copyright 1990 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | * | | | | | .SUBCKT AD847J 1 2 99 50 30 * * INPUT STAGE & POLE AT 300 MHZ * R1 2 3 5E11 R2 1 3 5E11 R3 5 99 813 R4 6 99 813 CIN 1 2 1.5E-12 C2 5 6 326E-15 I1 4 50 908E-6 IOS 1 2 150E-9 EOS 9 1 POLY(1) 19 23 1.0E-3 1 Q1 5 2 10 QX Q2 6 9 11 QX R5 10 4 756 R6 11 4 756 * EREF 98 0 23 0 1 * * GAIN STAGE & DOMINANT POLE AT 16.2 KHZ * R7 12 98 2.44E6 C3 12 98 4.036E-12 G1 98 12 5 6 1.230E-3 V2 99 13 3.1 V3 14 50 3.1 D3 12 13 DX D4 14 12 DX * * ZERO/POLE PAIR AT 70MHz/200MHz * R8 15 16 1E6 R9 16 98 1.86E6 L1 16 98 1.48E-3 G2 98 15 12 23 1E-6 * * POLE AT 300 MHZ * R41 41 98 1E6 C41 41 98 531E-18 G41 98 41 15 23 1E-6 * * POLE AT 300 MHZ * R42 42 98 1E6 C42 42 98 531E-18 G42 98 42 41 23 1E-6 * * POLE AT 400 MHZ * R43 43 98 1E6 C43 43 98 398E-18 G43 98 43 42 23 1E-6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 283 kHZ * R11 18 19 1E6 C6 18 19 562E-15 R12 19 98 1 E2 18 98 3 23 126 * * POLE AT 400 MHZ * R15 22 98 1E6 C8 22 98 398E-18 G3 98 22 43 23 1E-6 * * OUTPUT STAGE * RF 30 60 500 CF 60 12 12.5E-12 R16 23 99 100E3 R17 23 50 100E3 ISY 99 50 5.24E-3 R18 25 99 90 R19 25 50 90 L2 25 30 3E-8 G4 28 50 22 25 11.11E-3 G5 29 50 25 22 11.11E-3 G6 25 99 99 22 11.11E-3 G7 50 25 22 50 11.11E-3 V4 26 25 0.8 V5 25 27 0.8 D5 22 26 DX D6 27 22 DX D7 99 28 DX D8 99 29 DX D9 50 28 DY D10 50 29 DY * * MODELS USED * .MODEL QX NPN(BF=68.8) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * AD847S SPICE Macro-model 12/90, Rev. A * JCB / PMI * * This version of the AD847 model simulates the worst case * parameters of the 'S' grade. The worst case parameters * used correspond to those in the data sheet. * * Copyright 1990 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | * | | | | | .SUBCKT AD847S 1 2 99 50 30 * * INPUT STAGE & POLE AT 300 MHZ * R1 2 3 5E11 R2 1 3 5E11 R3 5 99 813 R4 6 99 813 CIN 1 2 1.5E-12 C2 5 6 326E-15 I1 4 50 908E-6 IOS 1 2 150E-9 EOS 9 1 POLY(1) 19 23 1.0E-3 1 Q1 5 2 10 QX Q2 6 9 11 QX R5 10 4 756 R6 11 4 756 * EREF 98 0 23 0 1 * * GAIN STAGE & DOMINANT POLE AT 16.2 KHZ * R7 12 98 2.44E6 C3 12 98 4.036E-12 G1 98 12 5 6 1.230E-3 V2 99 13 3.1 V3 14 50 3.1 D3 12 13 DX D4 14 12 DX * * ZERO/POLE PAIR AT 70MHz/200MHz * R8 15 16 1E6 R9 16 98 1.86E6 L1 16 98 1.48E-3 G2 98 15 12 23 1E-6 * * POLE AT 300 MHZ * R41 41 98 1E6 C41 41 98 531E-18 G41 98 41 15 23 1E-6 * * POLE AT 300 MHZ * R42 42 98 1E6 C42 42 98 531E-18 G42 98 42 41 23 1E-6 * * POLE AT 400 MHZ * R43 43 98 1E6 C43 43 98 398E-18 G43 98 43 42 23 1E-6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 224 kHZ * R11 18 19 1E6 C6 18 19 708E-15 R12 19 98 1 E2 18 98 3 23 100 * * POLE AT 400 MHZ * R15 22 98 1E6 C8 22 98 398E-18 G3 98 22 43 23 1E-6 * * OUTPUT STAGE * RF 30 60 500 CF 60 12 12.5E-12 R16 23 99 100E3 R17 23 50 100E3 ISY 99 50 5.24E-3 R18 25 99 90 R19 25 50 90 L2 25 30 3E-8 G4 28 50 22 25 11.11E-3 G5 29 50 25 22 11.11E-3 G6 25 99 99 22 11.11E-3 G7 50 25 22 50 11.11E-3 V4 26 25 0.8 V5 25 27 0.8 D5 22 26 DX D6 27 22 DX D7 99 28 DX D8 99 29 DX D9 50 28 DY D10 50 29 DY * * MODELS USED * .MODEL QX NPN(BF=90.8) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * AD848A SPICE Macro-model 3/94, Rev. B * JCB / PMI * Revision History: * Changed Negative Zero stage to remove the * negative capacitor value. * * This version of the AD848A model simulates the worst case * parameters of the 'A' grade. The worst case parameters * used correspond to those in the data sheet. * * Copyright 1990 by Analog Devices * * Refer to "README.DOC" file for License Statement. * Use of this model indicates your acceptance with * the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | * | | | | | .SUBCKT AD848A 1 2 99 50 30 * * INPUT STAGE & POLE AT 400 MHZ * R1 2 3 5E11 R2 1 3 5E11 R3 5 99 104.2 R4 6 99 104.2 CIN 1 2 1.5E-12 C2 5 6 1.909E-12 I1 4 50 1.72E-3 IOS 1 2 150E-9 EOS 9 1 POLY(1) 20 23 2.3E-3 1 Q1 5 2 10 QX Q2 6 9 11 QX R5 10 4 74.2 R6 11 4 74.2 * EREF 98 0 23 0 1 * * GAIN STAGE & DOMINANT POLE AT 16.7 KHZ * R7 12 98 1.25E6 C3 12 98 7.644E-12 G1 98 12 5 6 9.60E-3 V2 99 13 3.0 V3 14 50 3.0 D3 12 13 DX D4 14 12 DX * * NEGATIVE ZERO AT 160 MHZ * R8 15 16 1E6 R9 16 98 1 FX1 15 16 VX1 -1 E1 15 98 12 23 1E6 VX1 80 0 0 EX1 81 0 15 16 1 C4 80 81 0.995E-15 * * POLE AT 400 MHZ * R10 17 98 1E6 C5 17 98 398E-18 G2 98 17 16 23 1E-6 * * POLE AT 400 MHZ * R11 18 98 1E6 C6 18 98 398E-18 G3 98 18 17 23 1E-6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 447 kHZ * R12 19 20 1E6 C7 19 20 0.356E-12 R13 20 98 1 E2 19 98 3 23 25.1 * * POLE AT 400 MHZ * R14 21 98 1E6 C8 21 98 398E-18 G4 98 21 18 23 1E-6 * * OUTPUT STAGE * RF 25 22 500 CF 22 12 12.5E-12 R16 23 99 25E3 R17 23 50 25E3 ISY 99 50 0.5E-3 R18 25 99 90 R19 25 50 90 L2 25 30 4.48E-8 G5 28 50 21 25 11.11E-3 G6 29 50 25 21 11.11E-3 G7 25 99 99 21 11.11E-3 G8 50 25 21 50 11.11E-3 V4 26 25 0.8 V5 25 27 0.8 D5 21 26 DX D6 27 21 DX D7 99 28 DX D8 99 29 DX D9 50 28 DY D10 50 29 DY * * MODELS USED * .MODEL QX NPN(BF=172) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * AD848J SPICE Macro-model 3/94, Rev. B * JCB / PMI * * Revision History: * Changed Negative Zero stage to remove the * negative capacitor value. * * This version of the AD848A model simulates the worst case * parameters of the 'J' grade. The worst case parameters * used correspond to those in the data sheet. * * Copyright 1990 by Analog Devices * * Refer to "README.DOC" file for License Statement. * Use of this model indicates your acceptance with * the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | * | | | | | .SUBCKT AD848J 1 2 99 50 30 * * INPUT STAGE & POLE AT 400 MHZ * R1 2 3 5E11 R2 1 3 5E11 R3 5 99 104.2 R4 6 99 104.2 CIN 1 2 1.5E-12 C2 5 6 1.909E-12 I1 4 50 1.72E-3 IOS 1 2 150E-9 EOS 9 1 POLY(1) 20 23 2.3E-3 1 Q1 5 2 10 QX Q2 6 9 11 QX R5 10 4 74.2 R6 11 4 74.2 * EREF 98 0 23 0 1 * * GAIN STAGE & DOMINANT POLE AT 16.7 KHZ * R7 12 98 1.25E6 C3 12 98 7.644E-12 G1 98 12 5 6 9.60E-3 V2 99 13 3.0 V3 14 50 3.0 D3 12 13 DX D4 14 12 DX * * NEGATIVE ZERO AT 160 MHZ * R8 15 16 1E6 R9 16 98 1 FX1 15 16 VX1 -1 E1 15 98 12 23 1E6 VX1 80 0 0 EX1 81 0 15 16 1 C4 80 81 0.995E-15 * * POLE AT 400 MHZ * R10 17 98 1E6 C5 17 98 398E-18 G2 98 17 16 23 1E-6 * * POLE AT 400 MHZ * R11 18 98 1E6 C6 18 98 398E-18 G3 98 18 17 23 1E-6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 447 kHZ * R12 19 20 1E6 C7 19 20 0.356E-12 R13 20 98 1 E2 19 98 3 23 25.1 * * POLE AT 400 MHZ * R14 21 98 1E6 C8 21 98 398E-18 G4 98 21 18 23 1E-6 * * OUTPUT STAGE * RF 25 22 500 CF 22 12 12.5E-12 R16 23 99 25E3 R17 23 50 25E3 ISY 99 50 0.5E-3 R18 25 99 90 R19 25 50 90 L2 25 30 4.48E-8 G5 28 50 21 25 11.11E-3 G6 29 50 25 21 11.11E-3 G7 25 99 99 21 11.11E-3 G8 50 25 21 50 11.11E-3 V4 26 25 0.8 V5 25 27 0.8 D5 21 26 DX D6 27 21 DX D7 99 28 DX D8 99 29 DX D9 50 28 DY D10 50 29 DY * * MODELS USED * .MODEL QX NPN(BF=130.3) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * AD848S SPICE Macro-model 3/94, Rev. B * JCB / PMI * * Revision History: * Changed Negative Zero stage to remove the * negative capacitor value. * * This version of the AD848A model simulates the worst case * parameters of the 'S' grade. The worst case parameters * used correspond to those in the data sheet. * * Copyright 1990 by Analog Devices * * Refer to "README.DOC" file for License Statement. * Use of this model indicates your acceptance with * the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | * | | | | | .SUBCKT AD848S 1 2 99 50 30 * * INPUT STAGE & POLE AT 400 MHZ * R1 2 3 5E11 R2 1 3 5E11 R3 5 99 104.2 R4 6 99 104.2 CIN 1 2 1.5E-12 C2 5 6 1.909E-12 I1 4 50 1.72E-3 IOS 1 2 150E-9 EOS 9 1 POLY(1) 20 23 2.3E-3 1 Q1 5 2 10 QX Q2 6 9 11 QX R5 10 4 74.2 R6 11 4 74.2 * EREF 98 0 23 0 1 * * GAIN STAGE & DOMINANT POLE AT 16.7 KHZ * R7 12 98 1.25E6 C3 12 98 7.644E-12 G1 98 12 5 6 9.60E-3 V2 99 13 3.0 V3 14 50 3.0 D3 12 13 DX D4 14 12 DX * * NEGATIVE ZERO AT 160 MHZ * R8 15 16 1E6 R9 16 98 1 FX1 15 16 VX1 -1 E1 15 98 12 23 1E6 VX1 80 0 0 EX1 81 0 15 16 1 C4 80 81 0.995E-15 * * POLE AT 400 MHZ * R10 17 98 1E6 C5 17 98 398E-18 G2 98 17 16 23 1E-6 * * POLE AT 400 MHZ * R11 18 98 1E6 C6 18 98 398E-18 G3 98 18 17 23 1E-6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 447 kHZ * R12 19 20 1E6 C7 19 20 0.356E-12 R13 20 98 1 E2 19 98 3 23 25.1 * * POLE AT 400 MHZ * R14 21 98 1E6 C8 21 98 398E-18 G4 98 21 18 23 1E-6 * * OUTPUT STAGE * RF 25 22 500 CF 22 12 12.5E-12 R16 23 99 25E3 R17 23 50 25E3 ISY 99 50 0.5E-3 R18 25 99 90 R19 25 50 90 L2 25 30 4.48E-8 G5 28 50 21 25 11.11E-3 G6 29 50 25 21 11.11E-3 G7 25 99 99 21 11.11E-3 G8 50 25 21 50 11.11E-3 V4 26 25 0.8 V5 25 27 0.8 D5 21 26 DX D6 27 21 DX D7 99 28 DX D8 99 29 DX D9 50 28 DY D10 50 29 DY * * MODELS USED * .MODEL QX NPN(BF=172) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * AD8531 SPICE Macro-model 7/97, Rev. A * ARG/TAM ADSC * * Copyright 1996,1997 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance of the terms and provisions in the License * Statement. * *Changes: Removed PSPICE parameters RB and RG. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD8531 1 2 99 50 40 * * INPUT STAGE * m1 3 2 6 50 nix l=6u w=25u m2 4 7 6 50 nix l=6u w=25u m3 8 2 5 5 pix l=6u w=25u m4 9 7 5 5 pix l=6u w=25u eos 7 1 poly(1) 25 98 5e-3 0.451 iin1 1 98 5p iin2 2 98 5p ios 2 1 0.5p i1 99 5 50u i2 6 50 50u r1 99 3 4.833k r2 99 4 4.833k r3 8 50 4.833k r4 9 50 4.833k d3 5 99 dx d4 50 6 dx * * GAIN STAGE * eref 98 0 poly(2) 99 0 50 0 0 0.5 0.5 g1 98 21 poly(2) 4 3 9 8 0 145u 145u rg 21 98 18.078e6 cc 21 40 14p d1 21 22 dx d2 23 21 dx v1 99 22 1.37 v2 23 50 1.37 * * COMMON MODE GAIN STAGE * ecm 24 98 poly(2) 1 98 2 98 0 0.5 0.5 r5 24 25 1e6 r6 25 98 10k c1 24 25 0.75p * * OUTPUT STAGE * isy 99 50 450.4u gsy 99 50 poly(1) 99 50 -3.334e-4 6.667e-5 ep 99 39 poly(1) 98 21 0.78925 1 en 38 50 poly(1) 21 98 0.78925 1 m15 40 39 99 99 pox l=1.5u w=1500u m16 40 38 50 50 nox l=1.5u w=1500u c15 40 39 50p c16 40 38 50p .model dx d(rs=1 cjo=0.1p) * rg=1 rb=1 .model nix nmos(vto=0.75 kp=205.5u rd=1 rs=1 cgso=4e-9 +cgdo=4e-9 cgbo=16.667e-9 cbs=2.34e-13 cbd=2.34e-13) * rg=1 rb=1 .model nox nmos(vto=0.75 kp=195u rd=.5 rs=.5 cgso=66.667e-12 +cgdo=66.667e-12 cgbo=125e-9 cbs=2.34e-13 cbd=2.34e-13) * rg=1 rb=1 .model pix pmos(vto=-0.75 kp=205.5u rd=1 rs=1 cgso=4e-9 +cgdo=4e-9 cgbo=16.667e-9 cbs=2.34e-13 cbd=2.34e-13) * rg=1 rb=1 .model pox pmos(vto=-0.75 kp=195u rd=.5 rs=.5 cgso=66.667e-12 +cgdo=66.667e-12 cgbo=125e-9 cbs=2.34e-13 cbd=2.34e-13) .ends AD8531* AD8532 SPICE Macro-model 3/96, Rev. A * 5-Volt Version ARG / ADSC * * Copyright 1996 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance of the terms and provisions in the License * Statement. * *Changes: Removed PSPICE parameters RB and RG. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD8532 1 2 99 50 40 * * INPUT STAGE * m1 3 2 6 50 nix l=6u w=25u m2 4 7 6 50 nix l=6u w=25u m3 8 2 5 5 pix l=6u w=25u m4 9 7 5 5 pix l=6u w=25u eos 7 1 poly(1) 25 98 5e-3 0.451 iin1 1 98 5p iin2 2 98 5p ios 2 1 0.5p i1 99 5 50u i2 6 50 50u r1 99 3 4.833k r2 99 4 4.833k r3 8 50 4.833k r4 9 50 4.833k d3 5 99 dx d4 50 6 dx * * GAIN STAGE * eref 98 0 poly(2) 99 0 50 0 0 0.5 0.5 g1 98 21 poly(2) 4 3 9 8 0 145u 145u rg 21 98 18.078e6 cc 21 40 14p d1 21 22 dx d2 23 21 dx v1 99 22 1.37 v2 23 50 1.37 * * COMMON MODE GAIN STAGE * ecm 24 98 poly(2) 1 98 2 98 0 0.5 0.5 r5 24 25 1e6 r6 25 98 10k c1 24 25 0.75p * * OUTPUT STAGE * isy 99 50 450.4u gsy 99 50 poly(1) 99 50 -3.334e-4 6.667e-5 ep 99 39 poly(1) 98 21 0.78925 1 en 38 50 poly(1) 21 98 0.78925 1 m15 40 39 99 99 pox l=1.5u w=1500u m16 40 38 50 50 nox l=1.5u w=1500u c15 40 39 50p c16 40 38 50p .model dx d(rs=1 cjo=0.1p) * rg=1 rb=1 .model nix nmos(vto=0.75 kp=205.5u rd=1 rs=1 cgso=4e-9 +cgdo=4e-9 cgbo=16.667e-9 cbs=2.34e-13 cbd=2.34e-13) * rg=1 rb=1 .model nox nmos(vto=0.75 kp=195u rd=.5 rs=.5 cgso=66.667e-12 +cgdo=66.667e-12 cgbo=125e-9 cbs=2.34e-13 cbd=2.34e-13) * rg=1 rb=1 .model pix pmos(vto=-0.75 kp=205.5u rd=1 rs=1 cgso=4e-9 +cgdo=4e-9 cgbo=16.667e-9 cbs=2.34e-13 cbd=2.34e-13) * rg=1 rb=1 .model pox pmos(vto=-0.75 kp=195u rd=.5 rs=.5 cgso=66.667e-12 +cgdo=66.667e-12 cgbo=125e-9 cbs=2.34e-13 cbd=2.34e-13) .ends* AD8534 SPICE Macro-model 7/97, Rev. A * ARG/TAM ADSC * * Copyright 1996,1997 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance of the terms and provisions in the License * Statement. * *Changes: Removed PSPICE parameters RB and RG. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD8534 1 2 99 50 40 * * INPUT STAGE * m1 3 2 6 50 nix l=6u w=25u m2 4 7 6 50 nix l=6u w=25u m3 8 2 5 5 pix l=6u w=25u m4 9 7 5 5 pix l=6u w=25u eos 7 1 poly(1) 25 98 5e-3 0.451 iin1 1 98 5p iin2 2 98 5p ios 2 1 0.5p i1 99 5 50u i2 6 50 50u r1 99 3 4.833k r2 99 4 4.833k r3 8 50 4.833k r4 9 50 4.833k d3 5 99 dx d4 50 6 dx * * GAIN STAGE * eref 98 0 poly(2) 99 0 50 0 0 0.5 0.5 g1 98 21 poly(2) 4 3 9 8 0 145u 145u rg 21 98 18.078e6 cc 21 40 14p d1 21 22 dx d2 23 21 dx v1 99 22 1.37 v2 23 50 1.37 * * COMMON MODE GAIN STAGE * ecm 24 98 poly(2) 1 98 2 98 0 0.5 0.5 r5 24 25 1e6 r6 25 98 10k c1 24 25 0.75p * * OUTPUT STAGE * isy 99 50 450.4u gsy 99 50 poly(1) 99 50 -3.334e-4 6.667e-5 ep 99 39 poly(1) 98 21 0.78925 1 en 38 50 poly(1) 21 98 0.78925 1 m15 40 39 99 99 pox l=1.5u w=1500u m16 40 38 50 50 nox l=1.5u w=1500u c15 40 39 50p c16 40 38 50p .model dx d(rs=1 cjo=0.1p) * rg=1 rb=1 .model nix nmos(vto=0.75 kp=205.5u rd=1 rs=1 cgso=4e-9 +cgdo=4e-9 cgbo=16.667e-9 cbs=2.34e-13 cbd=2.34e-13) * rg=1 rb=1 .model nox nmos(vto=0.75 kp=195u rd=.5 rs=.5 cgso=66.667e-12 +cgdo=66.667e-12 cgbo=125e-9 cbs=2.34e-13 cbd=2.34e-13) * rg=1 rb=1 .model pix pmos(vto=-0.75 kp=205.5u rd=1 rs=1 cgso=4e-9 +cgdo=4e-9 cgbo=16.667e-9 cbs=2.34e-13 cbd=2.34e-13) * rg=1 rb=1 .model pox pmos(vto=-0.75 kp=195u rd=.5 rs=.5 cgso=66.667e-12 +cgdo=66.667e-12 cgbo=125e-9 cbs=2.34e-13 cbd=2.34e-13) .ends AD8534* AD9617 SPICE Macro-model 12/90, Rev. A * CLD * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD9617 1 2 100 110 15 * 1=VIN +, 2=VIN -, 100=VCC, 110=VEE, 15=VOUT C1 13 5 1.15E-12 C2 17 6 1.15E-12 C3 12 2 0.5E-12 C4 5 6 3.5E-12 C5 5 0 1.0E-12 C6 6 0 1.0E-12 C7 12 0 1.5E-12 CINN 1 0 1.5E-12 CINI 2 0 1.5E-12 F1 100 13 VM1 1.5 F2 17 110 VM2 1.5 GM1 12 9 POLY(2) 0 5 0 6 2.5M,-2.0M,-2.0M GM2 10 12 POLY(2) 0 6 0 5 2.5M,2.0M,2.0M I1 100 3 DC 1.98M I2 100 5 DC 3.93M I3 4 110 DC 2.0M I4 6 110 DC 4.0M I5 100 12 5.0M I6 12 110 5.0M Q1 3 3 1 110 QNA 1.05 Q2 5 3 2 110 QNA 1.05 Q3 4 4 1 100 QPA 1.05 Q4 6 4 2 100 QPA 1.05 Q5 110 12 13 100 QPA 1.25 Q6A 100 13 14 110 QNB 1.05 Q6B 100 13 14 110 QNB 1.05 Q7 100 12 17 110 QNA 1.11 Q8A 110 17 16 100 QPB Q8B 110 17 16 100 QPB R1 12 15 500 R2 14 15 5 R3 15 16 5 R4 100 5 190K R5 5 0 25K R6 6 110 395K R7 6 0 12K R8 7 20 350 VB1 5 7 DC 1.6 VB2 20 6 DC 1.6 VM1 100 10 DC 0 VM2 9 110 DC 0 * .MODEL QNA NPN RB=75, IRB=0, RBM=7, RC=20, RE=0.7, IS=540E-18, +XTB=2.4, BF=380, IKF=15M, VAF=30, ISE=22E-16, +ISC=35E-21, TF=25E-12, CJE=16E-14, CJC=2.2E-13, XCJC=.2 +CJS=4E-13, MJS=0.3, VJE=1 * .MODEL QNB NPN RB=24, IRB=0, RBM=2, RC=6, RE=0.5, IS=18E-16, +XTB=2, BF=380, IKF=49M, VAF=30, ISE=72E-16, +ISC=115E-21, TF=25E-12, CJE=54E-14, CJC=6E-13, XCJC=.2 +CJS=7E-13, MJS=0.3, VJE=1 * .MODEL QPA PNP RB=83, IRB=0M, RBM=14, RC=18, RE=0.5, IS=26E-17, +XTB=2, BF=190, IKF=24M, VAF=15, ISE=7E-15, +ISC=30E-19, TF=35E-12, CJE=11E-14, CJC=3.1E-13, XCJC=.2 +CJS=9E-13, MJS=0.35, VJE=1 * .MODEL QPB PNP RB=25, IRB=0, RBM=4, RC=5, RE=0.2, IS=88E-17, +XTB=2, BF=190, IKF=84E-3, VAF=15, ISE=22.3E-15, +ISC=100E-19, TF=35E-12, CJE=36E-14, CJC=8.5E-13, XCJC=.2 +CJS=1.4E-12, MJS=0.35, VJE=1 * .ENDS AD9617 * * **** MACRO17 TEST CIRCUIT ********************** * *VCC 5 0 DC 5 AC 0 *VEE 6 0 DC -5 AC 0 *V3 2 7 DC 0 *RFB 4 2 400 *RFF 1 2 200 *RL 4 0 100 * *X1 3 7 5 6 4 AD9617 * 3=VIN +, 7=VIN -, 5=VCC, 6=VEE, 4=VOUT * *V1 1 0 DC 0 AC 0 *V2 3 0 DC 0 AC 1 *.AC DEC 101 10K 1G *.PLOT AC VDB(4) IDB(V3) VP(4) IP(V3) I(V3) * *V2 3 0 PULSE(-.333 .333 5.000n 400.000E-12 400.000E-12 30.000n 65.000n ) *.TRAN 200E-12 65N *.PLOT TRAN V(4) V(2) * *V2 3 0 DC 0 AC 1 0 SIN(0 .333 20MEG 0 0) *.TRAN .2N 65N *.FOUR 20MEG V(4) *.PLOT TRAN V(4) * *.END * AD9618 SPICE Macro-model 12/90, Rev. A * CLD * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD9618 1 2 100 110 15 * 1=VIN +, 2=VIN -, 100=VCC, 110=VEE, 15=VOUT C1 12 5 .45E-12 C2 12 6 .45E-12 C3 12 2 0.2E-12 C5 5 0 1.25E-12 C6 6 0 1.25E-12 C7 12 0 1.25E-12 CINN 1 0 1.5E-12 CINI 2 0 1.5E-12 F1 100 13 VM1 1.2 F2 17 110 VM2 1.2 GM1 12 9 POLY(3) 0 5 0 6 5 6 1.6M,-4.0M,-4.0M GM2 10 12 POLY(3) 0 6 0 5 6 5 1.6M,4.0M,4.0M I1 100 3 DC 2.00M I2 100 5 DC 3.00M I3 4 110 DC 2.00M I4 6 110 DC 3.29M I5 100 12 5.0M I6 12 110 5.0M Q1 3 3 1 110 QNA 1.05 Q2 5 3 2 110 QNA 1.05 Q3 4 4 1 100 QPA 1.05 Q4 6 4 2 100 QPA 1.05 Q5 110 12 13 100 QPA .75 Q6A 100 13 14 110 QNB 1.05 Q6B 100 13 14 110 QNB 1.05 Q7 100 12 17 110 QNA .75 Q8A 110 17 16 100 QPB Q8B 110 17 16 100 QPB R1 12 0 20000 R2 14 15 6 R3 15 16 6 R4 100 5 120K R5 5 0 14K R6 6 110 450K R7 6 0 4.5K R8 7 20 280 VB1 5 7 DC 1.70 VB2 20 6 DC 1.70 VM1 100 10 DC 0 VM2 9 110 DC 0 * .MODEL QNA NPN RB=75, IRB=0, RBM=7, RC=20, RE=0.7, IS=540E-18, +XTB=2.4, BF=380, IKF=15M, VAF=30, ISE=22E-16, +ISC=35E-21, TF=25E-12, CJE=16E-14, CJC=2.2E-13, XCJC=.2 +CJS=4E-13, MJS=0.3, VJE=1 * .MODEL QNB NPN RB=24, IRB=0, RBM=2, RC=6, RE=0.5, IS=18E-16, +XTB=2, BF=380, IKF=49M, VAF=30, ISE=72E-16, +ISC=115E-21, TF=25E-12, CJE=54E-14, CJC=6E-13, XCJC=.2 +CJS=7E-13, MJS=0.3, VJE=1 * .MODEL QPA PNP RB=83, IRB=0M, RBM=14, RC=18, RE=0.5, IS=26E-17, +XTB=2, BF=190, IKF=24M, VAF=15, ISE=7E-15, +ISC=30E-19, TF=35E-12, CJE=11E-14, CJC=3.1E-13, XCJC=.2 +CJS=9E-13, MJS=0.35, VJE=1 * .MODEL QPB PNP RB=25, IRB=0, RBM=4, RC=5, RE=0.2, IS=88E-17, +XTB=2, BF=190, IKF=84E-3, VAF=15, ISE=22.3E-15, +ISC=100E-19, TF=35E-12, CJE=36E-14, CJC=8.5E-13, XCJC=.2 +CJS=1.4E-12, MJS=0.35, VJE=1 * .ENDS AD9618 * * **** MACRO18 TEST CIRCUIT ********************** * *VCC 5 0 DC 5 AC 0 *VEE 6 0 DC -5 AC 0 *V3 2 7 DC 0 *RFB 4 2 1000 *RFF 1 2 110 *RL 4 0 100 * *X1 3 7 5 6 4 AD9618 * 3=VIN +, 7=VIN -, 5=VCC, 6=VEE, 4=VOUT * *V1 1 0 DC 0 AC 0 *V2 3 0 DC 0 AC 1 *.AC DEC 101 10K 1G *.PLOT AC VDB(4) IDB(V3) VP(4) IP(V3) I(V3) * *V2 3 0 DC 0 AC 1 PULSE -.1 .1 5N .4N .4N 30N 65N *.TRAN .05N 65N *.PLOT TRAN V(4) V(2) * *V2 3 0 DC 0 AC 1 0 SIN(0 0.1 20MEG 0 0) *.TRAN .2N 65N *.FOUR 20MEG V(4) *.PLOT TRAN V(4) *.END * AD9621 SPICE MACRO MODEL 3/94, REV. B * CLD * * Revision History: * Changed parameter VJ=-1 to VJ=0.01 in diode model. * * Copyright 1992 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. * Use of this model indicates your acceptance with * the terms and provisions in the License Statement. * * NODE ASSIGNMENTS * POSITIVE INPUT * | NEGATIVE INPUT * | | POSITIVE SUPPLY * | | | * | | | NEGATIVE SUPPLY * | | | | OUTPUT * | | | | | .SUBCKT AD9621 VINP VINN 100 110 VOUT * C1 5 VOUT 1.5E-12 C2 VOUT 6 1.5E-12 CINT 13 0 7.5E-12 F1 100 5 V1 1 F2 6 110 V2 1 G1 100 9 POLY(1) (5,0) 0.392 -0.13 G2 10 110 POLY(1) (6,0) 0.392 0.13 GM1 5 7 POLY(1) (1,3) 0.006 0.002 GM2 8 6 POLY(1) (2,4) 0.006 -0.002 D1 9 100 D D2 110 10 D V1 100 8 0 V2 7 110 0 V3 6A 0 DC -2.4 D3 6A 6 D1 V4 5A 0 DC 2.4 D4 5 5A D1 V5 5B 0 DC 3.6 D5 5B 5 D1 V6 6B 0 DC -3.6 D6 6 6B D1 I1 100 1 .7E-3 I2 2 110 1.1E-3 I3 100 3 .7E-3 I4 4 110 1.1E-3 Q1 110 VINP 1 100 PA Q2 100 VINP 2 110 NA Q3 100 VINN 4 110 NA Q4 110 VINN 3 100 PA Q5 9 9 13 110 NB 1.2 Q6 10 10 13 100 PB Q7 100 9 11 110 NB 2.4 Q8 110 10 12 100 PB 2 R1 100 5 300 R2 6 110 300 R3 5 0 450 R4 6 0 450 R5 11 VOUT 7 R6 VOUT 12 7 * .MODEL NA NPN + IS = 1.6E-16 BF = 305 VAF = 74 + IKF = 2.2E-02 ISE = 2E-17 NE = 1.2 BR = 36 + VAR = 1.7 IKR = 3.0E-02 ISC = 1.5E-19 + NC = 1.7 RB = 90 IRB = 0 RBM = 20 + RE = 0.9 RC = 52 CJE = 1.2E-13 VJE =0.8 + MJE = 0.5 TF = 2.8E-11 XTF = 5.0 VTF = 2.7 + ITF = 2.6E-02 PTF = 0.0 CJC = 1.7E-13 VJC = 0.6 + MJC = 0.34 XCJC = 0.138 TR = 7.1E-11 CJS = 3.9E-13 + VJS = 0.5 MJS = 0.32 XTB = 1.1 EG = 1.18 + XTI = 2.0 FC = 0.82 .MODEL NB NPN + IS = 6.4E-16 BF = 305 VAF = 74 + IKF = 8.7E-02 ISE = 8E-17 NE = 1.2 BR = 40 + VAR = 1.7 IKR = 0.12 ISC = 4.6E-19 + NC = 1.7 RB = 23 IRB = 0 RBM = 5.0 + RE = 0.227 RC = 9.5 CJE = 4.8E-13 VJE = 0.8 + MJE = 0.5 TF = 2.7E-11 XTF = 5.1 VTF = 2.7 + ITF = 0.11 PTF = 0.0 CJC = 5.0E-13 VJC = 0.60 + MJC = 0.34 XCJC = 0.19 TR = 7.1E-11 CJS = 6.9E-13 + VJS = 0.5 MJS = 0.32 XTB = 1.1 EG = 1.18 + XTI = 2.0 FC = 0.82 .MODEL PA PNP + IS = 6.3E-17 BF = 69 VAF = 25 + IKF = 9.1E-03 ISE = 3.2E-16 NE = 1.4 BR = 16 + VAR = 1.8 IKR = 6.7E-02 ISC = 1.9E-18 + NC = 1.6 RB = 57 IRB = 0 RBM = 15 + RE = 1.3 RC = 51 CJE = 8.0E-14 VJE = 0.82 + MJE = 0.49 TF = 2.6E-11 XTF = 9.0 VTF = 2.7 + ITF = 2.7E-02 PTF = 0.0 CJC = 2.4E-13 VJC = 0.53 + MJC = 0.19 XCJC = 0.13 TR = 6.5E-11 CJS = 6.9E-13 + VJS = 0.60 MJS = 0.35 XTB = 2.5 EG = 1.18 + XTI = 2.0 FC = 0.90 .MODEL PB PNP + IS = 3.8E-16 BF = 69 VAF = 25 + IKF = 5.5E-02 ISE = 1.9E-15 NE = 1.4 BR = 19 + VAR = 1.8 IKR = 0.4 ISC = 1.1E-17 + NC = 1.6 RB = 9.5 IRB = 0 RBM = 2.5 + RE = 0.21 RC = 15 CJE = 4.8E-13 VJE = 0.82 + MJE = 0.49E-01 TF = 2.4E-11 XTF = 9.0 VTF = 2.7 + ITF = 0.16 PTF = 0.0 CJC = 9.5E-13 VJC = 0.53 + MJC = 0.19 XCJC = 0.19 TR = 6.5E-11 CJS = 1.5E-12 + VJS = 0.6 MJS = 0.35 XTB = 2.5 EG = 1.18 + XTI = 2.0 FC = 0.9 .MODEL D D (CJO=30E-12 VJ=0.01 M=2 ) .MODEL D1 D (IS=1E-14 ) .ENDS * * TEST CIRCUIT * *VIN VINPA 0 DC 0 AC 1 PULSE(-2.5 2.5 5.000n 1.000n 1.000n 30.000n 65.000n ) *VIN VINPA 0 DC 0 AC 1 SIN (0 1 20MEG 0 0 0) *VCC 100 0 DC 5 AC 0 *VEE 110 0 DC -5 AC 0 *RT VINPA VINP 25 *RL VOUT 0 100 *RF VOUT VINN 51 * *X1 VINP VINN 100 110 VOUT AD9621 * *.END * AD9622 SPICE MACRO MODEL 3/94, REV. B * CLD * * Revision History: * Changed parameter VJ=-1 to VJ=0.01 in diode model. * * Copyright 1992 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * * NODE ASSIGNMENTS * POSITIVE INPUT * | NEGATIVE INPUT * | | POSITIVE SUPPLY * | | | * | | | NEGATIVE SUPPLY * | | | | OUTPUT * | | | | | .SUBCKT AD9622 VINP VINN 100 110 VOUT * C1 5 VOUT 3.5E-12 C2 VOUT 6 3.5E-12 CINT 13 0 7.5E-12 F1 100 5 V1 1 F2 6 110 V2 1 G1 100 9 POLY(1) (5,0) 0.392 -0.13 G2 10 110 POLY(1) (6,0) 0.392 0.13 GM1 5 7 POLY(1) (1,3) 0.005 0.006 GM2 8 6 POLY(1) (2,4) 0.005 -0.006 V1 100 8 0 V2 7 110 0 V3 6A 0 DC -2.4 D3 6A 6 D1 V4 5A 0 DC 2.4 D4 5 5A D1 V5 5B 0 DC 3.6 D5 5B 5 D1 V6 6B 0 DC -3.6 D6 6 6B D1 I1 100 1 .7E-3 I2 2 110 1.1E-3 I3 100 3 .7E-3 I4 4 110 1.1E-3 Q1 110 VINP 1 100 PA Q2 100 VINP 2 110 NA Q3 100 VINN 4 110 NA Q4 110 VINN 3 100 PA Q5 9 9 13 110 NB 1.2 Q6 10 10 13 100 PB Q7 100 9 11 110 NB 2.4 Q8 110 10 12 100 PB 2 R1 100 5 300 R2 6 110 300 R3 5 0 450 R4 6 0 450 R5 11 VOUT 7 R6 VOUT 12 7 * .MODEL NA NPN + IS = 1.6E-16 BF = 305 VAF = 74 + IKF = 2.2E-02 ISE = 2E-17 NE = 1.2 BR = 36 + VAR = 1.7 IKR = 3.0E-02 ISC = 1.5E-19 + NC = 1.7 RB = 90 IRB = 0 RBM = 20 + RE = 0.9 RC = 52 CJE = 1.2E-13 VJE =0.8 + MJE = 0.5 TF = 2.8E-11 XTF = 5.0 VTF = 2.7 + ITF = 2.6E-02 PTF = 0.0 CJC = 1.7E-13 VJC = 0.6 + MJC = 0.34 XCJC = 0.138 TR = 7.1E-11 CJS = 3.9E-13 + VJS = 0.5 MJS = 0.32 XTB = 1.1 EG = 1.18 + XTI = 2.0 FC = 0.82 .MODEL NB NPN + IS = 6.4E-16 BF = 305 VAF = 74 + IKF = 8.7E-02 ISE = 8E-17 NE = 1.2 BR = 40 + VAR = 1.7 IKR = 0.12 ISC = 4.6E-19 + NC = 1.7 RB = 23 IRB = 0 RBM = 5.0 + RE = 0.227 RC = 9.5 CJE = 4.8E-13 VJE = 0.8 + MJE = 0.5 TF = 2.7E-11 XTF = 5.1 VTF = 2.7 + ITF = 0.11 PTF = 0.0 CJC = 5.0E-13 VJC = 0.60 + MJC = 0.34 XCJC = 0.19 TR = 7.1E-11 CJS = 6.9E-13 + VJS = 0.5 MJS = 0.32 XTB = 1.1 EG = 1.18 + XTI = 2.0 FC = 0.82 .MODEL PA PNP + IS = 6.3E-17 BF = 69 VAF = 25 + IKF = 9.1E-03 ISE = 3.2E-16 NE = 1.4 BR = 16 + VAR = 1.8 IKR = 6.7E-02 ISC = 1.9E-18 + NC = 1.6 RB = 57 IRB = 0 RBM = 15 + RE = 1.3 RC = 51 CJE = 8.0E-14 VJE = 0.82 + MJE = 0.49 TF = 2.6E-11 XTF = 9.0 VTF = 2.7 + ITF = 2.7E-02 PTF = 0.0 CJC = 2.4E-13 VJC = 0.53 + MJC = 0.19 XCJC = 0.13 TR = 6.5E-11 CJS = 6.9E-13 + VJS = 0.60 MJS = 0.35 XTB = 2.5 EG = 1.18 + XTI = 2.0 FC = 0.90 .MODEL PB PNP + IS = 3.8E-16 BF = 69 VAF = 25 + IKF = 5.5E-02 ISE = 1.9E-15 NE = 1.4 BR = 19 + VAR = 1.8 IKR = 0.4 ISC = 1.1E-17 + NC = 1.6 RB = 9.5 IRB = 0 RBM = 2.5 + RE = 0.21 RC = 15 CJE = 4.8E-13 VJE = 0.82 + MJE = 0.49E-01 TF = 2.4E-11 XTF = 9.0 VTF = 2.7 + ITF = 0.16 PTF = 0.0 CJC = 9.5E-13 VJC = 0.53 + MJC = 0.19 XCJC = 0.19 TR = 6.5E-11 CJS = 1.5E-12 + VJS = 0.6 MJS = 0.35 XTB = 2.5 EG = 1.18 + XTI = 2.0 FC = 0.9 .MODEL D D (CJO=30E-12 VJ=0.01 M=2 ) .MODEL D1 D (IS=1E-14 ) .ENDS * * TEST CIRCUIT * *VIN VINPA 0 DC 0 AC 1 PULSE(-1.25 1.25 5.000n 2.000n 2.000n 30.000n 65.000n ) *VIN VINPA 0 DC 0 AC 1 SIN (0 .5 20MEG 0 0 0) *VCC 100 0 DC 5 AC 0 *VEE 110 0 DC -5 AC 0 *RT VINPA VINP 25 *RL VOUT 0 100 *RF VOUT VINN 270 *RN VINN 0 270 * *X1 VINP VINN 100 110 VOUT AD9622 *.END * AD9623 SPICE MACRO MODEL 3/94, REV. B * CLD * * Revision History: * Changed parameter VJ=-1 to VJ=0.01 in diode model. * * Copyright 1992 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * * NODE ASSIGNMENTS * POSITIVE INPUT * | NEGATIVE INPUT * | | POSITIVE SUPPLY * | | | * | | | NEGATIVE SUPPLY * | | | | OUTPUT * | | | | | .SUBCKT AD9623 VINP VINN 100 110 VOUT * C1 5 VOUT 4.75E-12 C2 VOUT 6 4.75E-12 CINT 13 0 4.5E-12 F1 100 5 V1 1 F2 6 110 V2 1 G1 100 9 POLY(1) (5,0) 0.392 -0.13 G2 10 110 POLY(1) (6,0) 0.392 0.13 GM1 5 7 POLY(1) (1,3) 0.005 0.015 GM2 8 6 POLY(1) (2,4) 0.005 -0.015 V1 100 8 0 V2 7 110 0 V3 6A 0 DC -2.4 D3 6A 6 D1 V4 5A 0 DC 2.4 D4 5 5A D1 V5 5B 0 DC 3.6 D5 5B 5 D1 V6 6B 0 DC -3.6 D6 6 6B D1 I1 100 1 .7E-3 I2 2 110 1.1E-3 I3 100 3 .7E-3 I4 4 110 1.1E-3 Q1 110 VINP 1 100 PA Q2 100 VINP 2 110 NA Q3 100 VINN 4 110 NA Q4 110 VINN 3 100 PA Q5 9 9 13 110 NB 1.2 Q6 10 10 13 100 PB Q7 100 9 11 110 NB 2.4 Q8 110 10 12 100 PB 2 R1 100 5 300 R2 6 110 300 R3 5 0 450 R4 6 0 450 R5 11 VOUT 7 R6 VOUT 12 7 * .MODEL NA NPN + IS = 1.6E-16 BF = 305 VAF = 74 + IKF = 2.2E-02 ISE = 2E-17 NE = 1.2 BR = 36 + VAR = 1.7 IKR = 3.0E-02 ISC = 1.5E-19 + NC = 1.7 RB = 90 IRB = 0 RBM = 20 + RE = 0.9 RC = 52 CJE = 1.2E-13 VJE =0.8 + MJE = 0.5 TF = 2.8E-11 XTF = 5.0 VTF = 2.7 + ITF = 2.6E-02 PTF = 0.0 CJC = 1.7E-13 VJC = 0.6 + MJC = 0.34 XCJC = 0.138 TR = 7.1E-11 CJS = 3.9E-13 + VJS = 0.5 MJS = 0.32 XTB = 1.1 EG = 1.18 + XTI = 2.0 FC = 0.82 .MODEL NB NPN + IS = 6.4E-16 BF = 305 VAF = 74 + IKF = 8.7E-02 ISE = 8E-17 NE = 1.2 BR = 40 + VAR = 1.7 IKR = 0.12 ISC = 4.6E-19 + NC = 1.7 RB = 23 IRB = 0 RBM = 5.0 + RE = 0.227 RC = 9.5 CJE = 4.8E-13 VJE = 0.8 + MJE = 0.5 TF = 2.7E-11 XTF = 5.1 VTF = 2.7 + ITF = 0.11 PTF = 0.0 CJC = 5.0E-13 VJC = 0.60 + MJC = 0.34 XCJC = 0.19 TR = 7.1E-11 CJS = 6.9E-13 + VJS = 0.5 MJS = 0.32 XTB = 1.1 EG = 1.18 + XTI = 2.0 FC = 0.82 .MODEL PA PNP + IS = 6.3E-17 BF = 69 VAF = 25 + IKF = 9.1E-03 ISE = 3.2E-16 NE = 1.4 BR = 16 + VAR = 1.8 IKR = 6.7E-02 ISC = 1.9E-18 + NC = 1.6 RB = 57 IRB = 0 RBM = 15 + RE = 1.3 RC = 51 CJE = 8.0E-14 VJE = 0.82 + MJE = 0.49 TF = 2.6E-11 XTF = 9.0 VTF = 2.7 + ITF = 2.7E-02 PTF = 0.0 CJC = 2.4E-13 VJC = 0.53 + MJC = 0.19 XCJC = 0.13 TR = 6.5E-11 CJS = 6.9E-13 + VJS = 0.60 MJS = 0.35 XTB = 2.5 EG = 1.18 + XTI = 2.0 FC = 0.90 .MODEL PB PNP + IS = 3.8E-16 BF = 69 VAF = 25 + IKF = 5.5E-02 ISE = 1.9E-15 NE = 1.4 BR = 19 + VAR = 1.8 IKR = 0.4 ISC = 1.1E-17 + NC = 1.6 RB = 9.5 IRB = 0 RBM = 2.5 + RE = 0.21 RC = 15 CJE = 4.8E-13 VJE = 0.82 + MJE = 0.49E-01 TF = 2.4E-11 XTF = 9.0 VTF = 2.7 + ITF = 0.16 PTF = 0.0 CJC = 9.5E-13 VJC = 0.53 + MJC = 0.19 XCJC = 0.19 TR = 6.5E-11 CJS = 1.5E-12 + VJS = 0.6 MJS = 0.35 XTB = 2.5 EG = 1.18 + XTI = 2.0 FC = 0.9 .MODEL D D (CJO=30E-12 VJ=0.01 M=2 ) .MODEL D1 D (IS=1E-14 ) .ENDS * * TEST CIRCUIT * *VIN VINPA 0 DC 0 AC 1 PULSE(-.625 .625 5.000n 2.000n 2.000n 30.000n 65.000n ) *VIN VINPA 0 DC 0 AC 1 SIN (0 .25 20MEG 0 0 0) *VCC 100 0 DC 5 AC 0 *VEE 110 0 DC -5 AC 0 *RT VINPA VINP 25 *RL VOUT 0 100 *RF VOUT VINN 390 *RN VINN 0 130 * *X1 VINP VINN 100 110 VOUT AD9623 * *.END * AD9624 SPICE MACRO MODEL 3/94, REV. B * CLD * * Revision History: * Changed parameter VJ=-1 to VJ=0.01 in diode model. * * Copyright 1992 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * * NODE ASSIGNMENTS * POSITIVE INPUT * | NEGATIVE INPUT * | | POSITIVE SUPPLY * | | | * | | | NEGATIVE SUPPLY * | | | | OUTPUT * | | | | | .SUBCKT AD9624 VINP VINN 100 110 VOUT * C1 5 VOUT 4E-12 C2 VOUT 6 4E-12 F1 100 5 V1 1 F2 6 110 V2 1 G1 100 9 POLY(1) (5,0) 0.392 -0.13 G2 10 110 POLY(1) (6,0) 0.392 0.13 GM1 5 7 POLY(1) (1,3) 0.005 0.025 GM2 8 6 POLY(1) (2,4) 0.005 -0.025 D1 9 100 D D2 110 10 D V1 100 8 0 V2 7 110 0 V3 6A 0 DC -2.4 D3 6A 6 D1 V4 5A 0 DC 2.4 D4 5 5A D1 V5 5B 0 DC 3.5 D5 5B 5 D1 V6 6B 0 DC -3.5 D6 6 6B D1 I1 100 1 .7E-3 I2 2 110 1.1E-3 I3 100 3 .7E-3 I4 4 110 1.1E-3 Q1 110 VINP 1 100 PA Q2 100 VINP 2 110 NA Q3 100 VINN 4 110 NA Q4 110 VINN 3 100 PA Q5 9 9 13 110 NB 1.2 Q6 10 10 13 100 PB Q7 100 9 11 110 NB 2.4 Q8 110 10 12 100 PB 2 R1 100 5 300 R2 6 110 300 R3 5 0 450 R4 6 0 450 R5 11 VOUT 7 R6 VOUT 12 7 *** .MODEL NA NPN + IS = 1.6E-16 BF = 305 VAF = 74 + IKF = 2.2E-02 ISE = 2E-17 NE = 1.2 BR = 36 + VAR = 1.7 IKR = 3.0E-02 ISC = 1.5E-19 + NC = 1.7 RB = 90 IRB = 0 RBM = 20 + RE = 0.9 RC = 52 CJE = 1.2E-13 VJE =0.8 + MJE = 0.5 TF = 2.8E-11 XTF = 5.0 VTF = 2.7 + ITF = 2.6E-02 PTF = 0.0 CJC = 1.7E-13 VJC = 0.6 + MJC = 0.34 XCJC = 0.138 TR = 7.1E-11 CJS = 3.9E-13 + VJS = 0.5 MJS = 0.32 XTB = 1.1 EG = 1.18 + XTI = 2.0 FC = 0.82 .MODEL NB NPN + IS = 6.4E-16 BF = 305 VAF = 74 + IKF = 8.7E-02 ISE = 8E-17 NE = 1.2 BR = 40 + VAR = 1.7 IKR = 0.12 ISC = 4.6E-19 + NC = 1.7 RB = 23 IRB = 0 RBM = 5.0 + RE = 0.227 RC = 9.5 CJE = 4.8E-13 VJE = 0.8 + MJE = 0.5 TF = 2.7E-11 XTF = 5.1 VTF = 2.7 + ITF = 0.11 PTF = 0.0 CJC = 5.0E-13 VJC = 0.60 + MJC = 0.34 XCJC = 0.19 TR = 7.1E-11 CJS = 6.9E-13 + VJS = 0.5 MJS = 0.32 XTB = 1.1 EG = 1.18 + XTI = 2.0 FC = 0.82 .MODEL PA PNP + IS = 6.3E-17 BF = 69 VAF = 25 + IKF = 9.1E-03 ISE = 3.2E-16 NE = 1.4 BR = 16 + VAR = 1.8 IKR = 6.7E-02 ISC = 1.9E-18 + NC = 1.6 RB = 57 IRB = 0 RBM = 15 + RE = 1.3 RC = 51 CJE = 8.0E-14 VJE = 0.82 + MJE = 0.49 TF = 2.6E-11 XTF = 9.0 VTF = 2.7 + ITF = 2.7E-02 PTF = 0.0 CJC = 2.4E-13 VJC = 0.53 + MJC = 0.19 XCJC = 0.13 TR = 6.5E-11 CJS = 6.9E-13 + VJS = 0.60 MJS = 0.35 XTB = 2.5 EG = 1.18 + XTI = 2.0 FC = 0.90 .MODEL PB PNP + IS = 3.8E-16 BF = 69 VAF = 25 + IKF = 5.5E-02 ISE = 1.9E-15 NE = 1.4 BR = 19 + VAR = 1.8 IKR = 0.4 ISC = 1.1E-17 + NC = 1.6 RB = 9.5 IRB = 0 RBM = 2.5 + RE = 0.21 RC = 15 CJE = 4.8E-13 VJE = 0.82 + MJE = 0.49E-01 TF = 2.4E-11 XTF = 9.0 VTF = 2.7 + ITF = 0.16 PTF = 0.0 CJC = 9.5E-13 VJC = 0.53 + MJC = 0.19 XCJC = 0.19 TR = 6.5E-11 CJS = 1.5E-12 + VJS = 0.6 MJS = 0.35 XTB = 2.5 EG = 1.18 + XTI = 2.0 FC = 0.9 .MODEL D D (CJO=30E-12 VJ=0.01 M=2 ) .MODEL D1 D (IS=1E-14 ) .ENDS * * TEST CIRCUIT * *VIN VINPA 0 DC 0 AC 1 PULSE(-.3125 .3125 5.000n 2.000n 2.000n 30.000n 65.000n ) *VIN VINPA 0 DC 0 AC 1 SIN (0 .125 20MEG 0 0 0) *VCC 100 0 DC 5 AC 0 *VEE 110 0 DC -5 AC 0 *RT VINPA VINP 25 *RL VOUT 0 100 *RF VOUT VINN 430 *RN VINN 0 62 * *X1 VINP VINN 100 110 VOUT AD9624 * *.END * AD9630 SPICE Macro-Model 1/91, Rev. A * BT / IED * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * ************************************ *** WRITTEN BY BILL TOLLEY *** *** ANALOG DEVICES, IED DIVISION *** *** GREENSBORO, NORTH CAROLINA *** *** *** *** PATENT PENDING *** *** *** *** FOR APPLICATIONS ASSITANCE: *** *** CALL (919) 668-9511 AND ASK *** *** FOR MARKETING APPLICATIONS *** ************************************ * * .SUBCKT AD9630 1 14 100 110 * *** 1=VIN,14=VOUT,100=VCC,110=VEE ** * C1 100 7 5.0E-12 C2 5 110 5.0E-12 C3 2 0 2.4E-12 C4 3 0 2.7E-12 C5 8 0 2.4E-12 C6 6 0 2.7E-12 F1 100 7 V1 1 F2 5 110 V2 1 F3 1 110 V3 1 GM1 4 5 POLY(1) (2,6) -0.027 0.020 GM2 7 10 POLY(1) (3,8) -0.027 -0.020 I1 100 2 1.5E-3 I2 3 110 1.5E-3 I3 100 8 1.5E-3 I4 6 110 1.5E-3 I5 100 7 2E-3 I6 5 110 2E-3 I7 100 17 1.5E-3 I8 18 110 1.5E-3 Q1 110 1 2 100 QPA Q2 100 1 3 110 QNA Q3 100 14 6 110 QNA Q4 110 14 8 100 QPA Q5 7 7 11 110 QNA Q6 5 5 12 100 QPB Q7 100 7 13 110 QNB 8 Q8 110 5 15 100 QPB 8 Q9 110 16 17 100 QPA Q10 100 16 18 110 QNA R1 100 2 45E3 R2 3 110 161E3 R3 110 7 53E3 R4 5 110 17E3 R5 13 14 6 R6 14 15 6 R7 11 12 24 R8 100 8 45E3 R9 6 110 161E3 R10 100 17 45E3 R11 18 110 45E3 V1 100 4 0 V2 10 110 0 V3 16 110 DC 5 * * * .MODEL QNA NPN RB=35, IRB=0, RBM=8, RC=20, RE=0.56, + IS=4E-16, EG=1.2, XTI=2, XTB=2.4, BF=220, IKF=15E-3, + VAF=66, ISE=3E-15, NE=1.7, BR=4, IKR=1E6, VAR=3, + ISC=4.8E-20, NC=1.7, TF=24E-12, TR=4.4N, CJE=4.3E-13, + VJE=1.11, MJE=0.5, CJC=3.4E-13, VJC=0.642 + XCJC=0.18, CJS=4.9E-13, VJS=0.5, + MJS=0.32, ITF=65E-3, VTF=10, XTF=15 * .MODEL QNB NPN RB=6, IRB=0, RBM=1.33, RC=3.1, RE=0.09, + IS=24E-16, EG=1.21, XTI=2, XTB=2.4, BF=220, + IKF=90E-3, VAF=66, ISE=18E-15, NE=1.7, + BR=4, IKR=1E6, VAR=3, ISC=29E-20, NC=1.7, + TF=22E-12, TR=7.3N, CJE=1.8E-12, VJE=1.11, MJE=0.5, + CJC=1.59E-12, VJC=0.62, MJC=0.34, XCJC=0.23, + CJS=1.28E-12, VJS=0.5, MJS=0.32, + ITF=200E-3, VTF=10, XTF=15 * .MODEL QPA PNP RB=36, IRB=0, RBM=13, RC=14, RE=0.3, + IS=2.4E-16, EG=1.21, XTI=1.5, XTB=2.1, BF=115, + IKF=30E-3, VAF=30, ISE=12E-15, NE=1.6, + BR=4, IKR=1E6, VAR=1.4, ISC=5E-18, NC=1.6, + TF=41E-12, TR=5.3N, CJE=2.4E-13, VJE=0.89, MJE=0.49, + CJC=5.37E-13, VJC=0.53, MJC=0.19, XCJC=0.17, + CJS=1.11E-12, VJS=0.6, MJS=0.35, + ITF=150E-3, VTF=10, XTF=5 * .MODEL QPB PNP RB=29, IRB=0, RBM=10, RC=13, RE=0.24, + IS=3.03E-16, EG=1.21, XTI=1.5, XTB=2.1, BF=115, + IKF=38E-3, VAF=30, ISE=15E-15, NE=1.56, + BR=4, IKR=1E6, VAR=1.4, ISC=6E-18, NC=1.63, + TF=39E-12, TR=5.45N, CJE=3.9E-13, VJE=0.89, MJE=0.49, + CJC=6.41E-13, VJC=0.53, MJC=0.19, XCJC=0.18, + CJS=1E-12, VJS=0.6, MJS=0.35, + ITF=150E-3, VTF=10, XTF=5 * .MODEL QPC PNP RB=4.76, IRB=0, RBM=1.71, RC=2.84, RE=0.04, + IS=18.15E-16, EG=1.21, XTI=1.5, XTB=2.1, BF=115, + IKF=225E-3, VAF=30, ISE=92E-15, NE=1.56, + BR=4, IKR=1E6, VAR=1.4, ISC=3.74E-17, NC=1.63, + TF=31E-12, TR=7.6N, CJE=1.8E-12, VJE=0.89, MJE=0.49, + CJC=3E-12, VJC=0.53, MJC=0.19, XCJC=0.23, + CJS=4.52E-12, VJS=0.6, MJS=0.35, + ITF=200E-3, VTF=10, XTF=4 * .ENDS AD9630* AD9631an Spice Macro-model 2/17/97,SMR,REV A * * Copyright 1997 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. * Use of this model indicates your acceptance with * the terms and provisions in the License Statement. * * This is a second generation model of the AD9631a. In this * rev, voltage and current noise are modeled. Both of these * noise sources are referred to the inputs. * * The following parameters are also accurately modeled; * * open loop gain and phase vs frequency * output clamping voltage and current * CMRR vs freq * Slew rate * Output currents are reflected to V supplies * * Vos and Ibias are static and will not vary with Vcm. * Step response is modeled at unity gain w/100 ohm load * and Rf =250 ohms. * * Distortion is not characterized * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD9631an 1 2 99 50 61 * input stage * r1 1 2 500k cin1 1 98 1.2e-12 cin2 2 98 1.2e-12 q1 5 17 6 qn q2 7 2 8 qn eos 17 89 poly(1) (23,98) 3.3e-3 1 enoise 89 1 31 0 1 gnoise 99 2 36 0 1 r3 99 5 12.94 r4 99 7 12.94 r5 6 9 12.42 r6 8 9 12.42 c2 5 7 10.26pf itail 9 50 0.1 ** v noise generation ** dn1 80 81 dn dn2 81 82 dn vn3 82 0 0 rn1 82 0 340e-6 vn1 80 0 0.4 hn1 84 0 vn3 2.5 rn2 84 85 1.5 rn3 85 86 1 ln1 86 0 1.25e-9 en 30 0 85 0 1 rn4 30 31 1 cn1 31 0 0.3nf ** i noise generation ** vn4 87 0 0 rn5 87 0 2.92k hn2 35 0 vn4 1 rn6 35 36 1e-6 cn2 36 0 1e-1 * gain stage,clamping - open loop gain=52dB * * pd at 100khz * gm1 99 10 poly(1) 7 5 0 0.077 0 1e-3 gm2 50 10 poly(1) 7 5 0 0.077 0 1e-3 r7 99 10 10350 r8 10 50 10350 c3 99 10 76.9pf c4 10 50 76.9pf vcl1 99 14 1.77 vcl2 15 50 1.77 d1 10 14 dx d2 15 10 dx ***** frequency shaping stage, zero at 200mhz e1 11 98 10 98 10 rz1 11 12 0.9 rz2 12 13 0.1 l1 13 98 8e-11 ***** common mode reference ecmref 98 0 poly(2) 99 0 50 0 0 0.5 0.5 einref 18 0 poly(2) 1 0 2 0 0 0.5 0.5 ***** vcm generation ecm1 19 98 18 98 27e-6 rvcm1 19 20 666e-6 rvcm2 20 21 1e-6 lcm1 21 98 1.06e-12 ecm2 22 98 20 98 833 rvcm3 22 23 832e-6 rvcm4 23 24 1e-6 lcm2 24 98 1.3e-12 ***** buffer to output stage gbuf 98 16 12 98 1e-2 rbuf1 98 16 1e2 ***** output stage fo1 98 110 vcd 1 do1 110 111 dx do2 112 110 dx vi1 111 98 0 vi2 98 112 0 fsy 99 50 poly(2) vi1 vi2 -0.094 1 1 iq 99 50 11e-3 go3 60 99 99 16 0.1 go4 50 60 16 50 0.1 r03 60 99 10 r04 60 50 10 vcd 60 62 0 lo1 62 61 4e-8 ro2 61 98 1e9 do5 16 70 dx do6 71 16 dx vo1 70 60 0.27 vo2 60 71 0.27 .model dx d(kf=1e-30 af=0 is=1e-15) .model dn d(kf=1.16e-13 af=0 is=1e-15) .model qn npn(kf=1e-30 bf=6750 vaf=100 af=0) .ends AD9631an * AD9632an Spice Macro-model 3/7/97,SMR,Rev A * * Copyright 1997 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. * Use of this model indicates your acceptance with * the terms and provisions in the License Statement. * * The following parameters are modeled; * * open loop gain and phase vs frequency * output clamping voltage and current * input common mode range * CMRR vs freq * Slew rate * Output currents are reflected to V supplies * I bias is static and will not vary with Vcm * Vos is static and will not vary with Vcm * Step response is modeled at gain of 2 w/1k load * Slew rate is based on 10-90% change in output step * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD9632an 1 2 99 50 61 * input stage * gn 99 2 36 98 1 r1 1 18 250k r2 2 18 250k cin1 1 98 1.2e-12 cin2 2 98 1.2e-12 ibias1 50 1 8e-6 ibias2 99 2 8e-6 q1 5 17 6 qn1 q2 7 2 8 qn1 eos 17 1 poly(2) (23,98) (34,98) 2e-3 1 1 r3 99 5 50.23 r4 99 7 50.23 r5 6 9 47.63 r6 8 9 47.63 c2 5 7 2.26pf itail 9 50 0.02 irev 50 99 0.019 * vnoise generation dn1 30 31 dn vn1 31 98 0 rn1 31 98 100e-5 vn2 30 98 0.4 hn1 34 98 vn1 1 rn2 34 98 1 * inoise generation vn3 35 98 0 rn3 35 98 4k hn2 36 98 vn3 1 rn4 36 98 1e-6 * gain stage,clamping - open loop gain=64dB * * pd at 105khz * gm1 99 10 poly(1) 7 5 0 0.02 0 2.3e-3 gm2 50 10 poly(1) 7 5 0 0.02 0 2.3e-3 r7 99 10 79617 r8 10 50 79617 c3 99 10 13.33pf c4 10 50 13.33pf vcl1 99 14 1.65 vcl2 15 50 1.65 d1 10 14 dx d2 15 10 dx ******** frequency shaping stage ******** ***** zero at 200mhz, pole at 600mhz **** e1 11 98 10 98 3 rz1 11 12 2 rz2 12 13 1 l1 13 98 0.8e-9 ***** common mode reference eref 98 0 poly(2) 99 0 50 0 0 0.5 0.5 ***** vcm generation ecm1 19 98 18 98 38e-5 rvcm1 19 20 1.9e-9 rvcm2 20 21 1e-12 lcm1 21 98 1.516e-18 ecm2 22 98 20 98 25000 rvcm3 22 23 25e-8 rvcm4 23 24 1e-12 lcm2 24 98 1.990e-18 ***** buffer to output stage gbuf 98 16 12 98 1e-2 rbuf1 98 16 100 ***** output current mirrored to supplies fo1 98 110 vcd 1 do1 110 111 dx do2 112 110 dx vi1 111 98 0 vi2 98 112 0 fsy 99 50 poly(2) vi1 vi2 4.73e-3 1 1 iq 99 50 11e-3 ***** output stage go3 60 99 99 16 0.1 go4 50 60 16 50 0.1 r03 60 99 10 r04 60 50 10 vcd 60 62 0 lo1 62 61 0.75e-7 ro2 61 98 1e9 do5 16 70 dx do6 71 16 dx vo1 70 60 0.27 vo2 60 71 0.27 .model dx d(is=1e-15) .model dn d(af=0.6 kf=1.4e-10 is=1e-15) .model qn1 npn(af=0 kf=1e-30 is=1e-15 bf=1000) .ends AD9632an * OP-07A * Linear Technology OP07A op amp model * Written: 08-24-1989 12:35:59 Type: Bipolar npn input, internal comp. * OP07A updated from original model on 06-20-1990 * Typical specs: * Vos=1.0E-05, Ib=7.0E-10, Ios=3.0E-10, GBP=6.0E+05Hz, Phase mar.= 70 deg, * SR(+)=2.5E-01V/us, SR(-)=2.4E-01V/us, Av= 114 dB, CMMR= 126 dB, * Vsat(+)=2.00V, Vsat(-)=2.00V, Isc=+/-25.0mA, Iq=2500uA * (input differential mode clamp active) * * Connections: * Non-Inverting Input * | Inverting Input * | | Positive Power Supply * | | | Negative Power Supply * | | | | Output * | | | | | .SUBCKT OP07A 3 2 7 4 6 * INPUT RC1 7 80 8.842E+03 RC2 7 90 8.842E+03 Q1 80 102 10 QM1 Q2 90 103 11 QM2 RB1 2 102 5.000E+02 RB2 3 103 5.000E+02 DDM1 102 104 DM2 DDM3 104 103 DM2 DDM2 103 105 DM2 DDM4 105 102 DM2 C1 80 90 5.460E-12 RE1 10 12 1.948E+03 RE2 11 12 1.948E+03 IEE 12 4 7.502E-06 RE 12 0 2.666E+07 CE 12 0 1.579E-12 * INTERMEDIATE GCM 0 8 12 0 5.668E-11 GA 8 0 80 90 1.131E-04 R2 8 0 1.000E+05 C2 1 8 3.000E-11 GB 1 0 8 0 1.294E+03 * OUTPUT RO1 1 6 2.575E+01 RO2 1 0 3.425E+01 RC 17 0 6.634E-06 GC 0 17 6 0 1.507E+05 D1 1 17 DM1 D2 17 1 DM1 D3 6 13 DM2 D4 14 6 DM2 VC 7 13 2.803E+00 VE 14 4 2.803E+00 IP 7 4 2.492E-03 DSUB 4 7 DM2 * MODELS .MODEL QM1 NPN (IS=8.000E-16 BF=4.412E+03) .MODEL QM2 NPN (IS=8.003E-16 BF=6.818E+03) .MODEL DM1 D (IS=1.486E-08) .MODEL DM2 D (IS=8.000E-16) .ENDS OP07A* OP-07E * Linear Technology OP07E op amp model * Written: 08-24-1989 12:35:59 Type: Bipolar npn input, internal comp. * OP07E updated from original model on 06-20-1990 * Typical specs: * Vos=3.0E-05, Ib=1.2E-09, Ios=5.0E-10, GBP=6.0E+05Hz, Phase mar.= 70 deg, * SR(+)=2.5E-01V/us, SR(-)=2.4E-01V/us, Av= 114 dB, CMMR= 126 dB, * Vsat(+)=2.00V, Vsat(-)=2.00V, Isc=+/-25.0mA, Iq=2500uA * (input differential mode clamp active) * * Connections: * Non-Inverting Input * | Inverting Input * | | Positive Power Supply * | | | Negative Power Supply * | | | | Output * | | | | | .SUBCKT OP07E 3 2 7 4 6 * INPUT RC1 7 80 8.842E+03 RC2 7 90 8.842E+03 Q1 80 102 10 QM1 Q2 90 103 11 QM2 RB1 2 102 5.000E+02 RB2 3 103 5.000E+02 DDM1 102 104 DM2 DDM3 104 103 DM2 DDM2 103 105 DM2 DDM4 105 102 DM2 C1 80 90 5.460E-12 RE1 10 12 1.948E+03 RE2 11 12 1.948E+03 IEE 12 4 7.502E-06 RE 12 0 2.666E+07 CE 12 0 1.579E-12 * INTERMEDIATE GCM 0 8 12 0 5.668E-11 GA 8 0 80 90 1.131E-04 R2 8 0 1.000E+05 C2 1 8 3.000E-11 GB 1 0 8 0 1.294E+03 * OUTPUT RO1 1 6 2.575E+01 RO2 1 0 3.425E+01 RC 17 0 6.634E-06 GC 0 17 6 0 1.507E+05 D1 1 17 DM1 D2 17 1 DM1 D3 6 13 DM2 D4 14 6 DM2 VC 7 13 2.803E+00 VE 14 4 2.803E+00 IP 7 4 2.492E-03 DSUB 4 7 DM2 * MODELS .MODEL QM1 NPN (IS=8.000E-16 BF=2.586E+03) .MODEL QM2 NPN (IS=8.009E-16 BF=3.947E+03) .MODEL DM1 D (IS=1.486E-08) .MODEL DM2 D (IS=8.000E-16) .ENDS OP07E* OP113 SPICE Macro-model 3/94, Rev. A * ARG / PMI * * Copyright 1992 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. * Use of this model indicates your acceptance with * the terms and provisions in the License Statement. * * Node assignments * * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP113 3 2 7 4 6 * * INPUT STAGE * R3 4 19 1.5E3 R4 4 20 1.5E3 C1 19 20 5.31E-12 I1 7 18 106E-6 IOS 2 3 25E-09 EOS 12 5 POLY(1) 51 4 25E-06 1 Q1 19 3 18 PNP1 Q2 20 12 18 PNP1 CIN 3 2 3E-12 D1 3 1 DY D2 2 1 DY EN 5 2 22 0 1 GN1 0 2 25 0 1E-5 GN2 0 3 28 0 1E-5 * * VOLTAGE NOISE SOURCE WITH FLICKER NOISE * DN1 21 22 DEN DN2 22 23 DEN VN1 21 0 DC 2 VN2 0 23 DC 2 * * CURRENT NOISE SOURCE WITH FLICKER NOISE * DN3 24 25 DIN DN4 25 26 DIN VN3 24 0 DC 2 VN4 0 26 DC 2 * * SECOND CURRENT NOISE SOURCE * DN5 27 28 DIN DN6 28 29 DIN VN5 27 0 DC 2 VN6 0 29 DC 2 * * GAIN STAGE & DOMINANT POLE AT 2HZ * G2 34 36 19 20 2.65E-04 R7 34 36 39E6 V3 35 4 DC 6 D4 36 35 DX VB2 34 4 1.6 * * SUPPLY/2 GENERATOR * ISY 7 4 0.2E-3 R10 7 60 40E3 R11 60 4 40E3 C3 60 0 1E-9 * * CMRR STAGE & POLE AT 6kHZ * ECM 50 4 POLY(2) 3 60 2 60 0 0.8 0.8 CCM 50 51 26.5E-12 RCM1 50 51 1E6 RCM2 51 4 1 * * OUTPUT STAGE * R12 37 36 1E3 R13 38 36 500 C4 37 6 20E-12 C5 38 39 20E-12 M1 39 36 4 4 MN L=9E-6 W=1000E-6 AD=15E-9 AS=15E-9 M2 45 36 4 4 MN L=9E-6 W=1000E-6 AD=15E-9 AS=15E-9 D5 39 47 DX D6 47 45 DX Q3 39 40 41 QPA 8 VB 7 40 DC 0.861 R14 7 41 375 Q4 41 7 43 QNA 1 R17 7 43 15 Q5 43 39 6 QNA 20 Q6 46 45 6 QPA 20 R18 46 4 15 Q7 36 46 4 QNA 1 M3 6 36 4 4 MN L=9E-6 W=2000E-6 AD=30E-9 AS=30E-9 * * NONLINEAR MODELS USED * .MODEL DX D (IS=1E-15) .MODEL DY D (IS=1E-15 BV=7) .MODEL PNP1 PNP (BF=220) .MODEL DEN D(IS=1E-12 RS=1016 KF=3.278E-15 AF=1) .MODEL DIN D(IS=1E-12 RS=100019 KF=4.173E-15 AF=1) .MODEL QNA NPN(IS=1.19E-16 BF=253 VAF=193 VAR=15 RB=2.0E3 + IRB=7.73E-6 RBM=132.8 RE=4 RC=209 CJE=2.1E-13 VJE=0.573 + MJE=0.364 CJC=1.64E-13 VJC=0.534 MJC=0.5 CJS=1.37E-12 + VJS=0.59 MJS=0.5 TF=0.43E-9 PTF=30) .MODEL QPA PNP(IS=5.21E-17 BF=131 VAF=62 VAR=15 RB=1.52E3 + IRB=1.67E-5 RBM=368.5 RE=6.31 RC=354.4 CJE=1.1E-13 + VJE=0.745 MJE=0.33 CJC=2.37E-13 VJC=0.762 MJC=0.4 + CJS=7.11E-13 VJS=0.45 MJS=0.412 TF=1.0E-9 PTF=30) .MODEL MN NMOS(LEVEL=3 VTO=1.3 RS=0.3 RD=0.3 TOX=8.5E-8 + LD=1.48E-6 NSUB=1.53E16 UO=650 DELTA=10 VMAX=2E5 + XJ=1.75E-6 KAPPA=0.8 ETA=0.066 THETA=0.01 TPG=1 CJ=2.9E-4 + PB=0.837 MJ=0.407 CJSW=0.5E-9 MJSW=0.33) .ENDS * OP113E SPICE Macro-model 3/94, Rev. A * ARG / PMI * * This version of the OP113 model simulates the worst-case * parameters of the 'E' grade. The worst-case parameters * used correspond to those in the data sheet. * * Copyright 1992 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License * Statement. * * Node assignments * * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP113E 3 2 7 4 6 * * INPUT STAGE AND POLE AT 40MHZ * R3 4 19 1.5E3 R4 4 20 1.5E3 C1 19 20 1.326E-12 I1 7 18 106E-6 IOS 2 3 25E-9 EOS 12 5 POLY(1) 51 4 100E-6 1 Q1 19 3 18 PNP1 Q2 20 12 18 PNP1 CIN 3 2 3E-12 D1 3 1 DY D2 2 1 DY EN 5 2 22 0 1 GN1 0 2 25 0 1E-5 GN2 0 3 28 0 1E-5 * * VOLTAGE NOISE SOURCE WITH FLICKER NOISE * DN1 21 22 DEN DN2 22 23 DEN VN1 21 0 DC 2 VN2 0 23 DC 2 * * CURRENT NOISE SOURCE WITH FLICKER NOISE * DN3 24 25 DIN DN4 25 26 DIN VN3 24 0 DC 2 VN4 0 26 DC 2 * * SECOND CURRENT NOISE SOURCE * DN5 27 28 DIN DN6 28 29 DIN VN5 27 0 DC 2 VN6 0 29 DC 2 * * GAIN STAGE & DOMINANT POLE AT 1.581HZ * G2 34 36 19 20 54.814E-6 R7 34 36 39E6 V3 35 4 DC 6 D4 36 35 DX VB2 34 4 1.6 * * SUPPLY/2 GENERATOR * ISY 7 4 0.525E-3 R10 7 60 40E3 R11 60 4 40E3 C3 60 0 1E-9 * * CMRR STAGE & POLE AT 6KHZ * ECM 50 4 POLY(2) 3 60 2 60 0 0.5 0.5 CCM 50 51 26.5E-12 RCM1 50 51 1E6 RCM2 51 4 10 * * OUTPUT STAGE * R12 37 36 2E3 R13 38 36 200 C4 37 6 4E-12 C5 38 39 4E-12 M1 39 36 4 4 MN L=9E-6 W=1000E-6 AD=15E-9 AS=15E-9 M2 45 36 4 4 MN L=9E-6 W=1000E-6 AD=15E-9 AS=15E-9 D5 39 47 DX D6 47 45 DX Q3 39 40 41 QPA 8 VB 7 40 DC 0.861 R14 7 41 375 Q4 41 7 43 QNA 1 R17 7 43 15 Q5 43 39 6 QNA 20 Q6 46 45 6 QPA 20 R18 46 4 15 Q7 36 46 4 QNA 1 M3 6 36 4 4 MN L=9E-6 W=2000E-6 AD=30E-9 AS=30E-9 * * NONLINEAR MODELS USED * .MODEL DX D (IS=1E-15) .MODEL DY D (IS=1E-15 BV=7) .MODEL PNP1 PNP (BF=87.333) .MODEL DEN D(IS=1E-12 RS=1016 KF=3.278E-15 AF=1) .MODEL DIN D(IS=1E-12 RS=100019 KF=4.173E-15 AF=1) .MODEL QNA NPN(IS=1.19E-16 BF=253 VAF=193 VAR=15 RB=2.0E3 + IRB=7.73E-6 RBM=132.8 RE=4 RC=209 CJE=2.1E-13 VJE=0.573 + MJE=0.364 CJC=1.64E-13 VJC=0.534 MJC=0.5 CJS=0.685E-12 + VJS=0.59 MJS=0.5 TF=0.43E-9 PTF=30) .MODEL QPA PNP(IS=5.21E-17 BF=131 VAF=62 VAR=15 RB=1.52E3 + IRB=1.67E-5 RBM=368.5 RE=6.31 RC=354.4 CJE=1.1E-13 + VJE=0.745 MJE=0.33 CJC=2.37E-13 VJC=0.762 MJC=0.4 + CJS=7.11E-13 VJS=0.45 MJS=0.412 TF=1.0E-9 PTF=30) .MODEL MN NMOS(LEVEL=3 VTO=1.3 RS=0.3 RD=0.3 TOX=8.5E-8 + LD=1.48E-6 NSUB=1.53E16 UO=650 DELTA=10 VMAX=2E5 + XJ=1.75E-6 KAPPA=0.8 ETA=0.066 THETA=0.01 TPG=1 CJ=2.9E-5 + PB=0.837 MJ=0.407 CJSW=0.5E-10 MJSW=0.33) .ENDS OP113E * OP113F SPICE Macro-model 3/94, Rev. A * ARG / PMI * * This version of the OP113 model simulates the worst-case * parameters of the 'F' grade. The worst-case parameters * used correspond to those in the data sheet. * * Copyright 1992 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License * Statement. * * Node assignments * * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP113F 3 2 7 4 6 * * INPUT STAGE AND POLE AT 40MHZ * R3 4 19 1.5E3 R4 4 20 1.5E3 C1 19 20 1.326E-12 I1 7 18 106E-6 IOS 2 3 25E-9 EOS 12 5 POLY(1) 51 4 250E-6 1.585 Q1 19 3 18 PNP1 Q2 20 12 18 PNP1 CIN 3 2 3E-12 D1 3 1 DY D2 2 1 DY EN 5 2 22 0 1 GN1 0 2 25 0 1E-5 GN2 0 3 28 0 1E-5 * * VOLTAGE NOISE SOURCE WITH FLICKER NOISE * DN1 21 22 DEN DN2 22 23 DEN VN1 21 0 DC 2 VN2 0 23 DC 2 * * CURRENT NOISE SOURCE WITH FLICKER NOISE * DN3 24 25 DIN DN4 25 26 DIN VN3 24 0 DC 2 VN4 0 26 DC 2 * * SECOND CURRENT NOISE SOURCE * DN5 27 28 DIN DN6 28 29 DIN VN5 27 0 DC 2 VN6 0 29 DC 2 * * GAIN STAGE & DOMINANT POLE AT 1.581HZ * G2 34 36 19 20 54.814E-6 R7 34 36 39E6 V3 35 4 DC 6 D4 36 35 DX VB2 34 4 1.6 * * SUPPLY/2 GENERATOR * ISY 7 4 0.525E-3 R10 7 60 40E3 R11 60 4 40E3 C3 60 0 1E-9 * * CMRR STAGE & POLE AT 6KHZ * ECM 50 4 POLY(2) 3 60 2 60 0 0.5 0.5 CCM 50 51 26.5E-12 RCM1 50 51 1E6 RCM2 51 4 10 * * OUTPUT STAGE * R12 37 36 2E3 R13 38 36 200 C4 37 6 4E-12 C5 38 39 4E-12 M1 39 36 4 4 MN L=9E-6 W=1000E-6 AD=15E-9 AS=15E-9 M2 45 36 4 4 MN L=9E-6 W=1000E-6 AD=15E-9 AS=15E-9 D5 39 47 DX D6 47 45 DX Q3 39 40 41 QPA 8 VB 7 40 DC 0.861 R14 7 41 375 Q4 41 7 43 QNA 1 R17 7 43 15 Q5 43 39 6 QNA 20 Q6 46 45 6 QPA 20 R18 46 4 15 Q7 36 46 4 QNA 1 M3 6 36 4 4 MN L=9E-6 W=2000E-6 AD=30E-9 AS=30E-9 * * NONLINEAR MODELS USED * .MODEL DX D (IS=1E-15) .MODEL DY D (IS=1E-15 BV=7) .MODEL PNP1 PNP (BF=87.333) .MODEL DEN D(IS=1E-12 RS=1016 KF=3.278E-15 AF=1) .MODEL DIN D(IS=1E-12 RS=100019 KF=4.173E-15 AF=1) .MODEL QNA NPN(IS=1.19E-16 BF=253 VAF=193 VAR=15 RB=2.0E3 + IRB=7.73E-6 RBM=132.8 RE=4 RC=209 CJE=2.1E-13 VJE=0.573 + MJE=0.364 CJC=1.64E-13 VJC=0.534 MJC=0.5 CJS=0.685E-12 + VJS=0.59 MJS=0.5 TF=0.43E-9 PTF=30) .MODEL QPA PNP(IS=5.21E-17 BF=131 VAF=62 VAR=15 RB=1.52E3 + IRB=1.67E-5 RBM=368.5 RE=6.31 RC=354.4 CJE=1.1E-13 + VJE=0.745 MJE=0.33 CJC=2.37E-13 VJC=0.762 MJC=0.4 + CJS=7.11E-13 VJS=0.45 MJS=0.412 TF=1.0E-9 PTF=30) .MODEL MN NMOS(LEVEL=3 VTO=1.3 RS=0.3 RD=0.3 TOX=8.5E-8 + LD=1.48E-6 NSUB=1.53E16 UO=650 DELTA=10 VMAX=2E5 + XJ=1.75E-6 KAPPA=0.8 ETA=0.066 THETA=0.01 TPG=1 CJ=2.9E-5 + PB=0.837 MJ=0.407 CJSW=0.5E-10 MJSW=0.33) .ENDS * OP-15B * Linear Technology OP15B op amp model (with calls for OP15F) * Written: 05-10-1990 18:54:03 Type: PFET input, internal comp. * Typical specs: * Vos=4.0E-04, Ib=4.0E-11, Ios=1.0E-11, GBP=5.7E+06Hz, Phase mar.= 45 deg, * SR(low)=1.1E+01V/us, SR(high)=2.2E+01V/us, Av=107.0dB, CMRR=100.0dB, * Vsat(+)=2.0V, Vsat(-)=2.0V, Isc=+/-25mA, Rout= 100ohms, Iq= 3mA. * (input cm clamp *optional*) * * Connections: * Non-Inverting Input * | Inverting Input * | | Positive Power Supply * | | | Negative Power Supply * | | | | Output * | | | | | .SUBCKT OP15B 3 2 7 4 6 * INPUT VCM2 40 4 2.0000E+00 RD1 40 80 9.3073E+02 RD2 40 90 9.3073E+02 J1 80 102 12 JM1 J2 90 103 12 JM2 CIN 2 3 4.0000E-12 RG1 2 102 2.0000E+00 RG2 3 103 2.0000E+00 ** CM CLAMP * DCM1 107 103 DM4 * DCM2 105 107 DM4 * VCMC 105 4 4.0E+00 * ECMP 106 4 103 4 1 * RCMP 107 106 1E+04 * DCM3 109 102 DM4 * DCM4 105 109 DM4 * ECMN 108 4 102 4 1 * RCMN 109 108 1E+04 ** END CM CLAMP C1 80 90 1.5000E-11 ISS 7 12 4.4000E-04 GOSIT 7 12 90 80 2.2000E-04 * INTERMEDIATE GCM 0 8 12 0 1.0744E-08 GA 8 0 80 90 1.0744E-03 R2 8 0 1.0000E+05 C2 1 8 3.0000E-11 GB 1 0 8 0 2.1047E+01 RO2 1 0 9.9000E+01 * OUTPUT RSO 1 6 1.0000E+00 ECL 18 0 1 6 2.0598E+01 GCL 0 8 20 0 1.0000E+00 RCL 20 0 1.0000E+03 D1 18 20 DM1 D2 20 18 DM1 * D3A 131 70 DM3 D3B 13 131 DM3 GPL 0 8 70 7 1.0000E+00 VC 13 6 3.1528E+00 RPLA 7 70 1.0000E+04 RPLB 7 131 1.0000E+05 D4A 60 141 DM3 D4B 141 14 DM3 GNL 0 8 60 4 1.0000E+00 VE 6 14 3.1528E+00 RNLA 60 4 1.0000E+04 RNLB 141 4 1.0000E+05 * IP 7 4 2.2600E-03 DSUB 4 7 DM2 * MODELS .MODEL JM1 PJF (IS=4.5000E-11 BETA=1.3118E-03 VTO=-1.000000E+00) .MODEL JM2 PJF (IS=3.5000E-11 BETA=1.3118E-03 VTO=-9.996000E-01) .MODEL DM1 D (IS=1.0000E-15) .MODEL DM2 D (IS=8.0000E-16 BV=5.2800E+01) .MODEL DM3 D (IS=1.0000E-16) .MODEL DM4 D (IS=1.0000E-09) .ENDS OP15B* OP-15E * Connections: * Non-Inverting Input * | Inverting Input * | | Positive Power Supply * | | | Negative Power Supply * | | | | Output * | | | | | .SUBCKT OP15E 3 2 7 4 6 X_OP15E 3 2 7 4 6 OP15A .ENDS OP15E * * OP-15A * Linear Technology OP15A op amp model (with calls for OP15E) * Written: 05-10-1990 18:51:28 Type: PFET input, internal comp. * Typical specs: * Vos=2.0E-04, Ib=1.8E-11, Ios=5.0E-12, GBP=6.0E+06Hz, Phase mar.= 45 deg, * SR(low)=1.3E+01V/us, SR(high)=2.6E+01V/us, Av=108.0dB, CMRR=100.0dB, * Vsat(+)=2.0V, Vsat(-)=2.0V, Isc=+/-25mA, Rout= 100ohms, Iq= 3mA. * (input cm clamp *optional*) * * Connections: * Non-Inverting Input * | Inverting Input * | | Positive Power Supply * | | | Negative Power Supply * | | | | Output * | | | | | .SUBCKT OP15A 3 2 7 4 6 * INPUT VCM2 40 4 2.0000E+00 RD1 40 80 8.8419E+02 RD2 40 90 8.8419E+02 J1 80 102 12 JM1 J2 90 103 12 JM2 CIN 2 3 4.0000E-12 RG1 2 102 2.0000E+00 RG2 3 103 2.0000E+00 ** CM CLAMP * DCM1 107 103 DM4 * DCM2 105 107 DM4 * VCMC 105 4 4.0E+00 * ECMP 106 4 103 4 1 * RCMP 107 106 1E+04 * DCM3 109 102 DM4 * DCM4 105 109 DM4 * ECMN 108 4 102 4 1 * RCMN 109 108 1E+04 ** END CM CLAMP C1 80 90 1.5000E-11 ISS 7 12 5.2000E-04 GOSIT 7 12 90 80 2.6000E-04 * INTERMEDIATE GCM 0 8 12 0 1.1310E-08 GA 8 0 80 90 1.1310E-03 R2 8 0 1.0000E+05 C2 1 8 3.0000E-11 GB 1 0 8 0 2.2434E+01 RO2 1 0 9.9000E+01 * OUTPUT RSO 1 6 1.0000E+00 ECL 18 0 1 6 2.0774E+01 GCL 0 8 20 0 1.0000E+00 RCL 20 0 1.0000E+03 D1 18 20 DM1 D2 20 18 DM1 * D3A 131 70 DM3 D3B 13 131 DM3 GPL 0 8 70 7 1.0000E+00 VC 13 6 3.1575E+00 RPLA 7 70 1.0000E+04 RPLB 7 131 1.0000E+05 D4A 60 141 DM3 D4B 141 14 DM3 GNL 0 8 60 4 1.0000E+00 VE 6 14 3.1575E+00 RNLA 60 4 1.0000E+04 RNLB 141 4 1.0000E+05 * IP 7 4 2.1800E-03 DSUB 4 7 DM2 * MODELS .MODEL JM1 PJF (IS=2.0500E-11 BETA=1.2299E-03 VTO=-1.000000E+00) .MODEL JM2 PJF (IS=1.5500E-11 BETA=1.2299E-03 VTO=-9.998000E-01) .MODEL DM1 D (IS=1.0000E-15) .MODEL DM2 D (IS=8.0000E-16 BV=5.2800E+01) .MODEL DM3 D (IS=1.0000E-16) .MODEL DM4 D (IS=1.0000E-09) .ENDS OP15A* OP-15F * Connections: * Non-Inverting Input * | Inverting Input * | | Positive Power Supply * | | | Negative Power Supply * | | | | Output * | | | | | .SUBCKT OP15F 3 2 7 4 6 X_OP15F 3 2 7 4 6 OP15B .ENDS OP15F * * OP-15B * Linear Technology OP15B op amp model (with calls for OP15F) * Written: 05-10-1990 18:54:03 Type: PFET input, internal comp. * Typical specs: * Vos=4.0E-04, Ib=4.0E-11, Ios=1.0E-11, GBP=5.7E+06Hz, Phase mar.= 45 deg, * SR(low)=1.1E+01V/us, SR(high)=2.2E+01V/us, Av=107.0dB, CMRR=100.0dB, * Vsat(+)=2.0V, Vsat(-)=2.0V, Isc=+/-25mA, Rout= 100ohms, Iq= 3mA. * (input cm clamp *optional*) * * Connections: * Non-Inverting Input * | Inverting Input * | | Positive Power Supply * | | | Negative Power Supply * | | | | Output * | | | | | .SUBCKT OP15B 3 2 7 4 6 * INPUT VCM2 40 4 2.0000E+00 RD1 40 80 9.3073E+02 RD2 40 90 9.3073E+02 J1 80 102 12 JM1 J2 90 103 12 JM2 CIN 2 3 4.0000E-12 RG1 2 102 2.0000E+00 RG2 3 103 2.0000E+00 ** CM CLAMP * DCM1 107 103 DM4 * DCM2 105 107 DM4 * VCMC 105 4 4.0E+00 * ECMP 106 4 103 4 1 * RCMP 107 106 1E+04 * DCM3 109 102 DM4 * DCM4 105 109 DM4 * ECMN 108 4 102 4 1 * RCMN 109 108 1E+04 ** END CM CLAMP C1 80 90 1.5000E-11 ISS 7 12 4.4000E-04 GOSIT 7 12 90 80 2.2000E-04 * INTERMEDIATE GCM 0 8 12 0 1.0744E-08 GA 8 0 80 90 1.0744E-03 R2 8 0 1.0000E+05 C2 1 8 3.0000E-11 GB 1 0 8 0 2.1047E+01 RO2 1 0 9.9000E+01 * OUTPUT RSO 1 6 1.0000E+00 ECL 18 0 1 6 2.0598E+01 GCL 0 8 20 0 1.0000E+00 RCL 20 0 1.0000E+03 D1 18 20 DM1 D2 20 18 DM1 * D3A 131 70 DM3 D3B 13 131 DM3 GPL 0 8 70 7 1.0000E+00 VC 13 6 3.1528E+00 RPLA 7 70 1.0000E+04 RPLB 7 131 1.0000E+05 D4A 60 141 DM3 D4B 141 14 DM3 GNL 0 8 60 4 1.0000E+00 VE 6 14 3.1528E+00 RNLA 60 4 1.0000E+04 RNLB 141 4 1.0000E+05 * IP 7 4 2.2600E-03 DSUB 4 7 DM2 * MODELS .MODEL JM1 PJF (IS=4.5000E-11 BETA=1.3118E-03 VTO=-1.000000E+00) .MODEL JM2 PJF (IS=3.5000E-11 BETA=1.3118E-03 VTO=-9.996000E-01) .MODEL DM1 D (IS=1.0000E-15) .MODEL DM2 D (IS=8.0000E-16 BV=5.2800E+01) .MODEL DM3 D (IS=1.0000E-16) .MODEL DM4 D (IS=1.0000E-09) .ENDS OP15B* OP160A SPICE Macro-model 12/90, Rev. B * JCB / PMI * * Revision History: * REV. B * Re-ordered subcircuit call out nodes to put the * output node last. * * * This version of the OP-160 model simulates the worst case * parameters of the 'A' grade. The worst case parameters * used correspond to those in the data book. * * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP160A 1 2 99 50 28 * * INPUT STAGE * R1 99 8 1E3 R2 10 50 1E3 V1 99 9 5.4 D1 9 8 DX V2 11 50 5.4 D2 10 11 DX I1 99 5 175E-6 I2 4 50 175E-6 Q1 50 3 5 QP Q2 99 3 4 QN Q3 8 6 30 QN Q4 10 7 30 QP R3 5 6 300E3 R4 4 7 300E3 C1 99 6 0.0133E-12 C2 50 7 0.0133E-12 * * INPUT ERROR SOURCES * GB1 99 1 POLY(1) 1 22 1E-6 7.5E-8 GB2 99 30 POLY(1) 1 22 2E-5 7.5E-8 VOS 3 1 5E-3 LS1 30 2 1E-6 CS1 99 2 1.5E-12 CS2 50 2 1.5E-12 * EREF 97 0 22 0 1 * * GAIN STAGE & DOMINANT POLE * R5 12 97 3E6 C3 12 97 6E-12 G1 97 12 99 8 1E-3 G2 12 97 10 50 1E-3 V3 99 13 4.2 V4 14 50 4.2 D3 12 13 DX D4 14 12 DX CF 29 28 30E-12 RF 12 29 300 * * ZERO / POLE PAIR AT 50 MHZ / 300 MHZ * R6 15 16 1E6 L1 16 97 2.65E-3 R7 16 97 5E6 G3 97 15 12 22 1E-6 * * POLE AT 300 MHZ * R8 17 97 1E6 C4 17 97 0.531E-15 G4 97 17 15 22 1E-6 * * POLE AT 300 MHZ * R9 18 97 1E6 C5 18 97 0.531E-15 G5 97 18 17 22 1E-6 * * POLE AT 500 MHZ * R10 19 97 1E6 C6 19 97 0.318E-15 G6 97 19 18 22 1E-6 * * POLE AT 500 MHZ * R11 20 97 1E6 C7 20 97 0.318E-15 G7 97 20 19 22 1E-6 * * POLE AT 500 MHZ * R12 21 97 1E6 C8 21 97 0.318E-15 G8 97 21 20 22 1E-6 * * OUTPUT STAGE * ISY 99 50 3.15E-3 R13 22 99 3.333E3 R14 22 50 3.333E3 R15 27 99 40 R16 27 50 40 L2 27 28 4E-8 G9 25 50 21 27 25E-3 G10 26 50 27 21 25E-3 G11 27 99 99 21 25E-3 G12 50 27 21 50 25E-3 V5 23 27 0 V6 27 24 0 D5 21 23 DX D6 24 21 DX D7 99 25 DX D8 99 26 DX D9 50 25 DY D10 50 26 DY * * MODELS USED * .MODEL QN NPN(BF=1E9 IS=1E-15 VAF=51.6) .MODEL QP PNP(BF=1E9 IS=1E-15 VAF=51.6) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP160F SPICE Macro-model 12/90, Rev. B * JCB / PMI * * Revision History: * REV. B * Re-ordered subcircuit call out nodes to put the * output node last. * * * This version of the OP-160 model simulates the worst case * parameters of the 'F' grade. The worst case parameters * used correspond to those in the data book. * * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP160F 1 2 99 50 28 * * INPUT STAGE * R1 99 8 1E3 R2 10 50 1E3 V1 99 9 4.2 D1 9 8 DX V2 11 50 4.2 D2 10 11 DX I1 99 5 175E-6 I2 4 50 175E-6 Q1 50 3 5 QP Q2 99 3 4 QN Q3 8 6 30 QN Q4 10 7 30 QP R3 5 6 300E3 R4 4 7 300E3 C1 99 6 0.0133E-12 C2 50 7 0.0133E-12 * * INPUT ERROR SOURCES * GB1 99 1 POLY(1) 1 22 1E-6 7.5E-8 GB2 99 30 POLY(1) 1 22 2E-5 7.5E-8 VOS 3 1 5E-3 LS1 30 2 1E-6 CS1 99 2 1.5E-12 CS2 50 2 1.5E-12 * EREF 97 0 22 0 1 * * GAIN STAGE & DOMINANT POLE * R5 12 97 3E6 C3 12 97 6E-12 G1 97 12 99 8 1E-3 G2 12 97 10 50 1E-3 V3 99 13 4.2 V4 14 50 4.2 D3 12 13 DX D4 14 12 DX CF 29 28 30E-12 RF 12 29 300 * * ZERO / POLE PAIR AT 50 MHZ / 300 MHZ * R6 15 16 1E6 L1 16 97 2.65E-3 R7 16 97 5E6 G3 97 15 12 22 1E-6 * * POLE AT 300 MHZ * R8 17 97 1E6 C4 17 97 0.531E-15 G4 97 17 15 22 1E-6 * * POLE AT 300 MHZ * R9 18 97 1E6 C5 18 97 0.531E-15 G5 97 18 17 22 1E-6 * * POLE AT 500 MHZ * R10 19 97 1E6 C6 19 97 0.318E-15 G6 97 19 18 22 1E-6 * * POLE AT 500 MHZ * R11 20 97 1E6 C7 20 97 0.318E-15 G7 97 20 19 22 1E-6 * * POLE AT 500 MHZ * R12 21 97 1E6 C8 21 97 0.318E-15 G8 97 21 20 22 1E-6 * * OUTPUT STAGE * ISY 99 50 3.15E-3 R13 22 99 3.333E3 R14 22 50 3.333E3 R15 27 99 40 R16 27 50 40 L2 27 28 4E-8 G9 25 50 21 27 25E-3 G10 26 50 27 21 25E-3 G11 27 99 99 21 25E-3 G12 50 27 21 50 25E-3 V5 23 27 0 V6 27 24 0 D5 21 23 DX D6 24 21 DX D7 99 25 DX D8 99 26 DX D9 50 25 DY D10 50 26 DY * * MODELS USED * .MODEL QN NPN(BF=1E9 IS=1E-15 VAF=51.6) .MODEL QP PNP(BF=1E9 IS=1E-15 VAF=51.6) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP160G SPICE Macro-model 12/90, Rev. B * JCB / PMI * * Revision History: * REV. B * Re-ordered subcircuit call out nodes to put the * output node last. * * * This version of the OP-160 model simulates the worst case * parameters of the 'G' grade. The worst case parameters * used correspond to those in the data book. * * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP160G 1 2 99 50 28 * * INPUT STAGE * R1 99 8 1E3 R2 10 50 1E3 V1 99 9 4.2 D1 9 8 DX V2 11 50 4.2 D2 10 11 DX I1 99 5 175E-6 I2 4 50 175E-6 Q1 50 3 5 QP Q2 99 3 4 QN Q3 8 6 30 QN Q4 10 7 30 QP R3 5 6 300E3 R4 4 7 300E3 C1 99 6 0.0133E-12 C2 50 7 0.0133E-12 * * INPUT ERROR SOURCES * GB1 99 1 POLY(1) 1 22 1.5E-6 125E-8 GB2 99 30 POLY(1) 1 22 3E-5 125E-8 VOS 3 1 5E-3 LS1 30 2 1E-6 CS1 99 2 1.5E-12 CS2 50 2 1.5E-12 * EREF 97 0 22 0 1 * * GAIN STAGE & DOMINANT POLE * R5 12 97 3E6 C3 12 97 6E-12 G1 97 12 99 8 1E-3 G2 12 97 10 50 1E-3 V3 99 13 4.2 V4 14 50 4.2 D3 12 13 DX D4 14 12 DX CF 29 28 30E-12 RF 12 29 300 * * ZERO / POLE PAIR AT 50 MHZ / 300 MHZ * R6 15 16 1E6 L1 16 97 2.65E-3 R7 16 97 5E6 G3 97 15 12 22 1E-6 * * POLE AT 300 MHZ * R8 17 97 1E6 C4 17 97 0.531E-15 G4 97 17 15 22 1E-6 * * POLE AT 300 MHZ * R9 18 97 1E6 C5 18 97 0.531E-15 G5 97 18 17 22 1E-6 * * POLE AT 500 MHZ * R10 19 97 1E6 C6 19 97 0.318E-15 G6 97 19 18 22 1E-6 * * POLE AT 500 MHZ * R11 20 97 1E6 C7 20 97 0.318E-15 G7 97 20 19 22 1E-6 * * POLE AT 500 MHZ * R12 21 97 1E6 C8 21 97 0.318E-15 G8 97 21 20 22 1E-6 * * OUTPUT STAGE * ISY 99 50 3.15E-3 R13 22 99 3.333E3 R14 22 50 3.333E3 R15 27 99 40 R16 27 50 40 L2 27 28 4E-8 G9 25 50 21 27 25E-3 G10 26 50 27 21 25E-3 G11 27 99 99 21 25E-3 G12 50 27 21 50 25E-3 V5 23 27 0 V6 27 24 0 D5 21 23 DX D6 24 21 DX D7 99 25 DX D8 99 26 DX D9 50 25 DY D10 50 26 DY * * MODELS USED * .MODEL QN NPN(BF=1E9 IS=1E-15 VAF=51.6) .MODEL QP PNP(BF=1E9 IS=1E-15 VAF=51.6) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP162/OP262/OP462 SPICE Macro-model * 7/96, Ver. 1 * Troy Murphy / ADSC * * Copyright 1996 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance of the terms and provisions in the License * Statement. * * Node Assignments * noninverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | * | | | | | .SUBCKT OP162 1 2 99 50 45 * *INPUT STAGE * Q1 5 7 3 PIX 5 Q2 6 2 4 PIX 5 Ios 1 2 1.25E-9 I1 99 15 85E-6 EOS 7 1 POLY(1) (14,20) 45E-6 1 RC1 5 50 3.035E+3 RC2 6 50 3.035E+3 RE1 3 15 607 RE2 4 15 607 C1 5 6 600E-15 D1 3 8 DX D2 4 9 DX V1 99 8 DC 1 V2 99 9 DC 1 * * 1st GAIN STAGE * EREF 98 0 20 0 1 G1 98 10 5 6 10.5 R1 10 98 1 C2 10 98 3.3E-9 * * COMMON-MODE STAGE WITH ZERO AT 4kHz * ECM 13 98 POLY(2) (1,98) (2,98) 0 0.5 0.5 R2 13 14 1E+6 R3 14 98 70 C3 13 14 80E-12 * * POLE AT 1.5MHz, ZERO AT 3MHz * G2 21 98 10 98 .588E-6 R4 21 98 1.7E+6 R5 21 22 1.7E+6 C4 22 98 31.21E-15 * * POLE AT 6MHz, ZERO AT 3MHz * E1 23 98 21 98 2 R6 23 24 53E+3 R7 24 98 53E+3 C5 23 24 1E-12 * * SECOND GAIN STAGE * G3 25 98 24 98 40E-6 R8 25 98 1.65E+6 D3 25 99 DX D4 50 25 DX * * OUTPUT STAGE * GSY 99 50 POLY(1) (99,50) 277.5E-6 7.5E-6 R9 99 20 100E3 R10 20 50 100E3 Q3 45 41 99 POUT 4 Q4 45 43 50 NOUT 2 EB1 99 40 POLY(1) (98,25) 0.70366 1 EB2 42 50 POLY(1) (25,98) 0.73419 1 RB1 40 41 500 RB2 42 43 500 CF 45 25 11E-12 D5 46 99 DX D6 47 43 DX V3 46 41 0.7 V4 47 50 0.7 .MODEL PIX PNP (Bf=117.7) .MODEL POUT PNP (BF=119, IS=2.782E-17, VAF=28, KF=3E-7) .MODEL NOUT NPN (BF=110, IS=1.786E-17, VAF=90, KF=3E-7) .MODEL DX D() .ENDS OP162 * OP-16A * Linear Technology OP16A op amp model (with calls for OP16E) * Written: 05-10-1990 19:00:18 Type: PFET input, internal comp. * Typical specs: * Vos=2.0E-04, Ib=2.0E-11, Ios=5.0E-12, GBP=8.0E+06Hz, Phase mar.= 45 deg, * SR(low)=2.0E+01V/us, SR(high)=4.0E+01V/us, Av=108.0dB, CMRR=100.0dB, * Vsat(+)=2.0V, Vsat(-)=2.0V, Isc=+/-25mA, Rout= 75ohms, Iq= 5mA. * (input cm clamp *optional*) * * Connections: * Non-Inverting Input * | Inverting Input * | | Positive Power Supply * | | | Negative Power Supply * | | | | Output * | | | | | .SUBCKT OP16A 3 2 7 4 6 * INPUT VCM2 40 4 2.0000E+00 RD1 40 80 6.6315E+02 RD2 40 90 6.6315E+02 J1 80 102 12 JM1 J2 90 103 12 JM2 CIN 2 3 4.0000E-12 RG1 2 102 2.0000E+00 RG2 3 103 2.0000E+00 ** CM CLAMP * DCM1 107 103 DM4 * DCM2 105 107 DM4 * VCMC 105 4 4.0E+00 * ECMP 106 4 103 4 1 * RCMP 107 106 1E+04 * DCM3 109 102 DM4 * DCM4 105 109 DM4 * ECMN 108 4 102 4 1 * RCMN 109 108 1E+04 ** END CM CLAMP C1 80 90 1.5000E-11 ISS 7 12 8.0000E-04 GOSIT 7 12 90 80 4.0000E-04 * INTERMEDIATE GCM 0 8 12 0 1.5080E-08 GA 8 0 80 90 1.5080E-03 R2 8 0 1.0000E+05 C2 1 8 3.0000E-11 GB 1 0 8 0 2.2510E+01 RO2 1 0 7.4000E+01 * OUTPUT RSO 1 6 1.0000E+00 ECL 18 0 1 6 2.1231E+01 GCL 0 8 20 0 1.0000E+00 RCL 20 0 1.0000E+03 D1 18 20 DM1 D2 20 18 DM1 * D3A 131 70 DM3 D3B 13 131 DM3 GPL 0 8 70 7 1.0000E+00 VC 13 6 3.1696E+00 RPLA 7 70 1.0000E+04 RPLB 7 131 1.0000E+05 D4A 60 141 DM3 D4B 141 14 DM3 GNL 0 8 60 4 1.0000E+00 VE 6 14 3.1696E+00 RNLA 60 4 1.0000E+04 RNLB 141 4 1.0000E+05 * IP 7 4 3.8000E-03 DSUB 4 7 DM2 * MODELS .MODEL JM1 PJF (IS=2.2500E-11 BETA=1.4212E-03 VTO=-1.000000E+00) .MODEL JM2 PJF (IS=1.7500E-11 BETA=1.4212E-03 VTO=-9.998000E-01) .MODEL DM1 D (IS=1.0000E-15) .MODEL DM2 D (IS=8.0000E-16 BV=5.2800E+01) .MODEL DM3 D (IS=1.0000E-16) .MODEL DM4 D (IS=1.0000E-09) .ENDS OP16A* OP-16B * Linear Technology OP16B op amp model (with calls for OP16F) * Written: 05-10-1990 19:02:39 Type: PFET input, internal comp. * Typical specs: * Vos=4.0E-04, Ib=4.0E-11, Ios=1.0E-11, GBP=7.6E+06Hz, Phase mar.= 45 deg, * SR(low)=1.8E+01V/us, SR(high)=3.6E+01V/us, Av=107.0dB, CMRR=100.0dB, * Vsat(+)=2.0V, Vsat(-)=2.0V, Isc=+/-25mA, Rout= 75ohms, Iq= 5mA. * (input cm clamp *optional*) * * Connections: * Non-Inverting Input * | Inverting Input * | | Positive Power Supply * | | | Negative Power Supply * | | | | Output * | | | | | .SUBCKT OP16B 3 2 7 4 6 * INPUT VCM2 40 4 2.0000E+00 RD1 40 80 6.9805E+02 RD2 40 90 6.9805E+02 J1 80 102 12 JM1 J2 90 103 12 JM2 CIN 2 3 4.0000E-12 RG1 2 102 2.0000E+00 RG2 3 103 2.0000E+00 ** CM CLAMP * DCM1 107 103 DM4 * DCM2 105 107 DM4 * VCMC 105 4 4.0E+00 * ECMP 106 4 103 4 1 * RCMP 107 106 1E+04 * DCM3 109 102 DM4 * DCM4 105 109 DM4 * ECMN 108 4 102 4 1 * RCMN 109 108 1E+04 ** END CM CLAMP C1 80 90 1.5000E-11 ISS 7 12 7.2000E-04 GOSIT 7 12 90 80 3.6000E-04 * INTERMEDIATE GCM 0 8 12 0 1.4326E-08 GA 8 0 80 90 1.4326E-03 R2 8 0 1.0000E+05 C2 1 8 3.0000E-11 GB 1 0 8 0 2.1118E+01 RO2 1 0 7.4000E+01 * OUTPUT RSO 1 6 1.0000E+00 ECL 18 0 1 6 2.1119E+01 GCL 0 8 20 0 1.0000E+00 RCL 20 0 1.0000E+03 D1 18 20 DM1 D2 20 18 DM1 * D3A 131 70 DM3 D3B 13 131 DM3 GPL 0 8 70 7 1.0000E+00 VC 13 6 3.1666E+00 RPLA 7 70 1.0000E+04 RPLB 7 131 1.0000E+05 D4A 60 141 DM3 D4B 141 14 DM3 GNL 0 8 60 4 1.0000E+00 VE 6 14 3.1666E+00 RNLA 60 4 1.0000E+04 RNLB 141 4 1.0000E+05 * IP 7 4 3.8800E-03 DSUB 4 7 DM2 * MODELS .MODEL JM1 PJF (IS=4.5000E-11 BETA=1.4252E-03 VTO=-1.000000E+00) .MODEL JM2 PJF (IS=3.5000E-11 BETA=1.4252E-03 VTO=-9.996000E-01) .MODEL DM1 D (IS=1.0000E-15) .MODEL DM2 D (IS=8.0000E-16 BV=5.2800E+01) .MODEL DM3 D (IS=1.0000E-16) .MODEL DM4 D (IS=1.0000E-09) .ENDS OP16B* OP-16F * Connections: * Non-Inverting Input * | Inverting Input * | | Positive Power Supply * | | | Negative Power Supply * | | | | Output * | | | | | .SUBCKT OP16F 3 2 7 4 6 X_OP16F 3 2 7 4 6 OP16B .ENDS OP16F * * OP-16B * Linear Technology OP16B op amp model (with calls for OP16F) * Written: 05-10-1990 19:02:39 Type: PFET input, internal comp. * Typical specs: * Vos=4.0E-04, Ib=4.0E-11, Ios=1.0E-11, GBP=7.6E+06Hz, Phase mar.= 45 deg, * SR(low)=1.8E+01V/us, SR(high)=3.6E+01V/us, Av=107.0dB, CMRR=100.0dB, * Vsat(+)=2.0V, Vsat(-)=2.0V, Isc=+/-25mA, Rout= 75ohms, Iq= 5mA. * (input cm clamp *optional*) * * Connections: * Non-Inverting Input * | Inverting Input * | | Positive Power Supply * | | | Negative Power Supply * | | | | Output * | | | | | .SUBCKT OP16B 3 2 7 4 6 * INPUT VCM2 40 4 2.0000E+00 RD1 40 80 6.9805E+02 RD2 40 90 6.9805E+02 J1 80 102 12 JM1 J2 90 103 12 JM2 CIN 2 3 4.0000E-12 RG1 2 102 2.0000E+00 RG2 3 103 2.0000E+00 ** CM CLAMP * DCM1 107 103 DM4 * DCM2 105 107 DM4 * VCMC 105 4 4.0E+00 * ECMP 106 4 103 4 1 * RCMP 107 106 1E+04 * DCM3 109 102 DM4 * DCM4 105 109 DM4 * ECMN 108 4 102 4 1 * RCMN 109 108 1E+04 ** END CM CLAMP C1 80 90 1.5000E-11 ISS 7 12 7.2000E-04 GOSIT 7 12 90 80 3.6000E-04 * INTERMEDIATE GCM 0 8 12 0 1.4326E-08 GA 8 0 80 90 1.4326E-03 R2 8 0 1.0000E+05 C2 1 8 3.0000E-11 GB 1 0 8 0 2.1118E+01 RO2 1 0 7.4000E+01 * OUTPUT RSO 1 6 1.0000E+00 ECL 18 0 1 6 2.1119E+01 GCL 0 8 20 0 1.0000E+00 RCL 20 0 1.0000E+03 D1 18 20 DM1 D2 20 18 DM1 * D3A 131 70 DM3 D3B 13 131 DM3 GPL 0 8 70 7 1.0000E+00 VC 13 6 3.1666E+00 RPLA 7 70 1.0000E+04 RPLB 7 131 1.0000E+05 D4A 60 141 DM3 D4B 141 14 DM3 GNL 0 8 60 4 1.0000E+00 VE 6 14 3.1666E+00 RNLA 60 4 1.0000E+04 RNLB 141 4 1.0000E+05 * IP 7 4 3.8800E-03 DSUB 4 7 DM2 * MODELS .MODEL JM1 PJF (IS=4.5000E-11 BETA=1.4252E-03 VTO=-1.000000E+00) .MODEL JM2 PJF (IS=3.5000E-11 BETA=1.4252E-03 VTO=-9.996000E-01) .MODEL DM1 D (IS=1.0000E-15) .MODEL DM2 D (IS=8.0000E-16 BV=5.2800E+01) .MODEL DM3 D (IS=1.0000E-16) .MODEL DM4 D (IS=1.0000E-09) .ENDS OP16B* OP-16G * Connections: * Non-Inverting Input * | Inverting Input * | | Positive Power Supply * | | | Negative Power Supply * | | | | Output * | | | | | .SUBCKT OP16G 3 2 7 4 6 X_OP16G 3 2 7 4 6 OP16C .ENDS OP16G * * OP-16C * Linear Technology OP16C op amp model (with calls for OP16G) * Written: 05-10-1990 18:57:16 Type: PFET input, internal comp. * Typical specs: * Vos=5.0E-04, Ib=8.0E-11, Ios=2.0E-11, GBP=7.2E+06Hz, Phase mar.= 45 deg, * SR(low)=1.6E+01V/us, SR(high)=3.2E+01V/us, Av=106.0dB, CMRR= 96.0dB, * Vsat(+)=2.0V, Vsat(-)=2.0V, Isc=+/-25mA, Rout= 75ohms, Iq= 5mA. * (input cm clamp *optional*) * * Connections: * Non-Inverting Input * | Inverting Input * | | Positive Power Supply * | | | Negative Power Supply * | | | | Output * | | | | | .SUBCKT OP16C 3 2 7 4 6 * INPUT VCM2 40 4 2.0000E+00 RD1 40 80 7.3683E+02 RD2 40 90 7.3683E+02 J1 80 102 12 JM1 J2 90 103 12 JM2 CIN 2 3 4.0000E-12 RG1 2 102 2.0000E+00 RG2 3 103 2.0000E+00 ** CM CLAMP * DCM1 107 103 DM4 * DCM2 105 107 DM4 * VCMC 105 4 4.0E+00 * ECMP 106 4 103 4 1 * RCMP 107 106 1E+04 * DCM3 109 102 DM4 * DCM4 105 109 DM4 * ECMN 108 4 102 4 1 * RCMN 109 108 1E+04 ** END CM CLAMP C1 80 90 1.5000E-11 ISS 7 12 6.4000E-04 GOSIT 7 12 90 80 3.2000E-04 * INTERMEDIATE GCM 0 8 12 0 2.1510E-08 GA 8 0 80 90 1.3572E-03 R2 8 0 1.0000E+05 C2 1 8 3.0000E-11 GB 1 0 8 0 1.9867E+01 RO2 1 0 7.4000E+01 * OUTPUT RSO 1 6 1.0000E+00 ECL 18 0 1 6 2.0994E+01 GCL 0 8 20 0 1.0000E+00 RCL 20 0 1.0000E+03 D1 18 20 DM1 D2 20 18 DM1 * D3A 131 70 DM3 D3B 13 131 DM3 GPL 0 8 70 7 1.0000E+00 VC 13 6 3.1633E+00 RPLA 7 70 1.0000E+04 RPLB 7 131 1.0000E+05 D4A 60 141 DM3 D4B 141 14 DM3 GNL 0 8 60 4 1.0000E+00 VE 6 14 3.1633E+00 RNLA 60 4 1.0000E+04 RNLB 141 4 1.0000E+05 * IP 7 4 4.1600E-03 DSUB 4 7 DM2 * MODELS .MODEL JM1 PJF (IS=9.0000E-11 BETA=1.4390E-03 VTO=-1.000000E+00) .MODEL JM2 PJF (IS=7.0000E-11 BETA=1.4390E-03 VTO=-9.995000E-01) .MODEL DM1 D (IS=1.0000E-15) .MODEL DM2 D (IS=8.0000E-16 BV=4.3200E+01) .MODEL DM3 D (IS=1.0000E-16) .MODEL DM4 D (IS=1.0000E-09) .ENDS OP16C* OP176G SPICE Macro-model 11/93, Rev. A * ARG / PMI * * This version of the OP-176 model simulates the worst-case * parameters of the 'G' grade. The worst-case parameters * used correspond to those in the data sheet. * * Copyright 1992 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License * Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | * | | | | | .SUBCKT OP176G 1 2 99 50 34 * * INPUT STAGE & POLE AT 100MHZ * R3 5 51 1.492 R4 6 51 1.492 CIN 1 2 3.7E-12 CM1 1 98 7.5E-12 CM2 2 98 7.5E-12 C2 5 6 320E-12 I1 97 4 100E-3 IOS 1 2 25E-9 EOS 9 3 POLY(1) (26,28) 1E-3 1 Q1 5 2 7 QX Q2 6 9 8 QX R5 7 4 0.975 R6 8 4 0.975 D1 2 36 DZ D2 1 36 DZ EN 3 1 10 0 1 GN1 0 2 13 0 1E-3 GN2 0 1 16 0 1E-3 * EREF 98 0 28 0 1 EP 97 0 99 0 1 EM 51 0 50 0 1 * * VOLTAGE NOISE SOURCE * DN1 35 10 DEN DN2 10 11 DEN VN1 35 0 DC 2 VN2 0 11 DC 2 * * CURRENT NOISE SOURCE * DN3 12 13 DIN DN4 13 14 DIN VN3 12 0 DC 2 VN4 0 14 DC 2 * * CURRENT NOISE SOURCE * DN5 15 16 DIN DN6 16 17 DIN VN5 15 0 DC 2 VN6 0 17 DC 2 * * GAIN STAGE & DOMINANT POLE AT 64HZ * R7 18 98 373.019E3 C3 18 98 6.667E-9 G1 98 18 5 6 670.206E-3 V2 97 19 1.82 V3 20 51 1.82 D3 18 19 DX D4 20 18 DX * * POLE/ZERO PAIR AT 1.5MHZ/2.7MHZ * R8 21 98 1E3 R9 21 22 1.25E3 C4 22 98 47.2E-12 G2 98 21 18 28 1E-3 * * POLE AT 100MHZ * R10 23 98 1 C5 23 98 1.59E-9 G3 98 23 21 28 1 * * POLE AT 100MHZ * R11 24 98 1 C6 24 98 1.59E-9 G4 98 24 23 28 1 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 20KHZ * R12 25 26 1E6 C7 25 26 3.183E-12 R13 26 98 1 E2 25 98 POLY(2) (1,98) (2,98) 0 50 50 * * POLE AT 100MHZ * R14 27 98 1 C8 27 98 1.59E-9 G5 98 27 24 28 1 * * OUTPUT STAGE * R15 28 99 28E3 R16 28 50 28E3 C9 28 50 1E-6 ISY 99 50 1.964E-3 R17 29 99 100 R18 29 50 100 L2 29 34 1E-9 G6 32 50 27 29 10E-3 G7 33 50 29 27 10E-3 G8 29 99 99 27 10E-3 G9 50 29 27 50 10E-3 V4 30 29 0.475 V5 29 31 0.475 F1 29 0 V4 1 F2 0 29 V5 1 D5 27 30 DX D6 31 27 DX D7 99 32 DX D8 99 33 DX D9 50 32 DY D10 50 33 DY * * MODELS USED * .MODEL QX PNP(BF=142.857E3) .MODEL DX D(IS=1E-12) .MODEL DY D(IS=1E-15 BV=50) .MODEL DZ D(IS=1E-15 BV=7.0) .MODEL DEN D(IS=1E-12 RS=4.35K KF=1.95E-15 AF=1) .MODEL DIN D(IS=1E-12 RS=268 KF=1.08E-15 AF=1) .ENDS * OP177A SPICE Macro-model 12/90, Rev. B * JCB / PMI * * Revision History: * REV. B * Re-ordered subcircuit call out nodes to put the * output node last. * Changed Ios from 1E-9 to 0.5E-9 * Added F1 and F2 to fix short circuit current limit. * * * This version of the OP-177 model simulates the worst case * parameters of the 'A' grade. The worst case parameters * used correspond to those in the data book. * * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP177A 1 2 99 50 39 * * INPUT STAGE & POLE AT 6 MHZ * R1 2 3 5E11 R2 1 3 5E11 R3 5 97 0.0606 R4 6 97 0.0606 CIN 1 2 4E-12 C2 5 6 218.9E-9 I1 4 51 1 IOS 1 2 0.5E-9 EOS 9 10 POLY(1) 30 33 10E-6 1 Q1 5 2 7 QX Q2 6 9 8 QX R5 7 4 0.009 R6 8 4 0.009 D1 2 1 DX D2 1 2 DX EN 10 1 12 0 1 GN1 0 2 15 0 1 GN2 0 1 18 0 1 * EREF 98 0 33 0 1 EPLUS 97 0 99 0 1 ENEG 51 0 50 0 1 * * VOLTAGE NOISE SOURCE WITH FLICKER NOISE * DN1 11 12 DEN DN2 12 13 DEN VN1 11 0 DC 2 VN2 0 13 DC 2 * * CURRENT NOISE SOURCE WITH FLICKER NOISE * DN3 14 15 DIN DN4 15 16 DIN VN3 14 0 DC 2 VN4 0 16 DC 2 * * SECOND CURRENT NOISE SOURCE * DN5 17 18 DIN DN6 18 19 DIN VN5 17 0 DC 2 VN6 0 19 DC 2 * * FIRST GAIN STAGE * R7 20 98 1 G1 98 20 5 6 119.8 D3 20 21 DX D4 22 20 DX E1 97 21 POLY(1) 97 33 -2.4 1 E2 22 51 POLY(1) 33 51 -2.4 1 * * GAIN STAGE & DOMINANT POLE AT 0.127 HZ * R8 23 98 1.253E9 C3 23 98 1E-9 G2 98 23 20 33 33.3E-6 V1 97 24 1.8 V2 25 51 1.8 D5 23 24 DX D6 25 23 DX * * NEGATIVE ZERO AT -4MHZ * R9 26 27 1 C4 26 27 -39.75E-9 R10 27 98 1E-6 E3 26 98 23 33 1E6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 63 HZ * R13 30 31 1 L2 31 98 2.52E-3 G4 98 30 3 33 0.316E-6 D7 30 97 DX D8 51 30 DX * * POLE AT 2 MHZ * R14 32 98 1 C5 32 98 79.5E-9 G5 98 32 27 33 1 * * OUTPUT STAGE * R15 33 97 1 R16 33 51 1 GSY 99 50 POLY(1) 99 50 0.725E-3 0.0425E-3 F1 34 0 V3 1 F2 0 34 V4 1 R17 34 99 400 R18 34 50 400 L3 34 39 2E-7 G6 37 50 32 34 2.5E-3 G7 38 50 34 32 2.5E-3 G8 34 99 99 32 2.5E-3 G9 50 34 32 50 2.5E-3 V3 35 34 6.8 V4 34 36 4.4 D9 32 35 DX D10 36 32 DX D11 99 37 DX D12 99 38 DX D13 50 37 DY D14 50 38 DY * * MODELS USED * .MODEL QX NPN(BF=333.3E6) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .MODEL DEN D(IS=1E-12, RS=14.61K, KF=2E-17, AF=1) .MODEL DIN D(IS=1E-12, RS=7.55E-6, KF=3E-15, AF=1) .ENDS * OP177B SPICE Macro-model 12/90, Rev. B * JCB / PMI * * Revision History: * REV. B * Re-ordered subcircuit call out nodes to put the * output node last. * Changed Ios from 1.5E-9 to 0.75E-9 * Added F1 and F2 to fix short circuit current limit. * * * This version of the OP-177 model simulates the worst case * parameters of the 'B' grade. The worst case parameters * used correspond to those in the data book. * * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP177B 1 2 99 50 39 * * INPUT STAGE & POLE AT 6 MHZ * R1 2 3 5E11 R2 1 3 5E11 R3 5 97 0.0606 R4 6 97 0.0606 CIN 1 2 4E-12 C2 5 6 218.9E-9 I1 4 51 1 IOS 1 2 0.75E-9 EOS 9 10 POLY(1) 30 33 25E-6 1 Q1 5 2 7 QX Q2 6 9 8 QX R5 7 4 0.009 R6 8 4 0.009 D1 2 1 DX D2 1 2 DX EN 10 1 12 0 1 GN1 0 2 15 0 1 GN2 0 1 18 0 1 * EREF 98 0 33 0 1 EPLUS 97 0 99 0 1 ENEG 51 0 50 0 1 * * VOLTAGE NOISE SOURCE WITH FLICKER NOISE * DN1 11 12 DEN DN2 12 13 DEN VN1 11 0 DC 2 VN2 0 13 DC 2 * * CURRENT NOISE SOURCE WITH FLICKER NOISE * DN3 14 15 DIN DN4 15 16 DIN VN3 14 0 DC 2 VN4 0 16 DC 2 * * SECOND CURRENT NOISE SOURCE * DN5 17 18 DIN DN6 18 19 DIN VN5 17 0 DC 2 VN6 0 19 DC 2 * * FIRST GAIN STAGE * R7 20 98 1 G1 98 20 5 6 119.8 D3 20 21 DX D4 22 20 DX E1 97 21 POLY(1) 97 33 -2.4 1 E2 22 51 POLY(1) 33 51 -2.4 1 * * GAIN STAGE & DOMINANT POLE AT 0.127 HZ * R8 23 98 1.253E9 C3 23 98 1E-9 G2 98 23 20 33 33.3E-6 V1 97 24 1.8 V2 25 51 1.8 D5 23 24 DX D6 25 23 DX * * NEGATIVE ZERO AT -4MHZ * R9 26 27 1 C4 26 27 -39.75E-9 R10 27 98 1E-6 E3 26 98 23 33 1E6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 63 HZ * R13 30 31 1 L2 31 98 2.52E-3 G4 98 30 3 33 0.316E-6 D7 30 97 DX D8 51 30 DX * * POLE AT 2 MHZ * R14 32 98 1 C5 32 98 79.5E-9 G5 98 32 27 33 1 * * OUTPUT STAGE * R15 33 97 1 R16 33 51 1 GSY 99 50 POLY(1) 99 50 0.725E-3 0.0425E-3 F1 34 0 V3 1 F2 0 34 V4 1 R17 34 99 400 R18 34 50 400 L3 34 39 2E-7 G6 37 50 32 34 2.5E-3 G7 38 50 34 32 2.5E-3 G8 34 99 99 32 2.5E-3 G9 50 34 32 50 2.5E-3 V3 35 34 6.8 V4 34 36 4.4 D9 32 35 DX D10 36 32 DX D11 99 37 DX D12 99 38 DX D13 50 37 DY D14 50 38 DY * * MODELS USED * .MODEL QX NPN(BF=250E6) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .MODEL DEN D(IS=1E-12, RS=14.61K, KF=2E-17, AF=1) .MODEL DIN D(IS=1E-12, RS=7.55E-6, KF=3E-15, AF=1) .ENDS * OP-177E SPICE Macro-model 12/90, Rev. B * JCB / PMI * * Revision History: * REV. B * Re-ordered subcircuit call out nodes to put the * output node last. * Changed Ios from 1.0E-9 to 0.5E-9 * Added F1 and F2 to fix short circuit current limit. * * * This version of the OP-177 model simulates the worst case * parameters of the 'E' grade. The worst case parameters * used correspond to those in the data book. * * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP177E 1 2 99 50 39 * * INPUT STAGE & POLE AT 6 MHZ * R1 2 3 5E11 R2 1 3 5E11 R3 5 97 0.0606 R4 6 97 0.0606 CIN 1 2 4E-12 C2 5 6 218.9E-9 I1 4 51 1 IOS 1 2 0.5E-9 EOS 9 10 POLY(1) 30 33 10E-6 1 Q1 5 2 7 QX Q2 6 9 8 QX R5 7 4 0.009 R6 8 4 0.009 D1 2 1 DX D2 1 2 DX EN 10 1 12 0 1 GN1 0 2 15 0 1 GN2 0 1 18 0 1 * EREF 98 0 33 0 1 EPLUS 97 0 99 0 1 ENEG 51 0 50 0 1 * * VOLTAGE NOISE SOURCE WITH FLICKER NOISE * DN1 11 12 DEN DN2 12 13 DEN VN1 11 0 DC 2 VN2 0 13 DC 2 * * CURRENT NOISE SOURCE WITH FLICKER NOISE * DN3 14 15 DIN DN4 15 16 DIN VN3 14 0 DC 2 VN4 0 16 DC 2 * * SECOND CURRENT NOISE SOURCE * DN5 17 18 DIN DN6 18 19 DIN VN5 17 0 DC 2 VN6 0 19 DC 2 * * FIRST GAIN STAGE * R7 20 98 1 G1 98 20 5 6 119.8 D3 20 21 DX D4 22 20 DX E1 97 21 POLY(1) 97 33 -2.4 1 E2 22 51 POLY(1) 33 51 -2.4 1 * * GAIN STAGE & DOMINANT POLE AT 0.127 HZ * R8 23 98 1.253E9 C3 23 98 1E-9 G2 98 23 20 33 33.3E-6 V1 97 24 1.8 V2 25 51 1.8 D5 23 24 DX D6 25 23 DX * * NEGATIVE ZERO AT -4MHZ * R9 26 27 1 C4 26 27 -39.75E-9 R10 27 98 1E-6 E3 26 98 23 33 1E6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 63 HZ * R13 30 31 1 L2 31 98 2.52E-3 G4 98 30 3 33 0.316E-6 D7 30 97 DX D8 51 30 DX * * POLE AT 2 MHZ * R14 32 98 1 C5 32 98 79.5E-9 G5 98 32 27 33 1 * * OUTPUT STAGE * R15 33 97 1 R16 33 51 1 GSY 99 50 POLY(1) 99 50 0.725E-3 0.0425E-3 F1 34 0 V3 1 F2 0 34 V4 1 R17 34 99 400 R18 34 50 400 L3 34 39 2E-7 G6 37 50 32 34 2.5E-3 G7 38 50 34 32 2.5E-3 G8 34 99 99 32 2.5E-3 G9 50 34 32 50 2.5E-3 V3 35 34 6.8 V4 34 36 4.4 D9 32 35 DX D10 36 32 DX D11 99 37 DX D12 99 38 DX D13 50 37 DY D14 50 38 DY * * MODELS USED * .MODEL QX NPN(BF=333.3E6) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .MODEL DEN D(IS=1E-12, RS=14.61K, KF=2E-17, AF=1) .MODEL DIN D(IS=1E-12, RS=7.55E-6, KF=3E-15, AF=1) .ENDS * OP177F SPICE Macro-model 12/90, Rev. B * JCB / PMI * * Revision History: * REV. B * Re-ordered subcircuit call out nodes to put the * output node last. * Changed Ios from 1.5E-9 to 0.75E-9 * Added F1 and F2 to fix short circuit current limit. * * * This version of the OP-177 model simulates the worst case * parameters of the 'F' grade. The worst case parameters * used correspond to those in the data book. * * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP177F 1 2 99 50 39 * * INPUT STAGE & POLE AT 6 MHZ * R1 2 3 5E11 R2 1 3 5E11 R3 5 97 0.0606 R4 6 97 0.0606 CIN 1 2 4E-12 C2 5 6 218.9E-9 I1 4 51 1 IOS 1 2 0.75E-9 EOS 9 10 POLY(1) 30 33 25E-6 1 Q1 5 2 7 QX Q2 6 9 8 QX R5 7 4 0.009 R6 8 4 0.009 D1 2 1 DX D2 1 2 DX EN 10 1 12 0 1 GN1 0 2 15 0 1 GN2 0 1 18 0 1 * EREF 98 0 33 0 1 EPLUS 97 0 99 0 1 ENEG 51 0 50 0 1 * * VOLTAGE NOISE SOURCE WITH FLICKER NOISE * DN1 11 12 DEN DN2 12 13 DEN VN1 11 0 DC 2 VN2 0 13 DC 2 * * CURRENT NOISE SOURCE WITH FLICKER NOISE * DN3 14 15 DIN DN4 15 16 DIN VN3 14 0 DC 2 VN4 0 16 DC 2 * * SECOND CURRENT NOISE SOURCE * DN5 17 18 DIN DN6 18 19 DIN VN5 17 0 DC 2 VN6 0 19 DC 2 * * FIRST GAIN STAGE * R7 20 98 1 G1 98 20 5 6 119.8 D3 20 21 DX D4 22 20 DX E1 97 21 POLY(1) 97 33 -2.4 1 E2 22 51 POLY(1) 33 51 -2.4 1 * * GAIN STAGE & DOMINANT POLE AT 0.127 HZ * R8 23 98 1.253E9 C3 23 98 1E-9 G2 98 23 20 33 33.3E-6 V1 97 24 1.8 V2 25 51 1.8 D5 23 24 DX D6 25 23 DX * * NEGATIVE ZERO AT -4MHZ * R9 26 27 1 C4 26 27 -39.75E-9 R10 27 98 1E-6 E3 26 98 23 33 1E6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 63 HZ * R13 30 31 1 L2 31 98 2.52E-3 G4 98 30 3 33 0.316E-6 D7 30 97 DX D8 51 30 DX * * POLE AT 2 MHZ * R14 32 98 1 C5 32 98 79.5E-9 G5 98 32 27 33 1 * * OUTPUT STAGE * R15 33 97 1 R16 33 51 1 GSY 99 50 POLY(1) 99 50 0.725E-3 0.0425E-3 F1 34 0 V3 1 F2 0 34 V4 1 R17 34 99 400 R18 34 50 400 L3 34 39 2E-7 G6 37 50 32 34 2.5E-3 G7 38 50 34 32 2.5E-3 G8 34 99 99 32 2.5E-3 G9 50 34 32 50 2.5E-3 V3 35 34 6.8 V4 34 36 4.4 D9 32 35 DX D10 36 32 DX D11 99 37 DX D12 99 38 DX D13 50 37 DY D14 50 38 DY * * MODELS USED * .MODEL QX NPN(BF=250E6) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .MODEL DEN D(IS=1E-12, RS=14.61K, KF=2E-17, AF=1) .MODEL DIN D(IS=1E-12, RS=7.55E-6, KF=3E-15, AF=1) .ENDS * OP177G SPICE Macro-model 12/90, Rev. B * JCB / PMI * * Revision History: * REV. B * Re-ordered subcircuit call out nodes to put the * output node last. * Changed Ios from 2.8E-9 to 1.4E-9 * Added F1 and F2 to fix short circuit current limit. * * * This version of the OP-177 model simulates the worst case * parameters of the 'G' grade. The worst case parameters * used correspond to those in the data book. * * Copyright 1990 by Precision Monolithics, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP177G 1 2 99 50 39 * * INPUT STAGE & POLE AT 6 MHZ * R1 2 3 5E11 R2 1 3 5E11 R3 5 97 0.0606 R4 6 97 0.0606 CIN 1 2 4E-12 C2 5 6 218.9E-9 I1 4 51 1 IOS 1 2 1.4E-9 EOS 9 10 POLY(1) 30 33 60E-6 1 Q1 5 2 7 QX Q2 6 9 8 QX R5 7 4 0.009 R6 8 4 0.009 D1 2 1 DX D2 1 2 DX EN 10 1 12 0 1 GN1 0 2 15 0 1 GN2 0 1 18 0 1 * EREF 98 0 33 0 1 EPLUS 97 0 99 0 1 ENEG 51 0 50 0 1 * * VOLTAGE NOISE SOURCE WITH FLICKER NOISE * DN1 11 12 DEN DN2 12 13 DEN VN1 11 0 DC 2 VN2 0 13 DC 2 * * CURRENT NOISE SOURCE WITH FLICKER NOISE * DN3 14 15 DIN DN4 15 16 DIN VN3 14 0 DC 2 VN4 0 16 DC 2 * * SECOND CURRENT NOISE SOURCE * DN5 17 18 DIN DN6 18 19 DIN VN5 17 0 DC 2 VN6 0 19 DC 2 * * FIRST GAIN STAGE * R7 20 98 1 G1 98 20 5 6 119.9 D3 20 21 DX D4 22 20 DX E1 97 21 POLY(1) 97 33 -2.4 1 E2 22 51 POLY(1) 33 51 -2.4 1 * * GAIN STAGE & DOMINANT POLE AT 0.318 HZ * R8 23 98 501E6 C3 23 98 1E-9 G2 98 23 20 33 33.3E-6 V1 97 24 1.8 V2 25 51 1.8 D5 23 24 DX D6 25 23 DX * * NEGATIVE ZERO AT -4MHZ * R9 26 27 1 C4 26 27 -39.75E-9 R10 27 98 1E-6 E3 26 98 23 33 1E6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 355 HZ * R13 30 31 1 L2 31 98 0.448E-3 G4 98 30 3 33 1.778E-6 D7 30 97 DX D8 51 30 DX * * POLE AT 2 MHZ * R14 32 98 1 C5 32 98 79.5E-9 G5 98 32 27 33 1 * * OUTPUT STAGE * R15 33 97 1 R16 33 51 1 GSY 99 50 POLY(1) 99 50 0.725E-3 0.0425E-3 F1 34 0 V3 1 F2 0 34 V4 1 R17 34 99 400 R18 34 50 400 L3 34 39 2E-7 G6 37 50 32 34 2.5E-3 G7 38 50 34 32 2.5E-3 G8 34 99 99 32 2.5E-3 G9 50 34 32 50 2.5E-3 V3 35 34 6.8 V4 34 36 4.4 D9 32 35 DX D10 36 32 DX D11 99 37 DX D12 99 38 DX D13 50 37 DY D14 50 38 DY * * MODELS USED * .MODEL QX NPN(BF=178.6E6) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .MODEL DEN D(IS=1E-12, RS=14.61K, KF=2E-17, AF=1) .MODEL DIN D(IS=1E-12, RS=7.55E-6, KF=3E-15, AF=1) .ENDS * OP181 SPICE Macro-model * 9/96, Ver. 1 * Troy Murphy / ADSC * * Copyright 1996 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of this * model indicates your acceptance of the terms and provisions in * the License Statement. * * Node Assignments * noninverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | * | | | | | .SUBCKT OP181 1 2 99 50 45 * * INPUT STAGE * Q1 4 1 3 PIX Q2 6 7 5 PIX I1 99 8 1.28E-6 EOS 7 2 POLY(1) (12,98) 80E-6 1 IOS 1 2 1E-10 RC1 4 50 500E3 RC2 6 50 500E3 RE1 3 8 108 RE2 5 8 108 V1 99 13 DC .9 V2 99 14 DC .9 D1 3 13 DX D2 5 14 DX * * CMRR 76dB, ZERO AT 1kHz * ECM1 11 98 POLY(2) (1,98) (2,98) 0 .5 .5 R1 11 12 1.59E6 C1 11 12 100E-12 R2 12 98 283 * * POLE AT 900kHz * EREF 98 0 90 0 1 G1 98 20 4 6 1E-6 R3 20 98 1E6 C2 20 98 177E-15 * * POLE AT 500kHz * E2 21 98 20 98 1 R4 21 22 1E6 C3 22 98 320E-15 * * GAIN STAGE * CF 45 40 8.5E-12 R5 40 98 65.65E6 G3 98 40 22 98 4.08E-7 D3 40 41 DX D4 42 40 DX V3 99 41 DC 0.5 V4 42 50 DC 0.5 * * OUTPUT STAGE * ISY 99 50 1.375E-6 RS1 99 90 10E6 RS2 90 50 10E6 M1 45 46 99 99 POX L=1.5u W=300u M2 45 47 50 50 NOX L=1.5u W=300u EG1 99 46 POLY(1) (98,40) 0.77 1 EG2 47 50 POLY(1) (40,98) 0.77 1 * * MODELS * .MODEL POX PMOS (LEVEL=2, KP=25E-6, VTO=-0.75, LAMBDA=0.01) .MODEL NOX NMOS (LEVEL=2, KP=25E-6, VTO=0.75, LAMBDA=0.01) .MODEL PIX PNP (BF=200) .MODEL DX D(IS=1E-14) .ENDS OP181 * OP183G SPICE Macro-model Rev. A, 3/94 * ARG / PMI * * This version of the OP183 model simulates the worst-case * parameters of the 'G' grade. The worst-case parameters * used correspond to those in the data sheet. * * Copyright 1993 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of * this model indicates your acceptance of the terms and pro- * visions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP183G 2 1 99 50 45 * * INPUT STAGE AND POLE AT 600KHZ * I1 99 8 1E-4 Q1 4 1 6 QP Q2 5 3 7 QP CIN 1 2 1.5PF R1 50 4 796 R2 50 5 796 C1 4 5 167E-12 R3 6 8 279 R4 7 8 279 IOS 1 2 25E-9 EOS 3 2 POLY(1) (15,98) 1E-3 1 DC1 2 36 DZ DC2 1 36 DZ * * GAIN STAGE AND DOMINANT POLE AT 100HZ * EREF 98 0 POLY(2) (99,0) (50,0) 0 0.5 0.5 G1 98 9 4 5 1.257E-3 R5 9 98 79.577E6 C2 9 98 20E-12 D1 9 10 DX D2 11 9 DX E1 10 98 POLY(1) 99 98 -1.6185 1.0623 V2 50 11 -0.666 * * COMMON MODE STAGE WITH ZERO AT 17.7KHZ * ECM 14 98 POLY(2) (1,98) (2,98) 0 158 158 R7 14 15 1E6 C4 14 15 9E-12 R8 15 98 1 * * POLE AT 20MHZ * GP2 98 31 9 98 1E-6 RP2 31 98 1E6 CP2 31 98 7.96E-15 * * ZERO AT 1.5MHZ * EZ1 32 98 31 98 1E6 RZ1 32 33 1E6 RZ2 33 98 1 CZ1 32 33 106E-15 * * POLE AT 10MHZ * GP10 98 40 33 98 1E-6 RP10 40 98 1E6 CP10 40 98 15.9E-15 * * OUTPUT STAGE * RO1 99 45 140 RO2 45 50 140 G7 45 99 99 40 7.143E-3 G8 50 45 40 50 7.143E-3 G9 98 60 45 40 7.143E-3 D7 60 61 DX D8 62 60 DX V7 61 98 DC 0 V8 98 62 DC 0 GSY 99 50 99 50 5E-6 FSY 99 50 POLY(2) V7 V8 1.375E-3 1 1 D9 40 41 DX D10 42 40 DX V5 41 45 1.2 V6 45 42 1.5 * * MODELS USED * .MODEL DX D .MODEL DZ D(IS=1E-15 BV=7.0) .MODEL QP PNP(BF=82.333) .ENDS * OP184 SPICE Macro-model 11/95 / Rev. B * ARG / ADSC * * Revision History: * * Rev. B * Changed input transistor betas to conform to final data sheet * Ios typical spec of 60nA. * * * Copyright 1993 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance of the terms and provisions in the License * Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP184 1 2 99 50 45 * * INPUT STAGE * Q1 5 2 3 QIN 1 Q2 6 11 3 QIN 1 Q3 7 2 4 QIP 1 Q4 8 11 4 QIP 1 DC1 2 11 DC DC2 11 2 DC Q5 4 9 99 QIP 1 Q6 9 9 99 QIP 1 Q7 3 10 50 QIN 1 Q8 10 10 50 QIN 1 R1 99 5 4E3 R2 99 6 4E3 R3 7 50 4E3 R4 8 50 4E3 IREF 9 10 50.5E-6 EOS 1 11 POLY(2) (22,98) (14,98) -25E-6 1E-2 1 IOS 2 1 5E-9 CIN 1 2 2E-12 GN1 98 1 17 98 1E-3 GN2 98 2 23 98 1E-3 * * VOLTAGE NOISE SOURCE WITH FLICKER NOISE * VN1 13 98 DC 2 VN2 98 15 DC 2 DN1 13 14 DEN DN2 14 15 DEN * * CURRENT NOISE SOURCE WITH FLICKER NOISE * VN3 16 98 DC 2 VN4 98 18 DC 2 DN3 16 17 DIN DN4 17 18 DIN * * 2ND CURRENT NOISE SOURCE WITH FLICKER NOISE * VN5 19 98 DC 2 VN6 98 24 DC 2 DN5 19 23 DIN DN6 23 24 DIN * * GAIN STAGE * EREF 98 0 POLY(2) (99,0) (50,0) 0 0.5 0.5 G1 98 20 POLY(2) (6,5) (8,7) 0 0.5E-3 0.5E-3 R9 20 98 1E3 * * COMMON MODE STAGE WITH ZERO AT 100HZ * ECM 98 21 POLY(2) (1,98) (2,98) 0 0.5 0.5 R10 21 22 1 R11 22 98 100E-6 C4 21 22 1.592E-3 * * NEGATIVE ZERO AT 20MHZ * E1 27 98 20 98 1E6 R17 27 28 1 R18 28 98 1E-6 C8 25 26 7.958E-9 ENZ 25 98 27 28 1 VNZ 26 98 DC 0 FNZ 27 28 VNZ -1 * * POLE AT 40MHZ * G4 98 29 28 98 1 R19 29 98 1 C9 29 98 3.979E-9 * * POLE AT 40MHZ * G5 98 30 29 98 1 R20 30 98 1 C10 30 98 3.979E-9 * * OUTUT STAGE * ISY 99 50 0.276E-3 GIN 50 31 POLY(1) (30,98) .862574E-6 505.879E-6 RIN 31 50 2.75E6 VB 99 32 0.7 Q11 32 31 33 QON 1 R21 33 34 4.5E3 I1 34 50 50E-6 R22 99 35 6E3 Q12 36 36 35 QOP 1 I2 36 50 50E-6 R23 99 37 2.6E3 R24 34 38 5E3 Q13 39 36 37 QOP 1 Q14 39 38 40 QON 1.5 R25 40 50 40 Q15 39 39 41 QON 1 R26 41 42 1E3 R27 99 43 220 Q16 44 44 43 QOP 1.5 Q17 44 39 42 QON 1 R28 42 50 2E3 VSCP 99 97 DC 0 FSCP 46 99 VSCP 1 RSCP 46 99 40 Q20 44 46 99 QOP 1 Q18 45 44 97 QOP 4.5 Q19 45 34 51 QON 4.5 VSCN 51 50 DC 0 FSCN 50 47 VSCN 1 RSCN 47 50 40 Q21 34 47 50 QON 1 CC2 31 45 20E-12 CF1 31 34 15E-12 CF2 31 42 15E-12 CO1 34 45 15E-12 CO2 42 45 5E-12 D3 45 99 DX D4 50 45 DX .MODEL DC D(IS=130E-21) .MODEL DX D() .MODEL DEN D(RS=100 KF=12E-15 AF=1) .MODEL DIN D(RS=5.358 KF=56E-15 AF=1) .MODEL QIN NPN(BF=120 VA=200 IS=0.5E-16) .MODEL QIP PNP(BF=90 VA=60 IS=0.5E-16) .MODEL QON NPN(BF=200 VA=200 IS=0.5E-16 RC=50) .MODEL QOP PNP(BF=200 VA=200 IS=0.5E-16 RC=160) .ENDS OP184* OP191G SPICE Macro-model Rev. A, 12/94 * ARG / PMI * * This version of the OP191 model simulates the worst-case * parameters of the 'G' grade. The worst-case parameters * used correspond to those in the data sheet. * * Copyright 1994 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of * this model indicates your acceptance of the terms and pro- * visions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP191G 1 2 99 50 45 * * INPUT STAGE * I1 99 7 8.1E-6 Q1 6 4 7 QP Q2 5 3 7 QP D1 3 99 DX D2 4 99 DX D3 3 4 DX D4 4 3 DX R1 3 8 5E3 R2 4 2 5E3 R3 5 50 6.4654E3 R4 6 50 6.4654E3 EOS 8 1 POLY(1) (16,39) -0.5E-3 1.778 IOS 3 4 4E-9 GB1 3 98 21 98 83.333E-9 GB2 4 98 21 98 83.333E-9 CIN 1 2 1E-12 * * 1ST GAIN STAGE * EREF 98 0 39 0 1 G1 98 9 6 5 31.416E-6 R7 9 98 1E6 EC1 99 10 POLY(1) (99,39) -0.52 1 EC2 11 50 POLY(1) (39,50) -0.52 1 D5 9 10 DX D6 11 9 DX * * 2ND GAIN STAGE AND DOMINANT POLE AT 100HZ * G2 98 12 9 39 8E-6 R8 12 98 99.472E6 C2 12 98 16E-12 D7 12 13 DX D8 14 12 DX V1 99 13 0.58 V2 14 50 0.58 * * COMMON MODE STAGE * ECM 15 98 POLY(2) (1,39) (2,39) 0 0.5 0.5 R9 15 16 1E6 R10 16 98 100 * * POLE AT 2.5MHZ * G3 98 18 12 39 1E-6 R11 18 98 1E6 C4 18 98 63.662E-15 * * BIAS CURRENT-VS-COMMON MODE VOLTAGE * EP 97 0 99 0 1 VB 99 17 1.3 RB 17 50 1E9 E3 19 0 15 17 16 D13 19 20 DX R12 20 0 1E6 G4 98 21 20 0 1E-3 R13 21 98 5E3 D14 21 22 DY E4 97 22 (POLY(1) (99,98) -0.765 1 * * POLE AT 100MHZ * G6 98 40 18 39 1E-6 R20 40 98 1E6 C10 40 98 1.592E-15 * * OUTPUT STAGE * RS1 99 39 109.375E3 RS2 39 50 109.375E3 RO1 99 45 41.667 RO2 45 50 41.667 G7 45 99 99 40 24E-3 G8 50 45 40 50 24E-3 G9 98 60 45 40 24E-3 D9 60 61 DX D10 62 60 DX V7 61 98 DC 0 V8 98 62 DC 0 FSY 99 50 POLY(2) V7 V8 0.367E-3 1 1 D11 41 45 DZ D12 45 42 DZ V5 40 41 0.131 V6 42 40 0.131 .MODEL DX D() .MODEL DY D(IS=1E-9) .MODEL DZ D(IS=1E-6) .MODEL QP PNP(BF=80) .ENDS * OP193E SPICE Macro-model 1/95, Rev. A * ARG / ADI * * This version of the OP193 model simulates the worst-case * parameters of the 'E' grade. The worst-case parameters * used correspond to those in the data sheet. * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License * Statement. This model has been optimized for a total supply voltage of * 5V. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP193E 51 52 99 50 32 * * INPUT STAGE & POLE AT 16KHZ * R3 5 50 53.827E3 R4 6 50 53.827E3 R5 4 7 2.104E3 R6 4 8 2.104E3 CIN 1 2 4E-12 C2 5 6 92.4E-12 I1 99 4 1.03E-6 IOS 1 2 1E-9 EOS 9 1 POLY(2) (24,27) (102,0) 75E-6 0.1 1 Q1 5 2 7 QX Q2 6 9 8 QX EREF 98 0 POLY(2) (99,0) (50,0) 0 0.5 0.5 R24 1 51 2E3 R25 2 52 2E3 VN1 101 0 DC 2 VN2 0 103 DC 2 DN1 101 102 DEN DN2 102 103 DEN * * GAIN STAGE & DOMINANT POLE AT 0.473 HZ * R7 10 98 4.037E9 G1 98 10 5 6 18.578E-6 C3 10 98 83.333E-12 V1 99 11 0.65 D1 10 11 DX D2 50 10 DX * * NEGATIVE ZERO AT 50KHZ * R9 13 14 1E6 R10 14 98 1 FNZ 13 14 VNZ -1 E2 13 98 10 27 1 CNZ 15 16 3.183E-12 ENZ 15 98 13 14 1 VNZ 16 98 DC 0 * * ZERO-POLE PAIR AT 28KHZ / 84KHZ * R18 17 18 2E6 C4 17 18 2.842E-12 R19 18 98 1E6 E3 17 98 14 27 3E6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 3.16HZ * R1 23 24 1E6 R2 24 98 100 C5 23 24 50.33E-9 E4 23 98 POLY(2) (1,27) (2,27) 0 0.5 0.5 * * ZERO-POLE PAIR AT 40KHZ / 160KHZ * R20 25 26 3E6 C6 25 26 1.326E-12 R21 26 98 1E6 E5 25 98 18 27 4 * * OUTPUT STAGE * ISY 99 50 20.137E-6 R16 27 99 4.5E6 R17 27 50 4.5E6 EIN 28 98 POLY(1) (26,27) 0.51905 1 RIN 28 31 15E3 Q11 45 31 32 QN 6 Q12 32 33 44 QN 6 Q13 41 34 33 QN 1 Q14 34 35 36 QP 1 Q15 36 38 39 QN 8 Q16 35 35 37 QP 1 Q17 99 99 37 QN 1 Q18 99 99 36 QN 1 Q19 50 42 34 QP 1 Q20 42 42 34 QP 1 Q21 32 33 42 QN 1 Q22 99 40 41 QN 1 Q23 43 43 50 QN 1 Q24 34 43 50 QN 2 Q25 33 43 50 QN 2 Q26 34 44 50 QC 1 Q27 31 46 50 QC 1 EC 47 50 99 45 0.96 RC 46 47 1E3 IREF 99 43 4.5E-7 I13 35 50 4.5E-7 R11 99 40 75E3 R12 99 36 40E3 R13 31 38 20E3 R14 32 39 5E3 R15 40 37 75E3 R22 44 50 30 R23 99 45 50 * * MODELS USED * .MODEL QN NPN(BF=200 IS=1E-16 VA=150) .MODEL QP PNP(BF=100 IS=5E-17 VA=50) .MODEL QX PNP(BF=33.333 KF=2E-17) .MODEL QC NPN(BF=200 IS=2.22E-11) .MODEL DX D(IS=1E-15) .MODEL DEN D(RS=2.45E3 KF=33E-15) .ENDS * OP193F SPICE Macro-model 1/95, Rev. A * ARG / ADI * * This version of the OP193 model simulates the worst-case * parameters of the 'F' grade. The worst-case parameters * used correspond to those in the data sheet. * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License * Statement. This model has been optimized for a total supply voltage of * 5V. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP193F 51 52 99 50 32 * * INPUT STAGE & POLE AT 16KHZ * R3 5 50 53.827E3 R4 6 50 53.827E3 R5 4 7 2.104E3 R6 4 8 2.104E3 CIN 1 2 4E-12 C2 5 6 92.4E-12 I1 99 4 1.04E-6 IOS 1 2 2E-9 EOS 9 1 POLY(2) (24,27) (102,0) 150E-6 0.1585 1 Q1 5 2 7 QX Q2 6 9 8 QX EREF 98 0 POLY(2) (99,0) (50,0) 0 0.5 0.5 R24 1 51 2E3 R25 2 52 2E3 VN1 101 0 DC 2 VN2 0 103 DC 2 DN1 101 102 DEN DN2 102 103 DEN * * GAIN STAGE & DOMINANT POLE AT 0.473 HZ * R7 10 98 4.037E9 G1 98 10 5 6 18.578E-6 C3 10 98 83.333E-12 V1 99 11 0.9 D1 10 11 DX D2 50 10 DX * * NEGATIVE ZERO AT 50KHZ * R9 13 14 1E6 R10 14 98 1 FNZ 13 14 VNZ -1 E2 13 98 10 27 1 CNZ 15 16 3.183E-12 ENZ 15 98 13 14 1 VNZ 16 98 DC 0 * * ZERO-POLE PAIR AT 28KHZ / 84KHZ * R18 17 18 2E6 C4 17 18 2.842E-12 R19 18 98 1E6 E3 17 98 14 27 3E6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 5HZ * R1 23 24 1E6 R2 24 98 100 C5 23 24 32E-9 E4 23 98 POLY(2) (1,27) (2,27) 0 0.5 0.5 * * ZERO-POLE PAIR AT 40KHZ / 160KHZ * R20 25 26 3E6 C6 25 26 1.326E-12 R21 26 98 1E6 E5 25 98 18 27 4 * * OUTPUT STAGE * ISY 99 50 20.137E-6 R16 27 99 4.5E6 R17 27 50 4.5E6 EIN 28 98 POLY(1) (26,27) 0.51905 1 RIN 28 31 15E3 Q11 45 31 32 QN 6 Q12 32 33 44 QN 6 Q13 41 34 33 QN 1 Q14 34 35 36 QP 1 Q15 36 38 39 QN 8 Q16 35 35 37 QP 1 Q17 99 99 37 QN 1 Q18 99 99 36 QN 1 Q19 50 42 34 QP 1 Q20 42 42 34 QP 1 Q21 32 33 42 QN 1 Q22 99 40 41 QN 1 Q23 43 43 50 QN 1 Q24 34 43 50 QN 2 Q25 33 43 50 QN 2 Q26 34 44 50 QC 1 Q27 31 46 50 QC 1 EC 47 50 99 45 0.96 RC 46 47 1E3 IREF 99 43 4.5E-7 I13 35 50 4.5E-7 R11 99 40 75E3 R12 99 36 40E3 R13 31 38 20E3 R14 32 39 5E3 R15 40 37 75E3 R22 44 50 30 R23 99 45 50 * * MODELS USED * .MODEL QN NPN(BF=200 IS=1E-16 VA=150) .MODEL QP PNP(BF=100 IS=5E-17 VA=50) .MODEL QX PNP(BF=25 KF=2E-17) .MODEL QC NPN(BF=200 IS=2.22E-11) .MODEL DX D(IS=1E-15) .MODEL DEN D(RS=2.45E3 KF=33E-15) .ENDS * OP196G SPICE Macro-model Rev. A, 6/95 * ARG / ADSC * * This version of the OP196 model simulates the worst-case * parameters of the 'G' grade. The worst-case parameters * used correspond to those in the data sheet. * * Copyright 1995 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of * this model indicates your acceptance of the terms and pro- * visions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP196G 1 2 99 50 49 * * INPUT STAGE * IREF 21 50 1U QB1 21 21 99 99 QP 1 QB2 22 21 99 99 QP 1 QB3 4 21 99 99 QP 1.5 QB4 22 22 50 50 QN 2 QB5 11 22 50 50 QN 3 Q1 5 4 7 50 QN1 2 Q2 6 4 8 50 QN1 2 Q3 4 4 7 50 QN1 1 Q4 4 4 8 50 QN1 1 Q5 50 1 7 99 QP1 2 Q6 50 3 8 99 QP1 2 EOS 3 2 POLY(1) (17,98) 300E-6 1 Q7 99 1 9 50 QN1 2 Q8 99 3 10 50 QN1 2 Q9 12 11 9 99 QP1 2 Q10 13 11 10 99 QP1 2 Q11 11 11 9 99 QP1 1 Q12 11 11 10 99 QP1 1 R1 99 5 50K R2 99 6 50K R3 12 50 50K R4 13 50 50K IOS 1 2 2.5N C10 5 6 3.183P C11 12 13 3.183P CIN 1 2 1P * * GAIN STAGE * EREF 98 0 POLY(2) (99,0) (50,0) 0 0.5 0.5 G1 98 15 POLY(2) (6,5) (13,12) 0 10U 10U R10 15 98 120MEG CC 15 49 8P D1 15 99 DX D2 50 15 DX * * COMMON MODE STAGE * ECM 16 98 POLY(2) (1,98) (2,98) 0 0.5 0.5 R11 16 17 1E6 R12 17 98 100 * * OUTPUT STAGE * ISY 99 50 35E-6 EIN 35 50 POLY(1) (15,98) 1.42713 1 Q24 37 35 36 50 QN 1 QD4 37 37 38 99 QP 1 Q27 40 37 38 99 QP 1 R5 36 39 150K R6 99 38 45K Q26 39 42 50 50 QN 3 QD5 40 40 39 50 QN 1 Q28 41 40 44 50 QN 1 QL1 37 41 99 99 QP 1 R7 99 41 10.7K I4 99 43 2U QD7 42 42 50 50 QN 2 QD6 43 43 42 50 QN 2 Q29 47 43 44 50 QN 1 Q30 44 45 50 50 QN 1.5 QD10 45 46 50 50 QN 1 R9 45 46 175 Q31 46 47 48 99 QP 1 QD8 47 47 48 99 QP 1 QD9 48 48 51 99 QP 5 R8 99 51 2.9K I5 99 46 1U Q32 49 48 99 99 QOP 10 Q33 49 44 50 50 QON 4 .MODEL DX D() .MODEL QN NPN(BF=120 VAF=100) .MODEL QP PNP(BF=80 VAF=60) *.MODEL QON AKO:QN NPN(RC=2K) *.MODEL QOP AKO:QP PNP(RC=4K) *jg, 17/5/2000: Corrected syntax model .MODEL QON NPN(BF=120 VAF=100 RC=2K) .MODEL QOP PNP(BF=80 VAF=60 RC=4K) .MODEL QN1 NPN(BF=100 VAF=100) .MODEL QP1 PNP(BF=56 VAF=60) .ENDS * OP200A SPICE Macro-model 12/90, Rev. B * AAG / PMI * * This version of the OP-200 model simulates the worst case * parameters of the 'A' grade. The worst case parameters * used correspond to those in the data sheet. * * Revision History: * Re-ordered subcircuit call out nodes to put the * output node last. * Changed Ios from 1E-9 to 5E-10 * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP200A 1 2 100 101 29 * * INPUT STAGE & POLE AT 4.5 MHZ * RI1 2 9 1K RI2 1 10 1K IOS 10 9 0.5N CIN 9 10 3.2P R1 9 3 13MEG R2 3 10 13MEG D1 10 9 DX D2 9 10 DX R3 100 5 517.2 R4 100 6 517.2 C2 5 6 34.192P EOS 11 10 POLY(1) 20 23 75U 1 Q1 5 9 4 QX Q2 6 11 4 QX I1 4 101 0.1M * * FIRST GAIN STAGE * EREF 12 0 23 0 1 G1 12 13 5 6 117.81 R5 13 12 1 E1 100 14 POLY(1) 100 23 -2.4 1 D3 13 14 DX E2 15 101 POLY(1) 23 101 -2.4 1 D4 15 13 DX * * SECOND GAIN STAGE & DOMINANT POLE AT 0.3125 HZ * G2 12 16 13 23 33.33U R6 16 12 509.29MEG C3 16 12 1000P V1 100 17 DC 3.9725 D5 16 17 DX V2 18 101 DC 3.9725 D6 18 16 DX * * COMMON-MODE GAIN NETWORK WITH ZERO AT 112.47 HZ * ECM 19 12 3 23 1 R7 19 20 1MEG R8 20 12 1 C4 19 20 1.4151N * * POLE AT 4.5 MHZ * G3 12 21 16 23 1U R9 21 12 1MEG C5 21 12 35.368F * * POLE AT 4.5 MHZ * G4 12 22 21 23 1U R10 22 12 1MEG C6 22 12 35.368F * * OUTPUT STAGE * R11 100 23 533.33K R12 23 101 533.33K IDC 100 101 DC 597U V3 25 28 DC 2.15 D7 22 25 DX V4 28 26 DC 2.275 D8 26 22 DX D9 100 24 DX D10 100 27 DX G5 24 101 22 28 4M D11 101 24 DY G6 27 101 28 22 4M D12 101 27 DY G7 28 100 100 22 4M R13 100 28 250 G8 101 28 22 101 4M R14 28 101 250 L1 28 29 0.7U * * MODELS USED * .MODEL QX NPN(BF=25000) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP200E SPICE Macro-model 12/90, Rev. B * AAG / PMI * * Revision History: * Re-ordered subcircuit call out nodes to put the * output node last. * Changed Ios from 1E-9 to 5E-10 * * This version of the OP-200 model simulates the worst case * parameters of the 'E' grade. The worst case parameters * used correspond to those in the data sheet. * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP200E 1 2 100 101 29 * * INPUT STAGE & POLE AT 4.5 MHZ * RI1 2 9 1K RI2 1 10 1K IOS 10 9 0.5N CIN 9 10 3.2P R1 9 3 13MEG R2 3 10 13MEG D1 10 9 DX D2 9 10 DX R3 100 5 517.2 R4 100 6 517.2 C2 5 6 34.192P EOS 11 10 POLY(1) 20 23 75U 1 Q1 5 9 4 QX Q2 6 11 4 QX I1 4 101 0.1M * * FIRST GAIN STAGE * EREF 12 0 23 0 1 G1 12 13 5 6 117.81 R5 13 12 1 E1 100 14 POLY(1) 100 23 -2.4 1 D3 13 14 DX E2 15 101 POLY(1) 23 101 -2.4 1 D4 15 13 DX * * SECOND GAIN STAGE & DOMINANT POLE AT 0.3125 HZ * G2 12 16 13 23 33.33U R6 16 12 509.29MEG C3 16 12 1000P V1 100 17 DC 3.9725 D5 16 17 DX V2 18 101 DC 3.9725 D6 18 16 DX * * COMMON-MODE GAIN NETWORK WITH ZERO AT 112.47 HZ * ECM 19 12 3 23 1 R7 19 20 1MEG R8 20 12 1 C4 19 20 1.4151N * * POLE AT 4.5 MHZ * G3 12 21 16 23 1U R9 21 12 1MEG C5 21 12 35.368F * * POLE AT 4.5 MHZ * G4 12 22 21 23 1U R10 22 12 1MEG C6 22 12 35.368F * * OUTPUT STAGE * R11 100 23 533.33K R12 23 101 533.33K IDC 100 101 DC 597U V3 25 28 DC 2.15 D7 22 25 DX V4 28 26 DC 2.275 D8 26 22 DX D9 100 24 DX D10 100 27 DX G5 24 101 22 28 4M D11 101 24 DY G6 27 101 28 22 4M D12 101 27 DY G7 28 100 100 22 4M R13 100 28 250 G8 101 28 22 101 4M R14 28 101 250 L1 28 29 0.7U * * MODELS USED * .MODEL QX NPN(BF=25000) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP200F SPICE Macro-model 12/90, Rev. B * AAG / PMI * * Revision History: * Re-ordered subcircuit call out nodes to put the * output node last. * Changed Ios from 2E-9 to 1E-9 * * This version of the OP-200 model simulates the worst case * parameters of the 'F' grade. The worst case parameters * used correspond to those in the data sheet. * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP200F 1 2 100 101 29 * * INPUT STAGE & POLE AT 4.5 MHZ * RI1 2 9 1K RI2 1 10 1K IOS 10 9 1N CIN 9 10 3.2P R1 9 3 6.47MEG R2 3 10 6.47MEG D1 10 9 DX D2 9 10 DX R3 100 5 517.2 R4 100 6 517.2 C2 5 6 34.192P EOS 11 10 POLY(1) 20 23 150U 1 Q1 5 9 4 QX Q2 6 11 4 QX I1 4 101 0.1M * * FIRST GAIN STAGE * EREF 12 0 23 0 1 G1 12 13 5 6 117.81 R5 13 12 1 E1 100 14 POLY(1) 100 23 -2.4 1 D3 13 14 DX E2 15 101 POLY(1) 23 101 -2.4 1 D4 15 13 DX * * SECOND GAIN STAGE & DOMINANT POLE AT 0.417 HZ * G2 12 16 13 23 33.33U R6 16 12 381.97MEG C3 16 12 1000P V1 100 17 DC 3.9725 D5 16 17 DX V2 18 101 DC 3.9725 D6 18 16 DX * * COMMON-MODE GAIN NETWORK WITH ZERO AT 200 HZ * ECM 19 12 3 23 1.7783 R7 19 20 1MEG R8 20 12 1 C4 19 20 795.77P * * POLE AT 4.5 MHZ * G3 12 21 16 23 1U R9 21 12 1MEG C5 21 12 35.368F * * POLE AT 4.5 MHZ * G4 12 22 21 23 1U R10 22 12 1MEG C6 22 12 35.368F * * OUTPUT STAGE * R11 100 23 533.33K R12 23 101 533.33K IDC 100 101 DC 597U V3 25 28 DC 2.15 D7 22 25 DX V4 28 26 DC 2.275 D8 26 22 DX D9 100 24 DX D10 100 27 DX G5 24 101 22 28 4M D11 101 24 DY G6 27 101 28 22 4M D12 101 27 DY G7 28 100 100 22 4M R13 100 28 250 G8 101 28 22 101 4M R14 28 101 250 L1 28 29 0.7U * * MODELS USED * .MODEL QX NPN(BF=12500) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS OP200F * OP200G SPICE Macro-model 12/90, Rev. B * AAG / PMI * * Revision History: * Re-ordered subcircuit call out nodes to put the * output node last. * Changed Ios from 3.5E-9 to 1.75E-9 * * This version of the OP-200 model simulates the worst case * parameters of the 'G' grade. The worst case parameters * used correspond to those in the data sheet. * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP200G 1 2 100 101 29 * * INPUT STAGE & POLE AT 4.5 MHZ * RI1 2 9 1K RI2 1 10 1K IOS 10 9 1.75N CIN 9 10 3.2P R1 9 3 5.17MEG R2 3 10 5.17MEG D1 10 9 DX D2 9 10 DX R3 100 5 517.2 R4 100 6 517.2 C2 5 6 34.192P EOS 11 10 POLY(1) 20 23 200U 1 Q1 5 9 4 QX Q2 6 11 4 QX I1 4 101 0.1M * * FIRST GAIN STAGE * EREF 12 0 23 0 1 G1 12 13 5 6 117.81 R5 13 12 1 E1 100 14 POLY(1) 100 23 -2.4 1 D3 13 14 DX E2 15 101 POLY(1) 23 101 -2.4 1 D4 15 13 DX * * SECOND GAIN STAGE & DOMINANT POLE AT 0.417 HZ * G2 12 16 13 23 33.33U R6 16 12 381.97MEG C3 16 12 1000P V1 100 17 DC 3.9725 D5 16 17 DX V2 18 101 DC 3.9725 D6 18 16 DX * * COMMON-MODE GAIN NETWORK WITH ZERO AT 355.66 HZ * ECM 19 12 3 23 3.1623 R7 19 20 1MEG R8 20 12 1 C4 19 20 447.49P * * POLE AT 4.5 MHZ * G3 12 21 16 23 1U R9 21 12 1MEG C5 21 12 35.368F * * POLE AT 4.5 MHZ * G4 12 22 21 23 1U R10 22 12 1MEG C6 22 12 35.368F * * OUTPUT STAGE * R11 100 23 533.33K R12 23 101 533.33K IDC 100 101 DC 597U V3 25 28 DC 2.15 D7 22 25 DX V4 28 26 DC 2.275 D8 26 22 DX D9 100 24 DX D10 100 27 DX G5 24 101 22 28 4M D11 101 24 DY G6 27 101 28 22 4M D12 101 27 DY G7 28 100 100 22 4M R13 100 28 250 G8 101 28 22 101 4M R14 28 101 250 L1 28 29 0.7U * * MODELS USED * .MODEL QX NPN(BF=10000) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS OP200G * OP213 SPICE Macro-model 9/92, Rev. A * JCB / PMI * * Copyright 1992 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP213 3 2 7 4 6 * * INPUT STAGE * R3 4 19 1.5E3 R4 4 20 1.5E3 C1 19 20 5.31E-12 I1 7 18 106E-6 IOS 2 3 25E-09 EOS 12 5 POLY(1) 51 4 25E-06 1 Q1 19 3 18 PNP1 Q2 20 12 18 PNP1 CIN 3 2 3E-12 D1 3 1 DY D2 2 1 DY EN 5 2 22 0 1 GN1 0 2 25 0 1E-5 GN2 0 3 28 0 1E-5 * * VOLTAGE NOISE SOURCE WITH FLICKER NOISE * DN1 21 22 DEN DN2 22 23 DEN VN1 21 0 DC 2 VN2 0 23 DC 2 * * CURRENT NOISE SOURCE WITH FLICKER NOISE * DN3 24 25 DIN DN4 25 26 DIN VN3 24 0 DC 2 VN4 0 26 DC 2 * * SECOND CURRENT NOISE SOURCE * DN5 27 28 DIN DN6 28 29 DIN VN5 27 0 DC 2 VN6 0 29 DC 2 * * GAIN STAGE & DOMINANT POLE AT .2000E+01 HZ * G2 34 36 19 20 2.65E-04 R7 34 36 39E+06 V3 35 4 DC 6 D4 36 35 DX VB2 34 4 1.6 * * SUPPLY/2 GENERATOR * ISY 7 4 0.2E-3 R10 7 60 40E+3 R11 60 4 40E+3 C3 60 0 1E-9 * * CMRR STAGE & POLE AT 6 kHZ * ECM 50 4 POLY(2) 3 60 2 60 0 0.8 0.8 CCM 50 51 26.5E-12 RCM1 50 51 1E6 RCM2 51 4 1 * * OUTPUT STAGE * R12 37 36 1E3 R13 38 36 500 C4 37 6 20E-12 C5 38 39 20E-12 M1 39 36 4 4 MN L=9E-6 W=1000E-6 AD=15E-9 AS=15E-9 M2 45 36 4 4 MN L=9E-6 W=1000E-6 AD=15E-9 AS=15E-9 D5 39 47 DX D6 47 45 DX Q3 39 40 41 QPA 8 VB 7 40 DC 0.861 R14 7 41 375 Q4 41 7 43 QNA 1 R17 7 43 15 Q5 43 39 6 QNA 20 Q6 46 45 6 QPA 20 R18 46 4 15 Q7 36 46 4 QNA 1 M3 6 36 4 4 MN L=9E-6 W=2000E-6 AD=30E-9 AS=30E-9 * * NONLINEAR MODELS USED * .MODEL DX D (IS=1E-15) .MODEL DY D (IS=1E-15 BV=7) .MODEL PNP1 PNP (BF=220) .MODEL DEN D(IS=1E-12 RS=1016 KF=3.278E-15 AF=1) .MODEL DIN D(IS=1E-12 RS=100019 KF=4.173E-15 AF=1) .MODEL QNA NPN(IS=1.19E-16 BF=253 VAF=193 VAR=15 RB=2.0E3 + IRB=7.73E-6 RBM=132.8 RE=4 RC=209 CJE=2.1E-13 VJE=0.573 + MJE=0.364 CJC=1.64E-13 VJC=0.534 MJC=0.5 CJS=1.37E-12 + VJS=0.59 MJS=0.5 TF=0.43E-9 PTF=30) .MODEL QPA PNP(IS=5.21E-17 BF=131 VAF=62 VAR=15 RB=1.52E3 + IRB=1.67E-5 RBM=368.5 RE=6.31 RC=354.4 CJE=1.1E-13 + VJE=0.745 MJE=0.33 CJC=2.37E-13 VJC=0.762 MJC=0.4 + CJS=7.11E-13 VJS=0.45 MJS=0.412 TF=1.0E-9 PTF=30) .MODEL MN NMOS(LEVEL=3 VTO=1.3 RS=0.3 RD=0.3 TOX=8.5E-8 + LD=1.48E-6 NSUB=1.53E16 UO=650 DELTA=10 VMAX=2E5 + XJ=1.75E-6 KAPPA=0.8 ETA=0.066 THETA=0.01 TPG=1 CJ=2.9E-4 + PB=0.837 MJ=0.407 CJSW=0.5E-9 MJSW=0.33) * .ENDS * OP213E SPICE Macro-model 3/94, Rev. A * ARG / PMI * * This version of the OP213 model simulates the worst-case * parameters of the 'E' grade. The worst-case parameters * used correspond to those in the data sheet. * * Copyright 1992 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License * Statement. * * Node assignments * * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP213E 3 2 7 4 6 * * INPUT STAGE AND POLE AT 40MHZ * R3 4 19 1.5E3 R4 4 20 1.5E3 C1 19 20 1.326E-12 I1 7 18 106E-6 IOS 2 3 25E-9 EOS 12 5 POLY(1) 51 4 100E-6 1 Q1 19 3 18 PNP1 Q2 20 12 18 PNP1 CIN 3 2 3E-12 D1 3 1 DY D2 2 1 DY EN 5 2 22 0 1 GN1 0 2 25 0 1E-5 GN2 0 3 28 0 1E-5 * * VOLTAGE NOISE SOURCE WITH FLICKER NOISE * DN1 21 22 DEN DN2 22 23 DEN VN1 21 0 DC 2 VN2 0 23 DC 2 * * CURRENT NOISE SOURCE WITH FLICKER NOISE * DN3 24 25 DIN DN4 25 26 DIN VN3 24 0 DC 2 VN4 0 26 DC 2 * * SECOND CURRENT NOISE SOURCE * DN5 27 28 DIN DN6 28 29 DIN VN5 27 0 DC 2 VN6 0 29 DC 2 * * GAIN STAGE & DOMINANT POLE AT 1.581HZ * G2 34 36 19 20 54.814E-6 R7 34 36 39E6 V3 35 4 DC 6 D4 36 35 DX VB2 34 4 1.6 * * SUPPLY/2 GENERATOR * ISY 7 4 0.525E-3 R10 7 60 40E3 R11 60 4 40E3 C3 60 0 1E-9 * * CMRR STAGE & POLE AT 6KHZ * ECM 50 4 POLY(2) 3 60 2 60 0 0.5 0.5 CCM 50 51 26.5E-12 RCM1 50 51 1E6 RCM2 51 4 10 * * OUTPUT STAGE * R12 37 36 2E3 R13 38 36 200 C4 37 6 4E-12 C5 38 39 4E-12 M1 39 36 4 4 MN L=9E-6 W=1000E-6 AD=15E-9 AS=15E-9 M2 45 36 4 4 MN L=9E-6 W=1000E-6 AD=15E-9 AS=15E-9 D5 39 47 DX D6 47 45 DX Q3 39 40 41 QPA 8 VB 7 40 DC 0.861 R14 7 41 375 Q4 41 7 43 QNA 1 R17 7 43 15 Q5 43 39 6 QNA 20 Q6 46 45 6 QPA 20 R18 46 4 15 Q7 36 46 4 QNA 1 M3 6 36 4 4 MN L=9E-6 W=2000E-6 AD=30E-9 AS=30E-9 * * NONLINEAR MODELS USED * .MODEL DX D (IS=1E-15) .MODEL DY D (IS=1E-15 BV=7) .MODEL PNP1 PNP (BF=87.333) .MODEL DEN D(IS=1E-12 RS=1016 KF=3.278E-15 AF=1) .MODEL DIN D(IS=1E-12 RS=100019 KF=4.173E-15 AF=1) .MODEL QNA NPN(IS=1.19E-16 BF=253 VAF=193 VAR=15 RB=2.0E3 + IRB=7.73E-6 RBM=132.8 RE=4 RC=209 CJE=2.1E-13 VJE=0.573 + MJE=0.364 CJC=1.64E-13 VJC=0.534 MJC=0.5 CJS=0.685E-12 + VJS=0.59 MJS=0.5 TF=0.43E-9 PTF=30) .MODEL QPA PNP(IS=5.21E-17 BF=131 VAF=62 VAR=15 RB=1.52E3 + IRB=1.67E-5 RBM=368.5 RE=6.31 RC=354.4 CJE=1.1E-13 + VJE=0.745 MJE=0.33 CJC=2.37E-13 VJC=0.762 MJC=0.4 + CJS=7.11E-13 VJS=0.45 MJS=0.412 TF=1.0E-9 PTF=30) .MODEL MN NMOS(LEVEL=3 VTO=1.3 RS=0.3 RD=0.3 TOX=8.5E-8 + LD=1.48E-6 NSUB=1.53E16 UO=650 DELTA=10 VMAX=2E5 + XJ=1.75E-6 KAPPA=0.8 ETA=0.066 THETA=0.01 TPG=1 CJ=2.9E-5 + PB=0.837 MJ=0.407 CJSW=0.5E-10 MJSW=0.33) .ENDS * OP213F SPICE Macro-model 3/94, Rev. A * ARG / PMI * * This version of the OP213 model simulates the worst-case * parameters of the 'F' grade. The worst-case parameters * used correspond to those in the data sheet. * * Copyright 1992 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License * Statement. * * Node assignments * * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP213F 3 2 7 4 6 * * INPUT STAGE AND POLE AT 40MHZ * R3 4 19 1.5E3 R4 4 20 1.5E3 C1 19 20 1.326E-12 I1 7 18 106E-6 IOS 2 3 25E-9 EOS 12 5 POLY(1) 51 4 250E-6 1.585 Q1 19 3 18 PNP1 Q2 20 12 18 PNP1 CIN 3 2 3E-12 D1 3 1 DY D2 2 1 DY EN 5 2 22 0 1 GN1 0 2 25 0 1E-5 GN2 0 3 28 0 1E-5 * * VOLTAGE NOISE SOURCE WITH FLICKER NOISE * DN1 21 22 DEN DN2 22 23 DEN VN1 21 0 DC 2 VN2 0 23 DC 2 * * CURRENT NOISE SOURCE WITH FLICKER NOISE * DN3 24 25 DIN DN4 25 26 DIN VN3 24 0 DC 2 VN4 0 26 DC 2 * * SECOND CURRENT NOISE SOURCE * DN5 27 28 DIN DN6 28 29 DIN VN5 27 0 DC 2 VN6 0 29 DC 2 * * GAIN STAGE & DOMINANT POLE AT 1.581HZ * G2 34 36 19 20 54.814E-6 R7 34 36 39E6 V3 35 4 DC 6 D4 36 35 DX VB2 34 4 1.6 * * SUPPLY/2 GENERATOR * ISY 7 4 0.525E-3 R10 7 60 40E3 R11 60 4 40E3 C3 60 0 1E-9 * * CMRR STAGE & POLE AT 6KHZ * ECM 50 4 POLY(2) 3 60 2 60 0 0.5 0.5 CCM 50 51 26.5E-12 RCM1 50 51 1E6 RCM2 51 4 10 * * OUTPUT STAGE * R12 37 36 2E3 R13 38 36 200 C4 37 6 4E-12 C5 38 39 4E-12 M1 39 36 4 4 MN L=9E-6 W=1000E-6 AD=15E-9 AS=15E-9 M2 45 36 4 4 MN L=9E-6 W=1000E-6 AD=15E-9 AS=15E-9 D5 39 47 DX D6 47 45 DX Q3 39 40 41 QPA 8 VB 7 40 DC 0.861 R14 7 41 375 Q4 41 7 43 QNA 1 R17 7 43 15 Q5 43 39 6 QNA 20 Q6 46 45 6 QPA 20 R18 46 4 15 Q7 36 46 4 QNA 1 M3 6 36 4 4 MN L=9E-6 W=2000E-6 AD=30E-9 AS=30E-9 * * NONLINEAR MODELS USED * .MODEL DX D (IS=1E-15) .MODEL DY D (IS=1E-15 BV=7) .MODEL PNP1 PNP (BF=87.333) .MODEL DEN D(IS=1E-12 RS=1016 KF=3.278E-15 AF=1) .MODEL DIN D(IS=1E-12 RS=100019 KF=4.173E-15 AF=1) .MODEL QNA NPN(IS=1.19E-16 BF=253 VAF=193 VAR=15 RB=2.0E3 + IRB=7.73E-6 RBM=132.8 RE=4 RC=209 CJE=2.1E-13 VJE=0.573 + MJE=0.364 CJC=1.64E-13 VJC=0.534 MJC=0.5 CJS=0.685E-12 + VJS=0.59 MJS=0.5 TF=0.43E-9 PTF=30) .MODEL QPA PNP(IS=5.21E-17 BF=131 VAF=62 VAR=15 RB=1.52E3 + IRB=1.67E-5 RBM=368.5 RE=6.31 RC=354.4 CJE=1.1E-13 + VJE=0.745 MJE=0.33 CJC=2.37E-13 VJC=0.762 MJC=0.4 + CJS=7.11E-13 VJS=0.45 MJS=0.412 TF=1.0E-9 PTF=30) .MODEL MN NMOS(LEVEL=3 VTO=1.3 RS=0.3 RD=0.3 TOX=8.5E-8 + LD=1.48E-6 NSUB=1.53E16 UO=650 DELTA=10 VMAX=2E5 + XJ=1.75E-6 KAPPA=0.8 ETA=0.066 THETA=0.01 TPG=1 CJ=2.9E-5 + PB=0.837 MJ=0.407 CJSW=0.5E-10 MJSW=0.33) .ENDS * OP215A SPICE Macro-model 10/90, Rev. A * AN / PMI * * This version of the OP-215 model simulates the worst case * parameters of the 'A' grade. The worst case parameters * used correspond to those in the data sheet. * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP215A 1 2 99 50 26 * * INPUT STAGE & POLE AT 150 MHZ * R1 1 3 5E11 R2 2 3 5E11 R3 5 50 318 R4 6 50 318 CIN 1 2 3E-12 C2 5 6 1.67E-12 I1 99 4 1E-3 IOS 1 2 2.5E-11 EOS 7 1 POLY(1) 18 20 1E-3 1 J1 5 2 4 JX J2 6 7 4 JX * EREF 98 0 20 0 1 * * SECOND STAGE & POLE AT 33.33 HZ * R5 9 98 47.75E6 C3 9 98 100E-12 G1 98 9 5 6 3.14E-3 V2 99 8 4.12 V3 10 50 4.12 D1 9 8 DX D2 10 9 DX * * NEGATIVE ZERO AT 30 MHZ * R6 11 12 1E6 R7 12 98 1 E1 11 98 9 98 1E6 C4 11 12 -5.305E-15 * * POLE AT 200 MHZ * R8 13 98 1E6 C5 13 98 7.95E-16 G2 98 13 12 20 1E-6 * * POLE AT 100 MHZ * R9 14 98 1E6 C6 14 98 1.59E-15 G3 98 14 13 20 1E-6 * * POLE AT 150 MHZ * R10 15 98 1E6 C7 15 98 1.061E-15 G4 98 15 14 20 1E-6 * * POLE AT 100 MHZ * R11 16 98 1E6 C8 16 98 1.59E-15 G5 98 16 15 20 1E-6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 2 KHZ * R12 17 18 1E6 R13 18 98 1 C9 17 18 79.6E-12 E2 17 98 3 20 50 * * POLE AT 100 MHZ * R14 19 98 1E6 C10 19 98 1.59E-15 G6 98 19 16 20 1E-6 * * OUTPUT STAGE * R15 20 99 135E3 R16 20 50 135E3 ISY 99 50 7.4E-3 R17 25 99 172.78 R18 25 50 172.78 L2 25 26 4E-11 G7 23 50 19 25 5.79E-3 G8 24 50 25 19 5.79E-3 G9 25 99 99 19 5.79E-3 G10 50 25 19 50 5.79E-3 V4 21 25 1.4 V5 25 22 1.4 D3 19 21 DX D4 22 19 DX D5 99 23 DX D6 99 24 DX D7 50 23 DY D8 50 24 DY * * MODELS USED * .MODEL JX PJF(BETA=4.93E-3 VTO=-2.000 IS=100E-12) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP215B SPICE Macro-model 10/90, Rev. A * AN / PMI * * This version of the OP-215 model simulates the worst case * parameters of the 'B' grade. The worst case parameters * used correspond to those in the data sheet. * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP215B 1 2 99 50 26 * * INPUT STAGE & POLE AT 150 MHZ * R1 1 3 5E11 R2 2 3 5E11 R3 5 50 239 R4 6 50 239 CIN 1 2 3E-12 C2 5 6 2.22E-12 I1 99 4 1E-3 IOS 1 2 2.5E-11 EOS 7 1 POLY(1) 18 20 2E-3 1 J1 5 2 4 JX J2 6 7 4 JX * EREF 98 0 20 0 1 * * SECOND STAGE & POLE AT 66.7 HZ * R5 9 98 17.91E6 C3 9 98 133.3E-12 G1 98 9 5 6 4.19E-3 V2 99 8 4.12 V3 10 50 4.12 D1 9 8 DX D2 10 9 DX * * NEGATIVE ZERO AT 30 MHZ * R6 11 12 1E6 R7 12 98 1 E1 11 98 9 98 1E6 C4 11 12 -5.305E-15 * * POLE AT 200 MHZ * R8 13 98 1E6 C5 13 98 7.95E-16 G2 98 13 12 20 1E-6 * * POLE AT 100 MHZ * R9 14 98 1E6 C6 14 98 1.59E-15 G3 98 14 13 20 1E-6 * * POLE AT 150 MHZ * R10 15 98 1E6 C7 15 98 1.061E-15 G4 98 15 14 20 1E-6 * * POLE AT 100 MHZ * R11 16 98 1E6 C8 16 98 1.59E-15 G5 98 16 15 20 1E-6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 2 KHZ * R12 17 18 1E6 R13 18 98 1 C9 17 18 79.6E-12 E2 17 98 3 20 50 * * POLE AT 100 MHZ * R14 19 98 1E6 C10 19 98 1.59E-15 G6 98 19 16 20 1E-6 * * OUTPUT STAGE * R15 20 99 135E3 R16 20 50 135E3 ISY 99 50 7.4E-3 R17 25 99 172.78 R18 25 50 172.78 L2 25 26 4E-11 G7 23 50 19 25 5.79E-3 G8 24 50 25 19 5.79E-3 G9 25 99 99 19 5.79E-3 G10 50 25 19 50 5.79E-3 V4 21 25 1.5 V5 25 22 1.5 D3 19 21 DX D4 22 19 DX D5 99 23 DX D6 99 24 DX D7 50 23 DY D8 50 24 DY * * MODELS USED * .MODEL JX PJF(BETA=8.77E-3 VTO=-2.000 IS=200E-12) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP215C SPICE Macro-model 10/90, Rev. A * AN / PMI * * This version of the OP-215 model simulates the worst case * parameters of the 'C' grade. The worst case parameters * used correspond to those in the data sheet. * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP215C 1 2 99 50 26 * * INPUT STAGE & POLE AT 150 MHZ * R1 1 3 5E11 R2 2 3 5E11 R3 5 50 159 R4 6 50 159 CIN 1 2 3E-12 C2 5 6 3.33E-12 I1 99 4 1E-3 IOS 1 2 5E-11 EOS 7 1 POLY(1) 18 20 4E-3 1 J1 5 2 4 JX J2 6 7 4 JX * EREF 98 0 20 0 1 * * SECOND STAGE & POLE AT 100 HZ * R5 9 98 7.96E6 C3 9 98 200E-12 G1 98 9 5 6 6.28E-3 V2 99 8 4.12 V3 10 50 4.12 D1 9 8 DX D2 10 9 DX * * NEGATIVE ZERO AT 30 MHZ * R6 11 12 1E6 R7 12 98 1 E1 11 98 9 98 1E6 C4 11 12 -5.305E-15 * * POLE AT 200 MHZ * R8 13 98 1E6 C5 13 98 7.95E-16 G2 98 13 12 20 1E-6 * * POLE AT 100 MHZ * R9 14 98 1E6 C6 14 98 1.59E-15 G3 98 14 13 20 1E-6 * * POLE AT 150 MHZ * R10 15 98 1E6 C7 15 98 1.061E-15 G4 98 15 14 20 1E-6 * * POLE AT 100 MHZ * R11 16 98 1E6 C8 16 98 1.59E-15 G5 98 16 15 20 1E-6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 3.16 KHZ * R12 17 18 1E6 R13 18 98 1 C9 17 18 50.1E-12 E2 17 98 3 20 79 * * POLE AT 100 MHZ * R14 19 98 1E6 C10 19 98 1.59E-15 G6 98 19 16 20 1E-6 * * OUTPUT STAGE * R15 20 99 135E3 R16 20 50 135E3 ISY 99 50 8.9E-3 R17 25 99 172.78 R18 25 50 172.78 L2 25 26 4E-11 G7 23 50 19 25 5.79E-3 G8 24 50 25 19 5.79E-3 G9 25 99 99 19 5.79E-3 G10 50 25 19 50 5.79E-3 V4 21 25 1.4 V5 25 22 1.4 D3 19 21 DX D4 22 19 DX D5 99 23 DX D6 99 24 DX D7 50 23 DY D8 50 24 DY * * MODELS USED * .MODEL JX PJF(BETA=19.7E-3 VTO=-2.000 IS=300E-12) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP215E SPICE Macro-model 10/90, Rev. A * AN / PMI * * This version of the OP-215 model simulates the worst case * parameters of the 'E' grade. The worst case parameters * used correspond to those in the data sheet. * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP215E 1 2 99 50 26 * * INPUT STAGE & POLE AT 150 MHZ * R1 1 3 5E11 R2 2 3 5E11 R3 5 50 318 R4 6 50 318 CIN 1 2 3E-12 C2 5 6 1.67E-12 I1 99 4 1E-3 IOS 1 2 2.5E-11 EOS 7 1 POLY(1) 18 20 1E-3 1 J1 5 2 4 JX J2 6 7 4 JX * EREF 98 0 20 0 1 * * SECOND STAGE & POLE AT 33.33 HZ * R5 9 98 47.75E6 C3 9 98 100E-12 G1 98 9 5 6 3.14E-3 V2 99 8 4.12 V3 10 50 4.12 D1 9 8 DX D2 10 9 DX * * NEGATIVE ZERO AT 30 MHZ * R6 11 12 1E6 R7 12 98 1 E1 11 98 9 98 1E6 C4 11 12 -5.305E-15 * * POLE AT 200 MHZ * R8 13 98 1E6 C5 13 98 7.95E-16 G2 98 13 12 20 1E-6 * * POLE AT 100 MHZ * R9 14 98 1E6 C6 14 98 1.59E-15 G3 98 14 13 20 1E-6 * * POLE AT 150 MHZ * R10 15 98 1E6 C7 15 98 1.061E-15 G4 98 15 14 20 1E-6 * * POLE AT 100 MHZ * R11 16 98 1E6 C8 16 98 1.59E-15 G5 98 16 15 20 1E-6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 3.16 KHZ * R12 17 18 1E6 R13 18 98 1 C9 17 18 50.1E-12 E2 17 98 3 20 79 * * POLE AT 100 MHZ * R14 19 98 1E6 C10 19 98 1.59E-15 G6 98 19 16 20 1E-6 * * OUTPUT STAGE * R15 20 99 135E3 R16 20 50 135E3 ISY 99 50 7.4E-3 R17 25 99 172.78 R18 25 50 172.78 L2 25 26 4E-11 G7 23 50 19 25 5.79E-3 G8 24 50 25 19 5.79E-3 G9 25 99 99 19 5.79E-3 G10 50 25 19 50 5.79E-3 V4 21 25 1.4 V5 25 22 1.4 D3 19 21 DX D4 22 19 DX D5 99 23 DX D6 99 24 DX D7 50 23 DY D8 50 24 DY * * MODELS USED * .MODEL JX PJF(BETA=4.93E-3 VTO=-2.000 IS=100E-12) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP215F SPICE Macro-model 10/90, Rev. A * AN / PMI * * This version of the OP-215 model simulates the worst case * parameters of the 'F' grade. The worst case parameters * used correspond to those in the data sheet. * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP215F 1 2 99 50 26 * * INPUT STAGE & POLE AT 150 MHZ * R1 1 3 5E11 R2 2 3 5E11 R3 5 50 239 R4 6 50 239 CIN 1 2 3E-12 C2 5 6 2.22E-12 I1 99 4 1E-3 IOS 1 2 2.5E-11 EOS 7 1 POLY(1) 18 20 2E-3 1 J1 5 2 4 JX J2 6 7 4 JX * EREF 98 0 20 0 1 * * SECOND STAGE & POLE AT 66.7 HZ * R5 9 98 17.91E6 C3 9 98 133.3E-12 G1 98 9 5 6 4.19E-3 V2 99 8 4.12 V3 10 50 4.12 D1 9 8 DX D2 10 9 DX * * NEGATIVE ZERO AT 30 MHZ * R6 11 12 1E6 R7 12 98 1 E1 11 98 9 98 1E6 C4 11 12 -5.305E-15 * * POLE AT 200 MHZ * R8 13 98 1E6 C5 13 98 7.95E-16 G2 98 13 12 20 1E-6 * * POLE AT 100 MHZ * R9 14 98 1E6 C6 14 98 1.59E-15 G3 98 14 13 20 1E-6 * * POLE AT 150 MHZ * R10 15 98 1E6 C7 15 98 1.061E-15 G4 98 15 14 20 1E-6 * * POLE AT 100 MHZ * R11 16 98 1E6 C8 16 98 1.59E-15 G5 98 16 15 20 1E-6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 3.2 KHZ * R12 17 18 1E6 R13 18 98 1 C9 17 18 50.1E-12 E2 17 98 3 20 79.4 * * POLE AT 100 MHZ * R14 19 98 1E6 C10 19 98 1.59E-15 G6 98 19 16 20 1E-6 * * OUTPUT STAGE * R15 20 99 135E3 R16 20 50 135E3 ISY 99 50 7.4E-3 R17 25 99 172.78 R18 25 50 172.78 L2 25 26 4E-11 G7 23 50 19 25 5.79E-3 G8 24 50 25 19 5.79E-3 G9 25 99 99 19 5.79E-3 G10 50 25 19 50 5.79E-3 V4 21 25 1.5 V5 25 22 1.5 D3 19 21 DX D4 22 19 DX D5 99 23 DX D6 99 24 DX D7 50 23 DY D8 50 24 DY * * MODELS USED * .MODEL JX PJF(BETA=8.77E-3 VTO=-2.000 IS=200E-12) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP215G SPICE Macro-model 10/90, Rev. A * AN / PMI * * This version of the OP-215 model simulates the worst case * parameters of the 'G' grade. The worst case parameters * used correspond to those in the data sheet. * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP215G 1 2 99 50 26 * * INPUT STAGE & POLE AT 150 MHZ * R1 1 3 5E11 R2 2 3 5E11 R3 5 50 159 R4 6 50 159 CIN 1 2 3E-12 C2 5 6 3.33E-12 I1 99 4 1E-3 IOS 1 2 5E-11 EOS 7 1 POLY(1) 18 20 6E-3 1 J1 5 2 4 JX J2 6 7 4 JX * EREF 98 0 20 0 1 * * SECOND STAGE & POLE AT 100 HZ * R5 9 98 7.96E6 C3 9 98 200E-12 G1 98 9 5 6 6.28E-3 V2 99 8 4.12 V3 10 50 4.12 D1 9 8 DX D2 10 9 DX * * NEGATIVE ZERO AT 30 MHZ * R6 11 12 1E6 R7 12 98 1 E1 11 98 9 98 1E6 C4 11 12 -5.305E-15 * * POLE AT 200 MHZ * R8 13 98 1E6 C5 13 98 7.95E-16 G2 98 13 12 20 1E-6 * * POLE AT 100 MHZ * R9 14 98 1E6 C6 14 98 1.59E-15 G3 98 14 13 20 1E-6 * * POLE AT 150 MHZ * R10 15 98 1E6 C7 15 98 1.061E-15 G4 98 15 14 20 1E-6 * * POLE AT 100 MHZ * R11 16 98 1E6 C8 16 98 1.59E-15 G5 98 16 15 20 1E-6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 4 KHZ * R12 17 18 1E6 R13 18 98 1 C9 17 18 39.8E-12 E2 17 98 3 20 100 * * POLE AT 100 MHZ * R14 19 98 1E6 C10 19 98 1.59E-15 G6 98 19 16 20 1E-6 * * OUTPUT STAGE * R15 20 99 135E3 R16 20 50 135E3 ISY 99 50 10.9E-3 R17 25 99 172.78 R18 25 50 172.78 L2 25 26 4E-11 G7 23 50 19 25 5.79E-3 G8 24 50 25 19 5.79E-3 G9 25 99 99 19 5.79E-3 G10 50 25 19 50 5.79E-3 V4 21 25 1.4 V5 25 22 1.4 D3 19 21 DX D4 22 19 DX D5 99 23 DX D6 99 24 DX D7 50 23 DY D8 50 24 DY * * MODELS USED * .MODEL JX PJF(BETA=19.7E-3 VTO=-2.000 IS=300E-12) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP220A SPICE Macro-model 9/91, Rev. A * JCB / PMI * * This version of the OP-220 model simulates the worst case * parameters of the 'A' grade. The worst case parameters * used correspond to those in the data sheet. * * Copyright 1991 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP220A 1 2 99 50 30 * * INPUT STAGE & POLE AT 1.5 MEGHZ * R1 2 3 5E11 R2 1 3 5E11 R3 5 50 5.16K R4 6 50 5.16K CIN 1 2 4E-12 C2 5 6 15.42E-12 I1 99 4 10UA IOS 1 2 0.75E-9 EOS 9 1 POLY(1) 24 27 150E-6 1 Q1 5 2 4 QX Q2 6 9 4 QX * EREF 98 0 27 0 1 * * FIRST GAIN STAGE * R5 10 98 1E6 G1 98 10 5 6 50.27E-6 D1 10 11 DX D2 12 10 DX E1 99 11 POLY(1) 99 27 -1.475 1 E2 12 50 POLY(1) 27 50 -1.475 1 * * GAIN STAGE & DOMINANT POLE AT 0.2 HZ * R6 13 98 3.98E9 C3 13 98 200E-12 G2 98 13 10 27 5E-6 V1 99 14 1.0 V2 15 50 1.0 D3 13 14 DX D4 15 13 DX * * COMMON-MODE GAIN NETWORK WITH ZERO AT 356 HZ * R7 24 98 1 R8 23 24 1E6 C4 23 24 0.447E-9 E4 98 23 3 27 17.8 * * POLE AT 600 KHZ * R9 25 98 1E6 C5 25 98 265E-15 G3 98 25 13 27 1E-6 * * OUTPUT STAGE * ISY 99 50 48.6E-6 R10 27 99 568E3 R11 27 50 568E3 R12 30 99 2000 R13 30 50 2000 G4 28 50 25 30 0.5E-3 G5 29 50 30 25 0.5E-3 G6 30 99 99 25 0.5E-3 G7 50 30 25 50 0.5E-3 D5 99 28 DX D6 99 29 DX D7 50 28 DY D8 50 29 DY D9 25 31 DX V3 31 30 3.1 D10 32 25 DX V4 30 32 0.5 * * MODELS USED * .MODEL QX PNP(BF=250) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP220C SPICE Macro-model 4/91, Rev. A * JCB / PMI * * This version of the OP-220 model simulates the worst case * parameters of the 'C' grade. The worst case parameters * used correspond to those in the data sheet. * * Copyright 1991 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP220C 1 2 99 50 30 * * INPUT STAGE & POLE AT 1.5 MEGHZ * R1 2 3 5E11 R2 1 3 5E11 R3 5 50 5.16K R4 6 50 5.16K CIN 1 2 4E-12 C2 5 6 15.42E-12 I1 99 4 10UA IOS 1 2 1.75E-9 EOS 9 1 POLY(1) 24 27 750E-6 1 Q1 5 2 4 QX Q2 6 9 4 QX * EREF 98 0 27 0 1 * * FIRST GAIN STAGE * R5 10 98 1E6 G1 98 10 5 6 50.27E-6 D1 10 11 DX D2 12 10 DX E1 99 11 POLY(1) 99 27 -1.475 1 E2 12 50 POLY(1) 27 50 -1.475 1 * * GAIN STAGE & DOMINANT POLE AT 0.25 HZ * R6 13 98 3.18E9 C3 13 98 200E-12 G2 98 13 10 27 5E-6 V1 99 14 1.0 V2 15 50 1.0 D3 13 14 DX D4 15 13 DX * * COMMON-MODE GAIN NETWORK WITH ZERO AT 2000 HZ * R7 24 98 1 R8 23 24 1E6 C4 23 24 0.0796E-9 E4 98 23 3 27 100 * * POLE AT 600 KHZ * R9 25 98 1E6 C5 25 98 265E-15 G3 98 25 13 27 1E-6 * * OUTPUT STAGE * ISY 99 50 73.6E-6 R10 27 99 568E3 R11 27 50 568E3 R12 30 99 2000 R13 30 50 2000 G4 28 50 25 30 0.5E-3 G5 29 50 30 25 0.5E-3 G6 30 99 99 25 0.5E-3 G7 50 30 25 50 0.5E-3 D5 99 28 DX D6 99 29 DX D7 50 28 DY D8 50 29 DY D9 25 31 DX V3 31 30 3.1 D10 32 25 DX V4 30 32 0.5 * * MODELS USED * .MODEL QX PNP(BF=167) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP220E SPICE Macro-model 9/91, Rev. A * JCB / PMI * * This version of the OP-220 model simulates the worst case * parameters of the 'E' grade. The worst case parameters * used correspond to those in the data sheet. * * Copyright 1991 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP220E 1 2 99 50 30 * * INPUT STAGE & POLE AT 1.5 MEGHZ * R1 2 3 5E11 R2 1 3 5E11 R3 5 50 5.16K R4 6 50 5.16K CIN 1 2 4E-12 C2 5 6 15.42E-12 I1 99 4 10UA IOS 1 2 0.75E-9 EOS 9 1 POLY(1) 24 27 150E-6 1 Q1 5 2 4 QX Q2 6 9 4 QX * EREF 98 0 27 0 1 * * FIRST GAIN STAGE * R5 10 98 1E6 G1 98 10 5 6 50.27E-6 D1 10 11 DX D2 12 10 DX E1 99 11 POLY(1) 99 27 -1.475 1 E2 12 50 POLY(1) 27 50 -1.475 1 * * GAIN STAGE & DOMINANT POLE AT 0.2 HZ * R6 13 98 3.98E9 C3 13 98 200E-12 G2 98 13 10 27 5E-6 V1 99 14 1.0 V2 15 50 1.0 D3 13 14 DX D4 15 13 DX * * COMMON-MODE GAIN NETWORK WITH ZERO AT 356 HZ * R7 24 98 1 R8 23 24 1E6 C4 23 24 0.447E-9 E4 98 23 3 27 17.8 * * POLE AT 600 KHZ * R9 25 98 1E6 C5 25 98 265E-15 G3 98 25 13 27 1E-6 * * OUTPUT STAGE * ISY 99 50 48.6E-6 R10 27 99 568E3 R11 27 50 568E3 R12 30 99 2000 R13 30 50 2000 G4 28 50 25 30 0.5E-3 G5 29 50 30 25 0.5E-3 G6 30 99 99 25 0.5E-3 G7 50 30 25 50 0.5E-3 D5 99 28 DX D6 99 29 DX D7 50 28 DY D8 50 29 DY D9 25 31 DX V3 31 30 3.1 D10 32 25 DX V4 30 32 0.5 * * MODELS USED * .MODEL QX PNP(BF=250) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP220F SPICE Macro-model 9/91, Rev. A * JCB / PMI * * This version of the OP-220 model simulates the worst case * parameters of the 'F' grade. The worst case parameters * used correspond to those in the data sheet. * * Copyright 1991 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP220F 1 2 99 50 30 * * INPUT STAGE & POLE AT 1.5 MEGHZ * R1 2 3 5E11 R2 1 3 5E11 R3 5 50 5.16K R4 6 50 5.16K CIN 1 2 4E-12 C2 5 6 15.42E-12 I1 99 4 10UA IOS 1 2 1.0E-9 EOS 9 1 POLY(1) 24 27 300E-6 1 Q1 5 2 4 QX Q2 6 9 4 QX * EREF 98 0 27 0 1 * * FIRST GAIN STAGE * R5 10 98 1E6 G1 98 10 5 6 50.27E-6 D1 10 11 DX D2 12 10 DX E1 99 11 POLY(1) 99 27 -1.475 1 E2 12 50 POLY(1) 27 50 -1.475 1 * * GAIN STAGE & DOMINANT POLE AT 0.2 HZ * R6 13 98 3.98E9 C3 13 98 200E-12 G2 98 13 10 27 5E-6 V1 99 14 1.0 V2 15 50 1.0 D3 13 14 DX D4 15 13 DX * * COMMON-MODE GAIN NETWORK WITH ZERO AT 632 HZ * R7 24 98 1 R8 23 24 1E6 C4 23 24 0.252E-9 E4 98 23 3 27 31.6 * * POLE AT 600 KHZ * R9 25 98 1E6 C5 25 98 265E-15 G3 98 25 13 27 1E-6 * * OUTPUT STAGE * ISY 99 50 43.6E-6 R10 27 99 568E3 R11 27 50 568E3 R12 30 99 2000 R13 30 50 2000 G4 28 50 25 30 0.5E-3 G5 29 50 30 25 0.5E-3 G6 30 99 99 25 0.5E-3 G7 50 30 25 50 0.5E-3 D5 99 28 DX D6 99 29 DX D7 50 28 DY D8 50 29 DY D9 25 31 DX V3 31 30 3.1 D10 32 25 DX V4 30 32 0.5 * * MODELS USED * .MODEL QX PNP(BF=200) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP220G SPICE Macro-model 9/91, Rev. A * JCB / PMI * * This version of the OP-220 model simulates the worst case * parameters of the 'G' grade. The worst case parameters * used correspond to those in the data sheet. * * Copyright 1991 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP220G 1 2 99 50 30 * * INPUT STAGE & POLE AT 1.5 MEGHZ * R1 2 3 5E11 R2 1 3 5E11 R3 5 50 5.16K R4 6 50 5.16K CIN 1 2 4E-12 C2 5 6 15.42E-12 I1 99 4 10UA IOS 1 2 1.75E-9 EOS 9 1 POLY(1) 24 27 750E-6 1 Q1 5 2 4 QX Q2 6 9 4 QX * EREF 98 0 27 0 1 * * FIRST GAIN STAGE * R5 10 98 1E6 G1 98 10 5 6 50.27E-6 D1 10 11 DX D2 12 10 DX E1 99 11 POLY(1) 99 27 -1.475 1 E2 12 50 POLY(1) 27 50 -1.475 1 * * GAIN STAGE & DOMINANT POLE AT 0.25 HZ * R6 13 98 3.18E9 C3 13 98 200E-12 G2 98 13 10 27 5E-6 V1 99 14 1.0 V2 15 50 1.0 D3 13 14 DX D4 15 13 DX * * COMMON-MODE GAIN NETWORK WITH ZERO AT 2000 HZ * R7 24 98 1 R8 23 24 1E6 C4 23 24 0.0796E-9 E4 98 23 3 27 100 * * POLE AT 600 KHZ * R9 25 98 1E6 C5 25 98 265E-15 G3 98 25 13 27 1E-6 * * OUTPUT STAGE * ISY 99 50 73.6E-6 R10 27 99 568E3 R11 27 50 568E3 R12 30 99 2000 R13 30 50 2000 G4 28 50 25 30 0.5E-3 G5 29 50 30 25 0.5E-3 G6 30 99 99 25 0.5E-3 G7 50 30 25 50 0.5E-3 D5 99 28 DX D6 99 29 DX D7 50 28 DY D8 50 29 DY D9 25 31 DX V3 31 30 3.1 D10 32 25 DX V4 30 32 0.5 * * MODELS USED * .MODEL QX PNP(BF=167) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP221A SPICE Macro-model 9/91, Rev. A * JCB / PMI * * This version of the OP-221 model simulates the worst case * parameters of the 'A' grade. The worst case parameters * used correspond to those in the data sheet. * * Copyright 1991 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP221A 1 2 99 50 31 * * INPUT STAGE & POLE AT 1.9 MEGHZ * R1 2 3 5E11 R2 1 3 5E11 R3 5 50 5160 R4 6 50 5160 CIN 1 2 2E-12 C2 5 6 8.12E-12 I1 99 4 10E-6 IOS 1 2 1.5E-9 EOS 9 1 POLY(1) 24 27 150E-6 1 Q1 5 2 4 QX Q2 6 9 4 QX * EREF 98 0 27 0 1 * * FIRST GAIN STAGE * R5 10 98 1E6 G1 98 10 5 6 39E-6 D1 10 11 DX D2 12 10 DX E1 99 11 POLY(1) 99 27 -1.4 1 E2 12 50 POLY(1) 27 50 -1.4 1 * * GAIN STAGE & DOMINANT POLE AT 0.41 HZ * R7 13 98 7.7E9 C3 13 98 50E-12 G2 98 13 10 27 5E-6 V1 99 14 1.45 V2 15 50 1.3 D3 13 14 DX D4 15 13 DX * * POLE AT 3.0 MEGHZ * R8 16 98 1E6 C5 16 98 53.1E-15 G3 98 16 13 27 1E-6 * * POLE AT 3.0 MEGHZ * R9 17 98 1E6 C7 17 98 53.1E-15 G10 98 17 16 27 1E-6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 31.6 HZ * R10 24 98 1 R11 23 24 1E6 C4 23 24 5.033E-9 E4 98 23 3 27 31.62 * * POLE AT 3.0 MEGHZ * R12 25 98 1E6 C6 25 98 53.1E-15 G9 98 25 17 27 1E-6 * * OUTPUT STAGE * ISY 99 50 290E-6 R13 27 99 150E3 R14 27 50 150E3 R15 30 99 450 R16 30 50 450 L1 30 31 1E-8 G4 28 50 25 30 2.22E-3 G5 29 50 30 25 2.22E-3 G6 30 99 99 25 2.22E-3 G7 50 30 25 50 2.22E-3 D5 99 28 DX D6 99 29 DX D7 50 28 DY D8 50 29 DY D9 25 33 DX V3 33 30 1.6 D10 32 25 DX V4 30 32 1.6 * * MODELS USED * .MODEL QX PNP(BF=63.7) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP221B SPICE Macro-model 9/91, Rev. A * JCB / PMI * * This version of the OP-221 model simulates the worst case * parameters of the 'B' grade. The worst case parameters * used correspond to those in the data sheet. * * Copyright 1991 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP221B 1 2 99 50 31 * * INPUT STAGE & POLE AT 1.9 MEGHZ * R1 2 3 5E11 R2 1 3 5E11 R3 5 50 5160 R4 6 50 5160 CIN 1 2 2E-12 C2 5 6 8.12E-12 I1 99 4 10E-6 IOS 1 2 2.5E-9 EOS 9 1 POLY(1) 24 27 300E-6 1 Q1 5 2 4 QX Q2 6 9 4 QX * EREF 98 0 27 0 1 * * FIRST GAIN STAGE * R5 10 98 1E6 G1 98 10 5 6 39E-6 D1 10 11 DX D2 12 10 DX E1 99 11 POLY(1) 99 27 -1.4 1 E2 12 50 POLY(1) 27 50 -1.4 1 * * GAIN STAGE & DOMINANT POLE AT 0.62 HZ * R7 13 98 5.13E9 C3 13 98 50E-12 G2 98 13 10 27 5E-6 V1 99 14 1.45 V2 15 50 1.3 D3 13 14 DX D4 15 13 DX * * POLE AT 3.0 MEGHZ * R8 16 98 1E6 C5 16 98 53.1E-15 G3 98 16 13 27 1E-6 * * POLE AT 3.0 MEGHZ * R9 17 98 1E6 C7 17 98 53.1E-15 G10 98 17 16 27 1E-6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 56 HZ * R10 24 98 1 R11 23 24 1E6 C4 23 24 2.83E-9 E4 98 23 3 27 56.23 * * POLE AT 3.0 MEGHZ * R12 25 98 1E6 C6 25 98 53.1E-15 G9 98 25 17 27 1E-6 * * OUTPUT STAGE * ISY 99 50 315E-6 R13 27 99 150E3 R14 27 50 150E3 R15 30 99 450 R16 30 50 450 L1 30 31 1E-8 G4 28 50 25 30 2.22E-3 G5 29 50 30 25 2.22E-3 G6 30 99 99 25 2.22E-3 G7 50 30 25 50 2.22E-3 D5 99 28 DX D6 99 29 DX D7 50 28 DY D8 50 29 DY D9 25 33 DX V3 33 30 1.6 D10 32 25 DX V4 30 32 1.6 * * MODELS USED * .MODEL QX PNP(BF=51.3) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP221C SPICE Macro-model 9/91, Rev. A * JCB / PMI * * This version of the OP-221 model simulates the worst case * parameters of the 'C' grade. The worst case parameters * used correspond to those in the data sheet. * * Copyright 1991 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP221C 1 2 99 50 31 * * INPUT STAGE & POLE AT 1.9 MEGHZ * R1 2 3 5E11 R2 1 3 5E11 R3 5 50 5160 R4 6 50 5160 CIN 1 2 2E-12 C2 5 6 8.12E-12 I1 99 4 10E-6 IOS 1 2 3.5E-9 EOS 9 1 POLY(1) 24 27 500E-6 1 Q1 5 2 4 QX Q2 6 9 4 QX * EREF 98 0 27 0 1 * * FIRST GAIN STAGE * R5 10 98 1E6 G1 98 10 5 6 39E-6 D1 10 11 DX D2 12 10 DX E1 99 11 POLY(1) 99 27 -1.4 1 E2 12 50 POLY(1) 27 50 -1.4 1 * * GAIN STAGE & DOMINANT POLE AT 0.78 HZ * R7 13 98 4.11E9 C3 13 98 50E-12 G2 98 13 10 27 5E-6 V1 99 14 1.55 V2 15 50 1.4 D3 13 14 DX D4 15 13 DX * * POLE AT 3.0 MEGHZ * R8 16 98 1E6 C5 16 98 53.1E-15 G3 98 16 13 27 1E-6 * * POLE AT 3.0 MEGHZ * R9 17 98 1E6 C7 17 98 53.1E-15 G10 98 17 16 27 1E-6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 178 HZ * R10 24 98 1 R11 23 24 1E6 C4 23 24 0.895E-9 E4 98 23 3 27 177.8 * * POLE AT 3.0 MEGHZ * R12 25 98 1E6 C6 25 98 53.1E-15 G9 98 25 17 27 1E-6 * * OUTPUT STAGE * ISY 99 50 340E-6 R13 27 99 150E3 R14 27 50 150E3 R15 30 99 450 R16 30 50 450 L1 30 31 1E-8 G4 28 50 25 30 2.22E-3 G5 29 50 30 25 2.22E-3 G6 30 99 99 25 2.22E-3 G7 50 30 25 50 2.22E-3 D5 99 28 DX D6 99 29 DX D7 50 28 DY D8 50 29 DY D9 25 33 DX V3 33 30 1.6 D10 32 25 DX V4 30 32 1.6 * * MODELS USED * .MODEL QX PNP(BF=42.9) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP221E SPICE Macro-model 9/91, Rev. A * JCB / PMI * * This version of the OP-221 model simulates the worst case * parameters of the 'E' grade. The worst case parameters * used correspond to those in the data sheet. * * Copyright 1991 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP221E 1 2 99 50 31 * * INPUT STAGE & POLE AT 1.9 MEGHZ * R1 2 3 5E11 R2 1 3 5E11 R3 5 50 5160 R4 6 50 5160 CIN 1 2 2E-12 C2 5 6 8.12E-12 I1 99 4 10E-6 IOS 1 2 1.5E-9 EOS 9 1 POLY(1) 24 27 150E-6 1 Q1 5 2 4 QX Q2 6 9 4 QX * EREF 98 0 27 0 1 * * FIRST GAIN STAGE * R5 10 98 1E6 G1 98 10 5 6 39E-6 D1 10 11 DX D2 12 10 DX E1 99 11 POLY(1) 99 27 -1.4 1 E2 12 50 POLY(1) 27 50 -1.4 1 * * GAIN STAGE & DOMINANT POLE AT 0.41 HZ * R7 13 98 7.7E9 C3 13 98 50E-12 G2 98 13 10 27 5E-6 V1 99 14 1.45 V2 15 50 1.3 D3 13 14 DX D4 15 13 DX * * POLE AT 3.0 MEGHZ * R8 16 98 1E6 C5 16 98 53.1E-15 G3 98 16 13 27 1E-6 * * POLE AT 3.0 MEGHZ * R9 17 98 1E6 C7 17 98 53.1E-15 G10 98 17 16 27 1E-6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 31.6 HZ * R10 24 98 1 R11 23 24 1E6 C4 23 24 5.033E-9 E4 98 23 3 27 31.62 * * POLE AT 3.0 MEGHZ * R12 25 98 1E6 C6 25 98 53.1E-15 G9 98 25 17 27 1E-6 * * OUTPUT STAGE * ISY 99 50 290E-6 R13 27 99 150E3 R14 27 50 150E3 R15 30 99 450 R16 30 50 450 L1 30 31 1E-8 G4 28 50 25 30 2.22E-3 G5 29 50 30 25 2.22E-3 G6 30 99 99 25 2.22E-3 G7 50 30 25 50 2.22E-3 D5 99 28 DX D6 99 29 DX D7 50 28 DY D8 50 29 DY D9 25 33 DX V3 33 30 1.6 D10 32 25 DX V4 30 32 1.6 * * MODELS USED * .MODEL QX PNP(BF=63.7) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP221G SPICE Macro-model 9/91, Rev. A * JCB / PMI * * This version of the OP-221 model simulates the worst case * parameters of the 'G' grade. The worst case parameters * used correspond to those in the data sheet. * * Copyright 1991 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP221G 1 2 99 50 31 * * INPUT STAGE & POLE AT 1.9 MEGHZ * R1 2 3 5E11 R2 1 3 5E11 R3 5 50 5160 R4 6 50 5160 CIN 1 2 2E-12 C2 5 6 8.12E-12 I1 99 4 10E-6 IOS 1 2 3.5E-9 EOS 9 1 POLY(1) 24 27 500E-6 1 Q1 5 2 4 QX Q2 6 9 4 QX * EREF 98 0 27 0 1 * * FIRST GAIN STAGE * R5 10 98 1E6 G1 98 10 5 6 39E-6 D1 10 11 DX D2 12 10 DX E1 99 11 POLY(1) 99 27 -1.4 1 E2 12 50 POLY(1) 27 50 -1.4 1 * * GAIN STAGE & DOMINANT POLE AT 0.78 HZ * R7 13 98 4.11E9 C3 13 98 50E-12 G2 98 13 10 27 5E-6 V1 99 14 1.55 V2 15 50 1.4 D3 13 14 DX D4 15 13 DX * * POLE AT 3.0 MEGHZ * R8 16 98 1E6 C5 16 98 53.1E-15 G3 98 16 13 27 1E-6 * * POLE AT 3.0 MEGHZ * R9 17 98 1E6 C7 17 98 53.1E-15 G10 98 17 16 27 1E-6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 178 HZ * R10 24 98 1 R11 23 24 1E6 C4 23 24 0.895E-9 E4 98 23 3 27 177.8 * * POLE AT 3.0 MEGHZ * R12 25 98 1E6 C6 25 98 53.1E-15 G9 98 25 17 27 1E-6 * * OUTPUT STAGE * ISY 99 50 340E-6 R13 27 99 150E3 R14 27 50 150E3 R15 30 99 450 R16 30 50 450 L1 30 31 1E-8 G4 28 50 25 30 2.22E-3 G5 29 50 30 25 2.22E-3 G6 30 99 99 25 2.22E-3 G7 50 30 25 50 2.22E-3 D5 99 28 DX D6 99 29 DX D7 50 28 DY D8 50 29 DY D9 25 33 DX V3 33 30 1.6 D10 32 25 DX V4 30 32 1.6 * * MODELS USED * .MODEL QX PNP(BF=42.9) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP-227A * Connections: * Non-Inverting Input * | Inverting Input * | | Positive Power Supply * | | | Negative Power Supply * | | | | Output * | | | | | .SUBCKT OP227A 3 2 7 4 6 X_OP227A 3 2 7 4 6 OP27A .ENDS OP227A * * OP-27A * Linear Technology OP27A op amp model (with calls for OP27E, OP227A, OP227E) * Written: 11-21-1989 Type: Bipolar npn input, internal comp. * OP27A updated from original model on 06-20-1990 * Typical specs: * Ref. OP-27 data sheet, LTC 1990 databook p2-345 * Comments: * Uses extended phase compensation; input differential mode clamp. * * Connections: * Non-Inverting Input * | Inverting Input * | | Positive Power Supply * | | | Negative Power Supply * | | | | Output * | | | | | .SUBCKT OP27A 3 2 7 4 6 RC1 7 80 6.6315E+02 RC2 7 90 6.6315E+02 Q1 80 2 10 QM1 Q2 90 3 11 QM2 * C1 80 91 200E-12 RXC1 91 90 50 CXC1 91 90 500E-12 C2 8 98 4.000E-12 RXC2 8 98 4.00K CXC2 1 98 27.000E-12 * CIN 3 2 5E-12 DDM1 2 104 DM2 DDM3 104 3 DM2 DDM2 3 105 DM2 DDM4 105 2 DM2 RE1 10 12 -2.6233E+01 RE2 11 12 -2.6233E+01 IEE 12 4 7.5030E-05 RE 12 0 2.666E+06 CE 12 0 1.579E-12 GCM 0 8 12 0 7.558E-10 GA 8 0 80 90 1.5080E-03 R2 8 0 1.000E+05 GB 1 0 8 0 1.9176E+03 RO2 1 0 6.900E+01 * RS 1 6 1 ECL 18 0 1 6 2.828E+01 GCL 0 8 20 0 1 RCL 20 0 1E3 D1 18 20 DM1 D2 20 18 DM1 * D3A 131 70 DM3 D3B 13 131 DM3 GPL 0 8 70 7 1 VC 13 6 3.0909 RPLA 7 70 1E4 RPLB 7 131 1E5 D4A 60 141 DM3 D4B 141 14 DM3 GNL 0 8 60 4 1 VE 6 14 3.0909 RNLA 60 4 1E4 RNLB 141 4 1E5 * IP 7 4 2.625E-03 DSUB 4 7 DM2 * MODELS .MODEL QM1 NPN (IS=8.000E-16 BF=2.778E+03) .MODEL QM2 NPN (IS=8.003E-16 BF=5.769E+03) .MODEL DM1 D (IS=1.000E-19) .MODEL DM2 D (IS=8.000E-16) .MODEL DM3 D (IS=1.000E-20) .ENDS OP27A* OP-227E * Connections: * Non-Inverting Input * | Inverting Input * | | Positive Power Supply * | | | Negative Power Supply * | | | | Output * | | | | | .SUBCKT OP227E 3 2 7 4 6 X_OP227E 3 2 7 4 6 OP27A .ENDS OP227E * * OP-27A * Linear Technology OP27A op amp model (with calls for OP27E, OP227A, OP227E) * Written: 11-21-1989 Type: Bipolar npn input, internal comp. * OP27A updated from original model on 06-20-1990 * Typical specs: * Ref. OP-27 data sheet, LTC 1990 databook p2-345 * Comments: * Uses extended phase compensation; input differential mode clamp. * * Connections: * Non-Inverting Input * | Inverting Input * | | Positive Power Supply * | | | Negative Power Supply * | | | | Output * | | | | | .SUBCKT OP27A 3 2 7 4 6 RC1 7 80 6.6315E+02 RC2 7 90 6.6315E+02 Q1 80 2 10 QM1 Q2 90 3 11 QM2 * C1 80 91 200E-12 RXC1 91 90 50 CXC1 91 90 500E-12 C2 8 98 4.000E-12 RXC2 8 98 4.00K CXC2 1 98 27.000E-12 * CIN 3 2 5E-12 DDM1 2 104 DM2 DDM3 104 3 DM2 DDM2 3 105 DM2 DDM4 105 2 DM2 RE1 10 12 -2.6233E+01 RE2 11 12 -2.6233E+01 IEE 12 4 7.5030E-05 RE 12 0 2.666E+06 CE 12 0 1.579E-12 GCM 0 8 12 0 7.558E-10 GA 8 0 80 90 1.5080E-03 R2 8 0 1.000E+05 GB 1 0 8 0 1.9176E+03 RO2 1 0 6.900E+01 * RS 1 6 1 ECL 18 0 1 6 2.828E+01 GCL 0 8 20 0 1 RCL 20 0 1E3 D1 18 20 DM1 D2 20 18 DM1 * D3A 131 70 DM3 D3B 13 131 DM3 GPL 0 8 70 7 1 VC 13 6 3.0909 RPLA 7 70 1E4 RPLB 7 131 1E5 D4A 60 141 DM3 D4B 141 14 DM3 GNL 0 8 60 4 1 VE 6 14 3.0909 RNLA 60 4 1E4 RNLB 141 4 1E5 * IP 7 4 2.625E-03 DSUB 4 7 DM2 * MODELS .MODEL QM1 NPN (IS=8.000E-16 BF=2.778E+03) .MODEL QM2 NPN (IS=8.003E-16 BF=5.769E+03) .MODEL DM1 D (IS=1.000E-19) .MODEL DM2 D (IS=8.000E-16) .MODEL DM3 D (IS=1.000E-20) .ENDS OP27A* OP-227G .SUBCKT OP227G 3 2 7 4 6 X_OP227G 3 2 7 4 6 OP27C .ENDS OP227G * * OP-27C * Linear Technology OP27C op amp model (with calls for OP27G, OP227C, OP227G) * Written: 11-21-1989 Type: Bipolar npn input, internal comp. * OP27C updated from original model on 06-20-1990 * Typical specs: * Ref. OP-27 data sheet, LTC 1990 databook p2-345 * Comments: * Uses extended phase compensation; input differential mode clamp. * * Connections: * Non-Inverting Input * | Inverting Input * | | Positive Power Supply * | | | Negative Power Supply * | | | | Output * | | | | | .SUBCKT OP27C 3 2 7 4 6 RC1 7 80 6.6315E+02 RC2 7 90 6.6315E+02 Q1 80 2 10 QM1 Q2 90 3 11 QM2 * C1 80 91 200E-12 RXC1 91 90 50 CXC1 91 90 500E-12 C2 8 98 4.000E-12 RXC2 8 98 4.00K CXC2 1 98 27.000E-12 * CIN 3 2 5E-12 DDM1 2 104 DM2 DDM3 104 3 DM2 DDM2 3 105 DM2 DDM4 105 2 DM2 RE1 10 12 -2.6233E+01 RE2 11 12 -2.6233E+01 IEE 12 4 7.5030E-05 RE 12 0 2.666E+06 CE 12 0 1.579E-12 GCM 0 8 12 0 7.558E-10 GA 8 0 80 90 1.5080E-03 R2 8 0 1.000E+05 GB 1 0 8 0 1.9176E+03 RO2 1 0 6.900E+01 * RS 1 6 1 ECL 18 0 1 6 2.828E+01 GCL 0 8 20 0 1 RCL 20 0 1E3 D1 18 20 DM1 D2 20 18 DM1 * D3A 131 70 DM3 D3B 13 131 DM3 GPL 0 8 70 7 1 VC 13 6 3.0909 RPLA 7 70 1E4 RPLB 7 131 1E5 D4A 60 141 DM3 D4B 141 14 DM3 GNL 0 8 60 4 1 VE 6 14 3.0909 RNLA 60 4 1E4 RNLB 141 4 1E5 * IP 7 4 2.625E-03 DSUB 4 7 DM2 * MODELS .MODEL QM1 NPN (IS=8.0000E-16 BF=2.0000E+03) .MODEL QM2 NPN (IS=8.0093E-16 BF=4.6667E+03) .MODEL DM1 D (IS=1.000E-19) .MODEL DM2 D (IS=8.000E-16) .MODEL DM3 D (IS=1.000E-20) .ENDS OP27C* OP249A SPICE Macro-model 10/91, Rev. C * JCB / PMI * * Revision History: * REV. C * Corrected the supply current in G1 and G2 * REV. B * Re-ordered subcircuit call out nodes to put the * output node last. * Changed Ios from 25E-12 to 12.5E-12 * * * This version of the OP-249 model simulates the worst case * parameters of the 'A' grade. The worst case parameters * used correspond to those in the data book. * * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP249A 1 2 99 50 30 * * INPUT STAGE & POLE AT 100 MHZ * R1 1 3 5E11 R2 2 3 5E11 R3 5 50 469.3 R4 6 50 469.3 CIN 1 2 5E-12 C2 5 6 1.7E-12 I1 99 4 1E-3 IOS 1 2 12.5E-12 EOS 7 1 POLY(1) 20 24 500E-6 1 J1 5 2 4 JX J2 6 7 4 JX * * SECOND STAGE & POLE AT 6.1 HZ * R5 9 99 469.3E6 R6 9 50 469.3E6 C3 9 99 55.6E-12 C4 9 50 55.6E-12 G1 99 9 POLY(1) 5 6 2.4E-3 2.131E-3 G2 9 50 POLY(1) 6 5 2.4E-3 2.131E-3 V2 99 8 3.4 V3 10 50 3.4 D1 9 8 DX D2 10 9 DX * * POLE-ZERO PAIR AT 2 MHZ / 4.0 MHZ * R7 11 99 1E6 R8 11 50 1E6 R9 11 12 1E6 R10 11 13 1E6 C5 12 99 39.79E-15 C6 13 50 39.79E-15 G3 99 11 9 24 1E-6 G4 11 50 24 9 1E-6 * * ZERO-POLE PAIR AT 4 MHZ / 8 MHZ * R11 99 15 1E6 R12 14 15 1E6 R13 14 16 1E6 R14 50 16 1E6 L1 99 15 19.89E-3 L2 50 16 19.89E-3 G5 99 14 11 24 1E-6 G6 14 50 24 11 1E-6 * * POLE AT 20 MHZ * R15 17 99 1E6 R16 17 50 1E6 C9 17 99 7.96E-15 C10 17 50 7.96E-15 G7 99 17 14 24 1E-6 G8 17 50 24 14 1E-6 * * POLE AT 50 MHZ * R17 18 99 1E6 R18 18 50 1E6 C11 18 99 3.18E-15 C12 18 50 3.18E-15 G9 99 18 17 24 1E-6 G10 18 50 24 17 1E-6 * * POLE AT 50 MHZ * R19 19 99 1E6 R20 19 50 1E6 C13 19 99 3.18E-15 C14 19 50 3.18E-15 G11 99 19 18 24 1E-6 G12 19 50 24 18 1E-6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 190 KHZ * R21 20 21 1E6 R22 20 22 1E6 L3 21 99 0.837 L4 22 50 0.837 G13 99 20 3 24 100E-12 G14 20 50 24 3 100E-12 * * POLE AT 50 MHZ * R23 23 99 1E6 R24 23 50 1E6 C15 23 99 3.18E-15 C16 23 50 3.18E-15 G15 99 23 19 24 1E-6 G16 23 50 24 19 1E-6 * * OUTPUT STAGE * R25 24 99 10E6 R26 24 50 10E6 R27 29 99 70 R28 29 50 70 L5 29 30 4E-7 G17 27 50 23 29 14.3E-3 G18 28 50 29 23 14.3E-3 G19 29 99 99 23 14.3E-3 G20 50 29 23 50 14.3E-3 V4 25 29 .1 V5 29 26 .1 D3 23 25 DX D4 26 23 DX D5 99 27 DX D6 99 28 DX D7 50 27 DY D8 50 28 DY * * MODELS USED * .MODEL JX PJF(BETA=2.27E-3 VTO=-2.000 IS=75E-12) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP249E SPICE Macro-model 10/91, Rev. C * JCB / PMI * * Revision History: * REV. C * Corrected the supply current in G1 and G2 * REV. B * Re-ordered subcircuit call out nodes to put the * output node last. * Changed Ios from 15E-12 to 7.5E-12 * * * This version of the OP-249 model simulates the worst case * parameters of the 'E' grade. The worst case parameters * used correspond to those in the data book. * * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP249E 1 2 99 50 30 * * INPUT STAGE & POLE AT 100 MHZ * R1 1 3 5E11 R2 2 3 5E11 R3 5 50 469.3 R4 6 50 469.3 CIN 1 2 5E-12 C2 5 6 1.7E-12 I1 99 4 1E-3 IOS 1 2 7.5E-12 EOS 7 1 POLY(1) 20 24 300E-6 1 J1 5 2 4 JX J2 6 7 4 JX * * SECOND STAGE & POLE AT 6.1 HZ * R5 9 99 469.3E6 R6 9 50 469.3E6 C3 9 99 55.6E-12 C4 9 50 55.6E-12 G1 99 9 POLY(1) 5 6 2.4E-3 2.131E-3 G2 9 50 POLY(1) 6 5 2.4E-3 2.131E-3 V2 99 8 3.4 V3 10 50 3.4 D1 9 8 DX D2 10 9 DX * * POLE-ZERO PAIR AT 2 MHZ / 4.0 MHZ * R7 11 99 1E6 R8 11 50 1E6 R9 11 12 1E6 R10 11 13 1E6 C5 12 99 39.79E-15 C6 13 50 39.79E-15 G3 99 11 9 24 1E-6 G4 11 50 24 9 1E-6 * * ZERO-POLE PAIR AT 4 MHZ / 8 MHZ * R11 99 15 1E6 R12 14 15 1E6 R13 14 16 1E6 R14 50 16 1E6 L1 99 15 19.89E-3 L2 50 16 19.89E-3 G5 99 14 11 24 1E-6 G6 14 50 24 11 1E-6 * * POLE AT 20 MHZ * R15 17 99 1E6 R16 17 50 1E6 C9 17 99 7.96E-15 C10 17 50 7.96E-15 G7 99 17 14 24 1E-6 G8 17 50 24 14 1E-6 * * POLE AT 50 MHZ * R17 18 99 1E6 R18 18 50 1E6 C11 18 99 3.18E-15 C12 18 50 3.18E-15 G9 99 18 17 24 1E-6 G10 18 50 24 17 1E-6 * * POLE AT 50 MHZ * R19 19 99 1E6 R20 19 50 1E6 C13 19 99 3.18E-15 C14 19 50 3.18E-15 G11 99 19 18 24 1E-6 G12 19 50 24 18 1E-6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 95 KHZ * R21 20 21 1E6 R22 20 22 1E6 L3 21 99 1.67 L4 22 50 1.67 G13 99 20 3 24 50E-12 G14 20 50 24 3 50E-12 * * POLE AT 50 MHZ * R23 23 99 1E6 R24 23 50 1E6 C15 23 99 3.18E-15 C16 23 50 3.18E-15 G15 99 23 19 24 1E-6 G16 23 50 24 19 1E-6 * * OUTPUT STAGE * R25 24 99 10E6 R26 24 50 10E6 R27 29 99 70 R28 29 50 70 L5 29 30 4E-7 G17 27 50 23 29 14.3E-3 G18 28 50 29 23 14.3E-3 G19 29 99 99 23 14.3E-3 G20 50 29 23 50 14.3E-3 V4 25 29 .1 V5 29 26 .1 D3 23 25 DX D4 26 23 DX D5 99 27 DX D6 99 28 DX D7 50 27 DY D8 50 28 DY * * MODELS USED * .MODEL JX PJF(BETA=2.27E-3 VTO=-2.000 IS=50E-12) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP249F SPICE Macro-model 10/91, Rev. C * JCB / PMI * * Revision History: * REV. C * Corrected the supply current in G1 and G2 * REV. B * Re-ordered subcircuit call out nodes to put the * output node last. * Changed Ios from 25E-12 to 12.5E-12 * * * This version of the OP-249 model simulates the worst case * parameters of the 'F' grade. The worst case parameters * used correspond to those in the data book. * * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP249F 1 2 99 50 30 * * INPUT STAGE & POLE AT 100 MHZ * R1 1 3 5E11 R2 2 3 5E11 R3 5 50 469.7 R4 6 50 469.7 CIN 1 2 5E-12 C2 5 6 1.69E-12 I1 99 4 1E-3 IOS 1 2 12.5E-12 EOS 7 1 POLY(1) 20 24 700E-6 1 J1 5 2 4 JX J2 6 7 4 JX * * SECOND STAGE & POLE AT 12.2 HZ * R5 9 99 234.8E6 R6 9 50 234.8E6 C3 9 99 55.6E-12 C4 9 50 55.6E-12 G1 99 9 POLY(1) 5 6 2.4E-3 2.129E-3 G2 9 50 POLY(1) 6 5 2.4E-3 2.129E-3 V2 99 8 3.4 V3 10 50 3.4 D1 9 8 DX D2 10 9 DX * * POLE-ZERO PAIR AT 2 MHZ / 4.0 MHZ * R7 11 99 1E6 R8 11 50 1E6 R9 11 12 1E6 R10 11 13 1E6 C5 12 99 39.79E-15 C6 13 50 39.79E-15 G3 99 11 9 24 1E-6 G4 11 50 24 9 1E-6 * * ZERO-POLE PAIR AT 4 MHZ / 8 MHZ * R11 99 15 1E6 R12 14 15 1E6 R13 14 16 1E6 R14 50 16 1E6 L1 99 15 19.89E-3 L2 50 16 19.89E-3 G5 99 14 11 24 1E-6 G6 14 50 24 11 1E-6 * * POLE AT 20 MHZ * R15 17 99 1E6 R16 17 50 1E6 C9 17 99 7.96E-15 C10 17 50 7.96E-15 G7 99 17 14 24 1E-6 G8 17 50 24 14 1E-6 * * POLE AT 50 MHZ * R17 18 99 1E6 R18 18 50 1E6 C11 18 99 3.18E-15 C12 18 50 3.18E-15 G9 99 18 17 24 1E-6 G10 18 50 24 17 1E-6 * * POLE AT 50 MHZ * R19 19 99 1E6 R20 19 50 1E6 C13 19 99 3.18E-15 C14 19 50 3.18E-15 G11 99 19 18 24 1E-6 G12 19 50 24 18 1E-6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 190 KHZ * R21 20 21 1E6 R22 20 22 1E6 L3 21 99 0.837 L4 22 50 0.837 G13 99 20 3 24 100E-12 G14 20 50 24 3 100E-12 * * POLE AT 50 MHZ * R23 23 99 1E6 R24 23 50 1E6 C15 23 99 3.18E-15 C16 23 50 3.18E-15 G15 99 23 19 24 1E-6 G16 23 50 24 19 1E-6 * * OUTPUT STAGE * R25 24 99 10E6 R26 24 50 10E6 R27 29 99 70 R28 29 50 70 L5 29 30 4E-7 G17 27 50 23 29 14.3E-3 G18 28 50 29 23 14.3E-3 G19 29 99 99 23 14.3E-3 G20 50 29 23 50 14.3E-3 V4 25 29 .1 V5 29 26 .1 D3 23 25 DX D4 26 23 DX D5 99 27 DX D6 99 28 DX D7 50 27 DY D8 50 28 DY * * MODELS USED * .MODEL JX PJF(BETA=2.266E-3 VTO=-2.000 IS=75E-12) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP249G SPICE Macro-model 10/91, Rev. C * JCB / PMI * * Revision History: * REV. C * Corrected the supply current in G1 and G2 * REV. B * Re-ordered subcircuit call out nodes to put the * output node last. * Changed Ios from 25E-12 to 12.5E-12 * * * This version of the OP-249 model simulates the worst case * parameters of the 'G' grade. The worst case parameters * used correspond to those in the data book. * * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP249G 1 2 99 50 30 * * INPUT STAGE & POLE AT 100 MHZ * R1 1 3 5E11 R2 2 3 5E11 R3 5 50 469.7 R4 6 50 469.7 CIN 1 2 5E-12 C2 5 6 1.69E-12 I1 99 4 1E-3 IOS 1 2 12.5E-12 EOS 7 1 POLY(1) 20 24 2E-3 1 J1 5 2 4 JX J2 6 7 4 JX * * SECOND STAGE & POLE AT 12.2 HZ * R5 9 99 234.8E6 R6 9 50 234.8E6 C3 9 99 55.6E-12 C4 9 50 55.6E-12 G1 99 9 POLY(1) 5 6 2.4E-3 2.129E-3 G2 9 50 POLY(1) 6 5 2.4E-3 2.129E-3 V2 99 8 3.4 V3 10 50 3.4 D1 9 8 DX D2 10 9 DX * * POLE-ZERO PAIR AT 2 MHZ / 4.0 MHZ * R7 11 99 1E6 R8 11 50 1E6 R9 11 12 1E6 R10 11 13 1E6 C5 12 99 39.79E-15 C6 13 50 39.79E-15 G3 99 11 9 24 1E-6 G4 11 50 24 9 1E-6 * * ZERO-POLE PAIR AT 4 MHZ / 8 MHZ * R11 99 15 1E6 R12 14 15 1E6 R13 14 16 1E6 R14 50 16 1E6 L1 99 15 19.89E-3 L2 50 16 19.89E-3 G5 99 14 11 24 1E-6 G6 14 50 24 11 1E-6 * * POLE AT 20 MHZ * R15 17 99 1E6 R16 17 50 1E6 C9 17 99 7.96E-15 C10 17 50 7.96E-15 G7 99 17 14 24 1E-6 G8 17 50 24 14 1E-6 * * POLE AT 50 MHZ * R17 18 99 1E6 R18 18 50 1E6 C11 18 99 3.18E-15 C12 18 50 3.18E-15 G9 99 18 17 24 1E-6 G10 18 50 24 17 1E-6 * * POLE AT 50 MHZ * R19 19 99 1E6 R20 19 50 1E6 C13 19 99 3.18E-15 C14 19 50 3.18E-15 G11 99 19 18 24 1E-6 G12 19 50 24 18 1E-6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 300 KHZ * R21 20 21 1E6 R22 20 22 1E6 L3 21 99 0.530 L4 22 50 0.530 G13 99 20 3 24 158E-12 G14 20 50 24 3 158E-12 * * POLE AT 50 MHZ * R23 23 99 1E6 R24 23 50 1E6 C15 23 99 3.18E-15 C16 23 50 3.18E-15 G15 99 23 19 24 1E-6 G16 23 50 24 19 1E-6 * * OUTPUT STAGE * R25 24 99 135E3 R26 24 50 135E3 R27 29 99 70 R28 29 50 70 L5 29 30 4E-7 G17 27 50 23 29 14.3E-3 G18 28 50 29 23 14.3E-3 G19 29 99 99 23 14.3E-3 G20 50 29 23 50 14.3E-3 V4 25 29 .1 V5 29 26 .1 D3 23 25 DX D4 26 23 DX D5 99 27 DX D6 99 28 DX D7 50 27 DY D8 50 28 DY * * MODELS USED * .MODEL JX PJF(BETA=2.266E-3 VTO=-2.000 IS=75E-12) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP260 SPICE Macro-model 12/90, Rev. B * JCB / PMI * * Revision History: * REV. B * Re-ordered subcircuit call out nodes to put the * output node last. * * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP260 1 2 99 50 24 * * INPUT STAGE * R1 99 8 4E3 R2 10 50 4E3 V1 99 9 1.1 D1 9 8 DX V2 11 50 1.1 D2 10 11 DX I1 99 5 150E-6 I2 4 50 150E-6 Q1 50 3 5 QP Q2 99 3 4 QN Q3 8 6 2 QN Q4 10 7 2 QP R3 5 6 14.3E3 R4 4 7 14.3E3 C1 99 6 0.133E-12 C2 50 7 0.133E-12 * * INPUT ERROR SOURCES * GB1 99 2 POLY(1) 1 18 3E-6 4E-8 IB1 99 1 2E-7 VOS 3 1 1E-3 CS1 99 2 0.8E-12 CS2 50 2 0.8E-12 * * GAIN STAGE & DOMINANT POLE * R5 12 99 10E6 R6 12 50 10E6 C3 12 99 0.6E-12 C4 12 50 0.6E-12 G1 99 12 POLY(1) 99 8 4E-3 0.25E-3 G2 12 50 POLY(1) 10 50 4E-3 0.25E-3 V3 99 13 2.2 V4 14 50 2.2 D3 12 13 DX D4 14 12 DX * * POLE AT 80 MHZ * R7 15 99 1E6 R8 15 50 1E6 C5 15 99 2.5E-15 C6 15 50 2.5E-15 G3 99 15 12 18 1E-6 G4 15 50 18 12 1E-6 * * POLE AT 80 MHZ * R9 16 99 1E6 R10 16 50 1E6 C7 16 99 2.2E-15 C8 16 50 2.2E-15 G5 99 16 15 18 1E-6 G6 16 50 18 15 1E-6 * * POLE AT 80 MHZ * R11 17 99 1E6 R12 17 50 1E6 C9 17 99 2E-15 C10 17 50 2E-15 G7 99 17 16 18 1E-6 G8 17 50 18 16 1E-6 * * OUTPUT STAGE * R13 18 99 3.333E3 R14 18 50 3.333E3 R15 23 99 150 R16 23 50 150 L1 23 24 1.5E-8 CF1 24 2 1.8E-12 G9 21 50 17 23 6.66667E-3 G10 22 50 23 17 6.66667E-3 G11 23 99 99 17 6.66667E-3 G12 50 23 17 50 6.66667E-3 V5 19 23 1.55 V6 23 20 1.55 D5 17 19 DX D6 20 17 DX D7 99 21 DX D8 99 22 DX D9 50 21 DY D10 50 22 DY * * MODELS USED * .MODEL QN NPN(BF=1E9 IS=1E-15 VAF=150) .MODEL QP PNP(BF=1E9 IS=1E-15 VAF=150) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP262 SPICE Macro-model * 7/96, Ver. 1 * TAM / ADSC * * Copyright 1996 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance of the terms and provisions in the License * Statement. * * Node Assignments * noninverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | * | | | | | .SUBCKT OP262 1 2 99 50 45 * *INPUT STAGE * Q1 5 7 3 PIX 5 Q2 6 2 4 PIX 5 Ios 1 2 1.25E-9 I1 99 15 85E-6 EOS 7 1 POLY(1) (14,20) 45E-6 1 RC1 5 50 3.035E+3 RC2 6 50 3.035E+3 RE1 3 15 607 RE2 4 15 607 C1 5 6 600E-15 D1 3 8 DX D2 4 9 DX V1 99 8 DC 1 V2 99 9 DC 1 * * 1st GAIN STAGE * EREF 98 0 20 0 1 G1 98 10 5 6 10.5 R1 10 98 1 C2 10 98 3.3E-9 * * COMMON-MODE STAGE WITH ZERO AT 4kHz * ECM 13 98 POLY(2) (1,98) (2,98) 0 0.5 0.5 R2 13 14 1E+6 R3 14 98 70 C3 13 14 80E-12 * * POLE AT 1.5MHz, ZERO AT 3MHz * G2 21 98 10 98 .588E-6 R4 21 98 1.7E+6 R5 21 22 1.7E+6 C4 22 98 31.21E-15 * * POLE AT 6MHz, ZERO AT 3MHz * E1 23 98 21 98 2 R6 23 24 53E+3 R7 24 98 53E+3 C5 23 24 1E-12 * * SECOND GAIN STAGE * G3 25 98 24 98 40E-6 R8 25 98 1.65E+6 D3 25 99 DX D4 50 25 DX * * OUTPUT STAGE * GSY 99 50 POLY(1) (99,50) 277.5E-6 7.5E-6 R9 99 20 100E3 R10 20 50 100E3 Q3 45 41 99 POUT 4 Q4 45 43 50 NOUT 2 EB1 99 40 POLY(1) (98,25) 0.70366 1 EB2 42 50 POLY(1) (25,98) 0.73419 1 RB1 40 41 500 RB2 42 43 500 CF 45 25 11E-12 D5 46 99 DX D6 47 43 DX V3 46 41 0.7 V4 47 50 0.7 .MODEL PIX PNP (Bf=117.7) .MODEL POUT PNP (BF=119, IS=2.782E-17, VAF=28, KF=3E-7) .MODEL NOUT NPN (BF=110, IS=1.786E-17, VAF=90, KF=3E-7) .MODEL DX D() .ENDS OP262* OP275G SPICE Macro-model 10/92, Rev. B * JCB / PMI * * This version of the OP-275 model simulates the worst case * parameters of the 'G' grade. The worst case parameters * used correspond to those in the data sheet. * * Revision History: * Added common-mode input capacitance. * Corrected output short circuit current. * * Copyright 1992 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | * | | | | | .SUBCKT OP275G 1 2 99 50 34 * * INPUT STAGE & POLE AT 100 MHZ * R3 5 51 1.492 R4 6 51 1.492 CIN 1 2 3.7E-12 CM1 1 98 7.5E-12 CM2 2 98 7.5E-12 C2 5 6 533E-12 I1 97 4 100E-3 IOS 1 2 25E-9 EOS 9 3 POLY(1) 26 28 1.0E-3 1 Q1 5 2 7 QX Q2 6 9 8 QX R5 7 4 0.976 R6 8 4 0.976 D1 2 36 DZ D2 1 36 DZ EN 3 1 10 0 1 GN1 0 2 13 0 1E-3 GN2 0 1 16 0 1E-3 * EREF 98 0 28 0 1 EP 97 0 99 0 1 EM 51 0 50 0 1 * * VOLTAGE NOISE SOURCE * DN1 35 10 DEN DN2 10 11 DEN VN1 35 0 DC 2 VN2 0 11 DC 2 * * CURRENT NOISE SOURCE * DN3 12 13 DIN DN4 13 14 DIN VN3 12 0 DC 2 VN4 0 14 DC 2 * * CURRENT NOISE SOURCE * DN5 15 16 DIN DN6 16 17 DIN VN5 15 0 DC 2 VN6 0 17 DC 2 * * GAIN STAGE & DOMINANT POLE AT 64 HZ * R7 18 98 3.73E5 C3 18 98 6.67E-9 G1 98 18 5 6 6.70E-1 V2 97 19 1.76 V3 20 51 1.76 D3 18 19 DX D4 20 18 DX * * POLE/ZERO PAIR AT 1.5MHz/2.7MHz * R8 21 98 1E2 R9 21 22 1.25E2 C4 22 98 47.2E-11 G2 98 21 18 28 1E-2 * * POLE AT 100 MHZ * R10 23 98 1 C5 23 98 1.59E-9 G3 98 23 21 28 1 * * POLE AT 100 MHZ * R11 24 98 1 C6 24 98 1.59E-9 G4 98 24 23 28 1 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 20 kHZ * R12 25 26 1E6 C7 25 26 7.958E-12 R13 26 98 1 E2 25 98 POLY(2) 1 98 2 98 0 50 50 * * POLE AT 100 MHZ * R14 27 98 1 C8 27 98 1.59E-9 G5 98 27 24 28 1 * * OUTPUT STAGE * R15 28 99 100E3 R16 28 50 100E3 C9 28 50 1E-6 ISY 99 50 2.35E-3 R17 29 99 100 R18 29 50 100 L2 29 34 1E-9 G6 32 50 27 29 10E-3 G7 33 50 29 27 10E-3 G8 29 99 99 27 10E-3 G9 50 29 27 50 10E-3 V4 30 29 1.3 V5 29 31 3.8 F1 29 0 V4 1 F2 0 29 V5 1 D5 27 30 DX D6 31 27 DX D7 99 32 DX D8 99 33 DX D9 50 32 DY D10 50 33 DY * * MODELS USED * .MODEL QX PNP(BF=1.43E5) .MODEL DX D(IS=1E-12) .MODEL DY D(IS=1E-15 BV=50) .MODEL DZ D(IS=1E-15 BV=7.0) .MODEL DEN D(IS=1E-12 RS=4.35K KF=1.95E-15 AF=1) .MODEL DIN D(IS=1E-12 RS=268 KF=1.08E-15 AF=1) .ENDS * OP279G SPICE Macro-model Rev. A, 7/94 * ARG / PMI * * This version of the OP279 model simulates the worst-case * parameters of the 'G' grade. The worst-case parameters * used correspond to those in the data sheet. * * Copyright 1994 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of * this model indicates your acceptance of the terms and pro- * visions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP279G 3 2 99 50 45 * * INPUT STAGE AND POLE AT 5MHZ * I1 1 50 60.6E-6 Q1 5 2 7 QN Q2 6 4 8 QN D1 4 2 DX D2 2 4 DX R1 1 7 1.633E3 R2 1 8 1.633E3 R3 5 99 2.487E3 R4 6 99 2.487E3 C1 5 6 6.4E-12 EOS 4 3 POLY(1) (16,39) 4E-3 1 IOS 2 3 25E-9 GB1 2 98 24 98 100E-9 GB2 4 98 24 98 100E-9 CIN 2 3 1E-12 * * GAIN STAGE AND DOMINANT POLE AT 64HZ * EREF 98 0 39 0 1 G1 98 9 5 6 402.124E-6 R7 9 98 124.34E6 C2 9 98 20E-12 V1 99 10 0.58 V2 11 50 0.47 D5 9 10 DX D6 11 9 DX * * COMMON MODE STAGE WITH ZERO AT 20KHZ * ECM 15 98 POLY(2) (3,39) (2,39) 0 0.5 0.5 R9 15 16 1E6 R10 16 98 1E3 C3 15 16 7.958E-12 * * ZERO AT 1.5MHZ * E1 14 98 9 39 1E6 R5 14 18 1E6 R6 18 98 1 C4 14 18 106.103E-15 * * BIAS CURRENT-VS-COMMON MODE VOLTAGE * EP 97 0 99 0 1 EN 51 0 50 0 1 V3 20 21 1.6 V4 22 23 2.8 R12 97 20 530 R13 23 51 1E3 D13 15 21 DX D14 22 15 DX FIB 98 24 POLY(2) V3 V4 0 -1 1 RIB 24 98 10E3 E3 97 25 POLY(1) (99,39) -1.63 1 E4 26 51 POLY(1) (39,50) -2.73 1 D15 24 25 DX D16 26 24 DX * * POLE AT 6MHZ * G6 98 40 18 39 1E-6 R20 40 98 1E6 C10 40 98 26.526E-15 * * OUTPUT STAGE * RS1 99 39 6.0345E3 RS2 39 50 6.0345E3 RO1 99 45 40 RO2 45 50 40 G7 45 99 99 40 25E-3 G8 50 45 40 50 25E-3 G9 98 60 45 40 25E-3 D9 60 61 DX D10 62 60 DX V7 61 98 DC 0 V8 98 62 DC 0 FSY 99 50 POLY(2) V7 V8 2.611E-3 1 1 D11 41 45 DZ D12 45 42 DZ V5 40 41 0.95 V6 42 40 0.95 .MODEL DX D() .MODEL DZ D(IS=1E-6) .MODEL QN NPN(BF=100) .ENDS * OP27A SPICE Macro-model 12/90, Rev. B * JCB / PMI * * Revision History: * REV. B * Re-ordered subcircuit call out nodes to put the * output node last. * Changed Ios from 35E-9 to 17.5E-9 * Added F1 and F2 to fix short circuit current limit. * * * This version of the OP-27 model simulates the worst case * parameters of the 'A' grade. The worst case parameters * used correspond to those in the data book. * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP27A 1 2 99 50 39 * * INPUT STAGE & POLE AT 80 MHZ * R3 5 97 0.0619 R4 6 97 0.0619 CIN 1 2 4E-12 C2 5 6 16.07E-9 I1 4 51 1 IOS 1 2 17.5E-9 EOS 9 10 POLY(1) 30 33 25E-6 1 Q1 5 2 7 QX Q2 6 9 8 QX R5 7 4 0.0107 R6 8 4 0.0107 D1 2 1 DX D2 1 2 DX EN 10 1 12 0 1 GN1 0 2 15 0 1 GN2 0 1 18 0 1 * EREF 98 0 33 0 1 EPLUS 97 0 99 0 1 ENEG 51 0 50 0 1 * * VOLTAGE NOISE SOURCE WITH FLICKER NOISE * DN1 11 12 DEN DN2 12 13 DEN VN1 11 0 DC 2 VN2 0 13 DC 2 * * CURRENT NOISE SOURCE WITH FLICKER NOISE * DN3 14 15 DIN DN4 15 16 DIN VN3 14 0 DC 2 VN4 0 16 DC 2 * * SECOND CURRENT NOISE SOURCE * DN5 17 18 DIN DN6 18 19 DIN VN5 17 0 DC 2 VN6 0 19 DC 2 * * FIRST GAIN STAGE * RG1 40 98 1 GG1 98 40 5 6 79.86 DG3 40 41 DX DG4 42 40 DX EG1 97 41 POLY(1) 97 33 -2.1 1 EG2 42 51 POLY(1) 97 33 -2.1 1 * * GAIN STAGE & DOMINANT POLE AT 7.2 HZ * R7 20 98 37.58E3 C3 20 98 588E-9 G1 98 20 40 33 0.333 V1 97 21 1.9 V2 22 51 1.9 D5 20 21 DX D6 22 20 DX * * POLE - ZERO AT 2.9MHZ / 6MHZ * R8 23 98 1 R9 23 24 0.935 C4 24 98 28.4E-9 G2 98 23 20 33 1 * * ZERO - POLE AT 6.8MHZ / 40MHZ * R10 25 26 1 R11 26 98 4.88 L1 26 98 19.4E-9 G3 98 25 23 33 1 * * POLE AT 60 MHZ * R12 27 98 1 C5 27 98 2.65E-9 G4 98 27 25 33 1 * * ZERO AT 28 MHZ * R13 28 29 1 C6 28 29 -5.68E-9 R14 29 98 1E-6 E1 28 98 27 33 1E6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 11.9 KHZ * R15 30 31 1 L2 31 98 13.3E-6 G5 98 30 POLY(2) 1 33 2 33 0 997.6E-9 997.6E-9 D7 30 97 DX D8 51 30 DX * * POLE AT 80 MHZ * R16 32 98 1 C7 32 98 1.99E-9 G6 98 32 29 33 1 * * OUTPUT STAGE * R17 33 97 1 R18 33 51 1 GSY 99 50 POLY(1) 99 50 3.47E-3 40E-6 F1 34 0 V3 1 F2 0 34 V4 1 R19 34 99 180 R20 34 50 180 L3 34 39 1E-7 G7 37 50 32 34 5.56E-3 G8 38 50 34 32 5.56E-3 G9 34 99 99 32 5.56E-3 G10 50 34 32 50 5.56E-3 V3 35 34 2.5 V4 34 36 3.1 D9 32 35 DX D10 36 32 DX D11 99 37 DX D12 99 38 DX D13 50 37 DY D14 50 38 DY * * MODELS USED * .MODEL QX NPN(BF=12.5E6) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .MODEL DEN D(IS=1E-12, RS=1.74K, KF=4.01E-16, AF=1) .MODEL DIN D(IS=1E-12, RS=43.5E-6, KF=11.1E-15, AF=1) .ENDS * OP27B SPICE Macro-model 12/90, Rev. B * JCB / PMI * * Revision History: * REV. B * Re-ordered subcircuit call out nodes to put the * output node last. * Changed Ios from 50E-9 to 25E-9 * Added F1 and F2 to fix short circuit current limit. * * * This version of the OP-27 model simulates the worst case * parameters of the 'B' grade. The worst case parameters * used correspond to those in the data book. * * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP27B 1 2 99 50 39 * * INPUT STAGE & POLE AT 80 MHZ * R3 5 97 0.0619 R4 6 97 0.0619 CIN 1 2 4E-12 C2 5 6 16.07E-9 I1 4 51 1 IOS 1 2 25E-9 EOS 9 10 POLY(1) 30 33 60E-6 1 Q1 5 2 7 QX Q2 6 9 8 QX R5 7 4 0.0107 R6 8 4 0.0107 D1 2 1 DX D2 1 2 DX EN 10 1 12 0 1 GN1 0 2 15 0 1 GN2 0 1 18 0 1 * EREF 98 0 33 0 1 EPLUS 97 0 99 0 1 ENEG 51 0 50 0 1 * * VOLTAGE NOISE SOURCE WITH FLICKER NOISE * DN1 11 12 DEN DN2 12 13 DEN VN1 11 0 DC 2 VN2 0 13 DC 2 * * CURRENT NOISE SOURCE WITH FLICKER NOISE * DN3 14 15 DIN DN4 15 16 DIN VN3 14 0 DC 2 VN4 0 16 DC 2 * * SECOND CURRENT NOISE SOURCE * DN5 17 18 DIN DN6 18 19 DIN VN5 17 0 DC 2 VN6 0 19 DC 2 * * FIRST GAIN STAGE * RG1 40 98 1 GG1 98 40 5 6 79.86 DG3 40 41 DX DG4 42 40 DX EG1 97 41 POLY(1) 97 33 -2.1 1 EG2 42 51 POLY(1) 97 33 -2.1 1 * * GAIN STAGE & DOMINANT POLE AT 7.2 HZ * R7 20 98 37.58E3 C3 20 98 588E-9 G1 98 20 40 33 0.333 V1 97 21 1.9 V2 22 51 1.9 D5 20 21 DX D6 22 20 DX * * POLE - ZERO AT 2.9MHZ / 6MHZ * R8 23 98 1 R9 23 24 0.935 C4 24 98 28.4E-9 G2 98 23 20 33 1 * * ZERO - POLE AT 6.8MHZ / 40MHZ * R10 25 26 1 R11 26 98 4.88 L1 26 98 19.4E-9 G3 98 25 23 33 1 * * POLE AT 60 MHZ * R12 27 98 1 C5 27 98 2.65E-9 G4 98 27 25 33 1 * * ZERO AT 28 MHZ * R13 28 29 1 C6 28 29 -5.68E-9 R14 29 98 1E-6 E1 28 98 27 33 1E6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 30 KHZ * R15 30 31 1 L2 31 98 5.30E-6 G5 98 30 POLY(2) 1 33 2 33 0 2.51E-6 2.51E-6 D7 30 97 DX D8 51 30 DX * * POLE AT 80 MHZ * R16 32 98 1 C7 32 98 1.99E-9 G6 98 32 29 33 1 * * OUTPUT STAGE * R17 33 97 1 R18 33 51 1 GSY 99 50 POLY(1) 99 50 3.47E-3 40E-6 F1 34 0 V3 1 F2 0 34 V4 1 R19 34 99 180 R20 34 50 180 L3 34 39 1E-7 G7 37 50 32 34 5.56E-3 G8 38 50 34 32 5.56E-3 G9 34 99 99 32 5.56E-3 G10 50 34 32 50 5.56E-3 V3 35 34 2.5 V4 34 36 3.1 D9 32 35 DX D10 36 32 DX D11 99 37 DX D12 99 38 DX D13 50 37 DY D14 50 38 DY * * MODELS USED * .MODEL QX NPN(BF=9.09E6) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .MODEL DEN D(IS=1E-12, RS=1.74K, KF=4.01E-16, AF=1) .MODEL DIN D(IS=1E-12, RS=43.5E-6, KF=11.1E-15, AF=1) .ENDS * OP27C SPICE Macro-model 12/90, Rev. B * JCB / PMI * * Revision History: * REV. B * Re-ordered subcircuit call out nodes to put the * output node last. * Changed Ios from 75E-9 to 37.5E-9 * Added F1 and F2 to fix short circuit current limit. * * * This version of the OP-27 model simulates the worst case * parameters of the 'C' grade. The worst case parameters * used correspond to those in the data book. * * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP27C 1 2 99 50 39 * * INPUT STAGE & POLE AT 80 MHZ * R3 5 97 0.0619 R4 6 97 0.0619 CIN 1 2 4E-12 C2 5 6 16.07E-9 I1 4 51 1 IOS 1 2 37.5E-9 EOS 9 10 POLY(1) 30 33 100E-6 1 Q1 5 2 7 QX Q2 6 9 8 QX R5 7 4 0.0107 R6 8 4 0.0107 D1 2 1 DX D2 1 2 DX EN 10 1 12 0 1 GN1 0 2 15 0 1 GN2 0 1 18 0 1 * EREF 98 0 33 0 1 EPLUS 97 0 99 0 1 ENEG 51 0 50 0 1 * * VOLTAGE NOISE SOURCE WITH FLICKER NOISE * DN1 11 12 DEN DN2 12 13 DEN VN1 11 0 DC 2 VN2 0 13 DC 2 * * CURRENT NOISE SOURCE WITH FLICKER NOISE * DN3 14 15 DIN DN4 15 16 DIN VN3 14 0 DC 2 VN4 0 16 DC 2 * * SECOND CURRENT NOISE SOURCE * DN5 17 18 DIN DN6 18 19 DIN VN5 17 0 DC 2 VN6 0 19 DC 2 * * FIRST GAIN STAGE * RG1 40 98 1 GG1 98 40 5 6 79.88 DG3 40 41 DX DG4 42 40 DX EG1 97 41 POLY(1) 97 33 -2.1 1 EG2 42 51 POLY(1) 97 33 -2.1 1 * * GAIN STAGE & DOMINANT POLE AT 10.3 HZ * R7 20 98 26.32E3 C3 20 98 588E-9 G1 98 20 40 33 0.333 V1 97 21 2.4 V2 22 51 2.4 D5 20 21 DX D6 22 20 DX * * POLE - ZERO AT 2.9MHZ / 6MHZ * R8 23 98 1 R9 23 24 0.935 C4 24 98 28.4E-9 G2 98 23 20 33 1 * * ZERO - POLE AT 6.8MHZ / 40MHZ * R10 25 26 1 R11 26 98 4.88 L1 26 98 19.4E-9 G3 98 25 23 33 1 * * POLE AT 60 MHZ * R12 27 98 1 C5 27 98 2.65E-9 G4 98 27 25 33 1 * * ZERO AT 28 MHZ * R13 28 29 1 C6 28 29 -5.68E-9 R14 29 98 1E-6 E1 28 98 27 33 1E6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 60 KHZ * R15 30 31 1 L2 31 98 2.66E-6 G5 98 30 POLY(2) 1 33 2 33 0 5.0E-6 5.0E-6 D7 30 97 DX D8 51 30 DX * * POLE AT 80 MHZ * R16 32 98 1 C7 32 98 1.99E-9 G6 98 32 29 33 1 * * OUTPUT STAGE * R17 33 97 1 R18 33 51 1 GSY 99 50 POLY(1) 99 50 4.47E-3 40E-6 F1 34 0 V3 1 F2 0 34 V4 1 R19 34 99 180 R20 34 50 180 L3 34 39 1E-7 G7 37 50 32 34 5.56E-3 G8 38 50 34 32 5.56E-3 G9 34 99 99 32 5.56E-3 G10 50 34 32 50 5.56E-3 V3 35 34 2.5 V4 34 36 3.1 D9 32 35 DX D10 36 32 DX D11 99 37 DX D12 99 38 DX D13 50 37 DY D14 50 38 DY * * MODELS USED * .MODEL QX NPN(BF=6.25E6) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .MODEL DEN D(IS=1E-12, RS=2.45K, KF=7.93E-16, AF=1) .MODEL DIN D(IS=1E-12, RS=43.5E-6, KF=11.1E-15, AF=1) .ENDS * OP27E SPICE Macro-model 12/90, Rev. B * JCB / PMI * * Revision History: * REV. B * Re-ordered subcircuit call out nodes to put the * output node last. * Changed Ios from 35E-9 to 17.5E-9 * Added F1 and F2 to fix short circuit current limit. * * * This version of the OP-27 model simulates the worst case * parameters of the 'E' grade. The worst case parameters * used correspond to those in the data book. * * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP27E 1 2 99 50 39 * * INPUT STAGE & POLE AT 80 MHZ * R3 5 97 0.0619 R4 6 97 0.0619 CIN 1 2 4E-12 C2 5 6 16.07E-9 I1 4 51 1 IOS 1 2 17.5E-9 EOS 9 10 POLY(1) 30 33 25E-6 1 Q1 5 2 7 QX Q2 6 9 8 QX R5 7 4 0.0107 R6 8 4 0.0107 D1 2 1 DX D2 1 2 DX EN 10 1 12 0 1 GN1 0 2 15 0 1 GN2 0 1 18 0 1 * EREF 98 0 33 0 1 EPLUS 97 0 99 0 1 ENEG 51 0 50 0 1 * * VOLTAGE NOISE SOURCE WITH FLICKER NOISE * DN1 11 12 DEN DN2 12 13 DEN VN1 11 0 DC 2 VN2 0 13 DC 2 * * CURRENT NOISE SOURCE WITH FLICKER NOISE * DN3 14 15 DIN DN4 15 16 DIN VN3 14 0 DC 2 VN4 0 16 DC 2 * * SECOND CURRENT NOISE SOURCE * DN5 17 18 DIN DN6 18 19 DIN VN5 17 0 DC 2 VN6 0 19 DC 2 * * FIRST GAIN STAGE * RG1 40 98 1 GG1 98 40 5 6 79.86 DG3 40 41 DX DG4 42 40 DX EG1 97 41 POLY(1) 97 33 -2.1 1 EG2 42 51 POLY(1) 97 33 -2.1 1 * * GAIN STAGE & DOMINANT POLE AT 7.2 HZ * R7 20 98 37.58E3 C3 20 98 588E-9 G1 98 20 40 33 0.333 V1 97 21 1.9 V2 22 51 1.9 D5 20 21 DX D6 22 20 DX * * POLE - ZERO AT 2.9MHZ / 6MHZ * R8 23 98 1 R9 23 24 0.935 C4 24 98 28.4E-9 G2 98 23 20 33 1 * * ZERO - POLE AT 6.8MHZ / 40MHZ * R10 25 26 1 R11 26 98 4.88 L1 26 98 19.4E-9 G3 98 25 23 33 1 * * POLE AT 60 MHZ * R12 27 98 1 C5 27 98 2.65E-9 G4 98 27 25 33 1 * * ZERO AT 28 MHZ * R13 28 29 1 C6 28 29 -5.68E-9 R14 29 98 1E-6 E1 28 98 27 33 1E6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 11.9 KHZ * R15 30 31 1 L2 31 98 13.3E-6 G5 98 30 POLY(2) 1 33 2 33 0 997.6E-9 997.6E-9 D7 30 97 DX D8 51 30 DX * * POLE AT 80 MHZ * R16 32 98 1 C7 32 98 1.99E-9 G6 98 32 29 33 1 * * OUTPUT STAGE * R17 33 97 1 R18 33 51 1 GSY 99 50 POLY(1) 99 50 3.47E-3 40E-6 F1 34 0 V3 1 F2 0 34 V4 1 R19 34 99 180 R20 34 50 180 L3 34 39 1E-7 G7 37 50 32 34 5.56E-3 G8 38 50 34 32 5.56E-3 G9 34 99 99 32 5.56E-3 G10 50 34 32 50 5.56E-3 V3 35 34 2.5 V4 34 36 3.1 D9 32 35 DX D10 36 32 DX D11 99 37 DX D12 99 38 DX D13 50 37 DY D14 50 38 DY * * MODELS USED * .MODEL QX NPN(BF=12.5E6) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .MODEL DEN D(IS=1E-12, RS=1.74K, KF=4.01E-16, AF=1) .MODEL DIN D(IS=1E-12, RS=43.5E-6, KF=11.1E-15, AF=1) .ENDS * OP27F SPICE Macro-model 12/90, Rev. B * JCB / PMI * * Revision History: * REV. B * Re-ordered subcircuit call out nodes to put the * output node last. * Changed Ios from 50E-9 to 25E-9 * Added F1 and F2 to fix short circuit current limit. * * * This version of the OP-27 model simulates the worst case * parameters of the 'F' grade. The worst case parameters * used correspond to those in the data book. * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP27F 1 2 99 50 39 * * INPUT STAGE & POLE AT 80 MHZ * R3 5 97 0.0619 R4 6 97 0.0619 CIN 1 2 4E-12 C2 5 6 16.07E-9 I1 4 51 1 IOS 1 2 25E-9 EOS 9 10 POLY(1) 30 33 60E-6 1 Q1 5 2 7 QX Q2 6 9 8 QX R5 7 4 0.0107 R6 8 4 0.0107 D1 2 1 DX D2 1 2 DX EN 10 1 12 0 1 GN1 0 2 15 0 1 GN2 0 1 18 0 1 * EREF 98 0 33 0 1 EPLUS 97 0 99 0 1 ENEG 51 0 50 0 1 * * VOLTAGE NOISE SOURCE WITH FLICKER NOISE * DN1 11 12 DEN DN2 12 13 DEN VN1 11 0 DC 2 VN2 0 13 DC 2 * * CURRENT NOISE SOURCE WITH FLICKER NOISE * DN3 14 15 DIN DN4 15 16 DIN VN3 14 0 DC 2 VN4 0 16 DC 2 * * SECOND CURRENT NOISE SOURCE * DN5 17 18 DIN DN6 18 19 DIN VN5 17 0 DC 2 VN6 0 19 DC 2 * * FIRST GAIN STAGE * RG1 40 98 1 GG1 98 40 5 6 79.86 DG3 40 41 DX DG4 42 40 DX EG1 97 41 POLY(1) 97 33 -2.1 1 EG2 42 51 POLY(1) 97 33 -2.1 1 * * GAIN STAGE & DOMINANT POLE AT 7.2 HZ * R7 20 98 37.58E3 C3 20 98 588E-9 G1 98 20 40 33 0.333 V1 97 21 1.9 V2 22 51 1.9 D5 20 21 DX D6 22 20 DX * * POLE - ZERO AT 2.9MHZ / 6MHZ * R8 23 98 1 R9 23 24 0.935 C4 24 98 28.4E-9 G2 98 23 20 33 1 * * ZERO - POLE AT 6.8MHZ / 40MHZ * R10 25 26 1 R11 26 98 4.88 L1 26 98 19.4E-9 G3 98 25 23 33 1 * * POLE AT 60 MHZ * R12 27 98 1 C5 27 98 2.65E-9 G4 98 27 25 33 1 * * ZERO AT 28 MHZ * R13 28 29 1 C6 28 29 -5.68E-9 R14 29 98 1E-6 E1 28 98 27 33 1E6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 30 KHZ * R15 30 31 1 L2 31 98 5.3E-6 G5 98 30 POLY(2) 1 33 2 33 0 2.51E-6 2.51E-6 D7 30 97 DX D8 51 30 DX * * POLE AT 80 MHZ * R16 32 98 1 C7 32 98 1.99E-9 G6 98 32 29 33 1 * * OUTPUT STAGE * R17 33 97 1 R18 33 51 1 GSY 99 50 POLY(1) 99 50 3.47E-3 40E-6 F1 34 0 V3 1 F2 0 34 V4 1 R19 34 99 180 R20 34 50 180 L3 34 39 1E-7 G7 37 50 32 34 5.56E-3 G8 38 50 34 32 5.56E-3 G9 34 99 99 32 5.56E-3 G10 50 34 32 50 5.56E-3 V3 35 34 2.5 V4 34 36 3.1 D9 32 35 DX D10 36 32 DX D11 99 37 DX D12 99 38 DX D13 50 37 DY D14 50 38 DY * * MODELS USED * .MODEL QX NPN(BF=9.09E6) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .MODEL DEN D(IS=1E-12, RS=1.74K, KF=4.01E-16, AF=1) .MODEL DIN D(IS=1E-12, RS=43.5E-6, KF=11.1E-15, AF=1) .ENDS * OP27G SPICE Macro-model 12/90, Rev. B * JCB / PMI * * Revision History: * REV. B * Re-ordered subcircuit call out nodes to put the * output node last. * Changed Ios from 75E-9 to 37.5E-9 * Added F1 and F2 to fix short circuit current limit. * * * This version of the OP-27 model simulates the worst case * parameters of the 'G' grade. The worst case parameters * used correspond to those in the data book. * * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP27G 1 2 99 50 39 * * INPUT STAGE & POLE AT 80 MHZ * R3 5 97 0.0619 R4 6 97 0.0619 CIN 1 2 4E-12 C2 5 6 16.07E-9 I1 4 51 1 IOS 1 2 37.5E-9 EOS 9 10 POLY(1) 30 33 100E-6 1 Q1 5 2 7 QX Q2 6 9 8 QX R5 7 4 0.0107 R6 8 4 0.0107 D1 2 1 DX D2 1 2 DX EN 10 1 12 0 1 GN1 0 2 15 0 1 GN2 0 1 18 0 1 * EREF 98 0 33 0 1 EPLUS 97 0 99 0 1 ENEG 51 0 50 0 1 * * VOLTAGE NOISE SOURCE WITH FLICKER NOISE * DN1 11 12 DEN DN2 12 13 DEN VN1 11 0 DC 2 VN2 0 13 DC 2 * * CURRENT NOISE SOURCE WITH FLICKER NOISE * DN3 14 15 DIN DN4 15 16 DIN VN3 14 0 DC 2 VN4 0 16 DC 2 * * SECOND CURRENT NOISE SOURCE * DN5 17 18 DIN DN6 18 19 DIN VN5 17 0 DC 2 VN6 0 19 DC 2 * * FIRST GAIN STAGE * RG1 40 98 1 GG1 98 40 5 6 79.88 DG3 40 41 DX DG4 42 40 DX EG1 97 41 POLY(1) 97 33 -2.1 1 EG2 42 51 POLY(1) 97 33 -2.1 1 * * GAIN STAGE & DOMINANT POLE AT 10.3 HZ * R7 20 98 26.32E3 C3 20 98 588E-9 G1 98 20 40 33 0.333 V1 97 21 2.4 V2 22 51 2.4 D5 20 21 DX D6 22 20 DX * * POLE - ZERO AT 2.9MHZ / 6MHZ * R8 23 98 1 R9 23 24 0.935 C4 24 98 28.4E-9 G2 98 23 20 33 1 * * ZERO - POLE AT 6.8MHZ / 40MHZ * R10 25 26 1 R11 26 98 4.88 L1 26 98 19.4E-9 G3 98 25 23 33 1 * * POLE AT 60 MHZ * R12 27 98 1 C5 27 98 2.65E-9 G4 98 27 25 33 1 * * ZERO AT 28 MHZ * R13 28 29 1 C6 28 29 -5.68E-9 R14 29 98 1E-6 E1 28 98 27 33 1E6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 60 KHZ * R15 30 31 1 L2 31 98 2.66E-6 G5 98 30 POLY(2) 1 33 2 33 0 5.0E-6 5.0E-6 D7 30 97 DX D8 51 30 DX * * POLE AT 80 MHZ * R16 32 98 1 C7 32 98 1.99E-9 G6 98 32 29 33 1 * * OUTPUT STAGE * R17 33 97 1 R18 33 51 1 GSY 99 50 POLY(1) 99 50 4.47E-3 40E-6 F1 34 0 V3 1 F2 0 34 V4 1 R19 34 99 180 R20 34 50 180 L3 34 39 1E-7 G7 37 50 32 34 5.56E-3 G8 38 50 34 32 5.56E-3 G9 34 99 99 32 5.56E-3 G10 50 34 32 50 5.56E-3 V3 35 34 2.5 V4 34 36 3.1 D9 32 35 DX D10 36 32 DX D11 99 37 DX D12 99 38 DX D13 50 37 DY D14 50 38 DY * * MODELS USED * .MODEL QX NPN(BF=6.25E6) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .MODEL DEN D(IS=1E-12, RS=2.45K, KF=7.93E-16, AF=1) .MODEL DIN D(IS=1E-12, RS=43.5E-6, KF=11.1E-15, AF=1) .ENDS * OP281 SPICE Macro-model * 7/97, Ver. 1 * TAM / ADSC * * Copyright 1996,1997 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of this * model indicates your acceptance of the terms and provisions in * the License Statement. * * Node Assignments * noninverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | * | | | | | .SUBCKT OP281 1 2 99 50 45 * * INPUT STAGE * Q1 4 1 3 PIX Q2 6 7 5 PIX I1 99 8 1.28E-6 EOS 7 2 POLY(1) (12,98) 80E-6 1 IOS 1 2 1E-10 RC1 4 50 500E3 RC2 6 50 500E3 RE1 3 8 108 RE2 5 8 108 V1 99 13 DC .9 V2 99 14 DC .9 D1 3 13 DX D2 5 14 DX * * CMRR 76dB, ZERO AT 1kHz * ECM1 11 98 POLY(2) (1,98) (2,98) 0 .5 .5 R1 11 12 1.59E6 C1 11 12 100E-12 R2 12 98 283 * * POLE AT 900kHz * EREF 98 0 90 0 1 G1 98 20 4 6 1E-6 R3 20 98 1E6 C2 20 98 177E-15 * * POLE AT 500kHz * E2 21 98 20 98 1 R4 21 22 1E6 C3 22 98 320E-15 * * GAIN STAGE * CF 45 40 8.5E-12 R5 40 98 65.65E6 G3 98 40 22 98 4.08E-7 D3 40 41 DX D4 42 40 DX V3 99 41 DC 0.5 V4 42 50 DC 0.5 * * OUTPUT STAGE * ISY 99 50 1.375E-6 RS1 99 90 10E6 RS2 90 50 10E6 M1 48 46 99 99 POX L=1.5u W=300u M2 49 47 50 50 NOX L=1.5u W=300u RO1 48 45 400 RO2 49 45 200 EG1 99 46 POLY(1) (98,40) 0.77 1 EG2 47 50 POLY(1) (40,98) 0.77 1 * * MODELS * .MODEL POX PMOS (LEVEL=2, KP=25E-6, VTO=-0.75, LAMBDA=0.01) .MODEL NOX NMOS (LEVEL=2, KP=25E-6, VTO=0.75, LAMBDA=0.01) .MODEL PIX PNP (BF=200) .MODEL DX D(IS=1E-14) .ENDS OP281* OP282 SPICE Macro-model 8/91, Rev. A * JCB / PMI * * Copyright 1991 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP282 1 2 99 50 30 * * INPUT STAGE & POLE AT 15 MHZ * R1 1 3 5E11 R2 2 3 5E11 R3 5 50 3871.3 R4 6 50 3871.3 CIN 1 2 5E-12 C2 5 6 1.37E-12 I1 99 4 0.1E-3 IOS 1 2 5E-13 EOS 7 1 POLY(1) 21 24 200E-6 1 J1 5 2 4 JX J2 6 7 4 JX * EREF 98 0 24 0 1 * * GAIN STAGE & POLE AT 124 HZ * R5 9 98 1.16E8 C3 9 98 1.11E-11 G1 98 9 5 6 2.58E-4 V2 99 8 1.2 V3 10 50 1.2 D1 9 8 DX D2 10 9 DX * * NEGATIVE ZERO AT 4 MHZ * R6 11 12 1E6 R7 12 98 1 C4 11 12 39.8E-15 E2 11 98 9 24 1E6 * * POLE AT 15 MHZ * R8 13 98 1E6 C5 13 98 10.6E-15 G2 98 13 12 24 1E-6 * * POLE AT 15 MHZ * R9 14 98 1E6 C6 14 98 10.6E-15 G3 98 14 13 24 1E-6 * * POLE AT 15 MHZ * R19 19 98 1E6 C13 19 98 10.6E-15 G11 98 19 14 24 1E-6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 11 KHZ * R21 20 21 1E6 R22 21 98 1 C14 20 21 14.38E-12 E13 98 20 3 24 31.62 * * POLE AT 15 MHZ * R23 23 98 1E6 C15 23 98 10.6E-15 G15 98 23 19 24 1E-6 * * OUTPUT STAGE * R25 24 99 5E6 R26 24 50 5E6 ISY 99 50 107E-6 R27 29 99 700 R28 29 50 700 L5 29 30 1E-8 G17 27 50 23 29 1.43E-3 G18 28 50 29 23 1.43E-3 G19 29 99 99 23 1.43E-3 G20 50 29 23 50 1.43E-3 V4 25 29 2.8 V5 29 26 3.5 D3 23 25 DX D4 26 23 DX D5 99 27 DX D6 99 28 DX D7 50 27 DY D8 50 28 DY * * MODELS USED * .MODEL JX PJF(BETA=3.34E-4 VTO=-2.000 IS=3E-12) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP282G SPICE Macro-model 4/92, Rev. A * JCB / PMI * * This version of the OP-282 model simulates the worst case * parameters of the 'G' grade. The worst case parameters * used correspond to those in the data sheet. * * Copyright 1991 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP282G 1 2 99 50 30 * * INPUT STAGE & POLE AT 15 MHZ * R1 1 3 5E11 R2 2 3 5E11 R3 5 50 3011 R4 6 50 3011 CIN 1 2 5E-12 C2 5 6 1.76E-12 I1 99 4 0.1E-3 IOS 1 2 2.5E-11 EOS 7 1 POLY(1) 21 24 3E-3 1 J1 5 2 4 JX J2 6 7 4 JX * EREF 98 0 24 0 1 * * GAIN STAGE & POLE AT 185 HZ * R5 9 98 6.02E7 C3 9 98 1.43E-11 G1 98 9 5 6 3.32E-4 V2 99 8 1.2 V3 10 50 1.2 D1 9 8 DX D2 10 9 DX * * NEGATIVE ZERO AT 4 MHZ * R6 11 12 1E6 R7 12 98 1 C4 11 12 39.8E-15 E2 11 98 9 24 1E6 * * POLE AT 15 MHZ * R8 13 98 1E6 C5 13 98 10.6E-15 G2 98 13 12 24 1E-6 * * POLE AT 15 MHZ * R9 14 98 1E6 C6 14 98 10.6E-15 G3 98 14 13 24 1E-6 * * POLE AT 15 MHZ * R19 19 98 1E6 C13 19 98 10.6E-15 G11 98 19 14 24 1E-6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 110 KHZ * R21 20 21 1E6 R22 21 98 1 C14 20 21 1.438E-12 E13 98 20 3 24 316.2 * * POLE AT 15 MHZ * R23 23 98 1E6 C15 23 98 10.6E-15 G15 98 23 19 24 1E-6 * * OUTPUT STAGE * R25 24 99 5E6 R26 24 50 5E6 ISY 99 50 147E-6 R27 29 99 700 R28 29 50 700 L5 29 30 1E-8 G17 27 50 23 29 1.43E-3 G18 28 50 29 23 1.43E-3 G19 29 99 99 23 1.43E-3 G20 50 29 23 50 1.43E-3 V4 25 29 0.35 V5 29 26 2.1 D3 23 25 DX D4 26 23 DX D5 99 27 DX D6 99 28 DX D7 50 27 DY D8 50 28 DY * * MODELS USED * .MODEL JX PJF(BETA=5.51E-4 VTO=-2.000 IS=1E-10) .MODEL DX D(IS=1E-15 RS=1) .MODEL DY D(IS=1E-15 BV=50 RS=1) .ENDS * OP283G SPICE Macro-model Rev. A, 3/94 * ARG / PMI * * This version of the OP283 model simulates the worst-case * parameters of the 'G' grade. The worst-case parameters * used correspond to those in the data sheet. * * Copyright 1993 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of * this model indicates your acceptance of the terms and pro- * visions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP283G 2 1 99 50 45 * * INPUT STAGE AND POLE AT 600KHZ * I1 99 8 1E-4 Q1 4 1 6 QP Q2 5 3 7 QP CIN 1 2 1.5PF R1 50 4 796 R2 50 5 796 C1 4 5 167E-12 R3 6 8 279 R4 7 8 279 IOS 1 2 25E-9 EOS 3 2 POLY(1) (15,98) 1E-3 1 DC1 2 36 DZ DC2 1 36 DZ * * GAIN STAGE AND DOMINANT POLE AT 100HZ * EREF 98 0 POLY(2) (99,0) (50,0) 0 0.5 0.5 G1 98 9 4 5 1.257E-3 R5 9 98 79.577E6 C2 9 98 20E-12 D1 9 10 DX D2 11 9 DX E1 10 98 POLY(1) 99 98 -1.6185 1.0623 V2 50 11 -0.666 * * COMMON MODE STAGE WITH ZERO AT 17.7KHZ * ECM 14 98 POLY(2) (1,98) (2,98) 0 158 158 R7 14 15 1E6 C4 14 15 9E-12 R8 15 98 1 * * POLE AT 20MHZ * GP2 98 31 9 98 1E-6 RP2 31 98 1E6 CP2 31 98 7.96E-15 * * ZERO AT 1.5MHZ * EZ1 32 98 31 98 1E6 RZ1 32 33 1E6 RZ2 33 98 1 CZ1 32 33 106E-15 * * POLE AT 10MHZ * GP10 98 40 33 98 1E-6 RP10 40 98 1E6 CP10 40 98 15.9E-15 * * OUTPUT STAGE * RO1 99 45 140 RO2 45 50 140 G7 45 99 99 40 7.143E-3 G8 50 45 40 50 7.143E-3 G9 98 60 45 40 7.143E-3 D7 60 61 DX D8 62 60 DX V7 61 98 DC 0 V8 98 62 DC 0 GSY 99 50 99 50 5E-6 FSY 99 50 POLY(2) V7 V8 1.375E-3 1 1 D9 40 41 DX D10 42 40 DX V5 41 45 1.2 V6 45 42 1.5 * * MODELS USED * .MODEL DX D .MODEL DZ D(IS=1E-15 BV=7.0) .MODEL QP PNP(BF=82.333) .ENDS * OP284E SPICE Macro-model 11/95 / Rev. B * ARG / ADSC * * Revision History: * * Rev. B * Changed the short-circuit output current limit from +/- 7.5mA * to +/- 6.5mA to reflect final data sheet limits. * * Changed Vos spec to conform to final data sheet value of * 65uV, up from 50uV. * * * This version of the OP284 model simulates the worst-case * parameters of the 'E' grade. The worst-case parameters * used correspond to those in the data sheet. * * Copyright 1993 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance of the terms and provisions in the License * Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP284E 1 2 99 50 45 * * INPUT STAGE * Q1 5 2 3 QIN 1 Q2 6 11 3 QIN 1 Q3 7 2 4 QIP 1 Q4 8 11 4 QIP 1 DC1 2 11 DC DC2 11 2 DC Q5 4 9 99 QIP 1 Q6 9 9 99 QIP 1 Q7 3 10 50 QIN 1 Q8 10 10 50 QIN 1 R1 99 5 4E3 R2 99 6 4E3 R3 7 50 4E3 R4 8 50 4E3 IREF 9 10 50.5E-6 EOS 1 11 POLY(2) (22,98) (14,98) -65E-6 501.2E-3 1 IOS 2 1 25E-9 CIN 1 2 2E-12 GN1 98 1 17 98 1E-3 GN2 98 2 23 98 1E-3 * * VOLTAGE NOISE SOURCE WITH FLICKER NOISE * VN1 13 98 DC 2 VN2 98 15 DC 2 DN1 13 14 DEN DN2 14 15 DEN * * CURRENT NOISE SOURCE WITH FLICKER NOISE * VN3 16 98 DC 2 VN4 98 18 DC 2 DN3 16 17 DIN DN4 17 18 DIN * * 2ND CURRENT NOISE SOURCE WITH FLICKER NOISE * VN5 19 98 DC 2 VN6 98 24 DC 2 DN5 19 23 DIN DN6 23 24 DIN * * GAIN STAGE * EREF 98 0 POLY(2) (99,0) (50,0) 0 0.5 0.5 G1 98 20 POLY(2) (6,5) (8,7) 0 0.5E-3 0.5E-3 R9 20 98 1E3 * * COMMON MODE STAGE WITH ZERO AT 5KHZ * ECM 98 21 POLY(2) (1,98) (2,98) 0 0.5 0.5 R10 21 22 1 R11 22 98 100E-6 C4 21 22 31.756E-6 * * NEGATIVE ZERO AT 20MHZ * E1 27 98 20 98 1 R17 27 28 1 R18 28 98 1E-6 C8 25 26 7.958E-9 ENZ 25 98 27 28 1 VNZ 26 98 DC 0 FNZ 27 28 VNZ -1 * * POLE AT 40MHZ * G4 98 29 28 98 1E6 R19 29 98 1 C9 29 98 3.979E-9 * * POLE AT 40MHZ * G5 98 30 29 98 1 R20 30 98 1 C10 30 98 3.979E-9 * * OUTUT STAGE * ISY 99 50 0.526E-3 GIN 50 31 POLY(1) (30,98) 0.862574E-6 511.855E-6 RIN 31 50 2.75E6 VB 99 32 0.7 Q11 32 31 33 QON 1 R21 33 34 4.5E3 I1 34 50 50E-6 R22 99 35 6E3 Q12 36 36 35 QOP 1 I2 36 50 50E-6 R23 99 37 2.6E3 R24 34 38 5E3 Q13 39 36 37 QOP 1 Q14 39 38 40 QON 1.5 R25 40 50 40 Q15 39 39 41 QON 1 R26 41 42 1E3 R27 99 43 220 Q16 44 44 43 QOP 1.5 Q17 44 39 42 QON 1 R28 42 50 2E3 VSCP 99 97 DC 0 FSCP 46 99 VSCP 1 RSCP 46 99 125 Q20 44 46 99 QOP 1 Q18 45 44 97 QOP 4.5 Q19 45 34 51 QON 4.5 VSCN 51 50 DC 0 FSCN 50 47 VSCN 1 RSCN 47 50 122 Q21 34 47 50 QON 1 CC2 31 45 20E-12 CF1 31 34 15E-12 CF2 31 42 15E-12 CO1 34 45 15E-12 CO2 42 45 5E-12 D3 45 99 DX D4 50 45 DX .MODEL DC D(IS=130E-21) .MODEL DX D() .MODEL DEN D(RS=100 KF=12E-15 AF=1) .MODEL DIN D(RS=5.358 KF=56E-15 AF=1) .MODEL QIN NPN(BF=250 VA=200 IS=0.5E-16) .MODEL QIP PNP(BF=60 VA=100 IS=0.5E-16) .MODEL QON NPN(BF=200 VA=200 IS=0.5E-16 RC=140) .MODEL QOP PNP(BF=200 VA=200 IS=0.5E-16 RC=210) .ENDS * OP284F SPICE Macro-model 11/95 / Rev. B * ARG / ADSC * * Revision History: * * Rev. B * Changed the short-circuit output current limit from +/- 7.5mA * to +/- 6.5mA to reflect final data sheet limits. * * Changed Vos spec to conform to final data sheet value of * 125uV, up from 50uV. * * * This version of the OP284 model simulates the worst-case * parameters of the 'F' grade. The worst-case parameters * used correspond to those in the data sheet. * * Copyright 1993 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance of the terms and provisions in the License * Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP284F 1 2 99 50 45 * * INPUT STAGE * Q1 5 2 3 QIN 1 Q2 6 11 3 QIN 1 Q3 7 2 4 QIP 1 Q4 8 11 4 QIP 1 DC1 2 11 DC DC2 11 2 DC Q5 4 9 99 QIP 1 Q6 9 9 99 QIP 1 Q7 3 10 50 QIN 1 Q8 10 10 50 QIN 1 R1 99 5 4E3 R2 99 6 4E3 R3 7 50 4E3 R4 8 50 4E3 IREF 9 10 50.5E-6 EOS 1 11 POLY(2) (22,98) (14,98) -125E-6 501.2E-3 1 IOS 2 1 25E-9 CIN 1 2 2E-12 GN1 98 1 17 98 1E-3 GN2 98 2 23 98 1E-3 * * VOLTAGE NOISE SOURCE WITH FLICKER NOISE * VN1 13 98 DC 2 VN2 98 15 DC 2 DN1 13 14 DEN DN2 14 15 DEN * * CURRENT NOISE SOURCE WITH FLICKER NOISE * VN3 16 98 DC 2 VN4 98 18 DC 2 DN3 16 17 DIN DN4 17 18 DIN * * 2ND CURRENT NOISE SOURCE WITH FLICKER NOISE * VN5 19 98 DC 2 VN6 98 24 DC 2 DN5 19 23 DIN DN6 23 24 DIN * * GAIN STAGE * EREF 98 0 POLY(2) (99,0) (50,0) 0 0.5 0.5 G1 98 20 POLY(2) (6,5) (8,7) 0 0.5E-3 0.5E-3 R9 20 98 1E3 * * COMMON MODE STAGE WITH ZERO AT 5KHZ * ECM 98 21 POLY(2) (1,98) (2,98) 0 0.5 0.5 R10 21 22 1 R11 22 98 100E-6 C4 21 22 31.756E-6 * * NEGATIVE ZERO AT 20MHZ * E1 27 98 20 98 1 R17 27 28 1 R18 28 98 1E-6 C8 25 26 7.958E-9 ENZ 25 98 27 28 1 VNZ 26 98 DC 0 FNZ 27 28 VNZ -1 * * POLE AT 40MHZ * G4 98 29 28 98 1E6 R19 29 98 1 C9 29 98 3.979E-9 * * POLE AT 40MHZ * G5 98 30 29 98 1 R20 30 98 1 C10 30 98 3.979E-9 * * OUTUT STAGE * ISY 99 50 0.526E-3 GIN 50 31 POLY(1) (30,98) 0.862574E-6 511.855E-6 RIN 31 50 2.75E6 VB 99 32 0.7 Q11 32 31 33 QON 1 R21 33 34 4.5E3 I1 34 50 50E-6 R22 99 35 6E3 Q12 36 36 35 QOP 1 I2 36 50 50E-6 R23 99 37 2.6E3 R24 34 38 5E3 Q13 39 36 37 QOP 1 Q14 39 38 40 QON 1.5 R25 40 50 40 Q15 39 39 41 QON 1 R26 41 42 1E3 R27 99 43 220 Q16 44 44 43 QOP 1.5 Q17 44 39 42 QON 1 R28 42 50 2E3 VSCP 99 97 DC 0 FSCP 46 99 VSCP 1 RSCP 46 99 125 Q20 44 46 99 QOP 1 Q18 45 44 97 QOP 4.5 Q19 45 34 51 QON 4.5 VSCN 51 50 DC 0 FSCN 50 47 VSCN 1 RSCN 47 50 122 Q21 34 47 50 QON 1 CC2 31 45 20E-12 CF1 31 34 15E-12 CF2 31 42 15E-12 CO1 34 45 15E-12 CO2 42 45 5E-12 D3 45 99 DX D4 50 45 DX .MODEL DC D(IS=130E-21) .MODEL DX D() .MODEL DEN D(RS=100 KF=12E-15 AF=1) .MODEL DIN D(RS=5.358 KF=56E-15 AF=1) .MODEL QIN NPN(BF=250 VA=200 IS=0.5E-16) .MODEL QIP PNP(BF=60 VA=100 IS=0.5E-16) .MODEL QON NPN(BF=200 VA=200 IS=0.5E-16 RC=140) .MODEL QOP PNP(BF=200 VA=200 IS=0.5E-16 RC=210) .ENDS * OP285 SPICE Macro-model 6/92, Rev. A * ARG / PMI * * Copyright 1992 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | * | | | | | .SUBCKT OP285 1 2 99 50 34 * * INPUT STAGE & POLE AT 100 MHZ * R3 5 51 2.188 R4 6 51 2.188 CIN 1 2 1.5E-12 C2 5 6 364E-12 I1 97 4 100E-3 IOS 1 2 1E-9 EOS 9 3 POLY(1) 26 28 35E-6 1 Q1 5 2 7 QX Q2 6 9 8 QX R5 7 4 1.672 R6 8 4 1.672 D1 2 36 DZ D2 1 36 DZ EN 3 1 10 0 1 GN1 0 2 13 0 1 GN2 0 1 16 0 1 * EREF 98 0 28 0 1 EP 97 0 99 0 1 EM 51 0 50 0 1 * * VOLTAGE NOISE SOURCE * DN1 35 10 DEN DN2 10 11 DEN VN1 35 0 DC 2 VN2 0 11 DC 2 * * CURRENT NOISE SOURCE * DN3 12 13 DIN DN4 13 14 DIN VN3 12 0 DC 2 VN4 0 14 DC 2 CN1 13 0 7.53E-3 * * CURRENT NOISE SOURCE * DN5 15 16 DIN DN6 16 17 DIN VN5 15 0 DC 2 VN6 0 17 DC 2 CN2 16 0 7.53E-3 * * GAIN STAGE & DOMINANT POLE AT 32 HZ * R7 18 98 1.09E6 C3 18 98 4.55E-9 G1 98 18 5 6 4.57E-1 V2 97 19 1.4 V3 20 51 1.4 D3 18 19 DX D4 20 18 DX * * POLE/ZERO PAIR AT 1.5MHz/2.7MHz * R8 21 98 1E3 R9 21 22 1.25E3 C4 22 98 47.2E-12 G2 98 21 18 28 1E-3 * * POLE AT 100 MHZ * R10 23 98 1 C5 23 98 1.59E-9 G3 98 23 21 28 1 * * POLE AT 100 MHZ * R11 24 98 1 C6 24 98 1.59E-9 G4 98 24 23 28 1 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 1 kHZ * R12 25 26 1E6 C7 25 26 159.155E-12 R13 26 98 1 E2 25 98 POLY(2) 1 98 2 98 0 2.506 2.506 * * POLE AT 100 MHZ * R14 27 98 1 C8 27 98 1.59E-9 G5 98 27 24 28 1 * * OUTPUT STAGE * R15 28 99 100E3 R16 28 50 100E3 C9 28 50 1E-6 ISY 99 50 1.85E-3 R17 29 99 100 R18 29 50 100 L2 29 34 1E-9 G6 32 50 27 29 10E-3 G7 33 50 29 27 10E-3 G8 29 99 99 27 10E-3 G9 50 29 27 50 10E-3 V4 30 29 1.3 V5 29 31 3.8 F1 29 0 V4 1 F2 0 29 V5 1 D5 27 30 DX D6 31 27 DX D7 99 32 DX D8 99 33 DX D9 50 32 DY D10 50 33 DY * * MODELS USED * .MODEL QX PNP(BF=5E5) .MODEL DX D(IS=1E-12) .MODEL DY D(IS=1E-15 BV=50) .MODEL DZ D(IS=1E-15 BV=7.0) .MODEL DEN D(IS=1E-12 RS=4.35K KF=1.95E-15 AF=1) .MODEL DIN D(IS=1E-12 RS=77.3E-6 KF=3.38E-15 AF=1) .ENDS * OP285G SPICE Macro-model 4/92, Rev. A * ARG / PMI * * This version of the OP-285 model simulates the worst case * parameters of the 'G' grade. The worst case parameters * used correspond to those in the data sheet. * * Copyright 1992 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | * | | | | | .SUBCKT OP285G 1 2 99 50 34 * * INPUT STAGE & POLE AT 100 MHZ * R3 5 51 1.492 R4 6 51 1.492 CIN 1 2 1.5E-12 C2 5 6 533E-12 I1 97 4 100E-3 IOS 1 2 25E-9 EOS 9 3 POLY(1) 26 28 1.0E-3 1 Q1 5 2 7 QX Q2 6 9 8 QX R5 7 4 0.976 R6 8 4 0.976 D1 2 36 DZ D2 1 36 DZ EN 3 1 10 0 1 GN1 0 2 13 0 1 GN2 0 1 16 0 1 * EREF 98 0 28 0 1 EP 97 0 99 0 1 EM 51 0 50 0 1 * * VOLTAGE NOISE SOURCE * DN1 35 10 DEN DN2 10 11 DEN VN1 35 0 DC 2 VN2 0 11 DC 2 * * CURRENT NOISE SOURCE * DN3 12 13 DIN DN4 13 14 DIN VN3 12 0 DC 2 VN4 0 14 DC 2 CN1 13 0 7.53E-3 * * CURRENT NOISE SOURCE * DN5 15 16 DIN DN6 16 17 DIN VN5 15 0 DC 2 VN6 0 17 DC 2 CN2 16 0 7.53E-3 * * GAIN STAGE & DOMINANT POLE AT 64 HZ * R7 18 98 3.73E5 C3 18 98 6.67E-9 G1 98 18 5 6 6.70E-1 V2 97 19 1.76 V3 20 51 1.76 D3 18 19 DX D4 20 18 DX * * POLE/ZERO PAIR AT 1.5MHz/2.7MHz * R8 21 98 1E3 R9 21 22 1.25E3 C4 22 98 47.2E-12 G2 98 21 18 28 1E-3 * * POLE AT 100 MHZ * R10 23 98 1 C5 23 98 1.59E-9 G3 98 23 21 28 1 * * POLE AT 100 MHZ * R11 24 98 1 C6 24 98 1.59E-9 G4 98 24 23 28 1 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 20 kHZ * R12 25 26 1E6 C7 25 26 7.958E-12 R13 26 98 1 E2 25 98 POLY(2) 1 98 2 98 0 100 0 100 * * POLE AT 100 MHZ * R14 27 98 1 C8 27 98 1.59E-9 G5 98 27 24 28 1 * * OUTPUT STAGE * R15 28 99 100E3 R16 28 50 100E3 C9 28 50 1E-6 ISY 99 50 2.35E-3 R17 29 99 100 R18 29 50 100 L2 29 34 1E-9 G6 32 50 27 29 10E-3 G7 33 50 29 27 10E-3 G8 29 99 99 27 10E-3 G9 50 29 27 50 10E-3 V4 30 29 3.8 V5 29 31 1.3 F1 29 0 V4 1 F2 0 29 V5 1 D5 27 30 DX D6 31 27 DX D7 99 32 DX D8 99 33 DX D9 50 32 DY D10 50 33 DY * * MODELS USED * .MODEL QX PNP(BF=1.43E5) .MODEL DX D(IS=1E-12) .MODEL DY D(IS=1E-15 BV=50) .MODEL DZ D(IS=1E-15 BV=7.0) .MODEL DEN D(IS=1E-12 RS=4.35K KF=1.95E-15 AF=1) .MODEL DIN D(IS=1E-12 RS=77.3E-6 KF=3.38E-15 AF=1) .ENDS * OP290A SPICE Macro-model 10/92, Rev. C * JCB / PMI * * Revision History: * REV. C * Altered gain stage for proper open-loop gain. * REV. B * Re-ordered subcircuit call out nodes to put the * output node last. * Changed Ios from 3E-9 to 1.5E-9 * * * This version of the OP-290 model simulates the worst case * parameters of the 'A' grade. The worst case parameters * used correspond to those in the data book. * * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP290A 1 2 99 50 31 * * INPUT STAGE & POLE AT 10 KHZ * R1 2 3 5E11 R2 1 3 5E11 R3 5 51 61.6E3 R4 6 51 61.6E3 CIN 1 2 4E-12 C2 5 6 129.2E-12 I1 97 4 1E-6 IOS 1 2 1.5E-9 EOS 9 1 POLY(1) 23 27 200E-6 1 Q1 5 2 7 QX Q2 6 9 8 QX R5 7 4 10E3 R6 8 4 10E3 * EREF 98 0 27 0 1 EPLUS 97 0 99 0 1 ENEG 51 0 50 0 1 * * FIRST GAIN STAGE * R7 10 98 1E6 G1 98 10 5 6 101.47E-6 D1 10 11 DX D2 12 10 DX E1 97 11 POLY(1) 97 27 -1.4 1 E2 12 51 POLY(1) 27 51 -1.4 1 * * GAIN STAGE & DOMINANT POLE AT 0.323 HZ * R8 13 98 2.464E6 C3 13 98 200E-9 G2 98 13 10 27 0.5E-3 H2 97 14 POLY(1) VS2 2.2 -3E3 E5 15 51 POLY(2) (17,51) (97,27) 2.0 1.5 -0.405 D3 13 14 DX D4 15 13 DX * * ZERO-IN ZERO-OUT CLAMP * F1 51 17 VS2 -1000 RS1 17 51 1E9 D5 17 51 DX D6 51 17 DX * * NEGATIVE ZERO AT -100 KHZ * R9 19 20 1E6 C4 19 20 -1.59E-12 R10 20 98 1 E3 19 98 13 27 1E6 * * ZERO - POLE PAIR AT 28 KHZ / 100 KHZ * R11 21 22 1E6 L1 22 98 4.09 R12 22 98 2.57E6 G3 98 21 20 27 1E-6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 126 HZ * R13 23 24 1E6 L2 24 98 1.257E3 G4 98 23 3 27 1E-11 D8 23 97 DX D9 51 23 DX * * ZERO - POLE PAIR AT 40 KHZ / 160 KHZ * R14 25 26 1E6 L3 26 98 2.98 R15 26 98 3E6 G5 98 25 21 27 1E-6 * * OUTPUT STAGE * ISY 99 50 14.444E-6 R16 27 99 2.7E6 R17 27 50 2.7E6 R18 30 99 6000 R19 30 50 6000 VS2 30 31 DC 0 G6 28 50 25 30 166.7E-6 G7 29 50 30 25 166.7E-6 G8 30 99 99 25 166.7E-6 G9 50 30 25 50 166.7E-6 D10 99 28 DX D11 99 29 DX D12 50 28 DY D13 50 29 DY * * MODELS USED * .MODEL QX PNP(BF=33.333) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP290E SPICE Macro-model 10/92, Rev. c * JCB / PMI * * Revision History: * REV. C * Altered gain stage for proper open-loop gain. * REV. B * Re-ordered subcircuit call out nodes to put the * output node last. * Changed Ios from 3E-9 to 1.5E-9 * * * This version of the OP-290 model simulates the worst case * parameters of the 'E' grade. The worst case parameters * used correspond to those in the data book. * * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP290E 1 2 99 50 31 * * INPUT STAGE & POLE AT 10 KHZ * R1 2 3 5E11 R2 1 3 5E11 R3 5 51 61.6E3 R4 6 51 61.6E3 CIN 1 2 4E-12 C2 5 6 129.2E-12 I1 97 4 1E-6 IOS 1 2 1.5E-9 EOS 9 1 POLY(1) 23 27 200E-6 1 Q1 5 2 7 QX Q2 6 9 8 QX R5 7 4 10E3 R6 8 4 10E3 * EREF 98 0 27 0 1 EPLUS 97 0 99 0 1 ENEG 51 0 50 0 1 * * FIRST GAIN STAGE * R7 10 98 1E6 G1 98 10 5 6 101.47E-6 D1 10 11 DX D2 12 10 DX E1 97 11 POLY(1) 97 27 -1.4 1 E2 12 51 POLY(1) 27 51 -1.4 1 * * GAIN STAGE & DOMINANT POLE AT 0.323 HZ * R8 13 98 2.464E6 C3 13 98 200E-9 G2 98 13 10 27 0.5E-3 H2 97 14 POLY(1) VS2 2.2 -3E3 E5 15 51 POLY(2) (17,51) (97,27) 2.0 1.5 -0.405 D3 13 14 DX D4 15 13 DX * * ZERO-IN ZERO-OUT CLAMP * F1 51 17 VS2 -1000 RS1 17 51 1E9 D5 17 51 DX D6 51 17 DX * * NEGATIVE ZERO AT -100 KHZ * R9 19 20 1E6 C4 19 20 -1.59E-12 R10 20 98 1 E3 19 98 13 27 1E6 * * ZERO - POLE PAIR AT 28 KHZ / 100 KHZ * R11 21 22 1E6 L1 22 98 4.09 R12 22 98 2.57E6 G3 98 21 20 27 1E-6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 123 HZ * R13 23 24 1E6 L2 24 98 1.257E3 G4 98 23 3 27 1E-11 D8 23 97 DX D9 51 23 DX * * ZERO - POLE PAIR AT 40 KHZ / 160 KHZ * R14 25 26 1E6 L3 26 98 2.98 R15 26 98 3E6 G5 98 25 21 27 1E-6 * * OUTPUT STAGE * ISY 99 50 14.444E-6 R16 27 99 2.7E6 R17 27 50 2.7E6 R18 30 99 6000 R19 30 50 6000 VS2 30 31 DC 0 G6 28 50 25 30 166.7E-6 G7 29 50 30 25 166.7E-6 G8 30 99 99 25 166.7E-6 G9 50 30 25 50 166.7E-6 D10 99 28 DX D11 99 29 DX D12 50 28 DY D13 50 29 DY * * MODELS USED * .MODEL QX PNP(BF=33.333) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP290F SPICE Macro-model 10/92, Rev. C * JCB / PMI * * Revision History: * REV. C * Altered gain stage for proper open-loop gain. * REV. B * Re-ordered subcircuit call out nodes to put the * output node last. * Changed Ios from 5E-9 to 2.5E-9 * * * This version of the OP-290 model simulates the worst case * parameters of the 'F' grade. The worst case parameters * used correspond to those in the data book. * * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP290F 1 2 99 50 31 * * INPUT STAGE & POLE AT 10 KHZ * R1 2 3 5E11 R2 1 3 5E11 R3 5 51 61.6E3 R4 6 51 61.6E3 CIN 1 2 4E-12 C2 5 6 129.2E-12 I1 97 4 1E-6 IOS 1 2 2.5E-9 EOS 9 1 POLY(1) 23 27 300E-6 1 Q1 5 2 7 QX Q2 6 9 8 QX R5 7 4 10E3 R6 8 4 10E3 * EREF 98 0 27 0 1 EPLUS 97 0 99 0 1 ENEG 51 0 50 0 1 * * FIRST GAIN STAGE * R7 10 98 1E6 G1 98 10 5 6 101.36E-6 D1 10 11 DX D2 12 10 DX E1 97 11 POLY(1) 97 27 -1.4 1 E2 12 51 POLY(1) 27 51 -1.4 1 * * GAIN STAGE & DOMINANT POLE AT 0.403 HZ * R8 13 98 1.973E6 C3 13 98 200E-9 G2 98 13 10 27 0.5E-3 H2 97 14 POLY(1) VS2 2.2 -3E3 E5 15 51 POLY(2) (17,51) (97,27) 2.0 1.5 -0.405 D3 13 14 DX D4 15 13 DX * * ZERO-IN ZERO-OUT CLAMP * F1 51 17 VS2 -1000 RS1 17 51 1E9 D5 17 51 DX D6 51 17 DX * * NEGATIVE ZERO AT -100 KHZ * R9 19 20 1E6 C4 19 20 -1.59E-12 R10 20 98 1 E3 19 98 13 27 1E6 * * ZERO - POLE PAIR AT 28 KHZ / 100 KHZ * R11 21 22 1E6 L1 22 98 4.09 R12 22 98 2.57E6 G3 98 21 20 27 1E-6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 400 HZ * R13 23 24 1E6 L2 24 98 397.9 G4 98 23 3 27 3.162E-11 D8 23 97 DX D9 51 23 DX * * ZERO - POLE PAIR AT 40 KHZ / 160 KHZ * R14 25 26 1E6 L3 26 98 2.98 R15 26 98 3E6 G5 98 25 21 27 1E-6 * * OUTPUT STAGE * ISY 99 50 14.444E-6 R16 27 99 2.7E6 R17 27 50 2.7E6 R18 30 99 6000 R19 30 50 6000 VS2 30 31 DC 0 G6 28 50 25 30 166.7E-6 G7 29 50 30 25 166.7E-6 G8 30 99 99 25 166.7E-6 G9 50 30 25 50 166.7E-6 D10 99 28 DX D11 99 29 DX D12 50 28 DY D13 50 29 DY * * MODELS USED * .MODEL QX PNP(BF=25) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP290G SPICE Macro-model 10/92, Rev. C * JCB / PMI * * Revision History: * REV. C * Altered gain stage for proper open-loop gain. * REV. B * Re-ordered subcircuit call out nodes to put the * output node last. * Changed Ios from 5E-9 to 2.5E-9 * * * This version of the OP-290 model simulates the worst case * parameters of the 'G' grade. The worst case parameters * used correspond to those in the data book. * * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP290G 1 2 99 50 31 * * INPUT STAGE & POLE AT 10 KHZ * R1 2 3 5E11 R2 1 3 5E11 R3 5 51 61.6E3 R4 6 51 61.6E3 CIN 1 2 4E-12 C2 5 6 129.2E-12 I1 97 4 1E-6 IOS 1 2 2.5E-9 EOS 9 1 POLY(1) 23 27 500E-6 1 Q1 5 2 7 QX Q2 6 9 8 QX R5 7 4 10E3 R6 8 4 10E3 * EREF 98 0 27 0 1 EPLUS 97 0 99 0 1 ENEG 51 0 50 0 1 * * FIRST GAIN STAGE * R7 10 98 1E6 G1 98 10 5 6 101.36E-6 D1 10 11 DX D2 12 10 DX E1 97 11 POLY(1) 97 27 -1.4 1 E2 12 51 POLY(1) 27 51 -1.4 1 * * GAIN STAGE & DOMINANT POLE AT 0.403 HZ * R8 13 98 1.973E6 C3 13 98 200E-9 G2 98 13 10 27 0.5E-3 H2 97 14 POLY(1) VS2 2.2 -3E3 E5 15 51 POLY(2) (17,51) (97,27) 2.0 1.5 -0.405 D3 13 14 DX D4 15 13 DX * * ZERO-IN ZERO-OUT CLAMP * F1 51 17 VS2 -1000 RS1 17 51 1E9 D5 17 51 DX D6 51 17 DX * * NEGATIVE ZERO AT -100 KHZ * R9 19 20 1E6 C4 19 20 -1.59E-12 R10 20 98 1 E3 19 98 13 27 1E6 * * ZERO - POLE PAIR AT 28 KHZ / 100 KHZ * R11 21 22 1E6 L1 22 98 4.09 R12 22 98 2.57E6 G3 98 21 20 27 1E-6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 400 HZ * R13 23 24 1E6 L2 24 98 397.9 G4 98 23 3 27 3.162E-11 D8 23 97 DX D9 51 23 DX * * ZERO - POLE PAIR AT 40 KHZ / 160 KHZ * R14 25 26 1E6 L3 26 98 2.98 R15 26 98 3E6 G5 98 25 21 27 1E-6 * * OUTPUT STAGE * ISY 99 50 14.444E-6 R16 27 99 2.7E6 R17 27 50 2.7E6 R18 30 99 6000 R19 30 50 6000 VS2 30 31 DC 0 G6 28 50 25 30 166.7E-6 G7 29 50 30 25 166.7E-6 G8 30 99 99 25 166.7E-6 G9 50 30 25 50 166.7E-6 D10 99 28 DX D11 99 29 DX D12 50 28 DY D13 50 29 DY * * MODELS USED * .MODEL QX PNP(BF=20) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP291G SPICE Macro-model Rev. A, 5/94 * ARG / PMI * * This version of the OP291 model simulates the worst-case * parameters of the 'G' grade. The worst-case parameters * used correspond to those in the data sheet. * * Copyright 1994 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of * this model indicates your acceptance of the terms and pro- * visions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP291G 1 2 99 50 45 * * INPUT STAGE * I1 99 7 8.1E-6 Q1 6 4 7 QP Q2 5 3 7 QP D1 3 99 DX D2 4 99 DX D3 3 4 DX D4 4 3 DX R1 3 8 5E3 R2 4 2 5E3 R3 5 50 6.4654E3 R4 6 50 6.4654E3 EOS 8 1 POLY(1) (16,39) -0.7E-3 1.778 IOS 3 4 4E-9 GB1 3 98 21 98 83.333E-9 GB2 4 98 21 98 83.333E-9 CIN 1 2 1E-12 * * 1ST GAIN STAGE * EREF 98 0 39 0 1 G1 98 9 6 5 31.416E-6 R7 9 98 1E6 EC1 99 10 POLY(1) (99,39) -0.52 1 EC2 11 50 POLY(1) (39,50) -0.52 1 D5 9 10 DX D6 11 9 DX * * 2ND GAIN STAGE AND DOMINANT POLE AT 100HZ * G2 98 12 9 39 8E-6 R8 12 98 99.472E6 C2 12 98 16E-12 D7 12 13 DX D8 14 12 DX V1 99 13 0.58 V2 14 50 0.58 * * COMMON MODE STAGE * ECM 15 98 POLY(2) (1,39) (2,39) 0 0.5 0.5 R9 15 16 1E6 R10 16 98 100 * * POLE AT 2.5MHZ * G3 98 18 12 39 1E-6 R11 18 98 1E6 C4 18 98 63.662E-15 * * BIAS CURRENT-VS-COMMON MODE VOLTAGE * EP 97 0 99 0 1 VB 99 17 1.3 RB 17 50 1E9 E3 19 0 15 17 16 D13 19 20 DX R12 20 0 1E6 G4 98 21 20 0 1E-3 R13 21 98 5E3 D14 21 22 DY E4 97 22 (POLY(1) (99,98) -0.765 1 * * POLE AT 100MHZ * G6 98 40 18 39 1E-6 R20 40 98 1E6 C10 40 98 1.592E-15 * * OUTPUT STAGE * RS1 99 39 109.375E3 RS2 39 50 109.375E3 RO1 99 45 41.667 RO2 45 50 41.667 G7 45 99 99 40 24E-3 G8 50 45 40 50 24E-3 G9 98 60 45 40 24E-3 D9 60 61 DX D10 62 60 DX V7 61 98 DC 0 V8 98 62 DC 0 FSY 99 50 POLY(2) V7 V8 0.367E-3 1 1 D11 41 45 DZ D12 45 42 DZ V5 40 41 0.131 V6 42 40 0.131 .MODEL DX D() .MODEL DY D(IS=1E-9) .MODEL DZ D(IS=1E-6) .MODEL QP PNP(BF=80) .ENDS * OP292G SPICE Macro-model Rev. A, 3/95 * ARG / ADSC * * This version of the OP292 model simulates the worst-case * parameters of the 'G' grade. The worst-case parameters * used correspond to those in the data sheet. * * Copyright 1995 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of * this model indicates your acceptance of the terms and pro- * visions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP292G 2 1 99 50 34 * * INPUT STAGE AND POLE AT 40MHZ * I1 99 4 51.4E-6 IOS 2 1 25E-9 EOS 2 3 POLY(1) (21,30) 2E-3 16.8 CIN 1 2 2E-12 Q1 5 1 7 QP Q2 6 3 8 QP R3 5 50 2E3 R4 6 50 2E3 R5 4 7 965 R6 4 8 965 C1 5 6 .995E-12 * * GAIN STAGE * EREF 98 0 30 0 1 G1 98 9 5 6 500E-6 R7 9 98 14.388E3 D1 9 10 DX D2 11 9 DX V1 99 10 .6 V2 11 50 .6 * * ZERO/POLE AT 6MHZ/12MHZ * E1 12 98 9 30 2 R8 12 13 1 R9 13 98 1 C3 12 13 26.526E-9 * * ZERO AT 15MHZ * E2 14 98 13 30 1E6 R10 14 15 1E6 R11 15 98 1 C4 14 15 10.610E-15 * * COMMON MODE STAGE WITH ZERO AT 40KHZ * ECM 20 98 POLY(2) (1,30) (2,30) 0 0.5 0.5 R20 20 21 1E6 R21 21 98 10 *C5 20 21 3.979E-12 * * POLE AT 100MHZ * G2 98 16 9 30 1 R12 16 98 1 C6 16 98 1.592E-9 * * OUTPUT STAGE * RS1 99 30 1E6 RS2 30 50 1E6 ISY 99 50 .236E-3 G3 31 50 POLY(1) (16,30) -1.681511E-6 1E-6 R16 31 50 1E6 DCL 50 31 DZ I2 99 32 250E-6 RCP 99 36 75 RCL 33 50 75 Q6 35 36 99 QPA Q7 32 37 50 QNA R17 35 37 1E3 M1 32 31 50 50 MN L=9E-6 W=1000E-6 AD=15E-9 AS=15E-9 M2 34 31 50 50 MN L=9E-6 W=1000E-6 AD=15E-9 AS=15E-9 CC 31 32 0.23E-12 Q3 36 32 34 QNA Q4 33 32 34 QPA Q5 31 33 50 QNA .MODEL QNA NPN(IS=1.19E-16 BF=253 VAF=193 RC=400) .MODEL QPA PNP(IS=5.21E-17 BF=131 VAF=62 RC=250) *.MODEL MN NMOS(LEVEL=3 VTO=1.3 RS=0.3 RD=0.3 LD=1.48E-6 WD=1E-6) *jg, 18/5/00: corrected syntax model .MODEL MN NMOS(LEVEL=3 VTO=1.3 RS=0.3 RD=0.3 LD=1.48E-6) .MODEL QP PNP(BF=35.714) .MODEL DX D .MODEL DZ D(BV=3.6) .ENDS OP292G * OP293E SPICE Macro-model 1/95, Rev. A * ARG / ADI * * This version of the OP293 model simulates the worst-case * parameters of the 'E' grade. The worst-case parameters * used correspond to those in the data sheet. * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License * Statement. This model has been optimized for a total supply voltage of * 5V. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP293E 51 52 99 50 32 * * INPUT STAGE & POLE AT 16KHZ * R3 5 50 53.827E3 R4 6 50 53.827E3 R5 4 7 2.104E3 R6 4 8 2.104E3 CIN 1 2 4E-12 C2 5 6 92.4E-12 I1 99 4 1.03E-6 IOS 1 2 1E-9 EOS 9 1 POLY(2) (24,27) (102,0) 100E-6 0.1 1 Q1 5 2 7 QX Q2 6 9 8 QX EREF 98 0 POLY(2) (99,0) (50,0) 0 0.5 0.5 R24 1 51 2E3 R25 2 52 2E3 VN1 101 0 DC 2 VN2 0 103 DC 2 DN1 101 102 DEN DN2 102 103 DEN * * GAIN STAGE & DOMINANT POLE AT 0.473 HZ * R7 10 98 4.037E9 G1 98 10 5 6 18.578E-6 C3 10 98 83.333E-12 V1 99 11 0.65 D1 10 11 DX D2 50 10 DX * * NEGATIVE ZERO AT 50KHZ * R9 13 14 1E6 R10 14 98 1 FNZ 13 14 VNZ -1 E2 13 98 10 27 1 CNZ 15 16 3.183E-12 ENZ 15 98 13 14 1 VNZ 16 98 DC 0 * * ZERO-POLE PAIR AT 28KHZ / 84KHZ * R18 17 18 2E6 C4 17 18 2.842E-12 R19 18 98 1E6 E3 17 98 14 27 3E6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 3.16HZ * R1 23 24 1E6 R2 24 98 100 C5 23 24 50.33E-9 E4 23 98 POLY(2) (1,27) (2,27) 0 0.5 0.5 * * ZERO-POLE PAIR AT 40KHZ / 160KHZ * R20 25 26 3E6 C6 25 26 1.326E-12 R21 26 98 1E6 E5 25 98 18 27 4 * * OUTPUT STAGE * ISY 99 50 20.137E-6 R16 27 99 4.5E6 R17 27 50 4.5E6 EIN 28 98 POLY(1) (26,27) 0.51905 1 RIN 28 31 15E3 Q11 45 31 32 QN 6 Q12 32 33 44 QN 6 Q13 41 34 33 QN 1 Q14 34 35 36 QP 1 Q15 36 38 39 QN 8 Q16 35 35 37 QP 1 Q17 99 99 37 QN 1 Q18 99 99 36 QN 1 Q19 50 42 34 QP 1 Q20 42 42 34 QP 1 Q21 32 33 42 QN 1 Q22 99 40 41 QN 1 Q23 43 43 50 QN 1 Q24 34 43 50 QN 2 Q25 33 43 50 QN 2 Q26 34 44 50 QC 1 Q27 31 46 50 QC 1 EC 47 50 99 45 0.96 RC 46 47 1E3 IREF 99 43 4.5E-7 I13 35 50 4.5E-7 R11 99 40 75E3 R12 99 36 40E3 R13 31 38 20E3 R14 32 39 5E3 R15 40 37 75E3 R22 44 50 30 R23 99 45 50 * * MODELS USED * .MODEL QN NPN(BF=200 IS=1E-16 VA=150) .MODEL QP PNP(BF=100 IS=5E-17 VA=50) .MODEL QX PNP(BF=33.333 KF=2E-17) .MODEL QC NPN(BF=200 IS=2.22E-11) .MODEL DX D(IS=1E-15) .MODEL DEN D(RS=2.45E3 KF=33E-15) .ENDS * jg, 18/5/00: corrected syntax model* OP293F SPICE Macro-model 1/95, Rev. A * ARG / ADI * * This version of the OP293 model simulates the worst-case * parameters of the 'F' grade. The worst-case parameters * used correspond to those in the data sheet. * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License * Statement. This model has been optimized for a total supply voltage of * 5V. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP293F 51 52 99 50 32 * * INPUT STAGE & POLE AT 16KHZ * R3 5 50 53.827E3 R4 6 50 53.827E3 R5 4 7 2.104E3 R6 4 8 2.104E3 CIN 1 2 4E-12 C2 5 6 92.4E-12 I1 99 4 1.04E-6 IOS 1 2 2E-9 EOS 9 1 POLY(2) (24,27) (102,0) 250E-6 0.1585 1 Q1 5 2 7 QX Q2 6 9 8 QX EREF 98 0 POLY(2) (99,0) (50,0) 0 0.5 0.5 R24 1 51 2E3 R25 2 52 2E3 VN1 101 0 DC 2 VN2 0 103 DC 2 DN1 101 102 DEN DN2 102 103 DEN * * GAIN STAGE & DOMINANT POLE AT 0.473 HZ * R7 10 98 4.037E9 G1 98 10 5 6 18.578E-6 C3 10 98 83.333E-12 V1 99 11 0.65 D1 10 11 DX D2 50 10 DX * * NEGATIVE ZERO AT 50KHZ * R9 13 14 1E6 R10 14 98 1 FNZ 13 14 VNZ -1 E2 13 98 10 27 1 CNZ 15 16 3.183E-12 ENZ 15 98 13 14 1 VNZ 16 98 DC 0 * * ZERO-POLE PAIR AT 28KHZ / 84KHZ * R18 17 18 2E6 C4 17 18 2.842E-12 R19 18 98 1E6 E3 17 98 14 27 3E6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 5HZ * R1 23 24 1E6 R2 24 98 100 C5 23 24 32E-9 E4 23 98 POLY(2) (1,27) (2,27) 0 0.5 0.5 * * ZERO-POLE PAIR AT 40KHZ / 160KHZ * R20 25 26 3E6 C6 25 26 1.326E-12 R21 26 98 1E6 E5 25 98 18 27 4 * * OUTPUT STAGE * ISY 99 50 20.137E-6 R16 27 99 4.5E6 R17 27 50 4.5E6 EIN 28 98 POLY(1) (26,27) 0.51905 1 RIN 28 31 15E3 Q11 45 31 32 QN 6 Q12 32 33 44 QN 6 Q13 41 34 33 QN 1 Q14 34 35 36 QP 1 Q15 36 38 39 QN 8 Q16 35 35 37 QP 1 Q17 99 99 37 QN 1 Q18 99 99 36 QN 1 Q19 50 42 34 QP 1 Q20 42 42 34 QP 1 Q21 32 33 42 QN 1 Q22 99 40 41 QN 1 Q23 43 43 50 QN 1 Q24 34 43 50 QN 2 Q25 33 43 50 QN 2 Q26 34 44 50 QC 1 Q27 31 46 50 QC 1 EC 47 50 99 45 0.96 RC 46 47 1E3 IREF 99 43 4.5E-7 I13 35 50 4.5E-7 R11 99 40 75E3 R12 99 36 40E3 R13 31 38 20E3 R14 32 39 5E3 R15 40 37 75E3 R22 44 50 30 R23 99 45 50 * * MODELS USED * .MODEL QN NPN(BF=200 IS=1E-16 VA=150) .MODEL QP PNP(BF=100 IS=5E-17 VA=50) .MODEL QX PNP(BF=25 KF=2E-17) .MODEL QC NPN(BF=200 IS=2.22E-11) .MODEL DX D(IS=1E-15) .MODEL DEN D(RS=2.45E3 KF=33E-15) .ENDS * jg, 18/5/00: corrected syntax model* OP295A SPICE Macro-model 2/95, Rev. A * ARG / ADSC * * This version of the OP295 model simulates the worst-case * parameters of the 'A' grade. The worst-case parameters * used correspond to those in the data sheet. * * Copyright 1995 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License * Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP295A 1 2 99 50 20 * * INPUT STAGE * I1 99 4 2.04E-6 R1 1 6 5E3 R2 2 5 5E3 CIN 1 2 2E-12 IOS 1 2 1.5E-9 D1 5 3 DZ D2 6 3 DZ EOS 7 6 POLY(1) (31,39) 300E-6 0.316 Q1 8 5 4 QP Q2 9 7 4 QP R3 8 50 25.861E3 R4 9 50 25.861E3 * * GAIN STAGE * R7 10 98 72.8725E6 G1 98 10 POLY(1) (9,8) -15.8072E-9 27.8E-6 EREF 98 0 (39,0) 1 R5 99 39 417E3 R6 39 50 417E3 * * COMMON MODE STAGE * ECM 30 98 POLY(2) (1,39) (2,39) 0 0.5 0.5 R12 30 31 1E6 R13 31 98 100 * * OUTPUT STAGE * ISY 99 50 99E-6 I2 18 50 1.59E-6 V2 99 12 DC 2.2763 Q4 10 14 50 QNA 1.0 R11 14 50 54 M3 15 10 13 13 MN L=9E-6 W=102E-6 AD=15E-10 AS=15E-10 M4 13 10 50 50 MN L=9E-6 W=50E-6 AD=75E-11 AS=75E-11 D8 10 22 DX V3 22 50 DC 6 M2 20 10 14 14 MN L=9E-6 W=2000E-6 AD=30E-9 AS=30E-9 Q5 17 17 99 QPA 1.0 Q6 18 17 99 QPA 4.0 R8 18 99 2.2E6 Q7 18 19 99 QPA 1.0 R9 99 19 48 C2 18 99 20E-12 M6 15 12 17 99 MP L=9E-6 W=27E-6 AD=405E-12 AS=405E-12 M1 20 18 19 99 MP L=9E-6 W=2000E-6 AD=30E-9 AS=30E-9 D4 21 18 DX V4 99 21 DC 6 R10 10 11 6E3 C3 11 20 54E-12 .MODEL QNA NPN(IS=1.19E-16 BF=253 NF=0.99 VAF=193 IKF=2.76E-3 + ISE=2.57E-13 NE=5 BR=0.4 NR=0.988 VAR=15 IKR=1.465E-4 + ISC=6.9E-16 NC=0.99 RB=2.0E3 IRB=7.73E-6 RBM=132.8 RE=4 RC=209 + CJE=2.1E-13 VJE=0.573 MJE=0.364 FC=0.5 CJC=1.64E-13 VJC=0.534 MJC=0.5 + CJS=1.37E-12 VJS=0.59 MJS=0.5 TF=0.43E-9 PTF=30) .MODEL QPA PNP(IS=5.21E-17 BF=131 NF=0.99 VAF=62 IKF=8.35E-4 + ISE=1.09E-14 NE=2.61 BR=0.5 NR=0.984 VAR=15 IKR=3.96E-5 + ISC=7.58E-16 NC=0.985 RB=1.52E3 IRB=1.67E-5 RBM=368.5 RE=6.31 RC=354.4 + CJE=1.1E-13 VJE=0.745 MJE=0.33 FC=0.5 CJC=2.37E-13 VJC=0.762 MJC=0.4 + CJS=7.11E-13 VJS=0.45 MJS=0.412 TF=1.0E-9 PTF=30) .MODEL MN NMOS(LEVEL=3 VTO=1.3 RS=0.3 RD=0.3 + TOX=8.5E-8 LD=1.48E-6 NSUB=1.53E16 UO=650 DELTA=10 VMAX=2E5 + XJ=1.75E-6 KAPPA=0.8 ETA=0.066 THETA=0.01 TPG=1 CJ=2.9E-4 PB=0.837 + MJ=0.407 CJSW=0.5E-9 MJSW=0.33) .MODEL MP PMOS(LEVEL=3 VTO=-1.1 RS=0.7 RD=0.7 + TOX=9.5E-8 LD=1.4E-6 NSUB=2.4E15 UO=650 DELTA=5.6 VMAX=1E5 + XJ=1.75E-6 KAPPA=1.7 ETA=0.71 THETA=5.9E-3 TPG=-1 CJ=1.55E-4 PB=0.56 + MJ=0.442 CJSW=0.4E-9 MJSW=0.33) .MODEL DX D(IS=1E-15) .MODEL DZ D(IS=1E-15, BV=7) .MODEL QP PNP(BF=50) .ENDS * OP295G SPICE Macro-model 2/95, Rev. A * ARG / ADSC * * This version of the OP295 model simulates the worst-case * parameters of the 'G' grade. The worst-case parameters * used correspond to those in the data sheet. * * Copyright 1995 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License * Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP295G 1 2 99 50 20 * * INPUT STAGE * I1 99 4 2.04E-6 R1 1 6 5E3 R2 2 5 5E3 CIN 1 2 2E-12 IOS 1 2 1.5E-9 D1 5 3 DZ D2 6 3 DZ EOS 7 6 POLY(1) (31,39) 300E-6 0.316 Q1 8 5 4 QP Q2 9 7 4 QP R3 8 50 25.861E3 R4 9 50 25.861E3 * * GAIN STAGE * R7 10 98 72.8725E6 G1 98 10 POLY(1) (9,8) -15.8072E-9 27.8E-6 EREF 98 0 (39,0) 1 R5 99 39 417E3 R6 39 50 417E3 * * COMMON MODE STAGE * ECM 30 98 POLY(2) (1,39) (2,39) 0 0.5 0.5 R12 30 31 1E6 R13 31 98 100 * * OUTPUT STAGE * ISY 99 50 99E-6 I2 18 50 1.59E-6 V2 99 12 DC 2.2763 Q4 10 14 50 QNA 1.0 R11 14 50 54 M3 15 10 13 13 MN L=9E-6 W=102E-6 AD=15E-10 AS=15E-10 M4 13 10 50 50 MN L=9E-6 W=50E-6 AD=75E-11 AS=75E-11 D8 10 22 DX V3 22 50 DC 6 M2 20 10 14 14 MN L=9E-6 W=2000E-6 AD=30E-9 AS=30E-9 Q5 17 17 99 QPA 1.0 Q6 18 17 99 QPA 4.0 R8 18 99 2.2E6 Q7 18 19 99 QPA 1.0 R9 99 19 48 C2 18 99 20E-12 M6 15 12 17 99 MP L=9E-6 W=27E-6 AD=405E-12 AS=405E-12 M1 20 18 19 99 MP L=9E-6 W=2000E-6 AD=30E-9 AS=30E-9 D4 21 18 DX V4 99 21 DC 6 R10 10 11 6E3 C3 11 20 54E-12 .MODEL QNA NPN(IS=1.19E-16 BF=253 NF=0.99 VAF=193 IKF=2.76E-3 + ISE=2.57E-13 NE=5 BR=0.4 NR=0.988 VAR=15 IKR=1.465E-4 + ISC=6.9E-16 NC=0.99 RB=2.0E3 IRB=7.73E-6 RBM=132.8 RE=4 RC=209 + CJE=2.1E-13 VJE=0.573 MJE=0.364 FC=0.5 CJC=1.64E-13 VJC=0.534 MJC=0.5 + CJS=1.37E-12 VJS=0.59 MJS=0.5 TF=0.43E-9 PTF=30) .MODEL QPA PNP(IS=5.21E-17 BF=131 NF=0.99 VAF=62 IKF=8.35E-4 + ISE=1.09E-14 NE=2.61 BR=0.5 NR=0.984 VAR=15 IKR=3.96E-5 + ISC=7.58E-16 NC=0.985 RB=1.52E3 IRB=1.67E-5 RBM=368.5 RE=6.31 RC=354.4 + CJE=1.1E-13 VJE=0.745 MJE=0.33 FC=0.5 CJC=2.37E-13 VJC=0.762 MJC=0.4 + CJS=7.11E-13 VJS=0.45 MJS=0.412 TF=1.0E-9 PTF=30) .MODEL MN NMOS(LEVEL=3 VTO=1.3 RS=0.3 RD=0.3 + TOX=8.5E-8 LD=1.48E-6 NSUB=1.53E16 UO=650 DELTA=10 VMAX=2E5 + XJ=1.75E-6 KAPPA=0.8 ETA=0.066 THETA=0.01 TPG=1 CJ=2.9E-4 PB=0.837 + MJ=0.407 CJSW=0.5E-9 MJSW=0.33) .MODEL MP PMOS(LEVEL=3 VTO=-1.1 RS=0.7 RD=0.7 + TOX=9.5E-8 LD=1.4E-6 NSUB=2.4E15 UO=650 DELTA=5.6 VMAX=1E5 + XJ=1.75E-6 KAPPA=1.7 ETA=0.71 THETA=5.9E-3 TPG=-1 CJ=1.55E-4 PB=0.56 + MJ=0.442 CJSW=0.4E-9 MJSW=0.33) .MODEL DX D(IS=1E-15) .MODEL DZ D(IS=1E-15, BV=7) .MODEL QP PNP(BF=50) .ENDS * OP296 SPICE Macro-model Rev. A, 5/95 * ARG / ADSC * * Copyright 1995 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of * this model indicates your acceptance of the terms and pro- * visions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP296 1 2 99 50 49 * * INPUT STAGE * IREF 21 50 1U QB1 21 21 99 99 QP 1 QB2 22 21 99 99 QP 1 QB3 4 21 99 99 QP 1.5 QB4 22 22 50 50 QN 2 QB5 11 22 50 50 QN 3 Q1 5 4 7 50 QN 2 Q2 6 4 8 50 QN 2 Q3 4 4 7 50 QN 1 Q4 4 4 8 50 QN 1 Q5 50 1 7 99 QP 2 Q6 50 3 8 99 QP 2 EOS 3 2 POLY(1) (17,98) 35U 1 Q7 99 1 9 50 QN 2 Q8 99 3 10 50 QN 2 Q9 12 11 9 99 QP 2 Q10 13 11 10 99 QP 2 Q11 11 11 9 99 QP 1 Q12 11 11 10 99 QP 1 R1 99 5 50K R2 99 6 50K R3 12 50 50K R4 13 50 50K IOS 1 2 0.75N C10 5 6 3.183P C11 12 13 3.183P CIN 1 2 1P * * GAIN STAGE * EREF 98 0 POLY(2) (99,0) (50,0) 0 0.5 0.5 G1 98 15 POLY(2) (6,5) (13,12) 0 10U 10U R10 15 98 251.641MEG CC 15 49 8P D1 15 99 DX D2 50 15 DX * * COMMON MODE STAGE * ECM 16 98 POLY(2) (1,98) (2,98) 0 0.5 0.5 R11 16 17 1E6 R12 17 98 10 * * OUTPUT STAGE * ISY 99 50 20E-6 EIN 35 50 POLY(1) (15,98) 1.42735 1 Q24 37 35 36 50 QN 1 QD4 37 37 38 99 QP 1 Q27 40 37 38 99 QP 1 R5 36 39 150K R6 99 38 45K Q26 39 42 50 50 QN 3 QD5 40 40 39 50 QN 1 Q28 41 40 44 50 QN 1 QL1 37 41 99 99 QP 1 R7 99 41 10.7K I4 99 43 2U QD7 42 42 50 50 QN 2 QD6 43 43 42 50 QN 2 Q29 47 43 44 50 QN 1 Q30 44 45 50 50 QN 1.5 QD10 45 46 50 50 QN 1 R9 45 46 175 Q31 46 47 48 99 QP 1 QD8 47 47 48 99 QP 1 QD9 48 48 51 99 QP 5 R8 99 51 2.9K I5 99 46 1U Q32 49 48 99 99 QP 10 Q33 49 44 50 50 QN 4 .MODEL DX D() .MODEL QN NPN(BF=120 VAF=100) .MODEL QP PNP(BF=80 VAF=60) .ENDS * OP296G SPICE Macro-model Rev. A, 6/95 * ARG / ADSC * * This version of the OP296 model simulates the worst-case * parameters of the 'G' grade. The worst-case parameters * used correspond to those in the data sheet. * * Copyright 1995 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of * this model indicates your acceptance of the terms and pro- * visions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP296G 1 2 99 50 49 * * INPUT STAGE * IREF 21 50 1U QB1 21 21 99 99 QP 1 QB2 22 21 99 99 QP 1 QB3 4 21 99 99 QP 1.5 QB4 22 22 50 50 QN 2 QB5 11 22 50 50 QN 3 Q1 5 4 7 50 QN1 2 Q2 6 4 8 50 QN1 2 Q3 4 4 7 50 QN1 1 Q4 4 4 8 50 QN1 1 Q5 50 1 7 99 QP1 2 Q6 50 3 8 99 QP1 2 EOS 3 2 POLY(1) (17,98) 300E-6 1 Q7 99 1 9 50 QN1 2 Q8 99 3 10 50 QN1 2 Q9 12 11 9 99 QP1 2 Q10 13 11 10 99 QP1 2 Q11 11 11 9 99 QP1 1 Q12 11 11 10 99 QP1 1 R1 99 5 50K R2 99 6 50K R3 12 50 50K R4 13 50 50K IOS 1 2 2.5N C10 5 6 3.183P C11 12 13 3.183P CIN 1 2 1P * * GAIN STAGE * EREF 98 0 POLY(2) (99,0) (50,0) 0 0.5 0.5 G1 98 15 POLY(2) (6,5) (13,12) 0 10U 10U R10 15 98 120MEG CC 15 49 8P D1 15 99 DX D2 50 15 DX * * COMMON MODE STAGE * ECM 16 98 POLY(2) (1,98) (2,98) 0 0.5 0.5 R11 16 17 1E6 R12 17 98 100 * * OUTPUT STAGE * ISY 99 50 35E-6 EIN 35 50 POLY(1) (15,98) 1.42713 1 Q24 37 35 36 50 QN 1 QD4 37 37 38 99 QP 1 Q27 40 37 38 99 QP 1 R5 36 39 150K R6 99 38 45K Q26 39 42 50 50 QN 3 QD5 40 40 39 50 QN 1 Q28 41 40 44 50 QN 1 QL1 37 41 99 99 QP 1 R7 99 41 10.7K I4 99 43 2U QD7 42 42 50 50 QN 2 QD6 43 43 42 50 QN 2 Q29 47 43 44 50 QN 1 Q30 44 45 50 50 QN 1.5 QD10 45 46 50 50 QN 1 R9 45 46 175 Q31 46 47 48 99 QP 1 QD8 47 47 48 99 QP 1 QD9 48 48 51 99 QP 5 R8 99 51 2.9K I5 99 46 1U Q32 49 48 99 99 QOP 10 Q33 49 44 50 50 QON 4 .MODEL DX D() .MODEL QN NPN(BF=120 VAF=100) .MODEL QP PNP(BF=80 VAF=60) *.MODEL QON AKO:QN NPN(RC=2K) *.MODEL QOP AKO:QP PNP(RC=4K) * jg, 18/5/00: corrected syntax model .MODEL QON NPN(BF=120 VAF=100 RC=2K) .MODEL QOP PNP(BF=80 VAF=60 RC=4K) .MODEL QN1 NPN(BF=100 VAF=100) .MODEL QP1 PNP(BF=56 VAF=60) .ENDS * OP297A SPICE Macro-model 10/91, Rev. C * JCB / PMI * * Revision History: * REV. C * Changed ISY to correct the supply current * Altered V5 for short circuit current limit * REV. B * Re-ordered subcircuit call out nodes to put the * output node last. * Changed Ios from 100E-12 to 50E-12 * * * This version of the OP-297 model simulates the worst case * parameters of the 'A' grade. The worst case parameters * used correspond to those in the data book. * * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP297A 1 2 99 50 30 * * INPUT STAGE & POLE AT 6 MHZ * RIN1 1 7 2500 RIN2 2 8 2500 R1 8 3 5E11 R2 7 3 5E11 R3 5 99 612 R4 6 99 612 CIN 7 8 3E-12 C2 5 6 21.67E-12 I1 4 50 0.1E-3 IOS 7 8 50E-12 EOS 9 7 POLY(1) 19 23 50E-6 1 Q1 5 8 10 QX Q2 6 9 11 QX R5 10 4 96 R6 11 4 96 D1 8 9 DX D2 9 8 DX * EREF 98 0 23 0 1 * * FIRST GAIN STAGE * RG1 40 98 1E6 GG1 98 40 5 6 196.7E-6 DG3 40 41 DX DG4 42 40 DX EG1 99 41 POLY(1) 99 23 -2.1 1 EG2 42 50 POLY(1) 99 23 -2.1 1 * * GAIN STAGE & DOMINANT POLE AT 0.26 HZ * R7 12 98 1.22E9 C3 12 98 500E-12 G1 98 12 40 23 8.333E-6 V2 99 13 2.0 V3 14 50 2.0 D3 12 13 DX D4 14 12 DX * * NEGATIVE ZERO AT -1.8 MHZ * R8 15 16 1E6 C4 15 16 -88.4E-15 R9 16 98 1 E1 15 98 12 23 1E6 * * POLE AT 1.8 MHZ * R10 17 98 1E6 C5 17 98 88.4E-15 G2 98 17 16 23 1E-6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 500 HZ * R11 18 19 1E6 C6 18 19 0.3183E-9 R12 19 98 1 E2 18 98 3 23 1 * * POLE AT 6 MHZ * R15 22 98 1E6 C8 22 98 26.53E-15 G3 98 22 17 23 1E-6 * * OUTPUT STAGE * R16 23 99 500K R17 23 50 500K ISY 99 50 183E-6 R18 25 99 200 R19 25 50 200 L1 25 30 1E-7 G4 28 50 22 25 5E-3 G5 29 50 25 22 5E-3 G6 25 99 99 22 5E-3 G7 50 25 22 50 5E-3 V4 26 25 1.8 V5 25 27 1.8 D5 22 26 DX D6 27 22 DX D7 99 28 DX D8 99 29 DX D9 50 28 DY D10 50 29 DY * * MODELS USED * .MODEL QX NPN(BF=500E3) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP297E SPICE Macro-model 10/91, Rev. C * JCB / PMI * * Revision History: * REV. C * Changed ISY to correct the supply current * Altered V5 for short circuit current limit * REV. B * Re-ordered subcircuit call out nodes to put the * output node last. * Changed Ios from 100E-12 to 50E-12 * * * This version of the OP-297 model simulates the worst case * parameters of the 'E' grade. The worst case parameters * used correspond to those in the data book. * * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP297E 1 2 99 50 30 * * INPUT STAGE & POLE AT 6 MHZ * RIN1 1 7 2500 RIN2 2 8 2500 R1 8 3 5E11 R2 7 3 5E11 R3 5 99 612 R4 6 99 612 CIN 7 8 3E-12 C2 5 6 21.67E-12 I1 4 50 0.1E-3 IOS 7 8 50E-12 EOS 9 7 POLY(1) 19 23 50E-6 1 Q1 5 8 10 QX Q2 6 9 11 QX R5 10 4 96 R6 11 4 96 D1 8 9 DX D2 9 8 DX * EREF 98 0 23 0 1 * * FIRST GAIN STAGE * RG1 40 98 1E6 GG1 98 40 5 6 196.7E-6 DG3 40 41 DX DG4 42 40 DX EG1 99 41 POLY(1) 99 23 -2.1 1 EG2 42 50 POLY(1) 99 23 -2.1 1 * * GAIN STAGE & DOMINANT POLE AT 0.26 HZ * R7 12 98 1.22E9 C3 12 98 500E-12 G1 98 12 40 23 8.333E-6 V2 99 13 2.0 V3 14 50 2.0 D3 12 13 DX D4 14 12 DX * * NEGATIVE ZERO AT -1.8 MHZ * R8 15 16 1E6 C4 15 16 -88.4E-15 R9 16 98 1 E1 15 98 12 23 1E6 * * POLE AT 1.8 MHZ * R10 17 98 1E6 C5 17 98 88.4E-15 G2 98 17 16 23 1E-6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 500 HZ * R11 18 19 1E6 C6 18 19 0.3183E-9 R12 19 98 1 E2 18 98 3 23 1 * * POLE AT 6 MHZ * R15 22 98 1E6 C8 22 98 26.53E-15 G3 98 22 17 23 1E-6 * * OUTPUT STAGE * R16 23 99 500K R17 23 50 500K ISY 99 50 183E-6 R18 25 99 200 R19 25 50 200 L1 25 30 1E-7 G4 28 50 22 25 5E-3 G5 29 50 25 22 5E-3 G6 25 99 99 22 5E-3 G7 50 25 22 50 5E-3 V4 26 25 1.8 V5 25 27 1.8 D5 22 26 DX D6 27 22 DX D7 99 28 DX D8 99 29 DX D9 50 28 DY D10 50 29 DY * * MODELS USED * .MODEL QX NPN(BF=500E3) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP297F SPICE Macro-model 10/91, Rev. C * JCB / PMI * * Revision History: * REV. C * Changed ISY to correct the supply current * Altered V5 for short circuit current limit * REV. B * Re-ordered subcircuit call out nodes to put the * output node last. * Changed Ios from 150E-12 to 75E-12 * * * This version of the OP-297 model simulates the worst case * parameters of the 'F' grade. The worst case parameters * used correspond to those in the data book. * * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP297F 1 2 99 50 30 * * INPUT STAGE & POLE AT 6 MHZ * RIN1 1 7 2500 RIN2 2 8 2500 R1 8 3 5E11 R2 7 3 5E11 R3 5 99 612 R4 6 99 612 CIN 7 8 3E-12 C2 5 6 21.67E-12 I1 4 50 0.1E-3 IOS 7 8 75E-12 EOS 9 7 POLY(1) 19 23 100E-6 1 Q1 5 8 10 QX Q2 6 9 11 QX R5 10 4 96 R6 11 4 96 D1 8 9 DX D2 9 8 DX * EREF 98 0 23 0 1 * * FIRST GAIN STAGE * RG1 40 98 1E6 GG1 98 40 5 6 196.1E-6 DG3 40 41 DX DG4 42 40 DX EG1 99 41 POLY(1) 99 23 -2.1 1 EG2 42 50 POLY(1) 99 23 -2.1 1 * * GAIN STAGE & DOMINANT POLE AT 0.35 HZ * R7 12 98 918.1E6 C3 12 98 500E-12 G1 98 12 40 23 8.333E-6 V2 99 13 2.0 V3 14 50 2.0 D3 12 13 DX D4 14 12 DX * * NEGATIVE ZERO AT -1.8 MHZ * R8 15 16 1E6 C4 15 16 -88.4E-15 R9 16 98 1 E1 15 98 12 23 1E6 * * POLE AT 1.8 MHZ * R10 17 98 1E6 C5 17 98 88.4E-15 G2 98 17 16 23 1E-6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 1000 HZ * R11 18 19 1E6 C6 18 19 0.159E-9 R12 19 98 1 E2 18 98 3 23 2.0 * * POLE AT 6 MHZ * R15 22 98 1E6 C8 22 98 26.53E-15 G3 98 22 17 23 1E-6 * * OUTPUT STAGE * R16 23 99 500K R17 23 50 500K ISY 99 50 183E-6 R18 25 99 200 R19 25 50 200 L1 25 30 1E-7 G4 28 50 22 25 5E-3 G5 29 50 25 22 5E-3 G6 25 99 99 22 5E-3 G7 50 25 22 50 5E-3 V4 26 25 1.8 V5 25 27 1.8 D5 22 26 DX D6 27 22 DX D7 99 28 DX D8 99 29 DX D9 50 28 DY D10 50 29 DY * * MODELS USED * .MODEL QX NPN(BF=333E3) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP297G SPICE Macro-model 10/91, Rev. C * JCB / PMI * * Revision History: * REV. C * Changed ISY to correct the supply current * Altered V5 for short circuit current limit * REV. B * Re-ordered subcircuit call out nodes to put the * output node last. * Changed Ios from 200E-12 to 100E-12 * * * This version of the OP-297 model simulates the worst case * parameters of the 'G' grade. The worst case parameters * used correspond to those in the data book. * * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP297G 1 2 99 50 30 * * INPUT STAGE & POLE AT 6 MHZ * RIN1 1 7 2500 RIN2 2 8 2500 R1 8 3 5E11 R2 7 3 5E11 R3 5 99 612 R4 6 99 612 CIN 7 8 3E-12 C2 5 6 21.67E-12 I1 4 50 0.1E-3 IOS 7 8 100E-12 EOS 9 7 POLY(1) 19 23 200E-6 1 Q1 5 8 10 QX Q2 6 9 11 QX R5 10 4 96 R6 11 4 96 D1 8 9 DX D2 9 8 DX * EREF 98 0 23 0 1 * * FIRST GAIN STAGE * RG1 40 98 1E6 GG1 98 40 5 6 196E-6 DG3 40 41 DX DG4 42 40 DX EG1 99 41 POLY(1) 99 23 -2.1 1 EG2 42 50 POLY(1) 99 23 -2.1 1 * * GAIN STAGE & DOMINANT POLE AT 0.43 HZ * R7 12 98 734.6E6 C3 12 98 500E-12 G1 98 12 40 23 8.333E-6 V2 99 13 2.0 V3 14 50 2.0 D3 12 13 DX D4 14 12 DX * * NEGATIVE ZERO AT -1.8 MHZ * R8 15 16 1E6 C4 15 16 -88.4E-15 R9 16 98 1 E1 15 98 12 23 1E6 * * POLE AT 1.8 MHZ * R10 17 98 1E6 C5 17 98 88.4E-15 G2 98 17 16 23 1E-6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 1000 HZ * R11 18 19 1E6 C6 18 19 0.159E-9 R12 19 98 1 E2 18 98 3 23 2.0 * * POLE AT 6 MHZ * R15 22 98 1E6 C8 22 98 26.53E-15 G3 98 22 17 23 1E-6 * * OUTPUT STAGE * R16 23 99 500K R17 23 50 500K ISY 99 50 183E-6 R18 25 99 200 R19 25 50 200 L1 25 30 1E-7 G4 28 50 22 25 5E-3 G5 29 50 25 22 5E-3 G6 25 99 99 22 5E-3 G7 50 25 22 50 5E-3 V4 26 25 1.8 V5 25 27 1.8 D5 22 26 DX D6 27 22 DX D7 99 28 DX D8 99 29 DX D9 50 28 DY D10 50 29 DY * * MODELS USED * .MODEL QX NPN(BF=250E3) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP37A SPICE Model 1/90, Rev. A * ARG / PMI * * This version of the OP-37 model simulates the worst case * parameters of the 'A' grade. The worst case parameters * used correspond to those in the data sheet. * * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP37A 1 2 99 50 49 * * INPUT STAGE & POLE AT 100MHZ * R3 5 97 0.0516 R4 6 97 0.0516 CIN 1 2 4E-12 C2 5 6 15.42E-9 I1 4 51 1 IOS 1 2 17.5E-9 EOS 7 3 POLY(1) 30 43 25E-6 1 Q1 5 2 4 QX Q2 6 7 4 QX D1 2 1 DX D2 1 2 DX EN 3 1 9 0 1 GN1 0 2 12 0 1 GN2 0 1 15 0 1 EREF 98 0 43 0 1 EPLUS 97 0 99 0 1 ENEG 51 0 50 0 1 * * VOLTAGE NOISE SOURCE WITH FLICKER NOISE * DN1 8 9 DEN DN2 9 10 DEN VN1 8 0 DC 2 VN2 0 10 DC 2 * * CURRENT NOISE SOURCE WITH FLICKER NOISE * DN3 11 12 DIN DN4 12 13 DIN VN3 11 0 DC 2 VN4 0 13 DC 2 * * SECOND CURRENT NOISE SOURCE * DN5 14 15 DIN DN6 15 16 DIN VN5 14 0 DC 2 VN6 0 16 DC 2 * * 1ST GAIN STAGE * R5 17 98 1 G1A 98 17 5 6 98.71 D3 17 18 DX D4 19 17 DX E1 97 18 POLY(1) 97 43 -2.14 1 E2 19 51 POLY(1) 43 51 -2.14 1 * * 2ND GAIN STAGE & DOMINANT POLE AT 58HZ * R6 20 98 30.39E3 C3 20 98 90.91E-9 G1B 98 20 17 43 333.3E-3 V1 97 21 3.48 V2 22 51 3.48 D5 20 21 DX D6 22 20 DX * * POLE - ZERO AT .4MHZ / 1.0MHZ * R8 23 98 1 R9 23 24 0.667 C4 24 98 238.7E-9 G2 98 23 20 43 1 * * ZERO - POLE AT 10MHZ / 100MHZ * R10 25 26 1 R11 26 98 9 L1 26 98 14.32E-9 G3 98 25 23 43 1 * * POLE AT 100MHZ * R12 27 98 1 C5 27 98 1.59E-9 G4 98 27 25 43 1 * * POLE AT 100MHZ * R13 28 98 1 C6 28 98 1.59E-9 G5 98 28 27 43 1 * * POLE AT 100MHZ * R14 29 98 1 C7 29 98 1.59E-9 G6 98 29 28 43 1 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 28KHZ * R15 30 31 1 L2 31 98 5.68E-6 G7 98 30 POLY(2) 1 43 2 43 0 997.6E-9 997.6E-9 D7 30 97 DX D8 51 30 DX * * POLE AT 100MHZ * R16 32 98 1 C8 32 98 1.59E-9 G8 98 32 29 43 1 * * POLE AT 100MHZ * R17 33 98 1 C9 33 98 1.59E-9 G9 98 33 32 43 1 * * POLE AT 200MHZ * R18 34 98 1 C10 34 98 .796E-9 G10 98 34 33 43 1 * * OUTPUT STAGE * F1 44 0 V3 1 F2 0 44 V4 1 R27 43 97 1 R28 43 51 1 GSY 99 50 POLY(1) 99 50 3.32E-3 45E-6 R29 44 99 140 R30 44 50 140 L4 44 49 1E-7 G11 47 50 34 44 7.14E-3 G12 48 50 44 34 7.14E-3 G13 44 99 99 34 7.14E-3 G14 50 44 34 50 7.14E-3 V3 45 44 1.2 V4 44 46 1.55 D9 34 45 DX D10 46 34 DX D11 99 47 DX D12 99 48 DX D13 50 47 DY D14 50 48 DY * * MODELS USED * .MODEL QX NPN(BF=12.5E6) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .MODEL DEN D(IS=1E-12, RS=1.74K, KF=4.01E-16, AF=1) .MODEL DIN D(IS=1E-12, RS=43.5E-6, KF=11.1E-15, AF=1) .ENDS * OP37B SPICE Macro-model 1/91, Rev. A * ARG / PMI * * This version of the OP-37 model simulates the worst case * parameters of the 'B' grade. The worst case parameters * used correspond to those in the data sheet. * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP37B 1 2 99 50 49 * * INPUT STAGE & POLE AT 100MHZ * R3 5 97 0.0516 R4 6 97 0.0516 CIN 1 2 4E-12 C2 5 6 15.42E-9 I1 4 51 1 IOS 1 2 25E-9 EOS 7 3 POLY(1) 30 43 60E-6 1 Q1 5 2 4 QX Q2 6 7 4 QX D1 2 1 DX D2 1 2 DX EN 3 1 9 0 1 GN1 0 2 12 0 1 GN2 0 1 15 0 1 EREF 98 0 43 0 1 EPLUS 97 0 99 0 1 ENEG 51 0 50 0 1 * * VOLTAGE NOISE SOURCE WITH FLICKER NOISE * DN1 8 9 DEN DN2 9 10 DEN VN1 8 0 DC 2 VN2 0 10 DC 2 * * CURRENT NOISE SOURCE WITH FLICKER NOISE * DN3 11 12 DIN DN4 12 13 DIN VN3 11 0 DC 2 VN4 0 13 DC 2 * * SECOND CURRENT NOISE SOURCE * DN5 14 15 DIN DN6 15 16 DIN VN5 14 0 DC 2 VN6 0 16 DC 2 * * 1ST GAIN STAGE * R5 17 98 1 G1A 98 17 5 6 98.71 D3 17 18 DX D4 19 17 DX E1 97 18 POLY(1) 97 43 -2.14 1 E2 19 51 POLY(1) 43 51 -2.14 1 * * 2ND GAIN STAGE & DOMINANT POLE AT 58HZ * R6 20 98 30.39E3 C3 20 98 90.91E-9 G1B 98 20 17 43 333.3E-3 V1 97 21 3.48 V2 22 51 3.48 D5 20 21 DX D6 22 20 DX * * POLE - ZERO AT .4MHZ / 1.0MHZ * R8 23 98 1 R9 23 24 0.667 C4 24 98 238.7E-9 G2 98 23 20 43 1 * * ZERO - POLE AT 10MHZ / 100MHZ * R10 25 26 1 R11 26 98 9 L1 26 98 14.32E-9 G3 98 25 23 43 1 * * POLE AT 100MHZ * R12 27 98 1 C5 27 98 1.59E-9 G4 98 27 25 43 1 * * POLE AT 100MHZ * R13 28 98 1 C6 28 98 1.59E-9 G5 98 28 27 43 1 * * POLE AT 100MHZ * R14 29 98 1 C7 29 98 1.59E-9 G6 98 29 28 43 1 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 70KHZ * R15 30 31 1 L2 31 98 2.27E-6 G7 98 30 POLY(2) 1 43 2 43 0 2.506E-6 2.506E-6 D7 30 97 DX D8 51 30 DX * * POLE AT 100MHZ * R16 32 98 1 C8 32 98 1.59E-9 G8 98 32 29 43 1 * * POLE AT 100MHZ * R17 33 98 1 C9 33 98 1.59E-9 G9 98 33 32 43 1 * * POLE AT 200MHZ * R18 34 98 1 C10 34 98 .796E-9 G10 98 34 33 43 1 * * OUTPUT STAGE * F1 44 0 V3 1 F2 0 44 V4 1 R27 43 97 1 R28 43 51 1 GSY 99 50 POLY(1) 99 50 3.32E-3 45E-6 R29 44 99 140 R30 44 50 140 L4 44 49 1E-7 G11 47 50 34 44 7.14E-3 G12 48 50 44 34 7.14E-3 G13 44 99 99 34 7.14E-3 G14 50 44 34 50 7.14E-3 V3 45 44 1.2 V4 44 46 1.55 D9 34 45 DX D10 46 34 DX D11 99 47 DX D12 99 48 DX D13 50 47 DY D14 50 48 DY * * MODELS USED * .MODEL QX NPN(BF=9.09E6) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .MODEL DEN D(IS=1E-12, RS=1.74K, KF=4.01E-16, AF=1) .MODEL DIN D(IS=1E-12, RS=43.5E-6, KF=11.1E-15, AF=1) .ENDS * OP37C SPICE Macro-model 1/91, Rev. A * ARG / PMI * * This version of the OP-37 model simulates the worst case * parameters of the 'C' grade. The worst case parameters * used correspond to those in the data sheet. * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP37C 1 2 99 50 49 * * INPUT STAGE & POLE AT 100MHZ * R3 5 97 0.0516 R4 6 97 0.0516 CIN 1 2 4E-12 C2 5 6 15.42E-9 I1 4 51 1 IOS 1 2 37.5E-9 EOS 7 3 POLY(1) 30 43 100E-6 1 Q1 5 2 4 QX Q2 6 7 4 QX D1 2 1 DX D2 1 2 DX EN 3 1 9 0 1 GN1 0 2 12 0 1 GN2 0 1 15 0 1 EREF 98 0 43 0 1 EPLUS 97 0 99 0 1 ENEG 51 0 50 0 1 * * VOLTAGE NOISE SOURCE WITH FLICKER NOISE * DN1 8 9 DEN DN2 9 10 DEN VN1 8 0 DC 2 VN2 0 10 DC 2 * * CURRENT NOISE SOURCE WITH FLICKER NOISE * DN3 11 12 DIN DN4 12 13 DIN VN3 11 0 DC 2 VN4 0 13 DC 2 * * SECOND CURRENT NOISE SOURCE * DN5 14 15 DIN DN6 15 16 DIN VN5 14 0 DC 2 VN6 0 16 DC 2 * * 1ST GAIN STAGE * R5 17 98 1 G1A 98 17 5 6 98.70 D3 17 18 DX D4 19 17 DX E1 97 18 POLY(1) 97 43 -2.14 1 E2 19 51 POLY(1) 43 51 -2.14 1 * * 2ND GAIN STAGE & DOMINANT POLE AT 82HZ * R6 20 98 21.28E3 C3 20 98 90.91E-9 G1B 98 20 17 43 333.3E-3 V1 97 21 4 V2 22 51 4 D5 20 21 DX D6 22 20 DX * * POLE - ZERO AT .4MHZ / 1.0MHZ * R8 23 98 1 R9 23 24 0.667 C4 24 98 238.7E-9 G2 98 23 20 43 1 * * ZERO - POLE AT 10MHZ / 100MHZ * R10 25 26 1 R11 26 98 9 L1 26 98 14.32E-9 G3 98 25 23 43 1 * * POLE AT 100MHZ * R12 27 98 1 C5 27 98 1.59E-9 G4 98 27 25 43 1 * * POLE AT 100MHZ * R13 28 98 1 C6 28 98 1.59E-9 G5 98 28 27 43 1 * * POLE AT 100MHZ * R14 29 98 1 C7 29 98 1.59E-9 G6 98 29 28 43 1 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 140KHZ * R15 30 31 1 L2 31 98 1.14E-6 G7 98 30 POLY(2) 1 43 2 43 0 5E-6 5E-6 D7 30 97 DX D8 51 30 DX * * POLE AT 100MHZ * R16 32 98 1 C8 32 98 1.59E-9 G8 98 32 29 43 1 * * POLE AT 100MHZ * R17 33 98 1 C9 33 98 1.59E-9 G9 98 33 32 43 1 * * POLE AT 200MHZ * R18 34 98 1 C10 34 98 .796E-9 G10 98 34 33 43 1 * * OUTPUT STAGE * F1 44 0 V3 1 F2 0 44 V4 1 R27 43 97 1 R28 43 51 1 GSY 99 50 POLY(1) 99 50 4.32E-3 45E-6 R29 44 99 140 R30 44 50 140 L4 44 49 1E-7 G11 47 50 34 44 7.14E-3 G12 48 50 44 34 7.14E-3 G13 44 99 99 34 7.14E-3 G14 50 44 34 50 7.14E-3 V3 45 44 1.2 V4 44 46 1.55 D9 34 45 DX D10 46 34 DX D11 99 47 DX D12 99 48 DX D13 50 47 DY D14 50 48 DY * * MODELS USED * .MODEL QX NPN(BF=6.25E6) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .MODEL DEN D(IS=1E-12, RS=2.45K, KF=7.93E-16, AF=1) .MODEL DIN D(IS=1E-12, RS=43.5E-6, KF=11.1E-15, AF=1) .ENDS * OP37E SPICE Model 1/90, Rev. A * ARG / PMI * * This version of the OP-37 model simulates the worst case * parameters of the 'E' grade. The worst case parameters * used correspond to those in the data sheet. * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP37E 1 2 99 50 49 * * INPUT STAGE & POLE AT 100MHZ * R3 5 97 0.0516 R4 6 97 0.0516 CIN 1 2 4E-12 C2 5 6 15.42E-9 I1 4 51 1 IOS 1 2 17.5E-9 EOS 7 3 POLY(1) 30 43 25E-6 1 Q1 5 2 4 QX Q2 6 7 4 QX D1 2 1 DX D2 1 2 DX EN 3 1 9 0 1 GN1 0 2 12 0 1 GN2 0 1 15 0 1 EREF 98 0 43 0 1 EPLUS 97 0 99 0 1 ENEG 51 0 50 0 1 * * VOLTAGE NOISE SOURCE WITH FLICKER NOISE * DN1 8 9 DEN DN2 9 10 DEN VN1 8 0 DC 2 VN2 0 10 DC 2 * * CURRENT NOISE SOURCE WITH FLICKER NOISE * DN3 11 12 DIN DN4 12 13 DIN VN3 11 0 DC 2 VN4 0 13 DC 2 * * SECOND CURRENT NOISE SOURCE * DN5 14 15 DIN DN6 15 16 DIN VN5 14 0 DC 2 VN6 0 16 DC 2 * * 1ST GAIN STAGE * R5 17 98 1 G1A 98 17 5 6 98.71 D3 17 18 DX D4 19 17 DX E1 97 18 POLY(1) 97 43 -2.14 1 E2 19 51 POLY(1) 43 51 -2.14 1 * * 2ND GAIN STAGE & DOMINANT POLE AT 58HZ * R6 20 98 30.39E3 C3 20 98 90.91E-9 G1B 98 20 17 43 333.3E-3 V1 97 21 3.48 V2 22 51 3.48 D5 20 21 DX D6 22 20 DX * * POLE - ZERO AT .4MHZ / 1.0MHZ * R8 23 98 1 R9 23 24 0.667 C4 24 98 238.7E-9 G2 98 23 20 43 1 * * ZERO - POLE AT 10MHZ / 100MHZ * R10 25 26 1 R11 26 98 9 L1 26 98 14.32E-9 G3 98 25 23 43 1 * * POLE AT 100MHZ * R12 27 98 1 C5 27 98 1.59E-9 G4 98 27 25 43 1 * * POLE AT 100MHZ * R13 28 98 1 C6 28 98 1.59E-9 G5 98 28 27 43 1 * * POLE AT 100MHZ * R14 29 98 1 C7 29 98 1.59E-9 G6 98 29 28 43 1 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 28KHZ * R15 30 31 1 L2 31 98 5.68E-6 G7 98 30 POLY(2) 1 43 2 43 0 997.6E-9 997.6E-9 D7 30 97 DX D8 51 30 DX * * POLE AT 100MHZ * R16 32 98 1 C8 32 98 1.59E-9 G8 98 32 29 43 1 * * POLE AT 100MHZ * R17 33 98 1 C9 33 98 1.59E-9 G9 98 33 32 43 1 * * POLE AT 200MHZ * R18 34 98 1 C10 34 98 .796E-9 G10 98 34 33 43 1 * * OUTPUT STAGE * F1 44 0 V3 1 F2 0 44 V4 1 R27 43 97 1 R28 43 51 1 GSY 99 50 POLY(1) 99 50 3.32E-3 45E-6 R29 44 99 140 R30 44 50 140 L4 44 49 1E-7 G11 47 50 34 44 7.14E-3 G12 48 50 44 34 7.14E-3 G13 44 99 99 34 7.14E-3 G14 50 44 34 50 7.14E-3 V3 45 44 1.2 V4 44 46 1.55 D9 34 45 DX D10 46 34 DX D11 99 47 DX D12 99 48 DX D13 50 47 DY D14 50 48 DY * * MODELS USED * .MODEL QX NPN(BF=12.5E6) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .MODEL DEN D(IS=1E-12, RS=1.74K, KF=4.01E-16, AF=1) .MODEL DIN D(IS=1E-12, RS=43.5E-6, KF=11.1E-15, AF=1) .ENDS * OP37F SPICE Macro-model 1/91, Rev. A * ARG / PMI * * This version of the OP-37 model simulates the worst case * parameters of the 'F' grade. The worst case parameters * used correspond to those in the data sheet. * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP37F 1 2 99 50 49 * * INPUT STAGE & POLE AT 100MHZ * R3 5 97 0.0516 R4 6 97 0.0516 CIN 1 2 4E-12 C2 5 6 15.42E-9 I1 4 51 1 IOS 1 2 25E-9 EOS 7 3 POLY(1) 30 43 60E-6 1 Q1 5 2 4 QX Q2 6 7 4 QX D1 2 1 DX D2 1 2 DX EN 3 1 9 0 1 GN1 0 2 12 0 1 GN2 0 1 15 0 1 EREF 98 0 43 0 1 EPLUS 97 0 99 0 1 ENEG 51 0 50 0 1 * * VOLTAGE NOISE SOURCE WITH FLICKER NOISE * DN1 8 9 DEN DN2 9 10 DEN VN1 8 0 DC 2 VN2 0 10 DC 2 * * CURRENT NOISE SOURCE WITH FLICKER NOISE * DN3 11 12 DIN DN4 12 13 DIN VN3 11 0 DC 2 VN4 0 13 DC 2 * * SECOND CURRENT NOISE SOURCE * DN5 14 15 DIN DN6 15 16 DIN VN5 14 0 DC 2 VN6 0 16 DC 2 * * 1ST GAIN STAGE * R5 17 98 1 G1A 98 17 5 6 98.71 D3 17 18 DX D4 19 17 DX E1 97 18 POLY(1) 97 43 -2.14 1 E2 19 51 POLY(1) 43 51 -2.14 1 * * 2ND GAIN STAGE & DOMINANT POLE AT 58HZ * R6 20 98 30.39E3 C3 20 98 90.91E-9 G1B 98 20 17 43 333.3E-3 V1 97 21 3.48 V2 22 51 3.48 D5 20 21 DX D6 22 20 DX * * POLE - ZERO AT .4MHZ / 1.0MHZ * R8 23 98 1 R9 23 24 0.667 C4 24 98 238.7E-9 G2 98 23 20 43 1 * * ZERO - POLE AT 10MHZ / 100MHZ * R10 25 26 1 R11 26 98 9 L1 26 98 14.32E-9 G3 98 25 23 43 1 * * POLE AT 100MHZ * R12 27 98 1 C5 27 98 1.59E-9 G4 98 27 25 43 1 * * POLE AT 100MHZ * R13 28 98 1 C6 28 98 1.59E-9 G5 98 28 27 43 1 * * POLE AT 100MHZ * R14 29 98 1 C7 29 98 1.59E-9 G6 98 29 28 43 1 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 70KHZ * R15 30 31 1 L2 31 98 2.27E-6 G7 98 30 POLY(2) 1 43 2 43 0 2.506E-6 2.506E-6 D7 30 97 DX D8 51 30 DX * * POLE AT 100MHZ * R16 32 98 1 C8 32 98 1.59E-9 G8 98 32 29 43 1 * * POLE AT 100MHZ * R17 33 98 1 C9 33 98 1.59E-9 G9 98 33 32 43 1 * * POLE AT 200MHZ * R18 34 98 1 C10 34 98 .796E-9 G10 98 34 33 43 1 * * OUTPUT STAGE * F1 44 0 V3 1 F2 0 44 V4 1 R27 43 97 1 R28 43 51 1 GSY 99 50 POLY(1) 99 50 3.32E-3 45E-6 R29 44 99 140 R30 44 50 140 L4 44 49 1E-7 G11 47 50 34 44 7.14E-3 G12 48 50 44 34 7.14E-3 G13 44 99 99 34 7.14E-3 G14 50 44 34 50 7.14E-3 V3 45 44 1.2 V4 44 46 1.55 D9 34 45 DX D10 46 34 DX D11 99 47 DX D12 99 48 DX D13 50 47 DY D14 50 48 DY * * MODELS USED * .MODEL QX NPN(BF=9.09E6) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .MODEL DEN D(IS=1E-12, RS=1.74K, KF=4.01E-16, AF=1) .MODEL DIN D(IS=1E-12, RS=43.5E-6, KF=11.1E-15, AF=1) .ENDS * OP37G SPICE Macro-model 1/91, Rev. A * ARG / PMI * * This version of the OP-37 model simulates the worst case * parameters of the 'G' grade. The worst case parameters * used correspond to those in the data sheet. * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP37G 1 2 99 50 49 * * INPUT STAGE & POLE AT 100MHZ * R3 5 97 0.0516 R4 6 97 0.0516 CIN 1 2 4E-12 C2 5 6 15.42E-9 I1 4 51 1 IOS 1 2 37.5E-9 EOS 7 3 POLY(1) 30 43 100E-6 1 Q1 5 2 4 QX Q2 6 7 4 QX D1 2 1 DX D2 1 2 DX EN 3 1 9 0 1 GN1 0 2 12 0 1 GN2 0 1 15 0 1 EREF 98 0 43 0 1 EPLUS 97 0 99 0 1 ENEG 51 0 50 0 1 * * VOLTAGE NOISE SOURCE WITH FLICKER NOISE * DN1 8 9 DEN DN2 9 10 DEN VN1 8 0 DC 2 VN2 0 10 DC 2 * * CURRENT NOISE SOURCE WITH FLICKER NOISE * DN3 11 12 DIN DN4 12 13 DIN VN3 11 0 DC 2 VN4 0 13 DC 2 * * SECOND CURRENT NOISE SOURCE * DN5 14 15 DIN DN6 15 16 DIN VN5 14 0 DC 2 VN6 0 16 DC 2 * * 1ST GAIN STAGE * R5 17 98 1 G1A 98 17 5 6 98.70 D3 17 18 DX D4 19 17 DX E1 97 18 POLY(1) 97 43 -2.14 1 E2 19 51 POLY(1) 43 51 -2.14 1 * * 2ND GAIN STAGE & DOMINANT POLE AT 82HZ * R6 20 98 21.28E3 C3 20 98 90.91E-9 G1B 98 20 17 43 333.3E-3 V1 97 21 4 V2 22 51 4 D5 20 21 DX D6 22 20 DX * * POLE - ZERO AT .4MHZ / 1.0MHZ * R8 23 98 1 R9 23 24 0.667 C4 24 98 238.7E-9 G2 98 23 20 43 1 * * ZERO - POLE AT 10MHZ / 100MHZ * R10 25 26 1 R11 26 98 9 L1 26 98 14.32E-9 G3 98 25 23 43 1 * * POLE AT 100MHZ * R12 27 98 1 C5 27 98 1.59E-9 G4 98 27 25 43 1 * * POLE AT 100MHZ * R13 28 98 1 C6 28 98 1.59E-9 G5 98 28 27 43 1 * * POLE AT 100MHZ * R14 29 98 1 C7 29 98 1.59E-9 G6 98 29 28 43 1 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 140KHZ * R15 30 31 1 L2 31 98 1.14E-6 G7 98 30 POLY(2) 1 43 2 43 0 5E-6 5E-6 D7 30 97 DX D8 51 30 DX * * POLE AT 100MHZ * R16 32 98 1 C8 32 98 1.59E-9 G8 98 32 29 43 1 * * POLE AT 100MHZ * R17 33 98 1 C9 33 98 1.59E-9 G9 98 33 32 43 1 * * POLE AT 200MHZ * R18 34 98 1 C10 34 98 .796E-9 G10 98 34 33 43 1 * * OUTPUT STAGE * F1 44 0 V3 1 F2 0 44 V4 1 R27 43 97 1 R28 43 51 1 GSY 99 50 POLY(1) 99 50 4.32E-3 45E-6 R29 44 99 140 R30 44 50 140 L4 44 49 1E-7 G11 47 50 34 44 7.14E-3 G12 48 50 44 34 7.14E-3 G13 44 99 99 34 7.14E-3 G14 50 44 34 50 7.14E-3 V3 45 44 1.2 V4 44 46 1.55 D9 34 45 DX D10 46 34 DX D11 99 47 DX D12 99 48 DX D13 50 47 DY D14 50 48 DY * * MODELS USED * .MODEL QX NPN(BF=6.25E6) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .MODEL DEN D(IS=1E-12, RS=2.45K, KF=7.93E-16, AF=1) .MODEL DIN D(IS=1E-12, RS=43.5E-6, KF=11.1E-15, AF=1) .ENDS * OP400A SPICE Macro-model 12/90, Rev. B * AAG / PMI * * Revision History: * Re-ordered subcircuit call out nodes to put the * output node last. * Changed Ios from 1E-9 to 5E-10 * * This version of the OP-400 model simulates the worst case * parameters of the 'A' grade. The worst case parameters * used correspond to those in the data sheet. * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP400A 1 2 100 101 29 * * INPUT STAGE & POLE AT 4.5 MHZ * RI1 2 9 1K RI2 1 10 1K IOS 10 9 0.5N CIN 9 10 3.2P R1 9 3 8.62MEG R2 3 10 8.62MEG D1 10 9 DX D2 9 10 DX R3 100 5 517.2 R4 100 6 517.2 C2 5 6 34.192P EOS 11 10 POLY(1) 20 23 150U 1 Q1 5 9 4 QX Q2 6 11 4 QX I1 4 101 0.1M * * FIRST GAIN STAGE * EREF 12 0 23 0 1 G1 12 13 5 6 117.81 R5 13 12 1 E1 100 14 POLY(1) 100 23 -2.4 1 D3 13 14 DX E2 15 101 POLY(1) 23 101 -2.4 1 D4 15 13 DX * * SECOND GAIN STAGE & DOMINANT POLE AT 0.3125 HZ * G2 12 16 13 23 33.33U R6 16 12 509.29MEG C3 16 12 1000P V1 100 17 DC 3.9725 D5 16 17 DX V2 18 101 DC 3.9725 D6 18 16 DX * * COMMON-MODE GAIN NETWORK WITH ZERO AT 200 HZ * ECM 19 12 3 23 1 R7 19 20 1MEG R8 20 12 1 C4 19 20 795.77P * * POLE AT 4.5 MHZ * G3 12 21 16 23 1U R9 21 12 1MEG C5 21 12 35.368F * * POLE AT 4.5 MHZ * G4 12 22 21 23 1U R10 22 12 1MEG C6 22 12 35.368F * * OUTPUT STAGE * R11 100 23 533.33K R12 23 101 533.33K IDC 100 101 DC 597U V3 25 28 DC 2.9 D7 22 25 DX V4 28 26 DC 3.025 D8 26 22 DX D9 100 24 DX D10 100 27 DX G5 24 101 22 28 4M D11 101 24 DY G6 27 101 28 22 4M D12 101 27 DY G7 28 100 100 22 4M R13 100 28 250 G8 101 28 22 101 4M R14 28 101 250 L1 28 29 0.7U * * MODELS USED * .MODEL QX NPN(BF=16667) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP400E SPICE Macro-model 12/90, Rev. B * AAG / PMI * * Revision History: * Re-ordered subcircuit call out nodes to put the * output node last. * Changed Ios from 1E-9 to 5E-10 * * This version of the OP-400 model simulates the worst case * parameters of the 'E' grade. The worst case parameters * used correspond to those in the data sheet. * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP400E 1 2 100 101 29 * * INPUT STAGE & POLE AT 4.5 MHZ * RI1 2 9 1K RI2 1 10 1K IOS 10 9 0.5N CIN 9 10 3.2P R1 9 3 8.62MEG R2 3 10 8.62MEG D1 10 9 DX D2 9 10 DX R3 100 5 517.2 R4 100 6 517.2 C2 5 6 34.192P EOS 11 10 POLY(1) 20 23 150U 1 Q1 5 9 4 QX Q2 6 11 4 QX I1 4 101 0.1M * * FIRST GAIN STAGE * EREF 12 0 23 0 1 G1 12 13 5 6 117.81 R5 13 12 1 E1 100 14 POLY(1) 100 23 -2.4 1 D3 13 14 DX E2 15 101 POLY(1) 23 101 -2.4 1 D4 15 13 DX * * SECOND GAIN STAGE & DOMINANT POLE AT 0.3125 HZ * G2 12 16 13 23 33.33U R6 16 12 509.29MEG C3 16 12 1000P V1 100 17 DC 3.9725 D5 16 17 DX V2 18 101 DC 3.9725 D6 18 16 DX * * COMMON-MODE GAIN NETWORK WITH ZERO AT 200 HZ * ECM 19 12 3 23 1 R7 19 20 1MEG R8 20 12 1 C4 19 20 795.77P * * POLE AT 4.5 MHZ * G3 12 21 16 23 1U R9 21 12 1MEG C5 21 12 35.368F * * POLE AT 4.5 MHZ * G4 12 22 21 23 1U R10 22 12 1MEG C6 22 12 35.368F * * OUTPUT STAGE * R11 100 23 533.33K R12 23 101 533.33K IDC 100 101 DC 597U V3 25 28 DC 2.9 D7 22 25 DX V4 28 26 DC 3.025 D8 26 22 DX D9 100 24 DX D10 100 27 DX G5 24 101 22 28 4M D11 101 24 DY G6 27 101 28 22 4M D12 101 27 DY G7 28 100 100 22 4M R13 100 28 250 G8 101 28 22 101 4M R14 28 101 250 L1 28 29 0.7U * * MODELS USED * .MODEL QX NPN(BF=16667) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP400F SPICE Macro-model 12/90, Rev. B * AAG / PMI * * Revision History: * Re-ordered subcircuit call out nodes to put the * output node last. * Changed Ios from 2E-9 to 1E-9 * * This version of the OP-400 model simulates the worst case * parameters of the 'F' grade. The worst case parameters * used correspond to those in the data sheet. * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP400F 1 2 100 101 29 * * INPUT STAGE & POLE AT 4.5 MHZ * RI1 2 9 1K RI2 1 10 1K IOS 10 9 1N CIN 9 10 3.2P R1 9 3 4.31MEG R2 3 10 4.31MEG D1 10 9 DX D2 9 10 DX R3 100 5 517.2 R4 100 6 517.2 C2 5 6 34.192P EOS 11 10 POLY(1) 20 23 230U 1 Q1 5 9 4 QX Q2 6 11 4 QX I1 4 101 0.1M * * FIRST GAIN STAGE * EREF 12 0 23 0 1 G1 12 13 5 6 117.81 R5 13 12 1 E1 100 14 POLY(1) 100 23 -2.4 1 D3 13 14 DX E2 15 101 POLY(1) 23 101 -2.4 1 D4 15 13 DX * * SECOND GAIN STAGE & DOMINANT POLE AT 0.417 HZ * G2 12 16 13 23 33.33U R6 16 12 381.97MEG C3 16 12 1000P V1 100 17 DC 3.9725 D5 16 17 DX V2 18 101 DC 3.9725 D6 18 16 DX * * COMMON-MODE GAIN NETWORK WITH ZERO AT 355.66 HZ * ECM 19 12 3 23 1.7783 R7 19 20 1MEG R8 20 12 1 C4 19 20 447.49P * * POLE AT 4.5 MHZ * G3 12 21 16 23 1U R9 21 12 1MEG C5 21 12 35.368F * * POLE AT 4.5 MHZ * G4 12 22 21 23 1U R10 22 12 1MEG C6 22 12 35.368F * * OUTPUT STAGE * R11 100 23 533.33K R12 23 101 533.33K IDC 100 101 DC 597U V3 25 28 DC 2.9 D7 22 25 DX V4 28 26 DC 3.025 D8 26 22 DX D9 100 24 DX D10 100 27 DX G5 24 101 22 28 4M D11 101 24 DY G6 27 101 28 22 4M D12 101 27 DY G7 28 100 100 22 4M R13 100 28 250 G8 101 28 22 101 4M R14 28 101 250 L1 28 29 0.7U * * MODELS USED * .MODEL QX NPN(BF=8333) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP400G SPICE Macro-model 12/90, Rev. B * AAG / PMI * * Revision History: * Re-ordered subcircuit call out nodes to put the * output node last. * Changed Ios from 3.5E-9 to 1.75E-9 * * This version of the OP-400 model simulates the worst case * parameters of the 'G' grade. The worst case parameters * used correspond to those in the data sheet. * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP400G 1 2 100 101 29 * * INPUT STAGE & POLE AT 4.5 MHZ * RI1 2 9 1K RI2 1 10 1K IOS 10 9 1.75N CIN 9 10 3.2P R1 9 3 3.69MEG R2 3 10 3.69MEG D1 10 9 DX D2 9 10 DX R3 100 5 517.2 R4 100 6 517.2 C2 5 6 34.192P EOS 11 10 POLY(1) 20 23 300U 1 Q1 5 9 4 QX Q2 6 11 4 QX I1 4 101 0.1M * * FIRST GAIN STAGE * EREF 12 0 23 0 1 G1 12 13 5 6 117.81 R5 13 12 1 E1 100 14 POLY(1) 100 23 -2.4 1 D3 13 14 DX E2 15 101 POLY(1) 23 101 -2.4 1 D4 15 13 DX * * SECOND GAIN STAGE & DOMINANT POLE AT 0.417 HZ * G2 12 16 13 23 33.33U R6 16 12 381.97MEG C3 16 12 1000P V1 100 17 DC 3.9725 D5 16 17 DX V2 18 101 DC 3.9725 D6 18 16 DX * * COMMON-MODE GAIN NETWORK WITH ZERO AT 632.49 HZ * ECM 19 12 3 23 3.1623 R7 19 20 1MEG R8 20 12 1 C4 19 20 251.63P * * POLE AT 4.5 MHZ * G3 12 21 16 23 1U R9 21 12 1MEG C5 21 12 35.368F * * POLE AT 4.5 MHZ * G4 12 22 21 23 1U R10 22 12 1MEG C6 22 12 35.368F * * OUTPUT STAGE * R11 100 23 533.33K R12 23 101 533.33K IDC 100 101 DC 597U V3 25 28 DC 2.9 D7 22 25 DX V4 28 26 DC 3.025 D8 26 22 DX D9 100 24 DX D10 100 27 DX G5 24 101 22 28 4M D11 101 24 DY G6 27 101 28 22 4M D12 101 27 DY G7 28 100 100 22 4M R13 100 28 250 G8 101 28 22 101 4M R14 28 101 250 L1 28 29 0.7U * * MODELS USED * .MODEL QX NPN(BF=7143) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP400H SPICE Macro-model 12/90, Rev. B * AAG / PMI * * Revision History: * Re-ordered subcircuit call out nodes to put the * output node last. * Changed Ios from 3.5E-9 to 1.75E-9 * * This version of the OP-400 model simulates the worst case * parameters of the 'H' grade. The worst case parameters * used correspond to those in the data sheet. * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP400H 1 2 100 101 29 * * INPUT STAGE & POLE AT 4.5 MHZ * RI1 2 9 1K RI2 1 10 1K IOS 10 9 1.75N CIN 9 10 3.2P R1 9 3 3.69MEG R2 3 10 3.69MEG D1 10 9 DX D2 9 10 DX R3 100 5 517.2 R4 100 6 517.2 C2 5 6 34.192P EOS 11 10 POLY(1) 20 23 300U 1 Q1 5 9 4 QX Q2 6 11 4 QX I1 4 101 0.1M * * FIRST GAIN STAGE * EREF 12 0 23 0 1 G1 12 13 5 6 117.81 R5 13 12 1 E1 100 14 POLY(1) 100 23 -2.4 1 D3 13 14 DX E2 15 101 POLY(1) 23 101 -2.4 1 D4 15 13 DX * * SECOND GAIN STAGE & DOMINANT POLE AT 0.417 HZ * G2 12 16 13 23 33.33U R6 16 12 381.97MEG C3 16 12 1000P V1 100 17 DC 3.9725 D5 16 17 DX V2 18 101 DC 3.9725 D6 18 16 DX * * COMMON-MODE GAIN NETWORK WITH ZERO AT 632.49 HZ * ECM 19 12 3 23 3.1623 R7 19 20 1MEG R8 20 12 1 C4 19 20 251.63P * * POLE AT 4.5 MHZ * G3 12 21 16 23 1U R9 21 12 1MEG C5 21 12 35.368F * * POLE AT 4.5 MHZ * G4 12 22 21 23 1U R10 22 12 1MEG C6 22 12 35.368F * * OUTPUT STAGE * R11 100 23 533.33K R12 23 101 533.33K IDC 100 101 DC 597U V3 25 28 DC 2.9 D7 22 25 DX V4 28 26 DC 3.025 D8 26 22 DX D9 100 24 DX D10 100 27 DX G5 24 101 22 28 4M D11 101 24 DY G6 27 101 28 22 4M D12 101 27 DY G7 28 100 100 22 4M R13 100 28 250 G8 101 28 22 101 4M R14 28 101 250 L1 28 29 0.7U * * MODELS USED * .MODEL QX NPN(BF=7143) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP413 SPICE Macro-model 3/94, Rev. A * ARG / PMI * * Copyright 1992 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License * Statement. * * Node assignments * * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP413 3 2 7 4 6 * * INPUT STAGE * R3 4 19 1.5E3 R4 4 20 1.5E3 C1 19 20 5.31E-12 I1 7 18 106E-6 IOS 2 3 25E-09 EOS 12 5 POLY(1) 51 4 25E-06 1 Q1 19 3 18 PNP1 Q2 20 12 18 PNP1 CIN 3 2 3E-12 D1 3 1 DY D2 2 1 DY EN 5 2 22 0 1 GN1 0 2 25 0 1E-5 GN2 0 3 28 0 1E-5 * * VOLTAGE NOISE SOURCE WITH FLICKER NOISE * DN1 21 22 DEN DN2 22 23 DEN VN1 21 0 DC 2 VN2 0 23 DC 2 * * CURRENT NOISE SOURCE WITH FLICKER NOISE * DN3 24 25 DIN DN4 25 26 DIN VN3 24 0 DC 2 VN4 0 26 DC 2 * * SECOND CURRENT NOISE SOURCE * DN5 27 28 DIN DN6 28 29 DIN VN5 27 0 DC 2 VN6 0 29 DC 2 * * GAIN STAGE & DOMINANT POLE AT 2HZ * G2 34 36 19 20 2.65E-04 R7 34 36 39E6 V3 35 4 DC 6 D4 36 35 DX VB2 34 4 1.6 * * SUPPLY/2 GENERATOR * ISY 7 4 0.2E-3 R10 7 60 40E3 R11 60 4 40E3 C3 60 0 1E-9 * * CMRR STAGE & POLE AT 6kHZ * ECM 50 4 POLY(2) 3 60 2 60 0 0.8 0.8 CCM 50 51 26.5E-12 RCM1 50 51 1E6 RCM2 51 4 1 * * OUTPUT STAGE * R12 37 36 1E3 R13 38 36 500 C4 37 6 20E-12 C5 38 39 20E-12 M1 39 36 4 4 MN L=9E-6 W=1000E-6 AD=15E-9 AS=15E-9 M2 45 36 4 4 MN L=9E-6 W=1000E-6 AD=15E-9 AS=15E-9 D5 39 47 DX D6 47 45 DX Q3 39 40 41 QPA 8 VB 7 40 DC 0.861 R14 7 41 375 Q4 41 7 43 QNA 1 R17 7 43 15 Q5 43 39 6 QNA 20 Q6 46 45 6 QPA 20 R18 46 4 15 Q7 36 46 4 QNA 1 M3 6 36 4 4 MN L=9E-6 W=2000E-6 AD=30E-9 AS=30E-9 * * NONLINEAR MODELS USED * .MODEL DX D (IS=1E-15) .MODEL DY D (IS=1E-15 BV=7) .MODEL PNP1 PNP (BF=220) .MODEL DEN D(IS=1E-12 RS=1016 KF=3.278E-15 AF=1) .MODEL DIN D(IS=1E-12 RS=100019 KF=4.173E-15 AF=1) .MODEL QNA NPN(IS=1.19E-16 BF=253 VAF=193 VAR=15 RB=2.0E3 + IRB=7.73E-6 RBM=132.8 RE=4 RC=209 CJE=2.1E-13 VJE=0.573 + MJE=0.364 CJC=1.64E-13 VJC=0.534 MJC=0.5 CJS=1.37E-12 + VJS=0.59 MJS=0.5 TF=0.43E-9 PTF=30) .MODEL QPA PNP(IS=5.21E-17 BF=131 VAF=62 VAR=15 RB=1.52E3 + IRB=1.67E-5 RBM=368.5 RE=6.31 RC=354.4 CJE=1.1E-13 + VJE=0.745 MJE=0.33 CJC=2.37E-13 VJC=0.762 MJC=0.4 + CJS=7.11E-13 VJS=0.45 MJS=0.412 TF=1.0E-9 PTF=30) .MODEL MN NMOS(LEVEL=3 VTO=1.3 RS=0.3 RD=0.3 TOX=8.5E-8 + LD=1.48E-6 NSUB=1.53E16 UO=650 DELTA=10 VMAX=2E5 + XJ=1.75E-6 KAPPA=0.8 ETA=0.066 THETA=0.01 TPG=1 CJ=2.9E-4 + PB=0.837 MJ=0.407 CJSW=0.5E-9 MJSW=0.33) .ENDS * OP413E SPICE Macro-model 3/94, Rev. A * ARG / PMI * * This version of the OP413 model simulates the worst-case * parameters of the 'E' grade. The worst-case parameters * used correspond to those in the data sheet. * * Copyright 1992 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License * Statement. * * Node assignments * * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP413E 3 2 7 4 6 * * INPUT STAGE AND POLE AT 40MHZ * R3 4 19 1.5E3 R4 4 20 1.5E3 C1 19 20 1.326E-12 I1 7 18 106E-6 IOS 2 3 25E-9 EOS 12 5 POLY(1) 51 4 100E-6 1 Q1 19 3 18 PNP1 Q2 20 12 18 PNP1 CIN 3 2 3E-12 D1 3 1 DY D2 2 1 DY EN 5 2 22 0 1 GN1 0 2 25 0 1E-5 GN2 0 3 28 0 1E-5 * * VOLTAGE NOISE SOURCE WITH FLICKER NOISE * DN1 21 22 DEN DN2 22 23 DEN VN1 21 0 DC 2 VN2 0 23 DC 2 * * CURRENT NOISE SOURCE WITH FLICKER NOISE * DN3 24 25 DIN DN4 25 26 DIN VN3 24 0 DC 2 VN4 0 26 DC 2 * * SECOND CURRENT NOISE SOURCE * DN5 27 28 DIN DN6 28 29 DIN VN5 27 0 DC 2 VN6 0 29 DC 2 * * GAIN STAGE & DOMINANT POLE AT 1.581HZ * G2 34 36 19 20 54.814E-6 R7 34 36 39E6 V3 35 4 DC 6 D4 36 35 DX VB2 34 4 1.6 * * SUPPLY/2 GENERATOR * ISY 7 4 0.525E-3 R10 7 60 40E3 R11 60 4 40E3 C3 60 0 1E-9 * * CMRR STAGE & POLE AT 6KHZ * ECM 50 4 POLY(2) 3 60 2 60 0 0.5 0.5 CCM 50 51 26.5E-12 RCM1 50 51 1E6 RCM2 51 4 10 * * OUTPUT STAGE * R12 37 36 2E3 R13 38 36 200 C4 37 6 4E-12 C5 38 39 4E-12 M1 39 36 4 4 MN L=9E-6 W=1000E-6 AD=15E-9 AS=15E-9 M2 45 36 4 4 MN L=9E-6 W=1000E-6 AD=15E-9 AS=15E-9 D5 39 47 DX D6 47 45 DX Q3 39 40 41 QPA 8 VB 7 40 DC 0.861 R14 7 41 375 Q4 41 7 43 QNA 1 R17 7 43 15 Q5 43 39 6 QNA 20 Q6 46 45 6 QPA 20 R18 46 4 15 Q7 36 46 4 QNA 1 M3 6 36 4 4 MN L=9E-6 W=2000E-6 AD=30E-9 AS=30E-9 * * NONLINEAR MODELS USED * .MODEL DX D (IS=1E-15) .MODEL DY D (IS=1E-15 BV=7) .MODEL PNP1 PNP (BF=87.333) .MODEL DEN D(IS=1E-12 RS=1016 KF=3.278E-15 AF=1) .MODEL DIN D(IS=1E-12 RS=100019 KF=4.173E-15 AF=1) .MODEL QNA NPN(IS=1.19E-16 BF=253 VAF=193 VAR=15 RB=2.0E3 + IRB=7.73E-6 RBM=132.8 RE=4 RC=209 CJE=2.1E-13 VJE=0.573 + MJE=0.364 CJC=1.64E-13 VJC=0.534 MJC=0.5 CJS=0.685E-12 + VJS=0.59 MJS=0.5 TF=0.43E-9 PTF=30) .MODEL QPA PNP(IS=5.21E-17 BF=131 VAF=62 VAR=15 RB=1.52E3 + IRB=1.67E-5 RBM=368.5 RE=6.31 RC=354.4 CJE=1.1E-13 + VJE=0.745 MJE=0.33 CJC=2.37E-13 VJC=0.762 MJC=0.4 + CJS=7.11E-13 VJS=0.45 MJS=0.412 TF=1.0E-9 PTF=30) .MODEL MN NMOS(LEVEL=3 VTO=1.3 RS=0.3 RD=0.3 TOX=8.5E-8 + LD=1.48E-6 NSUB=1.53E16 UO=650 DELTA=10 VMAX=2E5 + XJ=1.75E-6 KAPPA=0.8 ETA=0.066 THETA=0.01 TPG=1 CJ=2.9E-5 + PB=0.837 MJ=0.407 CJSW=0.5E-10 MJSW=0.33) .ENDS * OP413F SPICE Macro-model 3/94, Rev. A * ARG / PMI * * This version of the OP413 model simulates the worst-case * parameters of the 'F' grade. The worst-case parameters * used correspond to those in the data sheet. * * Copyright 1992 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License * Statement. * * Node assignments * * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP413F 3 2 7 4 6 * * INPUT STAGE AND POLE AT 40MHZ * R3 4 19 1.5E3 R4 4 20 1.5E3 C1 19 20 1.326E-12 I1 7 18 106E-6 IOS 2 3 25E-9 EOS 12 5 POLY(1) 51 4 250E-6 1.585 Q1 19 3 18 PNP1 Q2 20 12 18 PNP1 CIN 3 2 3E-12 D1 3 1 DY D2 2 1 DY EN 5 2 22 0 1 GN1 0 2 25 0 1E-5 GN2 0 3 28 0 1E-5 * * VOLTAGE NOISE SOURCE WITH FLICKER NOISE * DN1 21 22 DEN DN2 22 23 DEN VN1 21 0 DC 2 VN2 0 23 DC 2 * * CURRENT NOISE SOURCE WITH FLICKER NOISE * DN3 24 25 DIN DN4 25 26 DIN VN3 24 0 DC 2 VN4 0 26 DC 2 * * SECOND CURRENT NOISE SOURCE * DN5 27 28 DIN DN6 28 29 DIN VN5 27 0 DC 2 VN6 0 29 DC 2 * * GAIN STAGE & DOMINANT POLE AT 1.581HZ * G2 34 36 19 20 54.814E-6 R7 34 36 39E6 V3 35 4 DC 6 D4 36 35 DX VB2 34 4 1.6 * * SUPPLY/2 GENERATOR * ISY 7 4 0.525E-3 R10 7 60 40E3 R11 60 4 40E3 C3 60 0 1E-9 * * CMRR STAGE & POLE AT 6KHZ * ECM 50 4 POLY(2) 3 60 2 60 0 0.5 0.5 CCM 50 51 26.5E-12 RCM1 50 51 1E6 RCM2 51 4 10 * * OUTPUT STAGE * R12 37 36 2E3 R13 38 36 200 C4 37 6 4E-12 C5 38 39 4E-12 M1 39 36 4 4 MN L=9E-6 W=1000E-6 AD=15E-9 AS=15E-9 M2 45 36 4 4 MN L=9E-6 W=1000E-6 AD=15E-9 AS=15E-9 D5 39 47 DX D6 47 45 DX Q3 39 40 41 QPA 8 VB 7 40 DC 0.861 R14 7 41 375 Q4 41 7 43 QNA 1 R17 7 43 15 Q5 43 39 6 QNA 20 Q6 46 45 6 QPA 20 R18 46 4 15 Q7 36 46 4 QNA 1 M3 6 36 4 4 MN L=9E-6 W=2000E-6 AD=30E-9 AS=30E-9 * * NONLINEAR MODELS USED * .MODEL DX D (IS=1E-15) .MODEL DY D (IS=1E-15 BV=7) .MODEL PNP1 PNP (BF=87.333) .MODEL DEN D(IS=1E-12 RS=1016 KF=3.278E-15 AF=1) .MODEL DIN D(IS=1E-12 RS=100019 KF=4.173E-15 AF=1) .MODEL QNA NPN(IS=1.19E-16 BF=253 VAF=193 VAR=15 RB=2.0E3 + IRB=7.73E-6 RBM=132.8 RE=4 RC=209 CJE=2.1E-13 VJE=0.573 + MJE=0.364 CJC=1.64E-13 VJC=0.534 MJC=0.5 CJS=0.685E-12 + VJS=0.59 MJS=0.5 TF=0.43E-9 PTF=30) .MODEL QPA PNP(IS=5.21E-17 BF=131 VAF=62 VAR=15 RB=1.52E3 + IRB=1.67E-5 RBM=368.5 RE=6.31 RC=354.4 CJE=1.1E-13 + VJE=0.745 MJE=0.33 CJC=2.37E-13 VJC=0.762 MJC=0.4 + CJS=7.11E-13 VJS=0.45 MJS=0.412 TF=1.0E-9 PTF=30) .MODEL MN NMOS(LEVEL=3 VTO=1.3 RS=0.3 RD=0.3 TOX=8.5E-8 + LD=1.48E-6 NSUB=1.53E16 UO=650 DELTA=10 VMAX=2E5 + XJ=1.75E-6 KAPPA=0.8 ETA=0.066 THETA=0.01 TPG=1 CJ=2.9E-5 + PB=0.837 MJ=0.407 CJSW=0.5E-10 MJSW=0.33) .ENDS * OP41A SPICE Macro-model 12/90, Rev. A * * * This version of the OP-41 model simulates the worst case * parameters of the 'A' grade. The worst case parameters * used correspond to those in the data book. * * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP41A 1 2 99 50 20 * * INPUT STAGE * R1 1 3 5E12 R2 2 3 5E12 R3 5 50 2.66K R4 6 50 2.66K CIN 1 2 5E-12 I1 99 4 1E-4 IOS 1 2 0.5E-12 EOS 7 1 POLY(1) 12 14 0.5E-3 1 J1 5 2 4 JX J2 6 7 4 JX GB1 2 50 POLY(3) 4,2 5,2 50,2 0 1E-12 1E-12 1E-12 GB2 7 50 POLY(3) 4,7 6,7 50,7 0 1E-12 1E-12 1E-12 * EREF 98 0 14 0 1 * * GAIN STAGE & DOMINANT POLE AT 0.60 HZ * R5 8 98 2.66E9 C2 8 98 100E-12 G1 98 8 5 6 376E-6 V2 99 9 2.7 V3 10 50 2.7 D1 8 9 DX D2 10 8 DX * * COMMON-MODE GAIN NETWORK WITH ZERO AT 1120 HZ * R6 11 12 1E6 C3 11 12 142E-12 R7 12 98 1 E2 11 98 3 14 10 * * POLE AT 2 MHZ * R8 13 98 1E6 C4 13 98 79.6E-15 G2 98 13 8 14 1E-6 * * OUTPUT STAGE * R9 14 99 400E3 R10 14 50 400E3 ISY 99 50 862.5E-6 R11 15 99 200 R12 15 50 200 L3 15 20 2.5E-8 G3 18 50 13 15 5E-3 G4 19 50 15 13 5E-3 G5 15 99 99 13 5E-3 G6 50 15 13 50 5E-3 V4 16 15 0.5 V5 15 17 0.5 D3 13 16 DX D4 17 13 DX D5 99 18 DX D6 99 19 DX D7 50 18 DY D8 50 19 DY * * MODELS USED * .MODEL JX PJF(BETA=706E-6 VTO=-2.000 IS=2.5E-12) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP41B SPICE Macro-model 12/90, Rev. A * * This version of the OP-41 model simulates the worst case * parameters of the 'B' grade. The worst case parameters * used correspond to those in the data book. * * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP41B 1 2 99 50 20 * * INPUT STAGE * R1 1 3 5E12 R2 2 3 5E12 R3 5 50 2.66K R4 6 50 2.66K CIN 1 2 5E-12 I1 99 4 1E-4 IOS 1 2 1E-12 EOS 7 1 POLY(1) 12 14 1.0E-3 1 J1 5 2 4 JX J2 6 7 4 JX GB1 2 50 POLY(3) 4,2 5,2 50,2 0 1E-12 1E-12 1E-12 GB2 7 50 POLY(3) 4,7 6,7 50,7 0 1E-12 1E-12 1E-12 * EREF 98 0 14 0 1 * * GAIN STAGE & DOMINANT POLE AT 1.2 HZ * R5 8 98 1.33E9 C2 8 98 100E-12 G1 98 8 5 6 376E-6 V2 99 9 3.0 V3 10 50 3.0 D1 8 9 DX D2 10 8 DX * * COMMON-MODE GAIN NETWORK WITH ZERO AT 3500 HZ * R6 11 12 1E6 C3 11 12 45.0E-12 R7 12 98 1 E2 11 98 3 14 31.6 * * POLE AT 2 MHZ * R8 13 98 1E6 C4 13 98 79.6E-15 G2 98 13 8 14 1E-6 * * OUTPUT STAGE * R9 14 99 400E3 R10 14 50 400E3 ISY 99 50 1062.5E-6 R11 15 99 200 R12 15 50 200 L3 15 20 2.5E-8 G3 18 50 13 15 5E-3 G4 19 50 15 13 5E-3 G5 15 99 99 13 5E-3 G6 50 15 13 50 5E-3 V4 16 15 0.5 V5 15 17 0.5 D3 13 16 DX D4 17 13 DX D5 99 18 DX D6 99 19 DX D7 50 18 DY D8 50 19 DY * * MODELS USED * .MODEL JX PJF(BETA=706E-6 VTO=-2.000 IS=5E-12) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP41E SPICE Macro-model 12/90, Rev. A * * This version of the OP-41 model simulates the worst case * parameters of the 'E' grade. The worst case parameters * used correspond to those in the data book. * * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP41E 1 2 99 50 20 * * INPUT STAGE * R1 1 3 5E12 R2 2 3 5E12 R3 5 50 2.66K R4 6 50 2.66K CIN 1 2 5E-12 I1 99 4 1E-4 IOS 1 2 0.5E-12 EOS 7 1 POLY(1) 12 14 0.25E-3 1 J1 5 2 4 JX J2 6 7 4 JX GB1 2 50 POLY(3) 4,2 5,2 50,2 0 1E-12 1E-12 1E-12 GB2 7 50 POLY(3) 4,7 6,7 50,7 0 1E-12 1E-12 1E-12 * EREF 98 0 14 0 1 * * GAIN STAGE & DOMINANT POLE AT 0.60 HZ * R5 8 98 2.66E9 C2 8 98 100E-12 G1 98 8 5 6 376E-6 V2 99 9 2.7 V3 10 50 2.7 D1 8 9 DX D2 10 8 DX * * COMMON-MODE GAIN NETWORK WITH ZERO AT 1120 HZ * R6 11 12 1E6 C3 11 12 142E-12 R7 12 98 1 E2 11 98 3 14 10 * * POLE AT 2 MHZ * R8 13 98 1E6 C4 13 98 79.6E-15 G2 98 13 8 14 1E-6 * * OUTPUT STAGE * R9 14 99 400E3 R10 14 50 400E3 ISY 99 50 862.5E-6 R11 15 99 200 R12 15 50 200 L3 15 20 2.5E-8 G3 18 50 13 15 5E-3 G4 19 50 15 13 5E-3 G5 15 99 99 13 5E-3 G6 50 15 13 50 5E-3 V4 16 15 0.5 V5 15 17 0.5 D3 13 16 DX D4 17 13 DX D5 99 18 DX D6 99 19 DX D7 50 18 DY D8 50 19 DY * * MODELS USED * .MODEL JX PJF(BETA=706E-6 VTO=-2.000 IS=2.5E-12) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP41F SPICE Macro-model 12/90, Rev. A * * This version of the OP-41 model simulates the worst case * parameters of the 'F' grade. The worst case parameters * used correspond to those in the data book. * * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP41F 1 2 99 50 20 * * INPUT STAGE * R1 1 3 5E12 R2 2 3 5E12 R3 5 50 2.66K R4 6 50 2.66K CIN 1 2 5E-12 I1 99 4 1E-4 IOS 1 2 1E-12 EOS 7 1 POLY(1) 12 14 0.75E-3 1 J1 5 2 4 JX J2 6 7 4 JX GB1 2 50 POLY(3) 4,2 5,2 50,2 0 1E-12 1E-12 1E-12 GB2 7 50 POLY(3) 4,7 6,7 50,7 0 1E-12 1E-12 1E-12 * EREF 98 0 14 0 1 * * GAIN STAGE & DOMINANT POLE AT 1.2 HZ * R5 8 98 1.33E9 C2 8 98 100E-12 G1 98 8 5 6 376E-6 V2 99 9 3.0 V3 10 50 3.0 D1 8 9 DX D2 10 8 DX * * COMMON-MODE GAIN NETWORK WITH ZERO AT 3500 HZ * R6 11 12 1E6 C3 11 12 45.0E-12 R7 12 98 1 E2 11 98 3 14 31.6 * * POLE AT 2 MHZ * R8 13 98 1E6 C4 13 98 79.6E-15 G2 98 13 8 14 1E-6 * * OUTPUT STAGE * R9 14 99 400E3 R10 14 50 400E3 ISY 99 50 1062.5E-6 R11 15 99 200 R12 15 50 200 L3 15 20 2.5E-8 G3 18 50 13 15 5E-3 G4 19 50 15 13 5E-3 G5 15 99 99 13 5E-3 G6 50 15 13 50 5E-3 V4 16 15 0.5 V5 15 17 0.5 D3 13 16 DX D4 17 13 DX D5 99 18 DX D6 99 19 DX D7 50 18 DY D8 50 19 DY * * MODELS USED * .MODEL JX PJF(BETA=706E-6 VTO=-2.000 IS=5E-12) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP41G SPICE Macro-model 12/90, Rev. A * * This version of the OP-41 model simulates the worst case * parameters of the 'G' grade. The worst case parameters * used correspond to those in the data book. * * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP41G 1 2 99 50 20 * * INPUT STAGE * R1 1 3 5E12 R2 2 3 5E12 R3 5 50 2.66K R4 6 50 2.66K CIN 1 2 5E-12 I1 99 4 1E-4 IOS 1 2 2.5E-12 EOS 7 1 POLY(1) 12 14 2.0E-3 1 J1 5 2 4 JX J2 6 7 4 JX GB1 2 50 POLY(3) 4,2 5,2 50,2 0 1E-12 1E-12 1E-12 GB2 7 50 POLY(3) 4,7 6,7 50,7 0 1E-12 1E-12 1E-12 * EREF 98 0 14 0 1 * * GAIN STAGE & DOMINANT POLE AT 1.2 HZ * R5 8 98 1.33E9 C2 8 98 100E-12 G1 98 8 5 6 376E-6 V2 99 9 3.0 V3 10 50 3.0 D1 8 9 DX D2 10 8 DX * * COMMON-MODE GAIN NETWORK WITH ZERO AT 3500 HZ * R6 11 12 1E6 C3 11 12 45.0E-12 R7 12 98 1 E2 11 98 3 14 31.6 * * POLE AT 2 MHZ * R8 13 98 1E6 C4 13 98 79.6E-15 G2 98 13 8 14 1E-6 * * OUTPUT STAGE * R9 14 99 400E3 R10 14 50 400E3 ISY 99 50 1062.5E-6 R11 15 99 200 R12 15 50 200 L3 15 20 2.5E-8 G3 18 50 13 15 5E-3 G4 19 50 15 13 5E-3 G5 15 99 99 13 5E-3 G6 50 15 13 50 5E-3 V4 16 15 -0.1 V5 15 17 -0.1 D3 13 16 DX D4 17 13 DX D5 99 18 DX D6 99 19 DX D7 50 18 DY D8 50 19 DY * * MODELS USED * .MODEL JX PJF(BETA=706E-6 VTO=-2.000 IS=10E-12) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP420B SPICE Macro-model 9/91, Rev. A * JCB / PMI * * This version of the OP-420 model simulates the worst case * parameters of the 'B' grade. The worst case parameters * used correspond to those in the data sheet. * * * Copyright 1991 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP420B 1 2 99 50 30 * * INPUT STAGE & POLE AT 1.5 MEGHZ * R1 2 3 5E11 R2 1 3 5E11 R3 5 50 5.16K R4 6 50 5.16K CIN 1 2 4E-12 C2 5 6 15.42E-12 I1 99 4 10UA IOS 1 2 0.75E-9 EOS 9 1 POLY(1) 24 27 2.5E-3 1 Q1 5 2 4 QX Q2 6 9 4 QX * EREF 98 0 27 0 1 * * FIRST GAIN STAGE * R5 10 98 1E6 G1 98 10 5 6 41.47E-6 D1 10 11 DX D2 12 10 DX E1 99 11 POLY(1) 99 27 -1.475 1 E2 12 50 POLY(1) 27 50 -1.475 1 * * GAIN STAGE & DOMINANT POLE AT 0.275 HZ * R6 13 98 2.894E9 C3 13 98 200E-12 G2 98 13 10 27 5E-6 V1 99 14 1.04 V2 15 50 1.04 D3 13 14 DX D4 15 13 DX * * COMMON-MODE GAIN NETWORK WITH ZERO AT 1.42K HZ * R7 24 98 1 R8 23 24 1E6 C4 23 24 112.4E-12 E4 98 23 3 27 70.79 * * POLE AT 600 KHZ * R9 25 98 1E6 C5 25 98 265E-15 G3 98 25 13 27 1E-6 * * OUTPUT STAGE * ISY 99 50 23E-6 R10 27 99 263E3 R11 27 50 263E3 R12 30 99 2000 R13 30 50 2000 G4 28 50 25 30 0.5E-3 G5 29 50 30 25 0.5E-3 G6 30 99 99 25 0.5E-3 G7 50 30 25 50 0.5E-3 D5 99 28 DX D6 99 29 DX D7 50 28 DY D8 50 29 DY D9 25 31 DX V3 31 30 5.3 D10 32 25 DX V4 30 32 0.9 * * MODELS USED * .MODEL QX PNP(BF=250) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP420C SPICE Macro-model 9/91, Rev. A * JCB / PMI * * This version of the OP-420 model simulates the worst case * parameters of the 'C' grade. The worst case parameters * used correspond to those in the data sheet. * * * Copyright 1991 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP420C 1 2 99 50 30 * * INPUT STAGE & POLE AT 1.5 MEGHZ * R1 2 3 5E11 R2 1 3 5E11 R3 5 50 5.16K R4 6 50 5.16K CIN 1 2 4E-12 C2 5 6 15.42E-12 I1 99 4 10UA IOS 1 2 1.25E-9 EOS 9 1 POLY(1) 24 27 4E-3 1 Q1 5 2 4 QX Q2 6 9 4 QX * EREF 98 0 27 0 1 * * FIRST GAIN STAGE * R5 10 98 1E6 G1 98 10 5 6 41.47E-6 D1 10 11 DX D2 12 10 DX E1 99 11 POLY(1) 99 27 -1.475 1 E2 12 50 POLY(1) 27 50 -1.475 1 * * GAIN STAGE & DOMINANT POLE AT 0.413 HZ * R6 13 98 1.929E9 C3 13 98 200E-12 G2 98 13 10 27 5E-6 V1 99 14 1.04 V2 15 50 1.04 D3 13 14 DX D4 15 13 DX * * COMMON-MODE GAIN NETWORK WITH ZERO AT 2K HZ * R7 24 98 1 R8 23 24 1E6 C4 23 24 79.6E-12 E4 98 23 3 27 100 * * POLE AT 600 KHZ * R9 25 98 1E6 C5 25 98 265E-15 G3 98 25 13 27 1E-6 * * OUTPUT STAGE * ISY 99 50 48E-6 R10 27 99 263E3 R11 27 50 263E3 R12 30 99 2000 R13 30 50 2000 G4 28 50 25 30 0.5E-3 G5 29 50 30 25 0.5E-3 G6 30 99 99 25 0.5E-3 G7 50 30 25 50 0.5E-3 D5 99 28 DX D6 99 29 DX D7 50 28 DY D8 50 29 DY D9 25 31 DX V3 31 30 5.3 D10 32 25 DX V4 30 32 0.9 * * MODELS USED * .MODEL QX PNP(BF=166.667) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP420F SPICE Macro-model 9/91, Rev. A * JCB / PMI * * This version of the OP-420 model simulates the worst case * parameters of the 'F' grade. The worst case parameters * used correspond to those in the data sheet. * * * Copyright 1991 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP420F 1 2 99 50 30 * * INPUT STAGE & POLE AT 1.5 MEGHZ * R1 2 3 5E11 R2 1 3 5E11 R3 5 50 5.16K R4 6 50 5.16K CIN 1 2 4E-12 C2 5 6 15.42E-12 I1 99 4 10UA IOS 1 2 0.75E-9 EOS 9 1 POLY(1) 24 27 2.5E-3 1 Q1 5 2 4 QX Q2 6 9 4 QX * EREF 98 0 27 0 1 * * FIRST GAIN STAGE * R5 10 98 1E6 G1 98 10 5 6 41.47E-6 D1 10 11 DX D2 12 10 DX E1 99 11 POLY(1) 99 27 -1.475 1 E2 12 50 POLY(1) 27 50 -1.475 1 * * GAIN STAGE & DOMINANT POLE AT 0.275 HZ * R6 13 98 2.894E9 C3 13 98 200E-12 G2 98 13 10 27 5E-6 V1 99 14 1.04 V2 15 50 1.04 D3 13 14 DX D4 15 13 DX * * COMMON-MODE GAIN NETWORK WITH ZERO AT 1.42K HZ * R7 24 98 1 R8 23 24 1E6 C4 23 24 112.4E-12 E4 98 23 3 27 70.79 * * POLE AT 600 KHZ * R9 25 98 1E6 C5 25 98 265E-15 G3 98 25 13 27 1E-6 * * OUTPUT STAGE * ISY 99 50 23E-6 R10 27 99 263E3 R11 27 50 263E3 R12 30 99 2000 R13 30 50 2000 G4 28 50 25 30 0.5E-3 G5 29 50 30 25 0.5E-3 G6 30 99 99 25 0.5E-3 G7 50 30 25 50 0.5E-3 D5 99 28 DX D6 99 29 DX D7 50 28 DY D8 50 29 DY D9 25 31 DX V3 31 30 5.3 D10 32 25 DX V4 30 32 0.9 * * MODELS USED * .MODEL QX PNP(BF=250) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP420G SPICE Macro-model 9/91, Rev. A * JCB / PMI * * This version of the OP-420 model simulates the worst case * parameters of the 'G' grade. The worst case parameters * used correspond to those in the data sheet. * * * Copyright 1991 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP420G 1 2 99 50 30 * * INPUT STAGE & POLE AT 1.5 MEGHZ * R1 2 3 5E11 R2 1 3 5E11 R3 5 50 5.16K R4 6 50 5.16K CIN 1 2 4E-12 C2 5 6 15.42E-12 I1 99 4 10UA IOS 1 2 1.25E-9 EOS 9 1 POLY(1) 24 27 4E-3 1 Q1 5 2 4 QX Q2 6 9 4 QX * EREF 98 0 27 0 1 * * FIRST GAIN STAGE * R5 10 98 1E6 G1 98 10 5 6 41.47E-6 D1 10 11 DX D2 12 10 DX E1 99 11 POLY(1) 99 27 -1.475 1 E2 12 50 POLY(1) 27 50 -1.475 1 * * GAIN STAGE & DOMINANT POLE AT 0.413 HZ * R6 13 98 1.929E9 C3 13 98 200E-12 G2 98 13 10 27 5E-6 V1 99 14 1.04 V2 15 50 1.04 D3 13 14 DX D4 15 13 DX * * COMMON-MODE GAIN NETWORK WITH ZERO AT 2K HZ * R7 24 98 1 R8 23 24 1E6 C4 23 24 79.6E-12 E4 98 23 3 27 100 * * POLE AT 600 KHZ * R9 25 98 1E6 C5 25 98 265E-15 G3 98 25 13 27 1E-6 * * OUTPUT STAGE * ISY 99 50 48E-6 R10 27 99 263E3 R11 27 50 263E3 R12 30 99 2000 R13 30 50 2000 G4 28 50 25 30 0.5E-3 G5 29 50 30 25 0.5E-3 G6 30 99 99 25 0.5E-3 G7 50 30 25 50 0.5E-3 D5 99 28 DX D6 99 29 DX D7 50 28 DY D8 50 29 DY D9 25 31 DX V3 31 30 5.3 D10 32 25 DX V4 30 32 0.9 * * MODELS USED * .MODEL QX PNP(BF=166.667) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP420H SPICE Macro-model 9/91, Rev. A * JCB / PMI * * This version of the OP-420 model simulates the worst case * parameters of the 'H' grade. The worst case parameters * used correspond to those in the data sheet. * * * Copyright 1991 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP420H 1 2 99 50 30 * * INPUT STAGE & POLE AT 1.5 MEGHZ * R1 2 3 5E11 R2 1 3 5E11 R3 5 50 5.16K R4 6 50 5.16K CIN 1 2 4E-12 C2 5 6 15.42E-12 I1 99 4 10UA IOS 1 2 3E-9 EOS 9 1 POLY(1) 24 27 6E-3 1 Q1 5 2 4 QX Q2 6 9 4 QX * EREF 98 0 27 0 1 * * FIRST GAIN STAGE * R5 10 98 1E6 G1 98 10 5 6 41.47E-6 D1 10 11 DX D2 12 10 DX E1 99 11 POLY(1) 99 27 -1.475 1 E2 12 50 POLY(1) 27 50 -1.475 1 * * GAIN STAGE & DOMINANT POLE AT 0.825 HZ * R6 13 98 964.57E6 C3 13 98 200E-12 G2 98 13 10 27 5E-6 V1 99 14 1.24 V2 15 50 1.24 D3 13 14 DX D4 15 13 DX * * COMMON-MODE GAIN NETWORK WITH ZERO AT 3.17K HZ * R7 24 98 1 R8 23 24 1E6 C4 23 24 50.21E-12 E4 98 23 3 27 158.5 * * POLE AT 600 KHZ * R9 25 98 1E6 C5 25 98 265E-15 G3 98 25 13 27 1E-6 * * OUTPUT STAGE * ISY 99 50 83E-6 R10 27 99 263E3 R11 27 50 263E3 R12 30 99 2000 R13 30 50 2000 G4 28 50 25 30 0.5E-3 G5 29 50 30 25 0.5E-3 G6 30 99 99 25 0.5E-3 G7 50 30 25 50 0.5E-3 D5 99 28 DX D6 99 29 DX D7 50 28 DY D8 50 29 DY D9 25 31 DX V3 31 30 5.3 D10 32 25 DX V4 30 32 0.9 * * MODELS USED * .MODEL QX PNP(BF=125) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP421B SPICE Macro-model 5/91, Rev. A * JCB / PMI * * * Copyright 1991 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP421B 1 2 99 50 31 * * INPUT STAGE & POLE AT 2.8 MEGHZ * R1 2 3 5E11 R2 1 3 5E11 R3 5 50 5.16K R4 6 50 5.16K CIN 1 2 2E-12 C2 5 6 5.51E-12 I1 99 4 10UA IOS 1 2 5.0E-9 EOS 9 1 POLY(1) 24 27 2500E-6 1 Q1 5 2 4 QX Q2 6 9 4 QX * EREF 98 0 27 0 1 * * FIRST GAIN STAGE * R5 10 98 1E6 G1 98 10 5 6 23.1E-6 D1 10 11 DX D2 12 10 DX E1 99 11 POLY(1) 99 27 -0.4 1 E2 12 50 POLY(1) 27 50 -0.4 1 * * GAIN STAGE & DOMINANT POLE AT 2.3 HZ * R6 13 98 1.73E9 C3 13 98 20E-12 G2 98 13 10 27 5E-6 V1 99 14 1.6 V2 15 50 1.3 D3 13 14 DX D4 15 13 DX * * POLE AT 3.0 MEGHZ * R9 16 98 1E6 C5 16 98 53.1E-15 G3 98 16 13 27 1E-6 * * POLE AT 3.0 MEGHZ * R15 17 98 1E6 C7 17 98 53.1E-15 G10 98 17 16 27 1E-6 ** * COMMON-MODE GAIN NETWORK WITH ZERO AT 21.2 KHZ * R7 24 98 1 R8 23 24 1E6 C4 23 24 7.5E-12 E4 98 23 3 27 70.8 * * POLE AT 3.0 MEGHZ * R14 25 98 1E6 C6 25 98 53.1E-15 G9 98 25 17 27 1E-6 * * OUTPUT STAGE * ISY 99 50 540E-6 R10 27 99 33.3E3 R11 27 50 33.3E3 R12 30 99 450 R13 30 50 450 L1 30 31 1E-8 G4 28 50 25 30 2.22E-3 G5 29 50 30 25 2.22E-3 G6 30 99 99 25 2.22E-3 G7 50 30 25 50 2.22E-3 D5 99 28 DX D6 99 29 DX D7 50 28 DY D8 50 29 DY D9 25 33 DX V3 33 30 1.7 D10 32 25 DX V4 30 32 1.7 * * MODELS USED * .MODEL QX PNP(BF=100) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP421C SPICE Macro-model 5/91, Rev. A * JCB / PMI * * * Copyright 1991 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP421C 1 2 99 50 31 * * INPUT STAGE & POLE AT 2.8 MEGHZ * R1 2 3 5E11 R2 1 3 5E11 R3 5 50 5.16K R4 6 50 5.16K CIN 1 2 2E-12 C2 5 6 5.51E-12 I1 99 4 10UA IOS 1 2 10E-9 EOS 9 1 POLY(1) 24 27 4000E-6 1 Q1 5 2 4 QX Q2 6 9 4 QX * EREF 98 0 27 0 1 * * FIRST GAIN STAGE * R5 10 98 1E6 G1 98 10 5 6 23.1E-6 D1 10 11 DX D2 12 10 DX E1 99 11 POLY(1) 99 27 -0.4 1 E2 12 50 POLY(1) 27 50 -0.4 1 * * GAIN STAGE & DOMINANT POLE AT 9.2 HZ * R6 13 98 0.865E9 C3 13 98 20E-12 G2 98 13 10 27 5E-6 V1 99 14 1.7 V2 15 50 1.4 D3 13 14 DX D4 15 13 DX * * POLE AT 3.0 MEGHZ * R9 16 98 1E6 C5 16 98 53.1E-15 G3 98 16 13 27 1E-6 * * POLE AT 3.0 MEGHZ * R15 17 98 1E6 C7 17 98 53.1E-15 G10 98 17 16 27 1E-6 ** * COMMON-MODE GAIN NETWORK WITH ZERO AT 30 KHZ * R7 24 98 1 R8 23 24 1E6 C4 23 24 5.3E-12 E4 98 23 3 27 100 * * POLE AT 3.0 MEGHZ * R14 25 98 1E6 C6 25 98 53.1E-15 G9 98 25 17 27 1E-6 * * OUTPUT STAGE * ISY 99 50 1040E-6 R10 27 99 33.3E3 R11 27 50 33.3E3 R12 30 99 450 R13 30 50 450 L1 30 31 1E-8 G4 28 50 25 30 2.22E-3 G5 29 50 30 25 2.22E-3 G6 30 99 99 25 2.22E-3 G7 50 30 25 50 2.22E-3 D5 99 28 DX D6 99 29 DX D7 50 28 DY D8 50 29 DY D9 25 33 DX V3 33 30 1.7 D10 32 25 DX V4 30 32 1.7 * * MODELS USED * .MODEL QX PNP(BF=62.5) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP421F SPICE Macro-model 5/91, Rev. A * JCB / PMI * * * Copyright 1991 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP421F 1 2 99 50 31 * * INPUT STAGE & POLE AT 2.8 MEGHZ * R1 2 3 5E11 R2 1 3 5E11 R3 5 50 5.16K R4 6 50 5.16K CIN 1 2 2E-12 C2 5 6 5.51E-12 I1 99 4 10UA IOS 1 2 5.0E-9 EOS 9 1 POLY(1) 24 27 2500E-6 1 Q1 5 2 4 QX Q2 6 9 4 QX * EREF 98 0 27 0 1 * * FIRST GAIN STAGE * R5 10 98 1E6 G1 98 10 5 6 23.1E-6 D1 10 11 DX D2 12 10 DX E1 99 11 POLY(1) 99 27 -0.4 1 E2 12 50 POLY(1) 27 50 -0.4 1 * * GAIN STAGE & DOMINANT POLE AT 2.3 HZ * R6 13 98 1.73E9 C3 13 98 20E-12 G2 98 13 10 27 5E-6 V1 99 14 1.6 V2 15 50 1.3 D3 13 14 DX D4 15 13 DX * * POLE AT 3.0 MEGHZ * R9 16 98 1E6 C5 16 98 53.1E-15 G3 98 16 13 27 1E-6 * * POLE AT 3.0 MEGHZ * R15 17 98 1E6 C7 17 98 53.1E-15 G10 98 17 16 27 1E-6 ** * COMMON-MODE GAIN NETWORK WITH ZERO AT 21.2 KHZ * R7 24 98 1 R8 23 24 1E6 C4 23 24 7.5E-12 E4 98 23 3 27 70.8 * * POLE AT 3.0 MEGHZ * R14 25 98 1E6 C6 25 98 53.1E-15 G9 98 25 17 27 1E-6 * * OUTPUT STAGE * ISY 99 50 540E-6 R10 27 99 33.3E3 R11 27 50 33.3E3 R12 30 99 450 R13 30 50 450 L1 30 31 1E-8 G4 28 50 25 30 2.22E-3 G5 29 50 30 25 2.22E-3 G6 30 99 99 25 2.22E-3 G7 50 30 25 50 2.22E-3 D5 99 28 DX D6 99 29 DX D7 50 28 DY D8 50 29 DY D9 25 33 DX V3 33 30 1.7 D10 32 25 DX V4 30 32 1.7 * * MODELS USED * .MODEL QX PNP(BF=100) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP421G SPICE Macro-model 5/91, Rev. A * JCB / PMI * * * Copyright 1991 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP421G 1 2 99 50 31 * * INPUT STAGE & POLE AT 2.8 MEGHZ * R1 2 3 5E11 R2 1 3 5E11 R3 5 50 5.16K R4 6 50 5.16K CIN 1 2 2E-12 C2 5 6 5.51E-12 I1 99 4 10UA IOS 1 2 10E-9 EOS 9 1 POLY(1) 24 27 4000E-6 1 Q1 5 2 4 QX Q2 6 9 4 QX * EREF 98 0 27 0 1 * * FIRST GAIN STAGE * R5 10 98 1E6 G1 98 10 5 6 23.1E-6 D1 10 11 DX D2 12 10 DX E1 99 11 POLY(1) 99 27 -0.4 1 E2 12 50 POLY(1) 27 50 -0.4 1 * * GAIN STAGE & DOMINANT POLE AT 9.2 HZ * R6 13 98 0.865E9 C3 13 98 20E-12 G2 98 13 10 27 5E-6 V1 99 14 1.7 V2 15 50 1.4 D3 13 14 DX D4 15 13 DX * * POLE AT 3.0 MEGHZ * R9 16 98 1E6 C5 16 98 53.1E-15 G3 98 16 13 27 1E-6 * * POLE AT 3.0 MEGHZ * R15 17 98 1E6 C7 17 98 53.1E-15 G10 98 17 16 27 1E-6 ** * COMMON-MODE GAIN NETWORK WITH ZERO AT 30 KHZ * R7 24 98 1 R8 23 24 1E6 C4 23 24 5.3E-12 E4 98 23 3 27 100 * * POLE AT 3.0 MEGHZ * R14 25 98 1E6 C6 25 98 53.1E-15 G9 98 25 17 27 1E-6 * * OUTPUT STAGE * ISY 99 50 1040E-6 R10 27 99 33.3E3 R11 27 50 33.3E3 R12 30 99 450 R13 30 50 450 L1 30 31 1E-8 G4 28 50 25 30 2.22E-3 G5 29 50 30 25 2.22E-3 G6 30 99 99 25 2.22E-3 G7 50 30 25 50 2.22E-3 D5 99 28 DX D6 99 29 DX D7 50 28 DY D8 50 29 DY D9 25 33 DX V3 33 30 1.7 D10 32 25 DX V4 30 32 1.7 * * MODELS USED * .MODEL QX PNP(BF=62.5) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP421H SPICE Macro-model 5/91, Rev. A * JCB / PMI * * * Copyright 1991 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP421H 1 2 99 50 31 * * INPUT STAGE & POLE AT 2.8 MEGHZ * R1 2 3 5E11 R2 1 3 5E11 R3 5 50 5.16K R4 6 50 5.16K CIN 1 2 2E-12 C2 5 6 5.51E-12 I1 99 4 10UA IOS 1 2 20E-9 EOS 9 1 POLY(1) 24 27 6000E-6 1 Q1 5 2 4 QX Q2 6 9 4 QX * EREF 98 0 27 0 1 * * FIRST GAIN STAGE * R5 10 98 1E6 G1 98 10 5 6 23.1E-6 D1 10 11 DX D2 12 10 DX E1 99 11 POLY(1) 99 27 -0.4 1 E2 12 50 POLY(1) 27 50 -0.4 1 * * GAIN STAGE & DOMINANT POLE AT 9.2 HZ * R6 13 98 0.865E9 C3 13 98 20E-12 G2 98 13 10 27 5E-6 V1 99 14 1.8 V2 15 50 1.5 D3 13 14 DX D4 15 13 DX * * POLE AT 3.0 MEGHZ * R9 16 98 1E6 C5 16 98 53.1E-15 G3 98 16 13 27 1E-6 * * POLE AT 3.0 MEGHZ * R15 17 98 1E6 C7 17 98 53.1E-15 G10 98 17 16 27 1E-6 ** * COMMON-MODE GAIN NETWORK WITH ZERO AT 47.5 KHZ * R7 24 98 1 R8 23 24 1E6 C4 23 24 3.35E-12 E4 98 23 3 27 158 * * POLE AT 3.0 MEGHZ * R14 25 98 1E6 C6 25 98 53.1E-15 G9 98 25 17 27 1E-6 * * OUTPUT STAGE * ISY 99 50 1540E-6 R10 27 99 33.3E3 R11 27 50 33.3E3 R12 30 99 450 R13 30 50 450 L1 30 31 1E-8 G4 28 50 25 30 2.22E-3 G5 29 50 30 25 2.22E-3 G6 30 99 99 25 2.22E-3 G7 50 30 25 50 2.22E-3 D5 99 28 DX D6 99 29 DX D7 50 28 DY D8 50 29 DY D9 25 33 DX V3 33 30 1.7 D10 32 25 DX V4 30 32 1.7 * * MODELS USED * .MODEL QX PNP(BF=33.3) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP42A SPICE Macro-model 12/90, Rev. B * JCB / PMI * * Revision History: * REV. B * Re-ordered subcircuit call out nodes to put the * output node last. * Changed Ios from 4E-11 to 2E-11 * * * This version of the OP-42 model simulates the worst case * parameters of the 'A' grade. The worst case parameters * used correspond to those in the data book. * * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP42A 1 2 99 50 32 * * INPUT STAGE & POLE AT 15.9 MHZ * R1 1 3 5E11 R2 2 3 5E11 R3 5 50 636.63 R4 6 50 636.63 CIN 1 2 5E-12 C2 5 6 7.9E-12 I1 99 4 1E-3 IOS 1 2 2E-11 EOS 7 1 POLY(1) 20 26 1E-3 1 J1 5 2 4 JX J2 6 7 4 JX * * SECOND STAGE & POLE AT 45 HZ * R5 9 99 63.663E6 R6 9 50 63.663E6 C3 9 99 22.222E-12 C4 9 50 22.222E-12 G1 99 9 POLY(1) 5 6 4.76E-3 1.571E-3 G2 9 50 POLY(1) 6 5 4.76E-3 1.571E-3 V2 99 8 3.582 V3 10 50 3.582 D1 9 8 DX D2 10 9 DX * * POLE-ZERO PAIR AT 1.80 MHZ / 2.20 MHZ * R7 11 99 1E6 R8 11 50 1E6 R9 11 12 4.5E6 R10 11 13 4.5E6 C5 12 99 16.1E-15 C6 13 50 16.1E-15 G3 99 11 9 26 1E-6 G4 11 50 26 9 1E-6 * * POLE-ZERO PAIR AT 1.80 MHZ / 2.20 MHZ * R11 14 99 1E6 R12 14 50 1E6 R13 14 15 4.5E6 R14 14 16 4.5E6 C7 15 99 16.1E-15 C8 16 50 16.1E-15 G5 99 14 11 26 1E-6 G6 14 50 26 11 1E-6 * * POLE AT 53 MHZ * R15 17 99 1E6 R16 17 50 1E6 C9 17 99 3E-15 C10 17 50 3E-15 G7 99 17 14 26 1E-6 G8 17 50 26 14 1E-6 * * POLE AT 53 MHZ * R17 18 99 1E6 R18 18 50 1E6 C11 18 99 3E-15 C12 18 50 3E-15 G9 99 18 17 26 1E-6 G10 18 50 26 17 1E-6 * * POLE AT 53 MHZ * R19 19 99 1E6 R20 19 50 1E6 C13 19 99 3E-15 C14 19 50 3E-15 G11 99 19 18 26 1E-6 G12 19 50 26 18 1E-6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 317 KHZ * R21 20 21 1E6 R22 20 23 1E6 L1 21 99 0.5017 L2 23 50 0.5017 G13 99 20 3 26 5.012E-11 G14 20 50 26 3 5.012E-11 * * POLE AT 79.6 MHZ * R24 25 99 1E6 R25 25 50 1E6 C15 25 99 2E-15 C16 25 50 2E-15 G15 99 25 19 26 1E-6 G16 25 50 26 19 1E-6 * * OUTPUT STAGE * R26 26 99 111.1E3 R27 26 50 111.1E3 R28 27 99 90 R29 27 50 90 L3 27 32 2.5E-7 G17 30 50 25 27 11.1111E-3 G18 31 50 27 25 11.1111E-3 G19 27 99 99 25 11.1111E-3 G20 50 27 25 50 11.1111E-3 V6 28 27 0.2 V7 27 29 0.2 D5 25 28 DX D6 29 25 DX D7 99 30 DX D8 99 31 DX D9 50 30 DY D10 50 31 DY * * MODELS USED * .MODEL JX PJF(BETA=1.245E-3 VTO=-2.000 IS=2E-10) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP42E SPICE Macro-model 12/90, Rev. B * JCB / PMI * * Revision History: * REV. B * Re-ordered subcircuit call out nodes to put the * output node last. * Changed Ios from 4E-11 to 2E-11 * * * This version of the OP-42 model simulates the worst case * parameters of the 'E' grade. The worst case parameters * used correspond to those in the data book. * * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP42E 1 2 99 50 32 * * INPUT STAGE & POLE AT 15.9 MHZ * R1 1 3 5E11 R2 2 3 5E11 R3 5 50 707.21 R4 6 50 707.21 CIN 1 2 5E-12 C2 5 6 7.077E-12 I1 99 4 1E-3 IOS 1 2 2E-11 EOS 7 1 POLY(1) 20 26 750E-6 1 J1 5 2 4 JX J2 6 7 4 JX * * SECOND STAGE & POLE AT 45 HZ * R5 9 99 70.736E6 R6 9 50 70.736E6 C3 9 99 20E-12 C4 9 50 20E-12 G1 99 9 POLY(1) 5 6 4.76E-3 1.414E-3 G2 9 50 POLY(1) 6 5 4.76E-3 1.414E-3 V2 99 8 3.582 V3 10 50 3.582 D1 9 8 DX D2 10 9 DX * * POLE-ZERO PAIR AT 1.80 MHZ / 2.20 MHZ * R7 11 99 1E6 R8 11 50 1E6 R9 11 12 4.5E6 R10 11 13 4.5E6 C5 12 99 16.1E-15 C6 13 50 16.1E-15 G3 99 11 9 26 1E-6 G4 11 50 26 9 1E-6 * * POLE-ZERO PAIR AT 1.80 MHZ / 2.20 MHZ * R11 14 99 1E6 R12 14 50 1E6 R13 14 15 4.5E6 R14 14 16 4.5E6 C7 15 99 16.1E-15 C8 16 50 16.1E-15 G5 99 14 11 26 1E-6 G6 14 50 26 11 1E-6 * * POLE AT 53 MHZ * R15 17 99 1E6 R16 17 50 1E6 C9 17 99 3E-15 C10 17 50 3E-15 G7 99 17 14 26 1E-6 G8 17 50 26 14 1E-6 * * POLE AT 53 MHZ * R17 18 99 1E6 R18 18 50 1E6 C11 18 99 3E-15 C12 18 50 3E-15 G9 99 18 17 26 1E-6 G10 18 50 26 17 1E-6 * * POLE AT 53 MHZ * R19 19 99 1E6 R20 19 50 1E6 C13 19 99 3E-15 C14 19 50 3E-15 G11 99 19 18 26 1E-6 G12 19 50 26 18 1E-6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 252 KHZ * R21 20 21 1E6 R22 20 23 1E6 L1 21 99 0.6316 L2 23 50 0.6316 G13 99 20 3 26 3.981E-11 G14 20 50 26 3 3.981E-11 * * POLE AT 79.6 MHZ * R24 25 99 1E6 R25 25 50 1E6 C15 25 99 2E-15 C16 25 50 2E-15 G15 99 25 19 26 1E-6 G16 25 50 26 19 1E-6 * * OUTPUT STAGE * R26 26 99 111.1E3 R27 26 50 111.1E3 R28 27 99 90 R29 27 50 90 L3 27 32 2.5E-7 G17 30 50 25 27 11.1111E-3 G18 31 50 27 25 11.1111E-3 G19 27 99 99 25 11.1111E-3 G20 50 27 25 50 11.1111E-3 V6 28 27 0.2 V7 27 29 0.2 D5 25 28 DX D6 29 25 DX D7 99 30 DX D8 99 31 DX D9 50 30 DY D10 50 31 DY * * MODELS USED * .MODEL JX PJF(BETA=999.7E-6 VTO=-2.000 IS=2E-10) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP42F SPICE Macro-model 12/90, Rev. B * JCB / PMI * * Revision History: * REV. B * Re-ordered subcircuit call out nodes to put the * output node last. * Changed Ios from 5E-11 to 2.5E-11 * * * This version of the OP-42 model simulates the worst case * parameters of the 'F' grade. The worst case parameters * used correspond to those in the data book. * * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP42F 1 2 99 50 32 * * INPUT STAGE & POLE AT 15.9 MHZ * R1 1 3 5E11 R2 2 3 5E11 R3 5 50 565.93 R4 6 50 565.93 CIN 1 2 5E-12 C2 5 6 8.444E-12 I1 99 4 1E-3 IOS 1 2 2.5E-11 EOS 7 1 POLY(1) 20 26 1.5E-3 1 J1 5 2 4 JX J2 6 7 4 JX * * SECOND STAGE & POLE AT 45 HZ * R5 9 99 56.588E6 R6 9 50 56.588E6 C3 9 99 25E-12 C4 9 50 25E-12 G1 99 9 POLY(1) 5 6 5.26E-3 1.767E-3 G2 9 50 POLY(1) 6 5 5.26E-3 1.767E-3 V2 99 8 3.582 V3 10 50 3.582 D1 9 8 DX D2 10 9 DX * * POLE-ZERO PAIR AT 1.80 MHZ / 2.20 MHZ * R7 11 99 1E6 R8 11 50 1E6 R9 11 12 4.5E6 R10 11 13 4.5E6 C5 12 99 16.1E-15 C6 13 50 16.1E-15 G3 99 11 9 26 1E-6 G4 11 50 26 9 1E-6 * * POLE-ZERO PAIR AT 1.80 MHZ / 2.20 MHZ * R11 14 99 1E6 R12 14 50 1E6 R13 14 15 4.5E6 R14 14 16 4.5E6 C7 15 99 16.1E-15 C8 16 50 16.1E-15 G5 99 14 11 26 1E-6 G6 14 50 26 11 1E-6 * * POLE AT 53 MHZ * R15 17 99 1E6 R16 17 50 1E6 C9 17 99 3E-15 C10 17 50 3E-15 G7 99 17 14 26 1E-6 G8 17 50 26 14 1E-6 * * POLE AT 53 MHZ * R17 18 99 1E6 R18 18 50 1E6 C11 18 99 3E-15 C12 18 50 3E-15 G9 99 18 17 26 1E-6 G10 18 50 26 17 1E-6 * * POLE AT 53 MHZ * R19 19 99 1E6 R20 19 50 1E6 C13 19 99 3E-15 C14 19 50 3E-15 G11 99 19 18 26 1E-6 G12 19 50 26 18 1E-6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 633 KHZ * R21 20 21 1E6 R22 20 23 1E6 L1 21 99 0.2515 L2 23 50 0.2515 G13 99 20 3 26 1.000E-10 G14 20 50 26 3 1.000E-10 * * POLE AT 79.6 MHZ * R24 25 99 1E6 R25 25 50 1E6 C15 25 99 2E-15 C16 25 50 2E-15 G15 99 25 19 26 1E-6 G16 25 50 26 19 1E-6 * * OUTPUT STAGE * R26 26 99 111.1E3 R27 26 50 111.1E3 R28 27 99 90 R29 27 50 90 L3 27 32 2.5E-7 G17 30 50 25 27 11.1111E-3 G18 31 50 27 25 11.1111E-3 G19 27 99 99 25 11.1111E-3 G20 50 27 25 50 11.1111E-3 V6 28 27 0.2 V7 27 29 0.2 D5 25 28 DX D6 29 25 DX D7 99 30 DX D8 99 31 DX D9 50 30 DY D10 50 31 DY * * MODELS USED * .MODEL JX PJF(BETA=1.561E-3 VTO=-2.000 IS=2.5E-10) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP42G SPICE Macro-model 12/90, Rev. B * JCB / PMI * * Revision History: * REV. B * Re-ordered subcircuit call out nodes to put the * output node last. * Changed Ios from 5E-11 to 2.5E-11 * * * This version of the OP-42 model simulates the worst case * parameters of the 'G' grade. The worst case parameters * used correspond to those in the data book. * * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP42G 1 2 99 50 32 * * INPUT STAGE & POLE AT 15.9 MHZ * R1 1 3 5E11 R2 2 3 5E11 R3 5 50 565.93 R4 6 50 565.93 CIN 1 2 5E-12 C2 5 6 8.444E-12 I1 99 4 1E-3 IOS 1 2 2.5E-11 EOS 7 1 POLY(1) 20 26 5E-3 1 J1 5 2 4 JX J2 6 7 4 JX * * SECOND STAGE & POLE AT 45 HZ * R5 9 99 56.588E6 R6 9 50 56.588E6 C3 9 99 25E-12 C4 9 50 25E-12 G1 99 9 POLY(1) 5 6 5.26E-3 1.767E-3 G2 9 50 POLY(1) 6 5 5.26E-3 1.767E-3 V2 99 8 3.582 V3 10 50 3.582 D1 9 8 DX D2 10 9 DX * * POLE-ZERO PAIR AT 1.80 MHZ / 2.20 MHZ * R7 11 99 1E6 R8 11 50 1E6 R9 11 12 4.5E6 R10 11 13 4.5E6 C5 12 99 16.1E-15 C6 13 50 16.1E-15 G3 99 11 9 26 1E-6 G4 11 50 26 9 1E-6 * * POLE-ZERO PAIR AT 1.80 MHZ / 2.20 MHZ * R11 14 99 1E6 R12 14 50 1E6 R13 14 15 4.5E6 R14 14 16 4.5E6 C7 15 99 16.1E-15 C8 16 50 16.1E-15 G5 99 14 11 26 1E-6 G6 14 50 26 11 1E-6 * * POLE AT 53 MHZ * R15 17 99 1E6 R16 17 50 1E6 C9 17 99 3E-15 C10 17 50 3E-15 G7 99 17 14 26 1E-6 G8 17 50 26 14 1E-6 * * POLE AT 53 MHZ * R17 18 99 1E6 R18 18 50 1E6 C11 18 99 3E-15 C12 18 50 3E-15 G9 99 18 17 26 1E-6 G10 18 50 26 17 1E-6 * * POLE AT 53 MHZ * R19 19 99 1E6 R20 19 50 1E6 C13 19 99 3E-15 C14 19 50 3E-15 G11 99 19 18 26 1E-6 G12 19 50 26 18 1E-6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 633 KHZ * R21 20 21 1E6 R22 20 23 1E6 L1 21 99 0.2515 L2 23 50 0.2515 G13 99 20 3 26 1.000E-10 G14 20 50 26 3 1.000E-10 * * POLE AT 79.6 MHZ * R24 25 99 1E6 R25 25 50 1E6 C15 25 99 2E-15 C16 25 50 2E-15 G15 99 25 19 26 1E-6 G16 25 50 26 19 1E-6 * * OUTPUT STAGE * R26 26 99 111.1E3 R27 26 50 111.1E3 R28 27 99 90 R29 27 50 90 L3 27 32 2.5E-7 G17 30 50 25 27 11.1111E-3 G18 31 50 27 25 11.1111E-3 G19 27 99 99 25 11.1111E-3 G20 50 27 25 50 11.1111E-3 V6 28 27 0.2 V7 27 29 0.2 D5 25 28 DX D6 29 25 DX D7 99 30 DX D8 99 31 DX D9 50 30 DY D10 50 31 DY * * MODELS USED * .MODEL JX PJF(BETA=1.561E-3 VTO=-2.000 IS=2.5E-10) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP44 SPICE Macro-model 12/90, Rev. B * ARG / PMI * * Revision History: * REV. B * Re-ordered subcircuit call out nodes to put the * output node last. * Changed Ios from 4E-12 to 2E-12 * * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP44 1 2 99 50 32 * * INPUT STAGE & POLE AT 60 MHZ * R1 1 3 5E11 R2 2 3 5E11 R3 5 50 541 R4 6 50 541 CIN 1 2 5E-12 C2 5 6 2.452E-12 I1 99 4 1.5E-3 IOS 1 2 2E-12 EOS 7 1 POLY(1) 22 26 300E-6 1 J1 5 2 4 JX J2 6 7 4 JX * * SECOND STAGE & POLE AT 79 HZ * R7 9 99 241.8E6 R8 9 50 241.8E6 C3 9 99 8.333E-12 C4 9 50 8.333E-12 G1 99 9 POLY(1) 5 6 4.825E-3 1.848E-3 G2 9 50 POLY(1) 6 5 4.825E-3 1.848E-3 V1 99 8 -10 V2 10 50 -10 D1 9 8 DX D2 10 9 DX * * POLE-ZERO PAIR AT 1.3 MHZ / 3.25 MHZ * R9 11 99 1E6 R10 11 50 1E6 R11 12 99 667E3 R12 13 50 667E3 C5 11 12 73.46E-15 C6 11 13 73.46E-15 G3 99 11 9 26 1E-6 G4 11 50 26 9 1E-6 V3 99 14 2.5 V4 15 50 3.1 D3 11 14 DX D4 15 11 DX * * POLE AT 100 MHZ * R13 16 99 1E6 R14 16 50 1E6 C7 16 99 1.592E-15 C8 16 50 1.592E-15 G5 99 16 11 26 1E-6 G6 16 50 26 11 1E-6 * * POLE AT 100 MHZ * R15 17 99 1E6 R16 17 50 1E6 C9 17 99 1.592E-15 C10 17 50 1.592E-15 G7 99 17 16 26 1E-6 G8 17 50 26 16 1E-6 * * POLE AT 100 MHZ * R17 18 99 1E6 R18 18 50 1E6 C13 18 99 1.592E-15 C14 18 50 1.592E-15 G9 99 18 17 26 1E-6 G10 18 50 26 17 1E-6 * * POLE AT 100 MHZ * R19 19 99 1E6 R20 19 50 1E6 C15 19 99 1.592E-15 C16 19 50 1.592E-15 G11 99 19 18 26 1E-6 G12 19 50 26 18 1E-6 * * POLE AT 200 MHZ * R21 20 99 1E6 R22 20 50 1E6 C17 20 99 .796E-15 C18 20 50 .796E-15 G13 99 20 19 26 1E-6 G14 20 50 26 19 1E-6 * * POLE AT 200 MHZ * R23 21 99 1E6 R24 21 50 1E6 C19 21 99 .796E-15 C20 21 50 .796E-15 G15 99 21 20 26 1E-6 G16 21 50 26 20 1E-6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 100 KHZ * R25 22 23 1E6 R26 22 24 1E6 L1 23 99 1.5915 L2 24 50 1.5915 D5 22 99 DX D6 50 22 DX G17 99 22 3 26 1.58E-11 G18 22 50 26 3 1.58E-11 * * POLE AT 200 MHZ * R27 25 99 1E6 R28 25 50 1E6 C21 25 99 .796E-15 C22 25 50 .796E-15 G19 99 25 21 26 1E-6 G20 25 50 26 21 1E-6 * * OUTPUT STAGE * R30 26 99 375.3E3 R31 26 50 375.3E3 R32 27 99 80 R33 27 50 80 L3 27 32 2.5E-7 G21 30 50 25 27 12.5E-3 G22 31 50 27 25 12.5E-3 G23 27 99 99 25 12.5E-3 G24 50 27 25 50 12.5E-3 V6 28 27 0.5 V7 27 29 0.3 D7 25 28 DX D8 29 25 DX D9 99 30 DX D10 99 31 DX D11 50 30 DY D12 50 31 DY * * MODELS USED * .MODEL JX PJF(BETA=1.139E-3 VTO=-1.5 IS=8E-11) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP462 SPICE Macro-model * 7/96, Ver. 1 * TAM / ADSC * * Copyright 1996 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance of the terms and provisions in the License * Statement. * * Node Assignments * noninverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | * | | | | | .SUBCKT OP462 1 2 99 50 45 * *INPUT STAGE * Q1 5 7 3 PIX 5 Q2 6 2 4 PIX 5 Ios 1 2 1.25E-9 I1 99 15 85E-6 EOS 7 1 POLY(1) (14,20) 45E-6 1 RC1 5 50 3.035E+3 RC2 6 50 3.035E+3 RE1 3 15 607 RE2 4 15 607 C1 5 6 600E-15 D1 3 8 DX D2 4 9 DX V1 99 8 DC 1 V2 99 9 DC 1 * * 1st GAIN STAGE * EREF 98 0 20 0 1 G1 98 10 5 6 10.5 R1 10 98 1 C2 10 98 3.3E-9 * * COMMON-MODE STAGE WITH ZERO AT 4kHz * ECM 13 98 POLY(2) (1,98) (2,98) 0 0.5 0.5 R2 13 14 1E+6 R3 14 98 70 C3 13 14 80E-12 * * POLE AT 1.5MHz, ZERO AT 3MHz * G2 21 98 10 98 .588E-6 R4 21 98 1.7E+6 R5 21 22 1.7E+6 C4 22 98 31.21E-15 * * POLE AT 6MHz, ZERO AT 3MHz * E1 23 98 21 98 2 R6 23 24 53E+3 R7 24 98 53E+3 C5 23 24 1E-12 * * SECOND GAIN STAGE * G3 25 98 24 98 40E-6 R8 25 98 1.65E+6 D3 25 99 DX D4 50 25 DX * * OUTPUT STAGE * GSY 99 50 POLY(1) (99,50) 277.5E-6 7.5E-6 R9 99 20 100E3 R10 20 50 100E3 Q3 45 41 99 POUT 4 Q4 45 43 50 NOUT 2 EB1 99 40 POLY(1) (98,25) 0.70366 1 EB2 42 50 POLY(1) (25,98) 0.73419 1 RB1 40 41 500 RB2 42 43 500 CF 45 25 11E-12 D5 46 99 DX D6 47 43 DX V3 46 41 0.7 V4 47 50 0.7 .MODEL PIX PNP (Bf=117.7) .MODEL POUT PNP (BF=119, IS=2.782E-17, VAF=28, KF=3E-7) .MODEL NOUT NPN (BF=110, IS=1.786E-17, VAF=90, KF=3E-7) .MODEL DX D() .ENDS OP462 * jg, 19/5/2000: corrected syntax model * OP467 SPICE Macro-model 5/92, Rev. A * ARG / PMI * * Copyright 1993 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of * this model indicates your acceptance of the terms and pro- * visions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP467 1 2 99 50 27 * * INPUT STAGE * I1 4 50 10E-3 CIN 1 2 1E-12 IOS 1 2 5E-9 Q1 5 2 8 QN Q2 6 7 9 QN R3 99 5 185.681 R4 99 6 185.681 R5 8 4 180.508 R6 9 4 180.508 EOS 7 1 POLY(1) (14,20) 0.2E-3 1 EREF 98 0 20 0 1 * * GAIN STAGE AND DOMINANT POLE AT 1.5KHZ * R7 10 0 3.714E6 C2 10 0 28.571E-12 G1 0 10 5 6 5.386E-3 V1 99 11 1.525 V2 12 50 1.525 D1 10 11 DX D2 12 10 DX RC 10 28 1.4E3 CC 28 27 12E-12 * * COMMON MODE STAGE WITH ZERO AT 1.26KHZ * ECM 13 98 POLY(2) (1,20) (2,20) 0 0.5 0.5 R8 13 14 1E6 R9 14 98 25.119 C3 13 14 126.721E-12 * * POLE AT 400E6 * R10 15 98 1E6 C4 15 98 0.398E-15 G2 98 15 10 20 1E-6 * * OUTPUT STAGE * ISY 99 50 -8.156E-3 RMP1 99 20 96.429E3 RMP2 20 50 96.429E3 RO1 99 26 200 RO2 26 50 200 L1 26 27 1E-7 GO1 26 99 99 15 5E-3 GO2 50 26 15 50 5E-3 G4 23 50 15 26 5E-3 G5 24 50 26 15 5E-3 D5 99 23 DX D6 99 24 DX D7 50 23 DY D8 50 24 DY * * MODELS USED * .MODEL QN NPN(BF=33.333E3) .MODEL DX D .MODEL DY D(BV=50) .ENDS * jg, 19/5/2000: corrected syntax model * OP467G SPICE Macro-model 5/92, Rev. A * ARG / PMI * * Copyright 1993 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of * this model indicates your acceptance of the terms and pro- * visions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP467G 1 2 99 50 27 * * INPUT STAGE * I1 4 50 10E-3 CIN 1 2 1E-12 IOS 1 2 50E-9 Q1 5 2 8 QN Q2 6 7 9 QN R3 99 5 66.472 R4 99 6 66.472 R5 8 4 61.3 R6 9 4 61.3 EOS 7 1 POLY(1) (14,20) 0.5E-3 4 EREF 98 0 20 0 1 * * GAIN STAGE AND DOMINANT POLE AT 2.12KHZ * R7 10 0 938.942E3 C2 10 0 80E-12 G1 0 10 5 6 15.044E-3 V1 99 11 2.025 V2 12 50 2.025 D1 10 11 DX D2 12 10 DX RC 10 28 1.4E3 CC 28 27 12E-12 * * COMMON MODE STAGE WITH ZERO AT 5.024KHZ * ECM 13 98 POLY(2) (1,20) (2,20) 0 0.5 0.5 R8 13 14 1E6 R9 14 98 25.119 C3 13 14 31.680E-12 * * POLE AT 400E6 * R10 15 98 1E6 C4 15 98 0.398E-15 G2 98 15 10 20 1E-6 * * OUTPUT STAGE * ISY 99 50 -7.656E-3 RMP1 99 20 96.429E3 RMP2 20 50 96.429E3 RO1 99 26 200 RO2 26 50 200 L1 26 27 1E-7 GO1 26 99 99 15 5E-3 GO2 50 26 15 50 5E-3 G4 23 50 15 26 5E-3 G5 24 50 26 15 5E-3 D5 99 23 DX D6 99 24 DX D7 50 23 DY D8 50 24 DY * * MODELS USED * .MODEL QN NPN(BF=8.333E3) .MODEL DX D .MODEL DY D(BV=50) .ENDS * jg, 19/5/2000: corrected syntax model * OP470 SPICE Macro-model 12/90, Rev. B * JCB / PMI * * Revision History: * REV. B * Re-ordered subcircuit call out nodes to put the * output node last. * Changed Ios from 3E-9 to 1.5E-9 * * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP470 1 2 99 50 35 * * INPUT STAGE & POLE AT 60 MHZ * R1 2 3 2E5 R2 1 3 2E5 R3 7 99 57.875 R4 8 99 57.875 CIN 1 2 2E-12 C2 7 8 22.92E-12 I1 11 50 1E-3 IOS 1 2 1.5E-9 EOS 6 1 POLY(1) 25 29 1E-4 1 Q1 7 2 9 QX Q2 8 6 10 QX R5 9 11 6.275 R6 10 11 6.275 D1 2 4 DX V1 4 6 0.7 V2 6 5 0.7 D2 5 2 DX * * FIRST GAIN STAGE & DOMINANT POLE AT 5.5 HZ * R7 12 99 57.875E6 R8 12 50 57.875E6 C3 12 99 500E-12 C4 12 50 500E-12 G1 99 12 POLY(1) 7 8 380E-6 17.279E-3 G2 12 50 POLY(1) 8 7 380E-6 17.279E-3 V3 99 13 1.9 V4 14 50 1.9 D3 12 13 DX D4 14 12 DX * * POLE-ZERO AT 2MHZ / 6 MHZ * R9 15 99 1E6 R10 15 50 1E6 R11 15 16 5E5 R12 15 17 5E5 C5 16 99 53.05E-15 C6 17 50 53.05E-15 G3 99 15 12 29 1E-6 G4 15 50 29 12 1E-6 * * ZERO-POLE AT 5MHZ / 60 MHZ * R13 99 19 11E6 R14 18 19 1E6 R15 18 20 1E6 R16 20 50 11E6 L1 99 19 29.18E-3 L2 50 20 29.18E-3 G5 99 18 15 29 1E-6 G6 18 50 29 15 1E-6 * * POLE AT 30 MHZ * R17 21 99 1E6 R18 21 50 1E6 C7 21 99 5.305E-15 C8 21 50 5.305E-15 G7 99 21 18 29 1E-6 G8 21 50 29 18 1E-6 * * POLE AT 50 MHZ * R19 22 99 1E6 R20 22 50 1E6 C9 22 99 3.18E-15 C10 22 50 3.18E-15 G9 99 22 21 29 1E-6 G10 22 50 29 21 1E-6 * * POLE AT 50 MHZ * R21 23 99 1E6 R22 23 50 1E6 C11 23 99 3.18E-15 C12 23 50 3.18E-15 G11 99 23 22 29 1E-6 G12 23 50 29 22 1E-6 * * POLE AT 50 MHZ * R23 24 99 1E6 R24 24 50 1E6 C13 24 99 3.18E-15 C14 24 50 3.18E-15 G13 99 24 23 29 1E-6 G14 24 50 29 23 1E-6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 100 HZ * R25 25 26 1E6 R26 25 27 1E6 L3 26 99 1.592E3 L4 27 50 1.592E3 G15 99 25 3 29 1E-12 G16 25 50 29 3 1E-12 D5 25 99 DX D6 50 25 DX * * POLE AT 50 MHZ * R27 28 99 1E6 R28 28 50 1E6 C15 28 99 3.18E-15 C16 28 50 3.18E-15 G17 99 28 24 29 1E-6 G18 28 50 29 24 1E-6 * * OUTPUT STAGE * R29 29 99 20E3 R30 29 50 20E3 R31 34 99 250 R32 34 50 250 L5 34 35 7E-7 G19 32 50 28 34 4E-3 G20 33 50 34 28 4E-3 G21 34 99 99 28 4E-3 G22 50 34 28 50 4E-3 V5 30 34 1.3 V6 34 31 1.3 D7 28 30 DX D8 31 28 DX D9 99 32 DX D10 99 33 DX D11 50 32 DY D12 50 33 DY * * MODELS USED * .MODEL QX NPN(BF=166667) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP481 SPICE Macro-model * 7/97, Ver. 1 * TAM / ADSC * * Copyright 1996,1997 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of this * model indicates your acceptance of the terms and provisions in * the License Statement. * * Node Assignments * noninverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | * | | | | | .SUBCKT OP481 1 2 99 50 45 * * INPUT STAGE * Q1 4 1 3 PIX Q2 6 7 5 PIX I1 99 8 1.28E-6 EOS 7 2 POLY(1) (12,98) 80E-6 1 IOS 1 2 1E-10 RC1 4 50 500E3 RC2 6 50 500E3 RE1 3 8 108 RE2 5 8 108 V1 99 13 DC .9 V2 99 14 DC .9 D1 3 13 DX D2 5 14 DX * * CMRR 76dB, ZERO AT 1kHz * ECM1 11 98 POLY(2) (1,98) (2,98) 0 .5 .5 R1 11 12 1.59E6 C1 11 12 100E-12 R2 12 98 283 * * POLE AT 900kHz * EREF 98 0 90 0 1 G1 98 20 4 6 1E-6 R3 20 98 1E6 C2 20 98 177E-15 * * POLE AT 500kHz * E2 21 98 20 98 1 R4 21 22 1E6 C3 22 98 320E-15 * * GAIN STAGE * CF 45 40 8.5E-12 R5 40 98 65.65E6 G3 98 40 22 98 4.08E-7 D3 40 41 DX D4 42 40 DX V3 99 41 DC 0.5 V4 42 50 DC 0.5 * * OUTPUT STAGE * ISY 99 50 1.375E-6 RS1 99 90 10E6 RS2 90 50 10E6 M1 48 46 99 99 POX L=1.5u W=300u M2 49 47 50 50 NOX L=1.5u W=300u RO1 48 45 400 RO2 49 45 200 EG1 99 46 POLY(1) (98,40) 0.77 1 EG2 47 50 POLY(1) (40,98) 0.77 1 * * MODELS * .MODEL POX PMOS (LEVEL=2, KP=25E-6, VTO=-0.75, LAMBDA=0.01) .MODEL NOX NMOS (LEVEL=2, KP=25E-6, VTO=0.75, LAMBDA=0.01) .MODEL PIX PNP (BF=200) .MODEL DX D(IS=1E-14) .ENDS OP481* OP482 SPICE Macro-model 8/91, Rev. A * JCB / PMI * * Copyright 1991 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP482 1 2 99 50 30 * * INPUT STAGE & POLE AT 15 MHZ * R1 1 3 5E11 R2 2 3 5E11 R3 5 50 3871.3 R4 6 50 3871.3 CIN 1 2 5E-12 C2 5 6 1.37E-12 I1 99 4 0.1E-3 IOS 1 2 5E-13 EOS 7 1 POLY(1) 21 24 200E-6 1 J1 5 2 4 JX J2 6 7 4 JX * EREF 98 0 24 0 1 * * GAIN STAGE & POLE AT 124 HZ * R5 9 98 1.16E8 C3 9 98 1.11E-11 G1 98 9 5 6 2.58E-4 V2 99 8 1.2 V3 10 50 1.2 D1 9 8 DX D2 10 9 DX * * ZERO AT 6 MHZ * R6 11 12 1E6 R7 12 98 1 C4 11 12 26.5E-15 E2 11 98 9 24 1E6 * * POLE AT 15 MHZ * R8 13 98 1E6 C5 13 98 1.06E-15 G2 98 13 12 24 1E-6 * * POLE AT 20 MHZ * R9 14 98 1E6 C6 14 98 7.96E-15 G3 98 14 13 24 1E-6 * * POLE AT 20 MHZ * R19 19 98 1E6 C13 19 98 7.96E-15 G11 98 19 14 24 1E-6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 11 KHZ * R21 20 21 1E6 R22 21 98 1 C14 20 21 8.388E-12 E13 98 20 3 24 31.62 * * POLE AT 25 MHZ * R23 23 98 1E6 C15 23 98 6.37E-15 G15 98 23 19 24 1E-6 * * OUTPUT STAGE * R25 24 99 5E6 R26 24 50 5E6 ISY 99 50 107E-6 R27 29 99 700 R28 29 50 700 L5 29 30 1E-8 G17 27 50 23 29 1.43E-3 G18 28 50 29 23 1.43E-3 G19 29 99 99 23 1.43E-3 G20 50 29 23 50 1.43E-3 V4 25 29 2.8 V5 29 26 3.5 D3 23 25 DX D4 26 23 DX D5 99 27 DX D6 99 28 DX D7 50 27 DY D8 50 28 DY * * MODELS USED * .MODEL JX PJF(BETA=3.34E-4 VTO=-2.000 IS=3E-12) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP482G SPICE Macro-model 4/92, Rev. A * JCB / PMI * * This version of the OP-482 model simulates the worst case * parameters of the 'G' grade. The worst case parameters * used correspond to those in the data sheet. * * Copyright 1991 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP482G 1 2 99 50 30 * * INPUT STAGE & POLE AT 15 MHZ * R1 1 3 5E11 R2 2 3 5E11 R3 5 50 3011 R4 6 50 3011 CIN 1 2 5E-12 C2 5 6 1.76E-12 I1 99 4 0.1E-3 IOS 1 2 2.5E-11 EOS 7 1 POLY(1) 21 24 4E-3 1 J1 5 2 4 JX J2 6 7 4 JX * EREF 98 0 24 0 1 * * GAIN STAGE & POLE AT 185 HZ * R5 9 98 6.02E7 C3 9 98 1.43E-11 G1 98 9 5 6 3.32E-4 V2 99 8 1.2 V3 10 50 1.2 D1 9 8 DX D2 10 9 DX * * ZERO AT 6 MHZ * R6 11 12 1E6 R7 12 98 1 C4 11 12 26.5E-15 E2 11 98 9 24 1E6 * * POLE AT 15 MHZ * R8 13 98 1E6 C5 13 98 1.06E-15 G2 98 13 12 24 1E-6 * * POLE AT 20 MHZ * R9 14 98 1E6 C6 14 98 7.96E-15 G3 98 14 13 24 1E-6 * * POLE AT 20 MHZ * R19 19 98 1E6 C13 19 98 7.96E-15 G11 98 19 14 24 1E-6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 190 KHZ * R21 20 21 1E6 R22 21 98 1 C14 20 21 0.8388E-12 E13 98 20 3 24 316.2 * * POLE AT 25 MHZ * R23 23 98 1E6 C15 23 98 6.37E-15 G15 98 23 19 24 1E-6 * * OUTPUT STAGE * R25 24 99 5E6 R26 24 50 5E6 ISY 99 50 147E-6 R27 29 99 700 R28 29 50 700 L5 29 30 1E-8 G17 27 50 23 29 1.43E-3 G18 28 50 29 23 1.43E-3 G19 29 99 99 23 1.43E-3 G20 50 29 23 50 1.43E-3 V4 25 29 0.35 V5 29 26 2.1 D3 23 25 DX D4 26 23 DX D5 99 27 DX D6 99 28 DX D7 50 27 DY D8 50 28 DY * * MODELS USED * .MODEL JX PJF(BETA=5.51E-4 VTO=-2.000 IS=1E-10) .MODEL DX D(IS=1E-15 RS=1) .MODEL DY D(IS=1E-15 BV=50 RS=1) .ENDS * OP484E SPICE Macro-model 11/95 / Rev. A * ARG / ADSC * * This version of the OP484 model simulates the worst-case * parameters of the 'E' grade. The worst-case parameters * used correspond to those in the data sheet. * * Copyright 1993 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance of the terms and provisions in the License * Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP484E 1 2 99 50 45 * * INPUT STAGE * Q1 5 2 3 QIN 1 Q2 6 11 3 QIN 1 Q3 7 2 4 QIP 1 Q4 8 11 4 QIP 1 DC1 2 11 DC DC2 11 2 DC Q5 4 9 99 QIP 1 Q6 9 9 99 QIP 1 Q7 3 10 50 QIN 1 Q8 10 10 50 QIN 1 R1 99 5 4E3 R2 99 6 4E3 R3 7 50 4E3 R4 8 50 4E3 IREF 9 10 50.5E-6 EOS 1 11 POLY(2) (22,98) (14,98) -75E-6 501.2E-3 1 IOS 2 1 25E-9 CIN 1 2 2E-12 GN1 98 1 17 98 1E-3 GN2 98 2 23 98 1E-3 * * VOLTAGE NOISE SOURCE WITH FLICKER NOISE * VN1 13 98 DC 2 VN2 98 15 DC 2 DN1 13 14 DEN DN2 14 15 DEN * * CURRENT NOISE SOURCE WITH FLICKER NOISE * VN3 16 98 DC 2 VN4 98 18 DC 2 DN3 16 17 DIN DN4 17 18 DIN * * 2ND CURRENT NOISE SOURCE WITH FLICKER NOISE * VN5 19 98 DC 2 VN6 98 24 DC 2 DN5 19 23 DIN DN6 23 24 DIN * * GAIN STAGE * EREF 98 0 POLY(2) (99,0) (50,0) 0 0.5 0.5 G1 98 20 POLY(2) (6,5) (8,7) 0 0.5E-3 0.5E-3 R9 20 98 1E3 * * COMMON MODE STAGE WITH ZERO AT 5KHZ * ECM 98 21 POLY(2) (1,98) (2,98) 0 0.5 0.5 R10 21 22 1 R11 22 98 100E-6 C4 21 22 31.756E-6 * * NEGATIVE ZERO AT 20MHZ * E1 27 98 20 98 1 R17 27 28 1 R18 28 98 1E-6 C8 25 26 7.958E-9 ENZ 25 98 27 28 1 VNZ 26 98 DC 0 FNZ 27 28 VNZ -1 * * POLE AT 40MHZ * G4 98 29 28 98 1E6 R19 29 98 1 C9 29 98 3.979E-9 * * POLE AT 40MHZ * G5 98 30 29 98 1 R20 30 98 1 C10 30 98 3.979E-9 * * OUTUT STAGE * ISY 99 50 0.526E-3 GIN 50 31 POLY(1) (30,98) 0.862574E-6 511.855E-6 RIN 31 50 2.75E6 VB 99 32 0.7 Q11 32 31 33 QON 1 R21 33 34 4.5E3 I1 34 50 50E-6 R22 99 35 6E3 Q12 36 36 35 QOP 1 I2 36 50 50E-6 R23 99 37 2.6E3 R24 34 38 5E3 Q13 39 36 37 QOP 1 Q14 39 38 40 QON 1.5 R25 40 50 40 Q15 39 39 41 QON 1 R26 41 42 1E3 R27 99 43 220 Q16 44 44 43 QOP 1.5 Q17 44 39 42 QON 1 R28 42 50 2E3 VSCP 99 97 DC 0 FSCP 46 99 VSCP 1 RSCP 46 99 125 Q20 44 46 99 QOP 1 Q18 45 44 97 QOP 4.5 Q19 45 34 51 QON 4.5 VSCN 51 50 DC 0 FSCN 50 47 VSCN 1 RSCN 47 50 122 Q21 34 47 50 QON 1 CC2 31 45 20E-12 CF1 31 34 15E-12 CF2 31 42 15E-12 CO1 34 45 15E-12 CO2 42 45 5E-12 D3 45 99 DX D4 50 45 DX .MODEL DC D(IS=130E-21) .MODEL DX D() .MODEL DEN D(RS=100 KF=12E-15 AF=1) .MODEL DIN D(RS=5.358 KF=56E-15 AF=1) .MODEL QIN NPN(BF=250 VA=200 IS=0.5E-16) .MODEL QIP PNP(BF=60 VA=100 IS=0.5E-16) .MODEL QON NPN(BF=200 VA=200 IS=0.5E-16 RC=140) .MODEL QOP PNP(BF=200 VA=200 IS=0.5E-16 RC=210) .ENDS *jg, 22/5/2000: corrected syntex model * OP484F SPICE Macro-model 11/95 / Rev. A * ARG / ADSC * * This version of the OP484 model simulates the worst-case * parameters of the 'F' grade. The worst-case parameters * used correspond to those in the data sheet. * * Copyright 1993 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance of the terms and provisions in the License * Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP484F 1 2 99 50 45 * * INPUT STAGE * Q1 5 2 3 QIN 1 Q2 6 11 3 QIN 1 Q3 7 2 4 QIP 1 Q4 8 11 4 QIP 1 DC1 2 11 DC DC2 11 2 DC Q5 4 9 99 QIP 1 Q6 9 9 99 QIP 1 Q7 3 10 50 QIN 1 Q8 10 10 50 QIN 1 R1 99 5 4E3 R2 99 6 4E3 R3 7 50 4E3 R4 8 50 4E3 IREF 9 10 50.5E-6 EOS 1 11 POLY(2) (22,98) (14,98) -150E-6 501.2E-3 1 IOS 2 1 25E-9 CIN 1 2 2E-12 GN1 98 1 17 98 1E-3 GN2 98 2 23 98 1E-3 * * VOLTAGE NOISE SOURCE WITH FLICKER NOISE * VN1 13 98 DC 2 VN2 98 15 DC 2 DN1 13 14 DEN DN2 14 15 DEN * * CURRENT NOISE SOURCE WITH FLICKER NOISE * VN3 16 98 DC 2 VN4 98 18 DC 2 DN3 16 17 DIN DN4 17 18 DIN * * 2ND CURRENT NOISE SOURCE WITH FLICKER NOISE * VN5 19 98 DC 2 VN6 98 24 DC 2 DN5 19 23 DIN DN6 23 24 DIN * * GAIN STAGE * EREF 98 0 POLY(2) (99,0) (50,0) 0 0.5 0.5 G1 98 20 POLY(2) (6,5) (8,7) 0 0.5E-3 0.5E-3 R9 20 98 1E3 * * COMMON MODE STAGE WITH ZERO AT 5KHZ * ECM 98 21 POLY(2) (1,98) (2,98) 0 0.5 0.5 R10 21 22 1 R11 22 98 100E-6 C4 21 22 31.756E-6 * * NEGATIVE ZERO AT 20MHZ * E1 27 98 20 98 1 R17 27 28 1 R18 28 98 1E-6 C8 25 26 7.958E-9 ENZ 25 98 27 28 1 VNZ 26 98 DC 0 FNZ 27 28 VNZ -1 * * POLE AT 40MHZ * G4 98 29 28 98 1E6 R19 29 98 1 C9 29 98 3.979E-9 * * POLE AT 40MHZ * G5 98 30 29 98 1 R20 30 98 1 C10 30 98 3.979E-9 * * OUTUT STAGE * ISY 99 50 0.526E-3 GIN 50 31 POLY(1) (30,98) 0.862574E-6 511.855E-6 RIN 31 50 2.75E6 VB 99 32 0.7 Q11 32 31 33 QON 1 R21 33 34 4.5E3 I1 34 50 50E-6 R22 99 35 6E3 Q12 36 36 35 QOP 1 I2 36 50 50E-6 R23 99 37 2.6E3 R24 34 38 5E3 Q13 39 36 37 QOP 1 Q14 39 38 40 QON 1.5 R25 40 50 40 Q15 39 39 41 QON 1 R26 41 42 1E3 R27 99 43 220 Q16 44 44 43 QOP 1.5 Q17 44 39 42 QON 1 R28 42 50 2E3 VSCP 99 97 DC 0 FSCP 46 99 VSCP 1 RSCP 46 99 125 Q20 44 46 99 QOP 1 Q18 45 44 97 QOP 4.5 Q19 45 34 51 QON 4.5 VSCN 51 50 DC 0 FSCN 50 47 VSCN 1 RSCN 47 50 122 Q21 34 47 50 QON 1 CC2 31 45 20E-12 CF1 31 34 15E-12 CF2 31 42 15E-12 CO1 34 45 15E-12 CO2 42 45 5E-12 D3 45 99 DX D4 50 45 DX .MODEL DC D(IS=130E-21) .MODEL DX D() .MODEL DEN D(RS=100 KF=12E-15 AF=1) .MODEL DIN D(RS=5.358 KF=56E-15 AF=1) .MODEL QIN NPN(BF=250 VA=200 IS=0.5E-16) .MODEL QIP PNP(BF=60 VA=100 IS=0.5E-16) .MODEL QON NPN(BF=200 VA=200 IS=0.5E-16 RC=140) .MODEL QOP PNP(BF=200 VA=200 IS=0.5E-16 RC=210) .ENDS * jg, 22/5/2000: corrected syntax model * OP490A SPICE Macro-model 10/92, Rev. C * JCB / PMI * * Revision History: * REV. C * Altered gain stage for proper open-loop gain. * REV. B * Re-ordered subcircuit call out nodes to put the * output node last. * Changed Ios from 3E-9 to 1.5E-9 * * * This version of the OP-490 model simulates the worst case * parameters of the 'A' grade. The worst case parameters * used correspond to those in the data book. * * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP490A 1 2 99 50 31 * * INPUT STAGE & POLE AT 10 KHZ * R1 2 3 5E11 R2 1 3 5E11 R3 5 51 61.6E3 R4 6 51 61.6E3 CIN 1 2 4E-12 C2 5 6 129.2E-12 I1 97 4 1E-6 IOS 1 2 1.5E-9 EOS 9 1 POLY(1) 23 27 5E-4 1 Q1 5 2 7 QX Q2 6 9 8 QX R5 7 4 10E3 R6 8 4 10E3 * EREF 98 0 27 0 1 EPLUS 97 0 99 0 1 ENEG 51 0 50 0 1 * * FIRST GAIN STAGE * R7 10 98 1E6 G1 98 10 5 6 101.47E-6 D1 10 11 DX D2 12 10 DX E1 97 11 POLY(1) 97 27 -1.4 1 E2 12 51 POLY(1) 27 51 -1.4 1 * * GAIN STAGE & DOMINANT POLE AT 0.323 HZ * R8 13 98 2.464E6 C3 13 98 200E-9 G2 98 13 10 27 0.5E-3 H2 97 14 POLY(1) VS2 2.2 -3E3 E5 15 51 POLY(2) (17,51) (97,27) 2.0 1.5 -0.405 D3 13 14 DX D4 15 13 DX * * ZERO-IN ZERO-OUT CLAMP * F1 51 17 VS2 -1000 RS1 17 51 1E9 D5 17 51 DX D6 51 17 DX * * NEGATIVE ZERO AT -100 KHZ * R9 19 20 1E6 C4 19 20 -1.59E-12 R10 20 98 1 E3 19 98 13 27 1E6 * * ZERO - POLE PAIR AT 28 KHZ / 100 KHZ * R11 21 22 1E6 L1 22 98 4.09 R12 22 98 2.57E6 G3 98 21 20 27 1E-6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 126 HZ * R13 23 24 1E6 L2 24 98 1.257E3 G4 98 23 3 27 1E-11 D8 23 97 DX D9 51 23 DX * * ZERO - POLE PAIR AT 40 KHZ / 160 KHZ * R14 25 26 1E6 L3 26 98 2.98 R15 26 98 3E6 G5 98 25 21 27 1E-6 * * OUTPUT STAGE * ISY 99 50 14.444E-6 R16 27 99 2.7E6 R17 27 50 2.7E6 R18 30 99 6000 R19 30 50 6000 VS2 30 31 DC 0 G6 28 50 25 30 166.7E-6 G7 29 50 30 25 166.7E-6 G8 30 99 99 25 166.7E-6 G9 50 30 25 50 166.7E-6 D10 99 28 DX D11 99 29 DX D12 50 28 DY D13 50 29 DY * * MODELS USED * .MODEL QX PNP(BF=33.333) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP490E SPICE Macro-model 10/92, Rev. C * JCB / PMI * * Revision History: * REV. C * Altered gain stage for proper open-loop gain. * REV. B * Re-ordered subcircuit call out nodes to put the * output node last. * Changed Ios from 3E-9 to 1.5E-9 * * * This version of the OP-490 model simulates the worst case * parameters of the 'E' grade. The worst case parameters * used correspond to those in the data book. * * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP490E 1 2 99 50 31 * * INPUT STAGE & POLE AT 10 KHZ * R1 2 3 5E11 R2 1 3 5E11 R3 5 51 61.6E3 R4 6 51 61.6E3 CIN 1 2 4E-12 C2 5 6 129.2E-12 I1 97 4 1E-6 IOS 1 2 1.5E-9 EOS 9 1 POLY(1) 23 27 5E-4 1 Q1 5 2 7 QX Q2 6 9 8 QX R5 7 4 10E3 R6 8 4 10E3 * EREF 98 0 27 0 1 EPLUS 97 0 99 0 1 ENEG 51 0 50 0 1 * * FIRST GAIN STAGE * R7 10 98 1E6 G1 98 10 5 6 101.47E-6 D1 10 11 DX D2 12 10 DX E1 97 11 POLY(1) 97 27 -1.4 1 E2 12 51 POLY(1) 27 51 -1.4 1 * * GAIN STAGE & DOMINANT POLE AT 0.323 HZ * R8 13 98 2.464E6 C3 13 98 200E-9 G2 98 13 10 27 0.5E-3 H2 97 14 POLY(1) VS2 2.2 -3E3 E5 15 51 POLY(2) (17,51) (97,27) 2.0 1.5 -0.405 D3 13 14 DX D4 15 13 DX * * ZERO-IN ZERO-OUT CLAMP * F1 51 17 VS2 -1000 RS1 17 51 1E9 D5 17 51 DX D6 51 17 DX * * NEGATIVE ZERO AT -100 KHZ * R9 19 20 1E6 C4 19 20 -1.59E-12 R10 20 98 1 E3 19 98 13 27 1E6 * * ZERO - POLE PAIR AT 28 KHZ / 100 KHZ * R11 21 22 1E6 L1 22 98 4.09 R12 22 98 2.57E6 G3 98 21 20 27 1E-6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 126 HZ * R13 23 24 1E6 L2 24 98 1.257E3 G4 98 23 3 27 1E-11 D8 23 97 DX D9 51 23 DX * * ZERO - POLE PAIR AT 40 KHZ / 160 KHZ * R14 25 26 1E6 L3 26 98 2.98 R15 26 98 3E6 G5 98 25 21 27 1E-6 * * OUTPUT STAGE * ISY 99 50 14.444E-6 R16 27 99 2.7E6 R17 27 50 2.7E6 R18 30 99 6000 R19 30 50 6000 VS2 30 31 DC 0 G6 28 50 25 30 166.7E-6 G7 29 50 30 25 166.7E-6 G8 30 99 99 25 166.7E-6 G9 50 30 25 50 166.7E-6 D10 99 28 DX D11 99 29 DX D12 50 28 DY D13 50 29 DY * * MODELS USED * .MODEL QX PNP(BF=33.333) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP490F SPICE Macro-model 10/92, Rev. C * JCB / PMI * * Revision History: * REV. C * Altered gain stage for proper open-loop gain. * REV. B * Re-ordered subcircuit call out nodes to put the * output node last. * Changed Ios from 5E-9 to 2.5E-9 * * * This version of the OP-490 model simulates the worst case * parameters of the 'F' grade. The worst case parameters * used correspond to those in the data book. * * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP490F 1 2 99 50 31 * * INPUT STAGE & POLE AT 10 KHZ * R1 2 3 5E11 R2 1 3 5E11 R3 5 51 61.6E3 R4 6 51 61.6E3 CIN 1 2 4E-12 C2 5 6 129.2E-12 I1 97 4 1E-6 IOS 1 2 2.5E-9 EOS 9 1 POLY(1) 23 27 .75E-3 1 Q1 5 2 7 QX Q2 6 9 8 QX R5 7 4 10E3 R6 8 4 10E3 * EREF 98 0 27 0 1 EPLUS 97 0 99 0 1 ENEG 51 0 50 0 1 * * FIRST GAIN STAGE * R7 10 98 1E6 G1 98 10 5 6 101.36E-6 D1 10 11 DX D2 12 10 DX E1 97 11 POLY(1) 97 27 -1.4 1 E2 12 51 POLY(1) 27 51 -1.4 1 * * GAIN STAGE & DOMINANT POLE AT 0.403 HZ * R8 13 98 1.973E6 C3 13 98 200E-9 G2 98 13 10 27 0.5E-3 H2 97 14 POLY(1) VS2 2.2 -3E3 E5 15 51 POLY(2) (17,51) (97,27) 2.0 1.5 -0.405 D3 13 14 DX D4 15 13 DX * * ZERO-IN ZERO-OUT CLAMP * F1 51 17 VS2 -1000 RS1 17 51 1E9 D5 17 51 DX D6 51 17 DX * * NEGATIVE ZERO AT -100 KHZ * R9 19 20 1E6 C4 19 20 -1.59E-12 R10 20 98 1 E3 19 98 13 27 1E6 * * ZERO - POLE PAIR AT 28 KHZ / 100 KHZ * R11 21 22 1E6 L1 22 98 4.09 R12 22 98 2.57E6 G3 98 21 20 27 1E-6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 400 HZ * R13 23 24 1E6 L2 24 98 397.9 G4 98 23 3 27 3.162E-11 D8 23 97 DX D9 51 23 DX * * ZERO - POLE PAIR AT 40 KHZ / 160 KHZ * R14 25 26 1E6 L3 26 98 2.98 R15 26 98 3E6 G5 98 25 21 27 1E-6 * * OUTPUT STAGE * ISY 99 50 14.444E-6 R16 27 99 2.7E6 R17 27 50 2.7E6 R18 30 99 6000 R19 30 50 6000 VS2 30 31 DC 0 G6 28 50 25 30 166.7E-6 G7 29 50 30 25 166.7E-6 G8 30 99 99 25 166.7E-6 G9 50 30 25 50 166.7E-6 D10 99 28 DX D11 99 29 DX D12 50 28 DY D13 50 29 DY * * MODELS USED * .MODEL QX PNP(BF=25) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP490G SPICE Macro-model 10/92, Rev. C * JCB / PMI * * Revision History: * REV. C * Altered gain stage for proper open-loop gain. * REV. B * Re-ordered subcircuit call out nodes to put the * output node last. * Changed Ios from 5E-9 to 2.5E-9 * * * This version of the OP-490 model simulates the worst case * parameters of the 'G' grade. The worst case parameters * used correspond to those in the data book. * * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP490G 1 2 99 50 31 * * INPUT STAGE & POLE AT 10 KHZ * R1 2 3 5E11 R2 1 3 5E11 R3 5 51 61.6E3 R4 6 51 61.6E3 CIN 1 2 4E-12 C2 5 6 129.2E-12 I1 97 4 1E-6 IOS 1 2 2.5E-9 EOS 9 1 POLY(1) 23 27 1E-3 1 Q1 5 2 7 QX Q2 6 9 8 QX R5 7 4 10E3 R6 8 4 10E3 * EREF 98 0 27 0 1 EPLUS 97 0 99 0 1 ENEG 51 0 50 0 1 * * FIRST GAIN STAGE * R7 10 98 1E6 G1 98 10 5 6 101.36E-6 D1 10 11 DX D2 12 10 DX E1 97 11 POLY(1) 97 27 -1.4 1 E2 12 51 POLY(1) 27 51 -1.4 1 * * GAIN STAGE & DOMINANT POLE AT 0.403 HZ * R8 13 98 1.973E6 C3 13 98 200E-9 G2 98 13 10 27 0.5E-3 H2 97 14 POLY(1) VS2 2.2 -3E3 E5 15 51 POLY(2) (17,51) (97,27) 2.0 1.5 -0.405 D3 13 14 DX D4 15 13 DX * * ZERO-IN ZERO-OUT CLAMP * F1 51 17 VS2 -1000 RS1 17 51 1E9 D5 17 51 DX D6 51 17 DX * * NEGATIVE ZERO AT -100 KHZ * R9 19 20 1E6 C4 19 20 -1.59E-12 R10 20 98 1 E3 19 98 13 27 1E6 * * ZERO - POLE PAIR AT 28 KHZ / 100 KHZ * R11 21 22 1E6 L1 22 98 4.09 R12 22 98 2.57E6 G3 98 21 20 27 1E-6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 400 HZ * R13 23 24 1E6 L2 24 98 397.9 G4 98 23 3 27 3.162E-11 D8 23 97 DX D9 51 23 DX * * ZERO - POLE PAIR AT 40 KHZ / 160 KHZ * R14 25 26 1E6 L3 26 98 2.98 R15 26 98 3E6 G5 98 25 21 27 1E-6 * * OUTPUT STAGE * ISY 99 50 14.444E-6 R16 27 99 2.7E6 R17 27 50 2.7E6 R18 30 99 6000 R19 30 50 6000 VS2 30 31 DC 0 G6 28 50 25 30 166.7E-6 G7 29 50 30 25 166.7E-6 G8 30 99 99 25 166.7E-6 G9 50 30 25 50 166.7E-6 D10 99 28 DX D11 99 29 DX D12 50 28 DY D13 50 29 DY * * MODELS USED * .MODEL QX PNP(BF=20) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP491G SPICE Macro-model Rev. A, 5/94 * ARG / PMI * * This version of the OP491 model simulates the worst-case * parameters of the 'G' grade. The worst-case parameters * used correspond to those in the data sheet. * * Copyright 1994 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of * this model indicates your acceptance of the terms and pro- * visions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP491G 1 2 99 50 45 * * INPUT STAGE * I1 99 7 8.1E-6 Q1 6 4 7 QP Q2 5 3 7 QP D1 3 99 DX D2 4 99 DX D3 3 4 DX D4 4 3 DX R1 3 8 5E3 R2 4 2 5E3 R3 5 50 6.4654E3 R4 6 50 6.4654E3 EOS 8 1 POLY(1) (16,39) -0.7E-3 1.778 IOS 3 4 4E-9 GB1 3 98 21 98 83.333E-9 GB2 4 98 21 98 83.333E-9 CIN 1 2 1E-12 * * 1ST GAIN STAGE * EREF 98 0 39 0 1 G1 98 9 6 5 31.416E-6 R7 9 98 1E6 EC1 99 10 POLY(1) (99,39) -0.52 1 EC2 11 50 POLY(1) (39,50) -0.52 1 D5 9 10 DX D6 11 9 DX * * 2ND GAIN STAGE AND DOMINANT POLE AT 100HZ * G2 98 12 9 39 8E-6 R8 12 98 99.472E6 C2 12 98 16E-12 D7 12 13 DX D8 14 12 DX V1 99 13 0.58 V2 14 50 0.58 * * COMMON MODE STAGE * ECM 15 98 POLY(2) (1,39) (2,39) 0 0.5 0.5 R9 15 16 1E6 R10 16 98 100 * * POLE AT 2.5MHZ * G3 98 18 12 39 1E-6 R11 18 98 1E6 C4 18 98 63.662E-15 * * BIAS CURRENT-VS-COMMON MODE VOLTAGE * EP 97 0 99 0 1 VB 99 17 1.3 RB 17 50 1E9 E3 19 0 15 17 16 D13 19 20 DX R12 20 0 1E6 G4 98 21 20 0 1E-3 R13 21 98 5E3 D14 21 22 DY E4 97 22 (POLY(1) (99,98) -0.765 1 * * POLE AT 100MHZ * G6 98 40 18 39 1E-6 R20 40 98 1E6 C10 40 98 1.592E-15 * * OUTPUT STAGE * RS1 99 39 109.375E3 RS2 39 50 109.375E3 RO1 99 45 41.667 RO2 45 50 41.667 G7 45 99 99 40 24E-3 G8 50 45 40 50 24E-3 G9 98 60 45 40 24E-3 D9 60 61 DX D10 62 60 DX V7 61 98 DC 0 V8 98 62 DC 0 FSY 99 50 POLY(2) V7 V8 0.367E-3 1 1 D11 41 45 DZ D12 45 42 DZ V5 40 41 0.131 V6 42 40 0.131 .MODEL DX D() .MODEL DY D(IS=1E-9) .MODEL DZ D(IS=1E-6) .MODEL QP PNP(BF=80) .ENDS *jg, 22/5/2000: corrected syntax model * OP492G SPICE Macro-model Rev. A, 3/95 * ARG / ADSC * * This version of the OP492 model simulates the worst-case * parameters of the 'G' grade. The worst-case parameters * used correspond to those in the data sheet. * * Copyright 1995 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of * this model indicates your acceptance of the terms and pro- * visions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP492G 2 1 99 50 34 * * INPUT STAGE AND POLE AT 40MHZ * I1 99 4 51.4E-6 IOS 2 1 25E-9 EOS 2 3 POLY(1) (21,30) 2E-3 16.8 CIN 1 2 2E-12 Q1 5 1 7 QP Q2 6 3 8 QP R3 5 50 2E3 R4 6 50 2E3 R5 4 7 965 R6 4 8 965 C1 5 6 .995E-12 * * GAIN STAGE * EREF 98 0 30 0 1 G1 98 9 5 6 500E-6 R7 9 98 14.388E3 D1 9 10 DX D2 11 9 DX V1 99 10 .6 V2 11 50 .6 * * ZERO/POLE AT 6MHZ/12MHZ * E1 12 98 9 30 2 R8 12 13 1 R9 13 98 1 C3 12 13 26.526E-9 * * ZERO AT 15MHZ * E2 14 98 13 30 1E6 R10 14 15 1E6 R11 15 98 1 C4 14 15 10.610E-15 * * COMMON MODE STAGE WITH ZERO AT 40KHZ * ECM 20 98 POLY(2) (1,30) (2,30) 0 0.5 0.5 R20 20 21 1E6 R21 21 98 10 *C5 20 21 3.979E-12 * * POLE AT 100MHZ * G2 98 16 9 30 1 R12 16 98 1 C6 16 98 1.592E-9 * * OUTPUT STAGE * RS1 99 30 1E6 RS2 30 50 1E6 ISY 99 50 .236E-3 G3 31 50 POLY(1) (16,30) -1.681511E-6 1E-6 R16 31 50 1E6 DCL 50 31 DZ I2 99 32 250E-6 RCP 99 36 75 RCL 33 50 75 Q6 35 36 99 QPA Q7 32 37 50 QNA R17 35 37 1E3 M1 32 31 50 50 MN L=9E-6 W=1000E-6 AD=15E-9 AS=15E-9 M2 34 31 50 50 MN L=9E-6 W=1000E-6 AD=15E-9 AS=15E-9 CC 31 32 0.23E-12 Q3 36 32 34 QNA Q4 33 32 34 QPA Q5 31 33 50 QNA .MODEL QNA NPN(IS=1.19E-16 BF=253 VAF=193 RC=400) .MODEL QPA PNP(IS=5.21E-17 BF=131 VAF=62 RC=250) *.MODEL MN NMOS(LEVEL=3 VTO=1.3 RS=0.3 RD=0.3 LD=1.48E-6 WD=1E-6) .MODEL MN NMOS(LEVEL=3 VTO=1.3 RS=0.3 RD=0.3 LD=1.48E-6) * jg, 22/5/2000: corrected syntax model .MODEL QP PNP(BF=35.714) .MODEL DX D .MODEL DZ D(BV=3.6) .ENDS OP492G * OP493E SPICE Macro-model 1/95, Rev. A * ARG / ADI * * This version of the OP493 model simulates the worst-case * parameters of the 'E' grade. The worst-case parameters * used correspond to those in the data sheet. * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License * Statement. This model has been optimized for a total supply voltage of * 5V. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP493E 51 52 99 50 32 * * INPUT STAGE & POLE AT 16KHZ * R3 5 50 53.827E3 R4 6 50 53.827E3 R5 4 7 2.104E3 R6 4 8 2.104E3 CIN 1 2 4E-12 C2 5 6 92.4E-12 I1 99 4 1.03E-6 IOS 1 2 1E-9 EOS 9 1 POLY(2) (24,27) (102,0) 125E-6 0.1 1 Q1 5 2 7 QX Q2 6 9 8 QX EREF 98 0 POLY(2) (99,0) (50,0) 0 0.5 0.5 R24 1 51 2E3 R25 2 52 2E3 VN1 101 0 DC 2 VN2 0 103 DC 2 DN1 101 102 DEN DN2 102 103 DEN * * GAIN STAGE & DOMINANT POLE AT 0.473 HZ * R7 10 98 4.037E9 G1 98 10 5 6 18.578E-6 C3 10 98 83.333E-12 V1 99 11 0.65 D1 10 11 DX D2 50 10 DX * * NEGATIVE ZERO AT 50KHZ * R9 13 14 1E6 R10 14 98 1 FNZ 13 14 VNZ -1 E2 13 98 10 27 1 CNZ 15 16 3.183E-12 ENZ 15 98 13 14 1 VNZ 16 98 DC 0 * * ZERO-POLE PAIR AT 28KHZ / 84KHZ * R18 17 18 2E6 C4 17 18 2.842E-12 R19 18 98 1E6 E3 17 98 14 27 3E6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 3.16HZ * R1 23 24 1E6 R2 24 98 100 C5 23 24 50.33E-9 E4 23 98 POLY(2) (1,27) (2,27) 0 0.5 0.5 * * ZERO-POLE PAIR AT 40KHZ / 160KHZ * R20 25 26 3E6 C6 25 26 1.326E-12 R21 26 98 1E6 E5 25 98 18 27 4 * * OUTPUT STAGE * ISY 99 50 20.137E-6 R16 27 99 4.5E6 R17 27 50 4.5E6 EIN 28 98 POLY(1) (26,27) 0.51905 1 RIN 28 31 15E3 Q11 45 31 32 QN 6 Q12 32 33 44 QN 6 Q13 41 34 33 QN 1 Q14 34 35 36 QP 1 Q15 36 38 39 QN 8 Q16 35 35 37 QP 1 Q17 99 99 37 QN 1 Q18 99 99 36 QN 1 Q19 50 42 34 QP 1 Q20 42 42 34 QP 1 Q21 32 33 42 QN 1 Q22 99 40 41 QN 1 Q23 43 43 50 QN 1 Q24 34 43 50 QN 2 Q25 33 43 50 QN 2 Q26 34 44 50 QC 1 Q27 31 46 50 QC 1 EC 47 50 99 45 0.96 RC 46 47 1E3 IREF 99 43 4.5E-7 I13 35 50 4.5E-7 R11 99 40 75E3 R12 99 36 40E3 R13 31 38 20E3 R14 32 39 5E3 R15 40 37 75E3 R22 44 50 30 R23 99 45 50 * * MODELS USED * .MODEL QN NPN(BF=200 IS=1E-16 VA=150) .MODEL QP PNP(BF=100 IS=5E-17 VA=50) .MODEL QX PNP(BF=33.333 KF=2E-17) .MODEL QC NPN(BF=200 IS=2.22E-11) .MODEL DX D(IS=1E-15) .MODEL DEN D(RS=2.45E3 KF=33E-15) .ENDS *jg, 22/5/2000: corrected syntax model* OP493F SPICE Macro-model 1/95, Rev. A * ARG / ADI * * This version of the OP493 model simulates the worst-case * parameters of the 'F' grade. The worst-case parameters * used correspond to those in the data sheet. * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License * Statement. This model has been optimized for a total supply voltage of * 5V. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP493F 51 52 99 50 32 * * INPUT STAGE & POLE AT 16KHZ * R3 5 50 53.827E3 R4 6 50 53.827E3 R5 4 7 2.104E3 R6 4 8 2.104E3 CIN 1 2 4E-12 C2 5 6 92.4E-12 I1 99 4 1.04E-6 IOS 1 2 2E-9 EOS 9 1 POLY(2) (24,27) (102,0) 275E-6 0.1585 1 Q1 5 2 7 QX Q2 6 9 8 QX EREF 98 0 POLY(2) (99,0) (50,0) 0 0.5 0.5 R24 1 51 2E3 R25 2 52 2E3 VN1 101 0 DC 2 VN2 0 103 DC 2 DN1 101 102 DEN DN2 102 103 DEN * * GAIN STAGE & DOMINANT POLE AT 0.473 HZ * R7 10 98 4.037E9 G1 98 10 5 6 18.578E-6 C3 10 98 83.333E-12 V1 99 11 0.65 D1 10 11 DX D2 50 10 DX * * NEGATIVE ZERO AT 50KHZ * R9 13 14 1E6 R10 14 98 1 FNZ 13 14 VNZ -1 E2 13 98 10 27 1 CNZ 15 16 3.183E-12 ENZ 15 98 13 14 1 VNZ 16 98 DC 0 * * ZERO-POLE PAIR AT 28KHZ / 84KHZ * R18 17 18 2E6 C4 17 18 2.842E-12 R19 18 98 1E6 E3 17 98 14 27 3E6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 5HZ * R1 23 24 1E6 R2 24 98 100 C5 23 24 32E-9 E4 23 98 POLY(2) (1,27) (2,27) 0 0.5 0.5 * * ZERO-POLE PAIR AT 40KHZ / 160KHZ * R20 25 26 3E6 C6 25 26 1.326E-12 R21 26 98 1E6 E5 25 98 18 27 4 * * OUTPUT STAGE * ISY 99 50 20.137E-6 R16 27 99 4.5E6 R17 27 50 4.5E6 EIN 28 98 POLY(1) (26,27) 0.51905 1 RIN 28 31 15E3 Q11 45 31 32 QN 6 Q12 32 33 44 QN 6 Q13 41 34 33 QN 1 Q14 34 35 36 QP 1 Q15 36 38 39 QN 8 Q16 35 35 37 QP 1 Q17 99 99 37 QN 1 Q18 99 99 36 QN 1 Q19 50 42 34 QP 1 Q20 42 42 34 QP 1 Q21 32 33 42 QN 1 Q22 99 40 41 QN 1 Q23 43 43 50 QN 1 Q24 34 43 50 QN 2 Q25 33 43 50 QN 2 Q26 34 44 50 QC 1 Q27 31 46 50 QC 1 EC 47 50 99 45 0.96 RC 46 47 1E3 IREF 99 43 4.5E-7 I13 35 50 4.5E-7 R11 99 40 75E3 R12 99 36 40E3 R13 31 38 20E3 R14 32 39 5E3 R15 40 37 75E3 R22 44 50 30 R23 99 45 50 * * MODELS USED * .MODEL QN NPN(BF=200 IS=1E-16 VA=150) .MODEL QP PNP(BF=100 IS=5E-17 VA=50) .MODEL QX PNP(BF=25 KF=2E-17) .MODEL QC NPN(BF=200 IS=2.22E-11) .MODEL DX D(IS=1E-15) .MODEL DEN D(RS=2.45E3 KF=33E-15) .ENDS *jg, 22/5/2000: corrected syntax model* OP495G SPICE Macro-model 2/95, Rev. A * ARG / ADSC * * This version of the OP495 model simulates the worst-case * parameters of the 'G' grade. The worst-case parameters * used correspond to those in the data sheet. * * Copyright 1995 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License * Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP495G 1 2 99 50 20 * * INPUT STAGE * I1 99 4 2.04E-6 R1 1 6 5E3 R2 2 5 5E3 CIN 1 2 2E-12 IOS 1 2 1.5E-9 D1 5 3 DZ D2 6 3 DZ EOS 7 6 POLY(1) (31,39) 300E-6 0.316 Q1 8 5 4 QP Q2 9 7 4 QP R3 8 50 25.861E3 R4 9 50 25.861E3 * * GAIN STAGE * R7 10 98 72.8725E6 G1 98 10 POLY(1) (9,8) -15.8072E-9 27.8E-6 EREF 98 0 (39,0) 1 R5 99 39 417E3 R6 39 50 417E3 * * COMMON MODE STAGE * ECM 30 98 POLY(2) (1,39) (2,39) 0 0.5 0.5 R12 30 31 1E6 R13 31 98 100 * * OUTPUT STAGE * ISY 99 50 99E-6 I2 18 50 1.59E-6 V2 99 12 DC 2.2763 Q4 10 14 50 QNA 1.0 R11 14 50 54 M3 15 10 13 13 MN L=9E-6 W=102E-6 AD=15E-10 AS=15E-10 M4 13 10 50 50 MN L=9E-6 W=50E-6 AD=75E-11 AS=75E-11 D8 10 22 DX V3 22 50 DC 6 M2 20 10 14 14 MN L=9E-6 W=2000E-6 AD=30E-9 AS=30E-9 Q5 17 17 99 QPA 1.0 Q6 18 17 99 QPA 4.0 R8 18 99 2.2E6 Q7 18 19 99 QPA 1.0 R9 99 19 48 C2 18 99 20E-12 M6 15 12 17 99 MP L=9E-6 W=27E-6 AD=405E-12 AS=405E-12 M1 20 18 19 99 MP L=9E-6 W=2000E-6 AD=30E-9 AS=30E-9 D4 21 18 DX V4 99 21 DC 6 R10 10 11 6E3 C3 11 20 54E-12 .MODEL QNA NPN(IS=1.19E-16 BF=253 NF=0.99 VAF=193 IKF=2.76E-3 + ISE=2.57E-13 NE=5 BR=0.4 NR=0.988 VAR=15 IKR=1.465E-4 + ISC=6.9E-16 NC=0.99 RB=2.0E3 IRB=7.73E-6 RBM=132.8 RE=4 RC=209 + CJE=2.1E-13 VJE=0.573 MJE=0.364 FC=0.5 CJC=1.64E-13 VJC=0.534 MJC=0.5 + CJS=1.37E-12 VJS=0.59 MJS=0.5 TF=0.43E-9 PTF=30) .MODEL QPA PNP(IS=5.21E-17 BF=131 NF=0.99 VAF=62 IKF=8.35E-4 + ISE=1.09E-14 NE=2.61 BR=0.5 NR=0.984 VAR=15 IKR=3.96E-5 + ISC=7.58E-16 NC=0.985 RB=1.52E3 IRB=1.67E-5 RBM=368.5 RE=6.31 RC=354.4 + CJE=1.1E-13 VJE=0.745 MJE=0.33 FC=0.5 CJC=2.37E-13 VJC=0.762 MJC=0.4 + CJS=7.11E-13 VJS=0.45 MJS=0.412 TF=1.0E-9 PTF=30) .MODEL MN NMOS(LEVEL=3 VTO=1.3 RS=0.3 RD=0.3 + TOX=8.5E-8 LD=1.48E-6 NSUB=1.53E16 UO=650 DELTA=10 VMAX=2E5 + XJ=1.75E-6 KAPPA=0.8 ETA=0.066 THETA=0.01 TPG=1 CJ=2.9E-4 PB=0.837 + MJ=0.407 CJSW=0.5E-9 MJSW=0.33) .MODEL MP PMOS(LEVEL=3 VTO=-1.1 RS=0.7 RD=0.7 + TOX=9.5E-8 LD=1.4E-6 NSUB=2.4E15 UO=650 DELTA=5.6 VMAX=1E5 + XJ=1.75E-6 KAPPA=1.7 ETA=0.71 THETA=5.9E-3 TPG=-1 CJ=1.55E-4 PB=0.56 + MJ=0.442 CJSW=0.4E-9 MJSW=0.33) .MODEL DX D(IS=1E-15) .MODEL DZ D(IS=1E-15, BV=7) .MODEL QP PNP(BF=50) .ENDS * OP496 SPICE Macro-model Rev. A, 5/95 * ARG / ADSC * * Copyright 1995 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of * this model indicates your acceptance of the terms and pro- * visions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP496 1 2 99 50 49 * * INPUT STAGE * IREF 21 50 1U QB1 21 21 99 99 QP 1 QB2 22 21 99 99 QP 1 QB3 4 21 99 99 QP 1.5 QB4 22 22 50 50 QN 2 QB5 11 22 50 50 QN 3 Q1 5 4 7 50 QN 2 Q2 6 4 8 50 QN 2 Q3 4 4 7 50 QN 1 Q4 4 4 8 50 QN 1 Q5 50 1 7 99 QP 2 Q6 50 3 8 99 QP 2 EOS 3 2 POLY(1) (17,98) 35U 1 Q7 99 1 9 50 QN 2 Q8 99 3 10 50 QN 2 Q9 12 11 9 99 QP 2 Q10 13 11 10 99 QP 2 Q11 11 11 9 99 QP 1 Q12 11 11 10 99 QP 1 R1 99 5 50K R2 99 6 50K R3 12 50 50K R4 13 50 50K IOS 1 2 0.75N C10 5 6 3.183P C11 12 13 3.183P CIN 1 2 1P * * GAIN STAGE * EREF 98 0 POLY(2) (99,0) (50,0) 0 0.5 0.5 G1 98 15 POLY(2) (6,5) (13,12) 0 10U 10U R10 15 98 251.641MEG CC 15 49 8P D1 15 99 DX D2 50 15 DX * * COMMON MODE STAGE * ECM 16 98 POLY(2) (1,98) (2,98) 0 0.5 0.5 R11 16 17 1E6 R12 17 98 10 * * OUTPUT STAGE * ISY 99 50 20E-6 EIN 35 50 POLY(1) (15,98) 1.42735 1 Q24 37 35 36 50 QN 1 QD4 37 37 38 99 QP 1 Q27 40 37 38 99 QP 1 R5 36 39 150K R6 99 38 45K Q26 39 42 50 50 QN 3 QD5 40 40 39 50 QN 1 Q28 41 40 44 50 QN 1 QL1 37 41 99 99 QP 1 R7 99 41 10.7K I4 99 43 2U QD7 42 42 50 50 QN 2 QD6 43 43 42 50 QN 2 Q29 47 43 44 50 QN 1 Q30 44 45 50 50 QN 1.5 QD10 45 46 50 50 QN 1 R9 45 46 175 Q31 46 47 48 99 QP 1 QD8 47 47 48 99 QP 1 QD9 48 48 51 99 QP 5 R8 99 51 2.9K I5 99 46 1U Q32 49 48 99 99 QP 10 Q33 49 44 50 50 QN 4 .MODEL DX D() .MODEL QN NPN(BF=120 VAF=100) .MODEL QP PNP(BF=80 VAF=60) .ENDS * OP496G SPICE Macro-model Rev. A, 6/95 * ARG / ADSC * * This version of the OP496 model simulates the worst-case * parameters of the 'G' grade. The worst-case parameters * used correspond to those in the data sheet. * * Copyright 1995 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of * this model indicates your acceptance of the terms and pro- * visions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP496G 1 2 99 50 49 * * INPUT STAGE * IREF 21 50 1U QB1 21 21 99 99 QP 1 QB2 22 21 99 99 QP 1 QB3 4 21 99 99 QP 1.5 QB4 22 22 50 50 QN 2 QB5 11 22 50 50 QN 3 Q1 5 4 7 50 QN1 2 Q2 6 4 8 50 QN1 2 Q3 4 4 7 50 QN1 1 Q4 4 4 8 50 QN1 1 Q5 50 1 7 99 QP1 2 Q6 50 3 8 99 QP1 2 EOS 3 2 POLY(1) (17,98) 300E-6 1 Q7 99 1 9 50 QN1 2 Q8 99 3 10 50 QN1 2 Q9 12 11 9 99 QP1 2 Q10 13 11 10 99 QP1 2 Q11 11 11 9 99 QP1 1 Q12 11 11 10 99 QP1 1 R1 99 5 50K R2 99 6 50K R3 12 50 50K R4 13 50 50K IOS 1 2 2.5N C10 5 6 3.183P C11 12 13 3.183P CIN 1 2 1P * * GAIN STAGE * EREF 98 0 POLY(2) (99,0) (50,0) 0 0.5 0.5 G1 98 15 POLY(2) (6,5) (13,12) 0 10U 10U R10 15 98 120MEG CC 15 49 8P D1 15 99 DX D2 50 15 DX * * COMMON MODE STAGE * ECM 16 98 POLY(2) (1,98) (2,98) 0 0.5 0.5 R11 16 17 1E6 R12 17 98 100 * * OUTPUT STAGE * ISY 99 50 35E-6 EIN 35 50 POLY(1) (15,98) 1.42713 1 Q24 37 35 36 50 QN 1 QD4 37 37 38 99 QP 1 Q27 40 37 38 99 QP 1 R5 36 39 150K R6 99 38 45K Q26 39 42 50 50 QN 3 QD5 40 40 39 50 QN 1 Q28 41 40 44 50 QN 1 QL1 37 41 99 99 QP 1 R7 99 41 10.7K I4 99 43 2U QD7 42 42 50 50 QN 2 QD6 43 43 42 50 QN 2 Q29 47 43 44 50 QN 1 Q30 44 45 50 50 QN 1.5 QD10 45 46 50 50 QN 1 R9 45 46 175 Q31 46 47 48 99 QP 1 QD8 47 47 48 99 QP 1 QD9 48 48 51 99 QP 5 R8 99 51 2.9K I5 99 46 1U Q32 49 48 99 99 QOP 10 Q33 49 44 50 50 QON 4 .MODEL DX D() .MODEL QN NPN(BF=120 VAF=100) .MODEL QP PNP(BF=80 VAF=60) *.MODEL QON AKO:QN NPN(RC=2K) *.MODEL QOP AKO:QP PNP(RC=4K) * jg, 18/5/00: corrected syntax model .MODEL QON NPN(BF=120 VAF=100 RC=2K) .MODEL QOP PNP(BF=80 VAF=60 RC=4K) .MODEL QN1 NPN(BF=100 VAF=100) .MODEL QP1 PNP(BF=56 VAF=60) .ENDS * OP497A SPICE Macro-model 4/91, Rev. B * AAG / PMI * * This version of the OP-497 model simulates the worst case * parameters of the 'A' grade. The worst case parameters * used correspond to those in the data sheet. * * Copyright 1991 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP497A 1 2 99 50 32 * * INPUT STAGE & POLE AT 6 MHZ * RIN1 1 7 2500 RIN2 2 8 2500 R1 8 3 2.586E8 R2 7 3 2.586E8 R3 5 99 517.2 R4 6 99 517.2 CIN 7 8 3E-12 C2 5 6 25.644E-12 I1 4 50 0.1E-3 IOS 7 8 50E-12 EOS 9 7 POLY(1) 19 24 50E-6 1 Q1 5 8 4 QX Q2 6 9 4 QX D1 8 9 DX D2 9 8 DX * EREF 98 0 24 0 1 * * 1st GAIN STAGE * G1 98 12 5 6 165.88E-6 R7 12 98 1E6 E1 99 13 POLY(1) 99 24 -2.4 1 D3 12 13 DX E2 14 50 POLY(1) 24 50 -2.4 1 D4 14 12 DX * * 2nd GAIN STAGE & DOMINANT POLE AT 0.22 HZ * G2 98 15 12 24 33.333E-6 R8 15 98 361.72E6 C3 15 98 2E-9 V1 99 16 DC 1.275 D5 15 16 DX V2 17 50 DC 1.275 D6 17 15 DX * * COMMON-MODE GAIN NETWORK WITH ZERO AT 281.17 HZ * ECM 18 98 3 24 1 RCM1 18 19 1E6 CCM 18 19 566.05E-12 RCM2 19 98 1 * * NEGATIVE ZERO AT 1.8 MHz * ENZ 20 98 15 24 1E6 RNZ1 20 21 1E6 CNZ 20 21 -88.419E-15 RNZ2 21 98 1 * * POLE AT 6 MHZ * G3 98 22 21 24 1E-6 R9 22 98 1E6 C4 22 98 26.526E-15 * * POLE AT 1.8 MHZ * G4 98 23 22 24 1E-6 R15 23 98 1E6 C8 23 98 88.419E-15 * * OUTPUT STAGE * R16 24 99 160k R17 24 50 160k ISY 99 50 431E-6 D7 23 28 DX V3 28 27 DC 1.9 D8 29 23 DX V4 27 29 DC 1.9 D9 99 30 DX G5 30 50 23 27 5E-3 D11 50 30 DY D10 99 31 DX G6 31 50 27 23 5E-3 D12 50 31 DY G7 27 99 99 23 5E-3 R18 27 99 200 G8 50 27 23 50 5E-3 R19 27 50 200 L1 27 32 0.1E-6 * * MODELS USED * .MODEL QX NPN(BF=500E3) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP497B SPICE Macro-model 4/91, Rev. B * AAG / PMI * * This version of the OP-497 model simulates the worst case * parameters of the 'B' grade. The worst case parameters * used correspond to those in the data sheet. * * Copyright 1991 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP497B 1 2 99 50 32 * * INPUT STAGE & POLE AT 6 MHZ * RIN1 1 7 2500 RIN2 2 8 2500 R1 8 3 1.724E8 R2 7 3 1.724E8 R3 5 99 517.2 R4 6 99 517.2 CIN 7 8 3E-12 C2 5 6 25.644E-12 I1 4 50 0.1E-3 IOS 7 8 75E-12 EOS 9 7 POLY(1) 19 24 75E-6 1 Q1 5 8 4 QX Q2 6 9 4 QX D1 8 9 DX D2 9 8 DX * EREF 98 0 24 0 1 * * 1st GAIN STAGE * G1 98 12 5 6 163.99E-6 R7 12 98 1E6 E1 99 13 POLY(1) 99 24 -2.4 1 D3 12 13 DX E2 14 50 POLY(1) 24 50 -2.4 1 D4 14 12 DX * * 2nd GAIN STAGE & DOMINANT POLE AT 0.29 HZ * G2 98 15 12 24 33.333E-6 R8 15 98 274.41E6 C3 15 98 2E-9 V1 99 16 DC 1.275 D5 15 16 DX V2 17 50 DC 1.275 D6 17 15 DX * * COMMON-MODE GAIN NETWORK WITH ZERO AT 561.01 HZ * ECM 18 98 3 24 1.9953 RCM1 18 19 1E6 CCM 18 19 283.69E-12 RCM2 19 98 1 * * NEGATIVE ZERO AT 1.8 MHz * ENZ 20 98 15 24 1E6 RNZ1 20 21 1E6 CNZ 20 21 -88.419E-15 RNZ2 21 98 1 * * POLE AT 6 MHZ * G3 98 22 21 24 1E-6 R9 22 98 1E6 C4 22 98 26.526E-15 * * POLE AT 1.8 MHZ * G4 98 23 22 24 1E-6 R15 23 98 1E6 C8 23 98 88.419E-15 * * OUTPUT STAGE * R16 24 99 160K R17 24 50 160K ISY 99 50 431E-6 D7 23 28 DX V3 28 27 DC 1.9 D8 29 23 DX V4 27 29 DC 1.9 D9 99 30 DX G5 30 50 23 27 5E-3 D11 50 30 DY D10 99 31 DX G6 31 50 27 23 5E-3 D12 50 31 DY G7 27 99 99 23 5E-3 R18 27 99 200 G8 50 27 23 50 5E-3 R19 27 50 200 L1 27 32 0.1E-6 * * MODELS USED * .MODEL QX NPN(BF=333.333E3) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP497C SPICE Macro-model 4/91, Rev. B * AAG / PMI * * This version of the OP-497 model simulates the worst case * parameters of the 'C' grade. The worst case parameters * used correspond to those in the data sheet. * * Copyright 1991 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP497C 1 2 99 50 32 * * INPUT STAGE & POLE AT 6 MHZ * RIN1 1 7 2500 RIN2 2 8 2500 R1 8 3 1.293E8 R2 7 3 1.293E8 R3 5 99 517.2 R4 6 99 517.2 CIN 7 8 3E-12 C2 5 6 25.644E-12 I1 4 50 0.1E-3 IOS 7 8 100E-12 EOS 9 7 POLY(1) 19 24 150E-6 1 Q1 5 8 4 QX Q2 6 9 4 QX D1 8 9 DX D2 9 8 DX * EREF 98 0 24 0 1 * * 1st GAIN STAGE * G1 98 12 5 6 167.39E-6 R7 12 98 1E6 E1 99 13 POLY(1) 99 24 -2.4 1 D3 12 13 DX E2 14 50 POLY(1) 24 50 -2.4 1 D4 14 12 DX * * 2nd GAIN STAGE & DOMINANT POLE AT 0.37 HZ * G2 98 15 12 24 33.333E-6 R8 15 98 215.07E6 C3 15 98 2E-9 V1 99 16 DC 1.275 D5 15 16 DX V2 17 50 DC 1.275 D6 17 15 DX * * COMMON-MODE GAIN NETWORK WITH ZERO AT 561.01 HZ * ECM 18 98 3 24 1.9953 RCM1 18 19 1E6 CCM 18 19 283.69E-12 RCM2 19 98 1 * * NEGATIVE ZERO AT 1.8 MHz * ENZ 20 98 15 24 1E6 RNZ1 20 21 1E6 CNZ 20 21 -88.419E-15 RNZ2 21 98 1 * * POLE AT 6 MHZ * G3 98 22 21 24 1E-6 R9 22 98 1E6 C4 22 98 26.526E-15 * * POLE AT 1.8 MHZ * G4 98 23 22 24 1E-6 R15 23 98 1E6 C8 23 98 88.419E-15 * * OUTPUT STAGE * R16 24 99 160K R17 24 50 160K ISY 99 50 431E-6 D7 23 28 DX V3 28 27 DC 1.9 D8 29 23 DX V4 27 29 DC 1.9 D9 99 30 DX G5 30 50 23 27 5E-3 D11 50 30 DY D10 99 31 DX G6 31 50 27 23 5E-3 D12 50 31 DY G7 27 99 99 23 5E-3 R18 27 99 200 G8 50 27 23 50 5E-3 R19 27 50 200 L1 27 32 0.1E-6 * * MODELS USED * .MODEL QX NPN(BF=250E3) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP497F SPICE Macro-model 4/91, Rev. B * AAG / PMI * * This version of the OP-497 model simulates the worst case * parameters of the 'F' grade. The worst case parameters * used correspond to those in the data sheet. * * Copyright 1991 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP497F 1 2 99 50 32 * * INPUT STAGE & POLE AT 6 MHZ * RIN1 1 7 2500 RIN2 2 8 2500 R1 8 3 1.724E8 R2 7 3 1.724E8 R3 5 99 517.2 R4 6 99 517.2 CIN 7 8 3E-12 C2 5 6 25.644E-12 I1 4 50 0.1E-3 IOS 7 8 75E-12 EOS 9 7 POLY(1) 19 24 75E-6 1 Q1 5 8 4 QX Q2 6 9 4 QX D1 8 9 DX D2 9 8 DX * EREF 98 0 24 0 1 * * 1st GAIN STAGE * G1 98 12 5 6 163.99E-6 R7 12 98 1E6 E1 99 13 POLY(1) 99 24 -2.4 1 D3 12 13 DX E2 14 50 POLY(1) 24 50 -2.4 1 D4 14 12 DX * * 2nd GAIN STAGE & DOMINANT POLE AT 0.29 HZ * G2 98 15 12 24 33.333E-6 R8 15 98 274.41E6 C3 15 98 2E-9 V1 99 16 DC 1.275 D5 15 16 DX V2 17 50 DC 1.275 D6 17 15 DX * * COMMON-MODE GAIN NETWORK WITH ZERO AT 561.01 HZ * ECM 18 98 3 24 1.9953 RCM1 18 19 1E6 CCM 18 19 283.69E-12 RCM2 19 98 1 * * NEGATIVE ZERO AT 1.8 MHz * ENZ 20 98 15 24 1E6 RNZ1 20 21 1E6 CNZ 20 21 -88.419E-15 RNZ2 21 98 1 * * POLE AT 6 MHZ * G3 98 22 21 24 1E-6 R9 22 98 1E6 C4 22 98 26.526E-15 * * POLE AT 1.8 MHZ * G4 98 23 22 24 1E-6 R15 23 98 1E6 C8 23 98 88.419E-15 * * OUTPUT STAGE * R16 24 99 160K R17 24 50 160K ISY 99 50 431E-6 D7 23 28 DX V3 28 27 DC 1.9 D8 29 23 DX V4 27 29 DC 1.9 D9 99 30 DX G5 30 50 23 27 5E-3 D11 50 30 DY D10 99 31 DX G6 31 50 27 23 5E-3 D12 50 31 DY G7 27 99 99 23 5E-3 R18 27 99 200 G8 50 27 23 50 5E-3 R19 27 50 200 L1 27 32 0.1E-6 * * MODELS USED * .MODEL QX NPN(BF=333.333E3) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP497G SPICE Macro-model 4/91, Rev. B * AAG / PMI * * This version of the OP-497 model simulates the worst case * parameters of the 'G' grade. The worst case parameters * used correspond to those in the data sheet. * * Copyright 1991 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP497G 1 2 99 50 32 * * INPUT STAGE & POLE AT 6 MHZ * RIN1 1 7 2500 RIN2 2 8 2500 R1 8 3 1.293E8 R2 7 3 1.293E8 R3 5 99 517.2 R4 6 99 517.2 CIN 7 8 3E-12 C2 5 6 25.644E-12 I1 4 50 0.1E-3 IOS 7 8 100E-12 EOS 9 7 POLY(1) 19 24 150E-6 1 Q1 5 8 4 QX Q2 6 9 4 QX D1 8 9 DX D2 9 8 DX * EREF 98 0 24 0 1 * * 1st GAIN STAGE * G1 98 12 5 6 167.39E-6 R7 12 98 1E6 E1 99 13 POLY(1) 99 24 -2.4 1 D3 12 13 DX E2 14 50 POLY(1) 24 50 -2.4 1 D4 14 12 DX * * 2nd GAIN STAGE & DOMINANT POLE AT 0.37 HZ * G2 98 15 12 24 33.333E-6 R8 15 98 215.07E6 C3 15 98 2E-9 V1 99 16 DC 1.275 D5 15 16 DX V2 17 50 DC 1.275 D6 17 15 DX * * COMMON-MODE GAIN NETWORK WITH ZERO AT 561.01 HZ * ECM 18 98 3 24 1.9953 RCM1 18 19 1E6 CCM 18 19 283.69E-12 RCM2 19 98 1 * * NEGATIVE ZERO AT 1.8 MHz * ENZ 20 98 15 24 1E6 RNZ1 20 21 1E6 CNZ 20 21 -88.419E-15 RNZ2 21 98 1 * * POLE AT 6 MHZ * G3 98 22 21 24 1E-6 R9 22 98 1E6 C4 22 98 26.526E-15 * * POLE AT 1.8 MHZ * G4 98 23 22 24 1E-6 R15 23 98 1E6 C8 23 98 88.419E-15 * * OUTPUT STAGE * R16 24 99 160K R17 24 50 160K ISY 99 50 431E-6 D7 23 28 DX V3 28 27 DC 1.9 D8 29 23 DX V4 27 29 DC 1.9 D9 99 30 DX G5 30 50 23 27 5E-3 D11 50 30 DY D10 99 31 DX G6 31 50 27 23 5E-3 D12 50 31 DY G7 27 99 99 23 5E-3 R18 27 99 200 G8 50 27 23 50 5E-3 R19 27 50 200 L1 27 32 0.1E-6 * * MODELS USED * .MODEL QX NPN(BF=250E3) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP61 SPICE Macro-model 12/90, Rev. B * ARG / PMI * * Revision History: * REV. B * Re-ordered subcircuit call out nodes to put the * output node last. * Changed Ios from 2E-7 to 1E-7 * * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP61 1 2 99 50 38 * * INPUT STAGE & POLE AT 300 MHZ * R1 2 3 5E11 R2 1 3 5E11 R3 5 99 51.6 R4 6 99 51.6 CIN 1 2 5E-12 C2 5 6 5.141E-12 I1 4 50 1E-3 IOS 1 2 1E-7 EOS 9 1 POLY(1) 26 32 400E-6 1 Q1 5 2 4 QX Q2 6 9 4 QX * * FIRST GAIN STAGE * R7 11 99 1E6 R8 11 50 1E6 D11 11 10 DX D12 12 11 DX G1 99 11 5 6 2E-4 G2 11 50 6 5 2E-4 E1 99 10 POLY(1) 99 32 -4.4 1 E2 12 50 POLY(1) 32 50 -4.4 1 * * SECOND GAIN STAGE & POLE AT 2.5 KHZ * R9 13 99 5.1598E6 R10 13 50 5.1598E6 C3 13 99 12.338E-12 C4 13 50 12.338E-12 G3 99 13 POLY(1) 11 32 4.24E-3 9.69E-5 G4 13 50 POLY(1) 32 11 4.24E-3 9.69E-5 V2 99 14 2.3 V3 15 50 2.3 D1 13 14 DX D2 15 13 DX * * POLE-ZERO PAIR AT 4 MHZ / 8 MHZ * R11 16 99 1E6 R12 16 50 1E6 R13 16 17 1E6 R14 16 18 1E6 C5 17 99 19.89E-15 C6 18 50 19.89E-15 G5 99 16 13 32 1E-6 G6 16 50 32 13 1E-6 * * ZERO-POLE PAIR AT 85 MHZ / 300 MHZ * R17 19 20 1E6 R18 19 21 1E6 R19 20 99 2.529E6 R20 21 50 2.529E6 L3 20 99 1.342E-3 L4 21 50 1.342E-3 G7 99 19 16 32 1E-6 G8 19 50 32 16 1E-6 * * POLE AT 40 MHZ * R21 22 99 1E6 R22 22 50 1E6 C7 22 99 3.979E-15 C8 22 50 3.979E-15 G9 99 22 19 32 1E-6 G10 22 50 32 19 1E-6 * * POLE AT 200 MHZ * R23 23 99 1E6 R24 23 50 1E6 C9 23 99 .796E-15 C10 23 50 .796E-15 G11 99 23 22 32 1E-6 G12 23 50 32 22 1E-6 * * POLE AT 200 MHZ * R25 24 99 1E6 R26 24 50 1E6 C11 24 99 .796E-15 C12 24 50 .796E-15 G13 99 24 23 32 1E-6 G14 24 50 32 23 1E-6 * * POLE AT 200 MHZ * R27 25 99 1E6 R28 25 50 1E6 C13 25 99 .796E-15 C14 25 50 .796E-15 G15 99 25 24 32 1E-6 G16 25 99 32 24 1E-6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 40 KHZ * R29 26 27 1E6 R30 26 28 1E6 L5 27 99 3.979 L6 28 50 3.979 G17 99 26 3 32 1E-11 G18 26 50 32 3 1E-11 * * POLE AT 300 MHZ * R32 31 99 1E6 R33 31 50 1E6 C15 31 99 .531E-15 C16 31 50 .531E-15 G19 99 31 25 32 1E-6 G20 31 50 32 25 1E-6 * * OUTPUT STAGE * R34 32 99 20.0E3 R35 32 50 20.0E3 R36 33 99 30 R37 33 50 30 L7 33 38 1.65E-7 G21 36 50 31 33 33.3333333E-3 G22 37 50 33 31 33.3333333E-3 G23 33 99 99 31 33.3333333E-3 G24 50 33 31 50 33.3333333E-3 V6 34 33 .2 V7 33 35 .2 D5 31 34 DX D6 35 31 DX D7 99 36 DX D8 99 37 DX D9 50 36 DY D10 50 37 DY * * MODELS USED * .MODEL QX NPN(BF=1250) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP64 SPICE Macro-model 12/90, Rev. C * JCB / PMI * * Revision History: * REV. C * Re-ordered subcircuit call out nodes to put the * output node last. * Changed Ios from 1E-7 to 0.5E-7 * * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP64 1 2 99 50 38 * * INPUT STAGE & POLE AT 39.8 MHZ * R1 2 3 5E11 R2 1 3 5E11 R3 5 99 474.86 R4 6 99 474.86 R5 4 7 423.26 R6 4 8 423.26 CIN 1 2 1E-15 C2 5 6 4.2106E-12 I1 4 50 1E-3 IOS 1 2 0.5E-7 EOS 9 1 POLY(1) 26 32 4E-4 1 Q1 5 2 7 QX Q2 6 9 8 QX * * SECOND STAGE & POLE AT 3.8 KHZ * R7 11 99 7.1229E6 R8 11 50 7.1229E6 C3 11 99 5.88E-12 C4 11 50 5.88E-12 G1 99 11 POLY(1) 5 6 4.31E-3 2.1059E-3 G2 11 50 POLY(1) 6 5 4.31E-3 2.1059E-3 V2 99 10 2.25 V3 12 50 2.25 D1 11 10 DX D2 12 11 DX * * POLE AT 39.8 MHZ * R9 13 99 1E6 R10 13 50 1E6 C5 13 99 4E-15 C6 13 50 4E-15 G3 99 13 11 32 1E-6 G4 13 50 32 11 1E-6 * * ZERO-POLE PAIR AT 26.5 MHZ / 159 MHZ * R13 16 17 1E6 R14 16 18 1E6 R15 17 99 5E6 R16 18 50 5E6 L1 17 99 5.005E-3 L2 18 50 5.005E-3 G5 99 16 13 32 1E-6 G6 16 50 32 13 1E-6 * * ZERO-POLE PAIR AT 31.8 MHZ / 39.8 MHZ * R17 19 20 1E6 R18 19 21 1E6 R19 20 99 2.5157E5 R20 21 50 2.5157E5 L3 20 99 1.006E-3 L4 21 50 1.006E-3 G7 99 19 16 32 1E-6 G8 19 50 32 16 1E-6 * * POLE AT 100 MHZ * R21 22 99 1E6 R22 22 50 1E6 C7 22 99 1.59E-15 C8 22 50 1.59E-15 G9 99 22 19 32 1E-6 G10 22 50 32 19 1E-6 * * POLE AT 159 MHZ * R23 23 99 1E6 R24 23 50 1E6 C9 23 99 1E-15 C10 23 50 1E-15 G11 99 23 22 32 1E-6 G12 23 50 32 22 1E-6 * * POLE AT 159 MHZ * R25 24 99 1E6 R26 24 50 1E6 C11 24 99 1E-15 C12 24 50 1E-15 G13 99 24 23 32 1E-6 G14 24 50 32 23 1E-6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 20 KHZ * R29 26 27 1E6 R30 26 28 1E6 L5 27 99 7.9575 L6 28 50 7.9575 G17 99 26 3 32 1E-11 G18 26 50 32 3 1E-11 * * POLE AT 159 MHZ * R32 31 99 1E6 R33 31 50 1E6 C15 31 99 1E-15 C16 31 50 1E-15 G19 99 31 24 32 1E-6 G20 31 50 32 24 1E-6 * * OUTPUT STAGE * R34 32 99 20.0E3 R35 32 50 20.0E3 R36 33 99 60 R37 33 50 60 L7 33 38 2.9E-7 G21 36 50 31 33 16.6666667E-3 G22 37 50 33 31 16.6666667E-3 G23 33 99 99 31 16.6666667E-3 G24 50 33 31 50 16.6666667E-3 V6 34 33 1.7 V7 33 35 1.7 D5 31 34 DX D6 35 31 DX D7 99 36 DX D8 99 37 DX D9 50 36 DY D10 50 37 DY * * MODELS USED * .MODEL QX NPN(BF=5000) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP77 SPICE Macro-model 12/90, Rev. B * JCB / PMI * * Revision History: * REV. B * Re-ordered subcircuit call out nodes to put the * output node last. * Changed Ios from 0.3E-9 to 0.15E-9 * Added F1 and F2 to fix short circuit current limit. * * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP77 1 2 99 50 39 * * INPUT STAGE & POLE AT 6 MHZ * R1 2 3 5E11 R2 1 3 5E11 R3 5 97 0.0606 R4 6 97 0.0606 CIN 1 2 4E-12 C2 5 6 218.9E-9 I1 4 51 1 IOS 1 2 0.15E-9 EOS 9 10 POLY(1) 30 33 10E-6 1 Q1 5 2 7 QX Q2 6 9 8 QX R5 7 4 0.009 R6 8 4 0.009 D1 2 1 DX D2 1 2 DX EN 10 1 12 0 1 GN1 0 2 15 0 1 GN2 0 1 18 0 1 * EREF 98 0 33 0 1 EPLUS 97 0 99 0 1 ENEG 51 0 50 0 1 * * VOLTAGE NOISE SOURCE WITH FLICKER NOISE * DN1 11 12 DEN DN2 12 13 DEN VN1 11 0 DC 2 VN2 0 13 DC 2 * * CURRENT NOISE SOURCE WITH FLICKER NOISE * DN3 14 15 DIN DN4 15 16 DIN VN3 14 0 DC 2 VN4 0 16 DC 2 * * SECOND CURRENT NOISE SOURCE * DN5 17 18 DIN DN6 18 19 DIN VN5 17 0 DC 2 VN6 0 19 DC 2 * * FIRST GAIN STAGE * R7 20 98 1 G1 98 20 5 6 59.91 D3 20 21 DX D4 22 20 DX E1 97 21 POLY(1) 97 33 -2.4 1 E2 22 51 POLY(1) 33 51 -2.4 1 * * GAIN STAGE & DOMINANT POLE AT 0.053 HZ * R8 23 98 6.01E9 C3 23 98 500E-12 G2 98 23 20 33 33.3E-6 V1 97 24 1.3 V2 25 51 1.3 D5 23 24 DX D6 25 23 DX * * NEGATIVE ZERO AT -4MHZ * R9 26 27 1 C4 26 27 -39.75E-9 R10 27 98 1E-6 E3 26 98 23 33 1E6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 20 HZ * R13 30 31 1 L2 31 98 7.96E-3 G4 98 30 3 33 1.0E-7 D7 30 97 DX D8 51 30 DX * * POLE AT 2 MHZ * R14 32 98 1 C5 32 98 79.5E-9 G5 98 32 27 33 1 * * OUTPUT STAGE * R15 33 97 1 R16 33 51 1 GSY 99 50 POLY(1) 99 50 0.325E-3 0.0425E-3 F1 34 0 V3 1 F2 0 34 V4 1 R17 34 99 400 R18 34 50 400 L3 34 39 2E-7 G6 37 50 32 34 2.5E-3 G7 38 50 34 32 2.5E-3 G8 34 99 99 32 2.5E-3 G9 50 34 32 50 2.5E-3 V3 35 34 6.8 V4 34 36 4.4 D9 32 35 DX D10 36 32 DX D11 99 37 DX D12 99 38 DX D13 50 37 DY D14 50 38 DY * * MODELS USED * .MODEL QX NPN(BF=417E6) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .MODEL DEN D(IS=1E-12, RS=12.08K, KF=1E-17, AF=1) .MODEL DIN D(IS=1E-12, RS=7.55E-6, KF=1.55E-15, AF=1) .ENDS * OP77A SPICE Macro-model 12/90, Rev. B * JCB / PMI * * Revision History: * REV. B * Re-ordered subcircuit call out nodes to put the * output node last. * Changed Ios from 1.5E-9 to 0.75E-9 * Added F1 and F2 to fix short circuit current limit. * * * This version of the OP-77 model simulates the worst case * parameters of the 'A' grade. The worst case parameters * used correspond to those in the data book. * * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP77A 1 2 99 50 39 * * INPUT STAGE & POLE AT 6 MHZ * R1 2 3 5E11 R2 1 3 5E11 R3 5 97 0.0606 R4 6 97 0.0606 CIN 1 2 4E-12 C2 5 6 218.9E-9 I1 4 51 1 IOS 1 2 0.75E-9 EOS 9 10 POLY(1) 30 33 25E-6 1 Q1 5 2 7 QX Q2 6 9 8 QX R5 7 4 0.009 R6 8 4 0.009 D1 2 1 DX D2 1 2 DX EN 10 1 12 0 1 GN1 0 2 15 0 1 GN2 0 1 18 0 1 * EREF 98 0 33 0 1 EPLUS 97 0 99 0 1 ENEG 51 0 50 0 1 * * VOLTAGE NOISE SOURCE WITH FLICKER NOISE * DN1 11 12 DEN DN2 12 13 DEN VN1 11 0 DC 2 VN2 0 13 DC 2 * * CURRENT NOISE SOURCE WITH FLICKER NOISE * DN3 14 15 DIN DN4 15 16 DIN VN3 14 0 DC 2 VN4 0 16 DC 2 * * SECOND CURRENT NOISE SOURCE * DN5 17 18 DIN DN6 18 19 DIN VN5 17 0 DC 2 VN6 0 19 DC 2 * * FIRST GAIN STAGE * R7 20 98 1 G1 98 20 5 6 119.8 D3 20 21 DX D4 22 20 DX E1 97 21 POLY(1) 97 33 -2.4 1 E2 22 51 POLY(1) 33 51 -2.4 1 * * GAIN STAGE & DOMINANT POLE AT 0.127 HZ * R8 23 98 1.253E9 C3 23 98 1E-9 G2 98 23 20 33 33.3E-6 V1 97 24 1.8 V2 25 51 1.8 D5 23 24 DX D6 25 23 DX * * NEGATIVE ZERO AT -4MHZ * R9 26 27 1 C4 26 27 -39.75E-9 R10 27 98 1E-6 E3 26 98 23 33 1E6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 200 HZ * R13 30 31 1 L2 31 98 0.796E-3 G4 98 30 3 33 1.0E-6 D7 30 97 DX D8 51 30 DX * * POLE AT 2 MHZ * R14 32 98 1 C5 32 98 79.5E-9 G5 98 32 27 33 1 * * OUTPUT STAGE * R15 33 97 1 R16 33 51 1 GSY 99 50 POLY(1) 99 50 0.725E-3 0.0425E-3 F1 34 0 V3 1 F2 0 34 V4 1 R17 34 99 400 R18 34 50 400 L3 34 39 2E-7 G6 37 50 32 34 2.5E-3 G7 38 50 34 32 2.5E-3 G8 34 99 99 32 2.5E-3 G9 50 34 32 50 2.5E-3 V3 35 34 6.8 V4 34 36 4.4 D9 32 35 DX D10 36 32 DX D11 99 37 DX D12 99 38 DX D13 50 37 DY D14 50 38 DY * * MODELS USED * .MODEL QX NPN(BF=250E6) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .MODEL DEN D(IS=1E-12, RS=14.61K, KF=2E-17, AF=1) .MODEL DIN D(IS=1E-12, RS=7.55E-6, KF=3E-15, AF=1) .ENDS * OP77B SPICE Macro-model 12/90, Rev. B * JCB / PMI * * Revision History: * REV. B * Re-ordered subcircuit call out nodes to put the * output node last. * Changed Ios from 2.8E-9 to 1.4E-9 * Added F1 and F2 to fix short circuit current limit. * * * This version of the OP-77 model simulates the worst case * parameters of the 'B' grade. The worst case parameters * used correspond to those in the data book. * * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP77B 1 2 99 50 39 * * INPUT STAGE & POLE AT 6 MHZ * R1 2 3 5E11 R2 1 3 5E11 R3 5 97 0.0606 R4 6 97 0.0606 CIN 1 2 4E-12 C2 5 6 218.9E-9 I1 4 51 1 IOS 1 2 1.4E-9 EOS 9 10 POLY(1) 30 33 60E-6 1 Q1 5 2 7 QX Q2 6 9 8 QX R5 7 4 0.009 R6 8 4 0.009 D1 2 1 DX D2 1 2 DX EN 10 1 12 0 1 GN1 0 2 15 0 1 GN2 0 1 18 0 1 * EREF 98 0 33 0 1 EPLUS 97 0 99 0 1 ENEG 51 0 50 0 1 * * VOLTAGE NOISE SOURCE WITH FLICKER NOISE * DN1 11 12 DEN DN2 12 13 DEN VN1 11 0 DC 2 VN2 0 13 DC 2 * * CURRENT NOISE SOURCE WITH FLICKER NOISE * DN3 14 15 DIN DN4 15 16 DIN VN3 14 0 DC 2 VN4 0 16 DC 2 * * SECOND CURRENT NOISE SOURCE * DN5 17 18 DIN DN6 18 19 DIN VN5 17 0 DC 2 VN6 0 19 DC 2 * * FIRST GAIN STAGE * R7 20 98 1 G1 98 20 5 6 119.8 D3 20 21 DX D4 22 20 DX E1 97 21 POLY(1) 97 33 -2.4 1 E2 22 51 POLY(1) 33 51 -2.4 1 * * GAIN STAGE & DOMINANT POLE AT 0.318 HZ * R8 23 98 501.3E6 C3 23 98 1E-9 G2 98 23 20 33 33.3E-6 V1 97 24 1.8 V2 25 51 1.8 D5 23 24 DX D6 25 23 DX * * NEGATIVE ZERO AT -4MHZ * R9 26 27 1 C4 26 27 -39.75E-9 R10 27 98 1E-6 E3 26 98 23 33 1E6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 320 HZ * R13 30 31 1 L2 31 98 0.498E-3 G4 98 30 3 33 1.6E-6 D7 30 97 DX D8 51 30 DX * * POLE AT 2 MHZ * R14 32 98 1 C5 32 98 79.5E-9 G5 98 32 27 33 1 * * OUTPUT STAGE * R15 33 97 1 R16 33 51 1 GSY 99 50 POLY(1) 99 50 0.725E-3 0.0425E-3 F1 34 0 V3 1 F2 0 34 V4 1 R17 34 99 400 R18 34 50 400 L3 34 39 2E-7 G6 37 50 32 34 2.5E-3 G7 38 50 34 32 2.5E-3 G8 34 99 99 32 2.5E-3 G9 50 34 32 50 2.5E-3 V3 35 34 6.8 V4 34 36 4.4 D9 32 35 DX D10 36 32 DX D11 99 37 DX D12 99 38 DX D13 50 37 DY D14 50 38 DY * * MODELS USED * .MODEL QX NPN(BF=178.6E6) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .MODEL DEN D(IS=1E-12, RS=14.61K, KF=2E-17, AF=1) .MODEL DIN D(IS=1E-12, RS=7.55E-6, KF=3E-15, AF=1) .ENDS * OP77E SPICE Macro-model 12/90, Rev. B * JCB / PMI * * Revision History: * REV. B * Re-ordered subcircuit call out nodes to put the * output node last. * Changed Ios from 1.5E-9 to 0.75E-9 * Added F1 and F2 to fix short circuit current limit. * * * This version of the OP-77 model simulates the worst case * parameters of the 'E' grade. The worst case parameters * used correspond to those in the data book. * * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP77E 1 2 99 50 39 * * INPUT STAGE & POLE AT 6 MHZ * R1 2 3 5E11 R2 1 3 5E11 R3 5 97 0.0606 R4 6 97 0.0606 CIN 1 2 4E-12 C2 5 6 218.9E-9 I1 4 51 1 IOS 1 2 0.75E-9 EOS 9 10 POLY(1) 30 33 25E-6 1 Q1 5 2 7 QX Q2 6 9 8 QX R5 7 4 0.009 R6 8 4 0.009 D1 2 1 DX D2 1 2 DX EN 10 1 12 0 1 GN1 0 2 15 0 1 GN2 0 1 18 0 1 * EREF 98 0 33 0 1 EPLUS 97 0 99 0 1 ENEG 51 0 50 0 1 * * VOLTAGE NOISE SOURCE WITH FLICKER NOISE * DN1 11 12 DEN DN2 12 13 DEN VN1 11 0 DC 2 VN2 0 13 DC 2 * * CURRENT NOISE SOURCE WITH FLICKER NOISE * DN3 14 15 DIN DN4 15 16 DIN VN3 14 0 DC 2 VN4 0 16 DC 2 * * SECOND CURRENT NOISE SOURCE * DN5 17 18 DIN DN6 18 19 DIN VN5 17 0 DC 2 VN6 0 19 DC 2 * * FIRST GAIN STAGE * R7 20 98 1 G1 98 20 5 6 119.8 D3 20 21 DX D4 22 20 DX E1 97 21 POLY(1) 97 33 -2.4 1 E2 22 51 POLY(1) 33 51 -2.4 1 * * GAIN STAGE & DOMINANT POLE AT 0.127 HZ * R8 23 98 1.253E9 C3 23 98 1E-9 G2 98 23 20 33 33.3E-6 V1 97 24 1.8 V2 25 51 1.8 D5 23 24 DX D6 25 23 DX * * NEGATIVE ZERO AT -4MHZ * R9 26 27 1 C4 26 27 -39.75E-9 R10 27 98 1E-6 E3 26 98 23 33 1E6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 200 HZ * R13 30 31 1 L2 31 98 0.796E-3 G4 98 30 3 33 1.0E-6 D7 30 97 DX D8 51 30 DX * * POLE AT 2 MHZ * R14 32 98 1 C5 32 98 79.5E-9 G5 98 32 27 33 1 * * OUTPUT STAGE * R15 33 97 1 R16 33 51 1 GSY 99 50 POLY(1) 99 50 0.725E-3 0.0425E-3 F1 34 0 V3 1 F2 0 34 V4 1 R17 34 99 400 R18 34 50 400 L3 34 39 2E-7 G6 37 50 32 34 2.5E-3 G7 38 50 34 32 2.5E-3 G8 34 99 99 32 2.5E-3 G9 50 34 32 50 2.5E-3 V3 35 34 6.8 V4 34 36 4.4 D9 32 35 DX D10 36 32 DX D11 99 37 DX D12 99 38 DX D13 50 37 DY D14 50 38 DY * * MODELS USED * .MODEL QX NPN(BF=250E6) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .MODEL DEN D(IS=1E-12, RS=14.61K, KF=2E-17, AF=1) .MODEL DIN D(IS=1E-12, RS=7.55E-6, KF=3E-15, AF=1) .ENDS * OP77F SPICE Macro-model 12/90, Rev. B * JCB / PMI * * Revision History: * REV. B * Re-ordered subcircuit call out nodes to put the * output node last. * Changed Ios from 2.8E-9 to 1.4E-9 * Added F1 and F2 to fix short circuit current limit. * * * This version of the OP-77 model simulates the worst case * parameters of the 'F' grade. The worst case parameters * used correspond to those in the data book. * * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP77F 1 2 99 50 39 * * INPUT STAGE & POLE AT 6 MHZ * R1 2 3 5E11 R2 1 3 5E11 R3 5 97 0.0606 R4 6 97 0.0606 CIN 1 2 4E-12 C2 5 6 218.9E-9 I1 4 51 1 IOS 1 2 1.4E-9 EOS 9 10 POLY(1) 30 33 60E-6 1 Q1 5 2 7 QX Q2 6 9 8 QX R5 7 4 0.009 R6 8 4 0.009 D1 2 1 DX D2 1 2 DX EN 10 1 12 0 1 GN1 0 2 15 0 1 GN2 0 1 18 0 1 * EREF 98 0 33 0 1 EPLUS 97 0 99 0 1 ENEG 51 0 50 0 1 * * VOLTAGE NOISE SOURCE WITH FLICKER NOISE * DN1 11 12 DEN DN2 12 13 DEN VN1 11 0 DC 2 VN2 0 13 DC 2 * * CURRENT NOISE SOURCE WITH FLICKER NOISE * DN3 14 15 DIN DN4 15 16 DIN VN3 14 0 DC 2 VN4 0 16 DC 2 * * SECOND CURRENT NOISE SOURCE * DN5 17 18 DIN DN6 18 19 DIN VN5 17 0 DC 2 VN6 0 19 DC 2 * * FIRST GAIN STAGE * R7 20 98 1 G1 98 20 5 6 119.8 D3 20 21 DX D4 22 20 DX E1 97 21 POLY(1) 97 33 -2.4 1 E2 22 51 POLY(1) 33 51 -2.4 1 * * GAIN STAGE & DOMINANT POLE AT 0.318 HZ * R8 23 98 501.3E6 C3 23 98 1E-9 G2 98 23 20 33 33.3E-6 V1 97 24 1.8 V2 25 51 1.8 D5 23 24 DX D6 25 23 DX * * NEGATIVE ZERO AT -4MHZ * R9 26 27 1 C4 26 27 -39.75E-9 R10 27 98 1E-6 E3 26 98 23 33 1E6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 320 HZ * R13 30 31 1 L2 31 98 0.498E-3 G4 98 30 3 33 1.6E-6 D7 30 97 DX D8 51 30 DX * * POLE AT 2 MHZ * R14 32 98 1 C5 32 98 79.5E-9 G5 98 32 27 33 1 * * OUTPUT STAGE * R15 33 97 1 R16 33 51 1 GSY 99 50 POLY(1) 99 50 0.725E-3 0.0425E-3 F1 34 0 V3 1 F2 0 34 V4 1 R17 34 99 400 R18 34 50 400 L3 34 39 2E-7 G6 37 50 32 34 2.5E-3 G7 38 50 34 32 2.5E-3 G8 34 99 99 32 2.5E-3 G9 50 34 32 50 2.5E-3 V3 35 34 6.8 V4 34 36 4.4 D9 32 35 DX D10 36 32 DX D11 99 37 DX D12 99 38 DX D13 50 37 DY D14 50 38 DY * * MODELS USED * .MODEL QX NPN(BF=178.6E6) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .MODEL DEN D(IS=1E-12, RS=14.61K, KF=2E-17, AF=1) .MODEL DIN D(IS=1E-12, RS=7.55E-6, KF=3E-15, AF=1) .ENDS * OP77G SPICE Macro-model 12/90, Rev. B * JCB / PMI * * Revision History: * REV. B * Re-ordered subcircuit call out nodes to put the * output node last. * Changed Ios from 2.8E-9 to 1.4E-9 * Added F1 and F2 to fix short circuit current limit. * * * This version of the OP-77 model simulates the worst case * parameters of the 'G' grades. The worst case parameters * used correspond to those in the data book. * * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP77G 1 2 99 50 39 * * INPUT STAGE & POLE AT 6 MHZ * R1 2 3 5E11 R2 1 3 5E11 R3 5 97 0.0606 R4 6 97 0.0606 CIN 1 2 4E-12 C2 5 6 218.9E-9 I1 4 51 1 IOS 1 2 1.4E-9 EOS 9 10 POLY(1) 30 33 100E-6 1 Q1 5 2 7 QX Q2 6 9 8 QX R5 7 4 0.009 R6 8 4 0.009 D1 2 1 DX D2 1 2 DX EN 10 1 12 0 1 GN1 0 2 15 0 1 GN2 0 1 18 0 1 * EREF 98 0 33 0 1 EPLUS 97 0 99 0 1 ENEG 51 0 50 0 1 * * VOLTAGE NOISE SOURCE WITH FLICKER NOISE * DN1 11 12 DEN DN2 12 13 DEN VN1 11 0 DC 2 VN2 0 13 DC 2 * * CURRENT NOISE SOURCE WITH FLICKER NOISE * DN3 14 15 DIN DN4 15 16 DIN VN3 14 0 DC 2 VN4 0 16 DC 2 * * SECOND CURRENT NOISE SOURCE * DN5 17 18 DIN DN6 18 19 DIN VN5 17 0 DC 2 VN6 0 19 DC 2 * * FIRST GAIN STAGE * R7 20 98 1 G1 98 20 5 6 119.8 D3 20 21 DX D4 22 20 DX E1 97 21 POLY(1) 97 33 -2.4 1 E2 22 51 POLY(1) 33 51 -2.4 1 * * GAIN STAGE & DOMINANT POLE AT 0.318 HZ * R8 23 98 501.3E6 C3 23 98 1E-9 G2 98 23 20 33 33.3E-6 V1 97 24 1.8 V2 25 51 1.8 D5 23 24 DX D6 25 23 DX * * NEGATIVE ZERO AT -4MHZ * R9 26 27 1 C4 26 27 -39.75E-9 R10 27 98 1E-6 E3 26 98 23 33 1E6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 320 HZ * R13 30 31 1 L2 31 98 0.498E-3 G4 98 30 3 33 1.6E-6 D7 30 97 DX D8 51 30 DX * * POLE AT 2 MHZ * R14 32 98 1 C5 32 98 79.5E-9 G5 98 32 27 33 1 * * OUTPUT STAGE * R15 33 97 1 R16 33 51 1 GSY 99 50 POLY(1) 99 50 0.725E-3 0.0425E-3 F1 34 0 V3 1 F2 0 34 V4 1 R17 34 99 400 R18 34 50 400 L3 34 39 2E-7 G6 37 50 32 34 2.5E-3 G7 38 50 34 32 2.5E-3 G8 34 99 99 32 2.5E-3 G9 50 34 32 50 2.5E-3 V3 35 34 6.8 V4 34 36 4.4 D9 32 35 DX D10 36 32 DX D11 99 37 DX D12 99 38 DX D13 50 37 DY D14 50 38 DY * * MODELS USED * .MODEL QX NPN(BF=178.6E6) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .MODEL DEN D(IS=1E-12, RS=14.61K, KF=2E-17, AF=1) .MODEL DIN D(IS=1E-12, RS=7.55E-6, KF=3E-15, AF=1) .ENDS * OP80B SPICE Macro-model 9/93, Rev. A * ARG / PMI * * This version of the OP-80 model simulates the worst-case * parameters of the 'B' grade. The worst-case parameters * used correspond to those in the data sheet. * * Copyright 1993 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of * this model indicates your acceptance of the terms and pro- * visions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP80B 1 2 99 50 45 * * INPUT STAGE AND POLE AT 500KHZ * I1 99 4 50E-6 M1 5 2 4 99 PNOM L=15U W=1500U M2 6 3 4 99 PNOM L=15U W=1500U EOS 3 1 POLY(1) (13,39) 2E-3 3.162E3 R1 5 50 1.563E3 R2 6 50 1.563E3 IB1 1 50 1.95E-12 IB2 2 50 2.05E-12 CIN 1 2 2E-12 C1 5 6 101.845E-12 * * GAIN STAGE AND DOMINANT POLE AT 4.074HZ * EREF 98 0 39 0 1 C2 9 98 250E-12 R7 9 98 156.272E6 G1 98 9 5 6 639.911E-6 D1 9 10 DX D2 11 9 DX V1 99 10 2.08 V2 11 50 0 * * COMMON MODE STAGE WITH ZERO AT 100KHZ * ECM 12 98 POLY(2) (1,39) (2,39) 0 0.5 0.5 R9 12 13 1E6 R10 13 98 1 C3 12 13 1.592E-12 * * POLE AT 100KHZ * G2 98 14 9 39 1E-6 R11 14 98 1E6 C4 14 98 1.592E-12 * * ZERO AT 185KHZ * E1 15 98 14 39 1E6 R12 15 16 1E6 R13 16 98 1 C5 15 16 .860E-12 * * OUTPUT STAGE * G3 98 40 16 39 1E-6 R14 40 98 1E6 RS1 99 39 56.818E3 RS2 39 50 56.818E3 R15 99 45 50 R16 45 50 50 G7 45 99 99 40 20E-3 G8 50 45 40 50 20E-3 G9 98 60 45 40 20E-3 D7 60 61 DX D8 62 60 DX V7 61 98 DC 0 V8 98 62 DC 0 FSY 99 50 POLY(2) V7 V8 187E-6 1 1 D9 41 45 DX D10 45 42 DX V5 40 41 .125 V6 42 40 -.125 .MODEL DX D() .MODEL PNOM PMOS(VTO=-0.9 KP=81.897U) .ENDS *jg, 22/5/2000: corrected syntax model* OP80E SPICE Macro-model 9/93, Rev. A * ARG / PMI * * This version of the OP-80 model simulates the worst-case * parameters of the 'E' grade. The worst-case parameters * used correspond to those in the data sheet. * * Copyright 1993 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of * this model indicates your acceptance of the terms and pro- * visions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP80E 1 2 99 50 45 * * INPUT STAGE AND POLE AT 500KHZ * I1 99 4 50E-6 M1 5 2 4 99 PNOM L=15U W=1500U M2 6 3 4 99 PNOM L=15U W=1500U EOS 3 1 POLY(1) (13,39) 1.5E-3 3.162E3 R1 5 50 1.563E3 R2 6 50 1.563E3 IB1 1 50 225E-15 IB2 2 50 275E-15 CIN 1 2 2E-12 C1 5 6 101.845E-12 * * GAIN STAGE AND DOMINANT POLE AT 4.1HZ * EREF 98 0 39 0 1 C2 9 98 250E-12 R7 9 98 156.272E6 G1 98 9 5 6 639.911E-6 D1 9 10 DX D2 11 9 DX V1 99 10 2.08 V2 11 50 0 * * COMMON MODE STAGE WITH ZERO AT 100KHZ * ECM 12 98 POLY(2) (1,39) (2,39) 0 0.5 0.5 R9 12 13 1E6 R10 13 98 1 C3 12 13 1.592E-12 * * POLE AT 100KHZ * G2 98 14 9 39 1E-6 R11 14 98 1E6 C4 14 98 1.592E-12 * * ZERO AT 185KHZ * E1 15 98 14 39 1E6 R12 15 16 1E6 R13 16 98 1 C5 15 16 .860E-12 * * OUTPUT STAGE * G3 98 40 16 39 1E-6 R14 40 98 1E6 RS1 99 39 56.818E3 RS2 39 50 56.818E3 R15 99 45 50 R16 45 50 50 G7 45 99 99 40 20E-3 G8 50 45 40 50 20E-3 G9 98 60 45 40 20E-3 D7 60 61 DX D8 62 60 DX V7 61 98 DC 0 V8 98 62 DC 0 FSY 99 50 POLY(2) V7 V8 187E-6 1 1 D9 41 45 DX D10 45 42 DX V5 40 41 .125 V6 42 40 -.125 .MODEL DX D() .MODEL PNOM PMOS(VTO=-0.9 KP=81.897U) .ENDS *jg, 22/5/2000: corrected syntax model* OP80F SPICE Macro-model 9/93, Rev. A * ARG / PMI * * This version of the OP-80 model simulates the worst-case * parameters of the 'F' grade. The worst-case parameters * used correspond to those in the data sheet. * * Copyright 1993 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of * this model indicates your acceptance of the terms and pro- * visions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP80F 1 2 99 50 45 * * INPUT STAGE AND POLE AT 500KHZ * I1 99 4 50E-6 M1 5 2 4 99 PNOM L=15U W=1500U M2 6 3 4 99 PNOM L=15U W=1500U EOS 3 1 POLY(1) (13,39) 1.5E-3 3.162E3 R1 5 50 1.563E3 R2 6 50 1.563E3 IB1 1 50 1.04E-12 IB2 2 50 .96E-12 CIN 1 2 2E-12 C1 5 6 101.845E-12 * * GAIN STAGE AND DOMINANT POLE AT 4.074HZ * EREF 98 0 39 0 1 C2 9 98 250E-12 R7 9 98 156.272E6 G1 98 9 5 6 639.911E-6 D1 9 10 DX D2 11 9 DX V1 99 10 2.08 V2 11 50 0 * * COMMON MODE STAGE WITH ZERO AT 100KHZ * ECM 12 98 POLY(2) (1,39) (2,39) 0 0.5 0.5 R9 12 13 1E6 R10 13 98 1 C3 12 13 1.592E-12 * * POLE AT 100KHZ * G2 98 14 9 39 1E-6 R11 14 98 1E6 C4 14 98 1.592E-12 * * ZERO AT 185KHZ * E1 15 98 14 39 1E6 R12 15 16 1E6 R13 16 98 1 C5 15 16 .860E-12 * * OUTPUT STAGE * G3 98 40 16 39 1E-6 R14 40 98 1E6 RS1 99 39 56.818E3 RS2 39 50 56.818E3 R15 99 45 50 R16 45 50 50 G7 45 99 99 40 20E-3 G8 50 45 40 50 20E-3 G9 98 60 45 40 20E-3 D7 60 61 DX D8 62 60 DX V7 61 98 DC 0 V8 98 62 DC 0 FSY 99 50 POLY(2) V7 V8 187E-6 1 1 D9 41 45 DX D10 45 42 DX V5 40 41 .125 V6 42 40 -.125 .MODEL DX D() .MODEL PNOM PMOS(VTO=-0.9 KP=81.897U) .ENDS *jg, 22/5/2000: corrected syntax model* OP80G SPICE Macro-model 9/93, Rev. A * ARG / PMI * * This version of the OP-80 model simulates the worst-case * parameters of the 'G' grade. The worst-case parameters * used correspond to those in the data sheet. * * Copyright 1993 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of * this model indicates your acceptance of the terms and pro- * visions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP80G 1 2 99 50 45 * * INPUT STAGE AND POLE AT 500KHZ * I1 99 4 50E-6 M1 5 2 4 99 PNOM L=15U W=1500U M2 6 3 4 99 PNOM L=15U W=1500U EOS 3 1 POLY(1) (13,39) 2.5E-3 3.162E3 R1 5 50 1.563E3 R2 6 50 1.563E3 IB1 1 50 1.95E-12 IB2 2 50 2.05E-12 CIN 1 2 2E-12 C1 5 6 101.845E-12 * * GAIN STAGE AND DOMINANT POLE AT 5.432HZ * EREF 98 0 39 0 1 C2 9 98 250E-12 R7 9 98 117.204E6 G1 98 9 5 6 639.911E-6 D1 9 10 DX D2 11 9 DX V1 99 10 2.08 V2 11 50 0 * * COMMON MODE STAGE WITH ZERO AT 100KHZ * ECM 12 98 POLY(2) (1,39) (2,39) 0 0.5 0.5 R9 12 13 1E6 R10 13 98 1 C3 12 13 1.592E-12 * * POLE AT 100KHZ * G2 98 14 9 39 1E-6 R11 14 98 1E6 C4 14 98 1.592E-12 * * ZERO AT 185KHZ * E1 15 98 14 39 1E6 R12 15 16 1E6 R13 16 98 1 C5 15 16 .860E-12 * * OUTPUT STAGE * G3 98 40 16 39 1E-6 R14 40 98 1E6 RS1 99 39 56.818E3 RS2 39 50 56.818E3 R15 99 45 50 R16 45 50 50 G7 45 99 99 40 20E-3 G8 50 45 40 50 20E-3 G9 98 60 45 40 20E-3 D7 60 61 DX D8 62 60 DX V7 61 98 DC 0 V8 98 62 DC 0 FSY 99 50 POLY(2) V7 V8 187E-6 1 1 D9 41 45 DX D10 45 42 DX V5 40 41 .125 V6 42 40 -.125 .MODEL DX D() .MODEL PNOM PMOS(VTO=-0.9 KP=81.897U) .ENDS *jg, 22/5/2000: corrected syntax model* OP90A SPICE Macro-model 10/92, Rev. C * JCB / PMI * * Revision History: * REV. C * Altered gain stage for proper open-loop gain. * REV. B * Re-ordered subcircuit call out nodes to put the * output node last. * Changed Ios from 3E-9 to 1.5E-9 * * * This version of the OP-90 model simulates the worst case * parameters of the 'A' grade. The worst case parameters * used correspond to those in the data book. * * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP90A 1 2 99 50 31 * * INPUT STAGE & POLE AT 10 KHZ * R1 2 3 5E11 R2 1 3 5E11 R3 5 51 61.6E3 R4 6 51 61.6E3 CIN 1 2 4E-12 C2 5 6 129.2E-12 I1 97 4 1E-6 IOS 1 2 1.5E-9 EOS 9 1 POLY(1) 23 27 150E-6 1 Q1 5 2 7 QX Q2 6 9 8 QX R5 7 4 10E3 R6 8 4 10E3 * EREF 98 0 27 0 1 EPLUS 97 0 99 0 1 ENEG 51 0 50 0 1 * * FIRST GAIN STAGE * R7 10 98 1E6 G1 98 10 5 6 101.47E-6 D1 10 11 DX D2 12 10 DX E1 97 11 POLY(1) 97 27 -1.4 1 E2 12 51 POLY(1) 27 51 -1.4 1 * * GAIN STAGE & DOMINANT POLE AT 0.323 HZ * R8 13 98 2.464E6 C3 13 98 200E-9 G2 98 13 10 27 0.5E-3 H2 97 14 POLY(1) VS2 2.2 -3E3 E5 15 51 POLY(2) (17,51) (97,27) 2.0 1.5 -0.405 D3 13 14 DX D4 15 13 DX * * ZERO-IN ZERO-OUT CLAMP * F1 51 17 VS2 -1000 RS1 17 51 1E9 D5 17 51 DX D6 51 17 DX * * NEGATIVE ZERO AT -100 KHZ * R9 19 20 1E6 C4 19 20 -1.59E-12 R10 20 98 1 E3 19 98 13 27 1E6 * * ZERO - POLE PAIR AT 28 KHZ / 100 KHZ * R11 21 22 1E6 L1 22 98 4.09 R12 22 98 2.57E6 G3 98 21 20 27 1E-6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 126 HZ * R13 23 24 1E6 L2 24 98 1.257E3 G4 98 23 3 27 1E-11 D8 23 97 DX D9 51 23 DX * * ZERO - POLE PAIR AT 40 KHZ / 160 KHZ * R14 25 26 1E6 L3 26 98 2.98 R15 26 98 3E6 G5 98 25 21 27 1E-6 * * OUTPUT STAGE * ISY 99 50 8.444E-6 R16 27 99 2.7E6 R17 27 50 2.7E6 R18 30 99 6000 R19 30 50 6000 VS2 30 31 DC 0 G6 28 50 25 30 166.7E-6 G7 29 50 30 25 166.7E-6 G8 30 99 99 25 166.7E-6 G9 50 30 25 50 166.7E-6 D10 99 28 DX D11 99 29 DX D12 50 28 DY D13 50 29 DY * * MODELS USED * .MODEL QX PNP(BF=33.333) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP90E SPICE Macro-model 10/92, Rev. C * JCB / PMI * * Revision History: * REV. C * Altered gain stage for proper open-loop gain. * REV. B * Re-ordered subcircuit call out nodes to put the * output node last. * Changed Ios from 3E-9 to 1.5E-9 * * * This version of the OP-90 model simulates the worst case * parameters of the 'E' grade. The worst case parameters * used correspond to those in the data book. * * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP90E 1 2 99 50 31 * * INPUT STAGE & POLE AT 10 KHZ * R1 2 3 5E11 R2 1 3 5E11 R3 5 51 61.6E3 R4 6 51 61.6E3 CIN 1 2 4E-12 C2 5 6 129.2E-12 I1 97 4 1E-6 IOS 1 2 1.5E-9 EOS 9 1 POLY(1) 23 27 150E-6 1 Q1 5 2 7 QX Q2 6 9 8 QX R5 7 4 10E3 R6 8 4 10E3 * EREF 98 0 27 0 1 EPLUS 97 0 99 0 1 ENEG 51 0 50 0 1 * * FIRST GAIN STAGE * R7 10 98 1E6 G1 98 10 5 6 101.47E-6 D1 10 11 DX D2 12 10 DX E1 97 11 POLY(1) 97 27 -1.4 1 E2 12 51 POLY(1) 27 51 -1.4 1 * * GAIN STAGE & DOMINANT POLE AT 0.323 HZ * R8 13 98 2.464E6 C3 13 98 200E-9 G2 98 13 10 27 0.5E-3 H2 97 14 POLY(1) VS2 2.2 -3E3 E5 15 51 POLY(2) (17,51) (97,27) 2.0 1.5 -0.405 D3 13 14 DX D4 15 13 DX * * ZERO-IN ZERO-OUT CLAMP * F1 51 17 VS2 -1000 RS1 17 51 1E9 D5 17 51 DX D6 51 17 DX * * NEGATIVE ZERO AT -100 KHZ * R9 19 20 1E6 C4 19 20 -1.59E-12 R10 20 98 1 E3 19 98 13 27 1E6 * * ZERO - POLE PAIR AT 28 KHZ / 100 KHZ * R11 21 22 1E6 L1 22 98 4.09 R12 22 98 2.57E6 G3 98 21 20 27 1E-6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 126 HZ * R13 23 24 1E6 L2 24 98 1.257E3 G4 98 23 3 27 1E-11 D8 23 97 DX D9 51 23 DX * * ZERO - POLE PAIR AT 40 KHZ / 160 KHZ * R14 25 26 1E6 L3 26 98 2.98 R15 26 98 3E6 G5 98 25 21 27 1E-6 * * OUTPUT STAGE * ISY 99 50 8.444E-6 R16 27 99 2.7E6 R17 27 50 2.7E6 R18 30 99 6000 R19 30 50 6000 VS2 30 31 DC 0 G6 28 50 25 30 166.7E-6 G7 29 50 30 25 166.7E-6 G8 30 99 99 25 166.7E-6 G9 50 30 25 50 166.7E-6 D10 99 28 DX D11 99 29 DX D12 50 28 DY D13 50 29 DY * * MODELS USED * .MODEL QX PNP(BF=33.333) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP90F SPICE Macro-model 10/92, Rev. C * JCB / PMI * * Revision History: * REV. C * Altered gain stage for proper open-loop gain. * REV. B * Re-ordered subcircuit call out nodes to put the * output node last. * Changed Ios from 5E-9 to 2.5E-9 * * * This version of the OP-90 model simulates the worst case * parameters of the 'F' grade. The worst case parameters * used correspond to those in the data book. * * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP90F 1 2 99 50 31 * * INPUT STAGE & POLE AT 10 KHZ * R1 2 3 5E11 R2 1 3 5E11 R3 5 51 61.6E3 R4 6 51 61.6E3 CIN 1 2 4E-12 C2 5 6 129.2E-12 I1 97 4 1E-6 IOS 1 2 2.5E-9 EOS 9 1 POLY(1) 23 27 250E-6 1 Q1 5 2 7 QX Q2 6 9 8 QX R5 7 4 10E3 R6 8 4 10E3 * EREF 98 0 27 0 1 EPLUS 97 0 99 0 1 ENEG 51 0 50 0 1 * * FIRST GAIN STAGE * R7 10 98 1E6 G1 98 10 5 6 101.36E-6 D1 10 11 DX D2 12 10 DX E1 97 11 POLY(1) 97 27 -1.4 1 E2 12 51 POLY(1) 27 51 -1.4 1 * * GAIN STAGE & DOMINANT POLE AT 0.403 HZ * R8 13 98 1.973E6 C3 13 98 200E-9 G2 98 13 10 27 0.5E-3 H2 97 14 POLY(1) VS2 2.2 -3E3 E5 15 51 POLY(2) (17,51) (97,27) 2.0 1.5 -0.405 D3 13 14 DX D4 15 13 DX * * ZERO-IN ZERO-OUT CLAMP * F1 51 17 VS2 -1000 RS1 17 51 1E9 D5 17 51 DX D6 51 17 DX * * NEGATIVE ZERO AT -100 KHZ * R9 19 20 1E6 C4 19 20 -1.59E-12 R10 20 98 1 E3 19 98 13 27 1E6 * * ZERO - POLE PAIR AT 28 KHZ / 100 KHZ * R11 21 22 1E6 L1 22 98 4.09 R12 22 98 2.57E6 G3 98 21 20 27 1E-6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 400 HZ * R13 23 24 1E6 L2 24 98 397.9 G4 98 23 3 27 3.162E-11 D8 23 97 DX D9 51 23 DX * * ZERO - POLE PAIR AT 40 KHZ / 160 KHZ * R14 25 26 1E6 L3 26 98 2.98 R15 26 98 3E6 G5 98 25 21 27 1E-6 * * OUTPUT STAGE * ISY 99 50 8.444E-6 R16 27 99 2.7E6 R17 27 50 2.7E6 R18 30 99 6000 R19 30 50 6000 VS2 30 31 DC 0 G6 28 50 25 30 166.7E-6 G7 29 50 30 25 166.7E-6 G8 30 99 99 25 166.7E-6 G9 50 30 25 50 166.7E-6 D10 99 28 DX D11 99 29 DX D12 50 28 DY D13 50 29 DY * * MODELS USED * .MODEL QX PNP(BF=25) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP90G SPICE Macro-model 10/92, Rev. C * JCB / PMI * * Revision History: * REV. C * Altered gain stage for proper open-loop gain. * REV. B * Re-ordered subcircuit call out nodes to put the * output node last. * Changed Ios from 5E-9 to 2.5E-9 * * * This version of the OP-90 model simulates the worst case * parameters of the 'G' grade. The worst case parameters * used correspond to those in the data book. * * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP90G 1 2 99 50 31 * * INPUT STAGE & POLE AT 10 KHZ * R1 2 3 5E11 R2 1 3 5E11 R3 5 51 61.6E3 R4 6 51 61.6E3 CIN 1 2 4E-12 C2 5 6 129.2E-12 I1 97 4 1E-6 IOS 1 2 2.5E-9 EOS 9 1 POLY(1) 23 27 450E-6 1 Q1 5 2 7 QX Q2 6 9 8 QX R5 7 4 10E3 R6 8 4 10E3 * EREF 98 0 27 0 1 EPLUS 97 0 99 0 1 ENEG 51 0 50 0 1 * * FIRST GAIN STAGE * R7 10 98 1E6 G1 98 10 5 6 101.36E-6 D1 10 11 DX D2 12 10 DX E1 97 11 POLY(1) 97 27 -1.4 1 E2 12 51 POLY(1) 27 51 -1.4 1 * * GAIN STAGE & DOMINANT POLE AT 0.403 HZ * R8 13 98 1.973E6 C3 13 98 200E-9 G2 98 13 10 27 0.5E-3 H2 97 14 POLY(1) VS2 2.2 -3E3 E5 15 51 POLY(2) (17,51) (97,27) 2.0 1.5 -0.405 D3 13 14 DX D4 15 13 DX * * ZERO-IN ZERO-OUT CLAMP * F1 51 17 VS2 -1000 RS1 17 51 1E9 D5 17 51 DX D6 51 17 DX * * NEGATIVE ZERO AT -100 KHZ * R9 19 20 1E6 C4 19 20 -1.59E-12 R10 20 98 1 E3 19 98 13 27 1E6 * * ZERO - POLE PAIR AT 28 KHZ / 100 KHZ * R11 21 22 1E6 L1 22 98 4.09 R12 22 98 2.57E6 G3 98 21 20 27 1E-6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 400 HZ * R13 23 24 1E6 L2 24 98 397.9 G4 98 23 3 27 3.162E-11 D8 23 97 DX D9 51 23 DX * * ZERO - POLE PAIR AT 40 KHZ / 160 KHZ * R14 25 26 1E6 L3 26 98 2.98 R15 26 98 3E6 G5 98 25 21 27 1E-6 * * OUTPUT STAGE * ISY 99 50 8.444E-6 R16 27 99 2.7E6 R17 27 50 2.7E6 R18 30 99 6000 R19 30 50 6000 VS2 30 31 DC 0 G6 28 50 25 30 166.7E-6 G7 29 50 30 25 166.7E-6 G8 30 99 99 25 166.7E-6 G9 50 30 25 50 166.7E-6 D10 99 28 DX D11 99 29 DX D12 50 28 DY D13 50 29 DY * * MODELS USED * .MODEL QX PNP(BF=20) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP97A SPICE Macro-model 4/92, Rev. B * JCB / PMI * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP97A 1 2 99 50 38 * * INPUT STAGE & POLE AT 15 MHZ * R1 2 3 5E11 R2 1 3 5E11 R3 5 99 516 R4 6 99 516 CIN 1 2 4E-12 C2 5 6 10.28E-12 I1 4 50 0.1E-3 IOS 1 2 50E-12 EOS 9 1 POLY(1) 26 32 25E-6 1 Q1 5 2 4 QX Q2 6 9 4 QX D12 2 9 DX D13 9 2 DX * * FIRST GAIN STAGE * R5 99 10 1E6 R6 50 10 1E6 GX1 99 10 5 6 3.268E-5 GX2 10 50 6 5 3.268E-5 E1 99 11 POLY(1) 99 32 -0.4 1 DX1 10 11 DX E2 12 50 POLY(1) 32 50 -0.4 1 DX2 12 10 DX * * GAIN STAGE & DOMINANT POLE AT 1.73 HZ * R9 13 99 9.18E7 R10 13 50 9.18E7 C3 13 99 1E-9 C4 13 50 1E-9 G3 99 13 10 32 0.1E-3 G4 13 50 32 10 0.1E-3 V2 99 14 2.2 V3 15 50 2.2 D1 13 14 DX D2 15 13 DX GS 99 50 POLY(1) 99 50 0.28E-3 -3.7E-6 * * ZERO-POLE PAIR AT 150 KHZ / 285 KHZ * R17 19 20 1E6 R18 19 21 1E6 R19 20 99 0.9E6 R20 21 50 0.9E6 L3 20 99 0.503 L4 21 50 0.503 G7 99 19 13 32 1E-6 G8 19 50 32 13 1E-6 * * POLE AT 4.8 MHZ * R21 22 99 1E6 R22 22 50 1E6 C7 22 99 33.2E-15 C8 22 50 33.2E-15 G9 99 22 19 32 1E-6 G10 22 50 32 19 1E-6 * * POLE AT 8 MHZ * R23 23 99 1E6 R24 23 50 1E6 C9 23 99 19.9E-15 C10 23 50 19.9E-15 G11 99 23 22 32 1E-6 G12 23 50 32 22 1E-6 * * POLE AT 10 MHZ * R25 24 99 1E6 R26 24 50 1E6 C11 24 99 15.9E-15 C12 24 50 15.9E-15 G13 99 24 23 32 1E-6 G14 24 50 32 23 1E-6 * * POLE AT 15 MHZ * R27 25 99 1E6 R28 25 50 1E6 C13 25 99 10.6E-15 C14 25 50 10.6E-15 G15 99 25 24 32 1E-6 G16 25 99 32 24 1E-6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 200 HZ * R29 26 27 1E6 R30 26 28 1E6 L5 27 99 796 L6 28 50 796 RS1 27 99 16E9 RS2 28 50 16E9 G17 99 26 3 32 2E-12 G18 26 50 32 3 2E-12 D3 26 99 DX D4 50 26 DX * * POLE AT 12 MHZ * R32 31 99 1E6 R33 31 50 1E6 C15 31 99 13.2E-15 C16 31 50 13.2E-15 G19 99 31 25 32 1E-6 G20 31 50 32 25 1E-6 * * OUTPUT STAGE * R34 32 99 1E6 R35 32 50 1E6 R36 33 99 600 R37 33 50 600 L7 33 38 2.65E-7 G21 36 50 31 33 1.6667E-3 G22 37 50 33 31 1.6667E-3 G23 33 99 99 31 1.6667E-3 G24 50 33 31 50 1.6667E-3 V6 34 33 3.6 V7 33 35 3.0 D5 31 34 DX D6 35 31 DX D7 99 36 DX D8 99 37 DX D9 50 36 DY D10 50 37 DY * * MODELS USED * .MODEL QX NPN(BF=5E5) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP97E SPICE Macro-model 4/92, Rev. B * JCB / PMI * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP97E 1 2 99 50 38 * * INPUT STAGE & POLE AT 15 MHZ * R1 2 3 5E11 R2 1 3 5E11 R3 5 99 516 R4 6 99 516 CIN 1 2 4E-12 C2 5 6 10.28E-12 I1 4 50 0.1E-3 IOS 1 2 50E-12 EOS 9 1 POLY(1) 26 32 25E-6 1 Q1 5 2 4 QX Q2 6 9 4 QX D12 2 9 DX D13 9 2 DX * * FIRST GAIN STAGE * R5 99 10 1E6 R6 50 10 1E6 GX1 99 10 5 6 3.268E-5 GX2 10 50 6 5 3.268E-5 E1 99 11 POLY(1) 99 32 -0.4 1 DX1 10 11 DX E2 12 50 POLY(1) 32 50 -0.4 1 DX2 12 10 DX * * GAIN STAGE & DOMINANT POLE AT 1.73 HZ * R9 13 99 9.18E7 R10 13 50 9.18E7 C3 13 99 1E-9 C4 13 50 1E-9 G3 99 13 10 32 0.1E-3 G4 13 50 32 10 0.1E-3 V2 99 14 2.2 V3 15 50 2.2 D1 13 14 DX D2 15 13 DX GS 99 50 POLY(1) 99 50 0.28E-3 -3.7E-6 * * ZERO-POLE PAIR AT 150 KHZ / 285 KHZ * R17 19 20 1E6 R18 19 21 1E6 R19 20 99 0.9E6 R20 21 50 0.9E6 L3 20 99 0.503 L4 21 50 0.503 G7 99 19 13 32 1E-6 G8 19 50 32 13 1E-6 * * POLE AT 4.8 MHZ * R21 22 99 1E6 R22 22 50 1E6 C7 22 99 33.2E-15 C8 22 50 33.2E-15 G9 99 22 19 32 1E-6 G10 22 50 32 19 1E-6 * * POLE AT 8 MHZ * R23 23 99 1E6 R24 23 50 1E6 C9 23 99 19.9E-15 C10 23 50 19.9E-15 G11 99 23 22 32 1E-6 G12 23 50 32 22 1E-6 * * POLE AT 10 MHZ * R25 24 99 1E6 R26 24 50 1E6 C11 24 99 15.9E-15 C12 24 50 15.9E-15 G13 99 24 23 32 1E-6 G14 24 50 32 23 1E-6 * * POLE AT 15 MHZ * R27 25 99 1E6 R28 25 50 1E6 C13 25 99 10.6E-15 C14 25 50 10.6E-15 G15 99 25 24 32 1E-6 G16 25 99 32 24 1E-6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 200 HZ * R29 26 27 1E6 R30 26 28 1E6 L5 27 99 796 L6 28 50 796 RS1 27 99 16E9 RS2 28 50 16E9 G17 99 26 3 32 2E-12 G18 26 50 32 3 2E-12 D3 26 99 DX D4 50 26 DX * * POLE AT 12 MHZ * R32 31 99 1E6 R33 31 50 1E6 C15 31 99 13.2E-15 C16 31 50 13.2E-15 G19 99 31 25 32 1E-6 G20 31 50 32 25 1E-6 * * OUTPUT STAGE * R34 32 99 1E6 R35 32 50 1E6 R36 33 99 600 R37 33 50 600 L7 33 38 2.65E-7 G21 36 50 31 33 1.6667E-3 G22 37 50 33 31 1.6667E-3 G23 33 99 99 31 1.6667E-3 G24 50 33 31 50 1.6667E-3 V6 34 33 3.6 V7 33 35 3.0 D5 31 34 DX D6 35 31 DX D7 99 36 DX D8 99 37 DX D9 50 36 DY D10 50 37 DY * * MODELS USED * .MODEL QX NPN(BF=5E5) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP97F SPICE Macro-model 4/92, Rev. B * JCB / PMI * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP97F 1 2 99 50 38 * * INPUT STAGE & POLE AT 15 MHZ * R1 2 3 5E11 R2 1 3 5E11 R3 5 99 516 R4 6 99 516 CIN 1 2 4E-12 C2 5 6 10.28E-12 I1 4 50 0.1E-3 IOS 1 2 75E-12 EOS 9 1 POLY(1) 26 32 75E-6 1 Q1 5 2 4 QX Q2 6 9 4 QX D12 2 9 DX D13 9 2 DX * * FIRST GAIN STAGE * R5 99 10 1E6 R6 50 10 1E6 GX1 99 10 5 6 3.268E-5 GX2 10 50 6 5 3.268E-5 E1 99 11 POLY(1) 99 32 -0.4 1 DX1 10 11 DX E2 12 50 POLY(1) 32 50 -0.4 1 DX2 12 10 DX * * GAIN STAGE & DOMINANT POLE AT 2.6 HZ * R9 13 99 6.12E7 R10 13 50 6.12E7 C3 13 99 1E-9 C4 13 50 1E-9 G3 99 13 10 32 0.1E-3 G4 13 50 32 10 0.1E-3 V2 99 14 2.2 V3 15 50 2.2 D1 13 14 DX D2 15 13 DX GS 99 50 POLY(1) 99 50 0.28E-3 -3.7E-6 * * ZERO-POLE PAIR AT 150 KHZ / 285 KHZ * R17 19 20 1E6 R18 19 21 1E6 R19 20 99 0.9E6 R20 21 50 0.9E6 L3 20 99 0.503 L4 21 50 0.503 G7 99 19 13 32 1E-6 G8 19 50 32 13 1E-6 * * POLE AT 4.8 MHZ * R21 22 99 1E6 R22 22 50 1E6 C7 22 99 33.2E-15 C8 22 50 33.2E-15 G9 99 22 19 32 1E-6 G10 22 50 32 19 1E-6 * * POLE AT 8 MHZ * R23 23 99 1E6 R24 23 50 1E6 C9 23 99 19.9E-15 C10 23 50 19.9E-15 G11 99 23 22 32 1E-6 G12 23 50 32 22 1E-6 * * POLE AT 10 MHZ * R25 24 99 1E6 R26 24 50 1E6 C11 24 99 15.9E-15 C12 24 50 15.9E-15 G13 99 24 23 32 1E-6 G14 24 50 32 23 1E-6 * * POLE AT 15 MHZ * R27 25 99 1E6 R28 25 50 1E6 C13 25 99 10.6E-15 C14 25 50 10.6E-15 G15 99 25 24 32 1E-6 G16 25 99 32 24 1E-6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 316 HZ * R29 26 27 1E6 R30 26 28 1E6 L5 27 99 504 L6 28 50 504 RS1 27 99 16E9 RS2 28 50 16E9 G17 99 26 3 32 3.16E-12 G18 26 50 32 3 3.16E-12 D3 26 99 DX D4 50 26 DX * * POLE AT 12 MHZ * R32 31 99 1E6 R33 31 50 1E6 C15 31 99 13.2E-15 C16 31 50 13.2E-15 G19 99 31 25 32 1E-6 G20 31 50 32 25 1E-6 * * OUTPUT STAGE * R34 32 99 1E6 R35 32 50 1E6 R36 33 99 600 R37 33 50 600 L7 33 38 2.65E-7 G21 36 50 31 33 1.6667E-3 G22 37 50 33 31 1.6667E-3 G23 33 99 99 31 1.6667E-3 G24 50 33 31 50 1.6667E-3 V6 34 33 3.6 V7 33 35 3.0 D5 31 34 DX D6 35 31 DX D7 99 36 DX D8 99 37 DX D9 50 36 DY D10 50 37 DY * * MODELS USED * .MODEL QX NPN(BF=3.33E5) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * PM1012 SPICE Macro-model 12/90, Rev. B * JCB / PMI * * Revision History: * REV. B * Re-ordered subcircuit call out nodes to put the * output node last. * Changed Ios from 15E-12 to 7.5E-12 * * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT PM1012 1 2 99 50 38 * * INPUT STAGE & POLE AT 15 MHZ * R1 2 3 5E11 R2 1 3 5E11 R3 5 99 612 R4 6 99 612 CIN 1 2 4E-12 C2 5 6 8.67E-12 I1 4 50 0.1E-3 IOS 1 2 7.5E-12 EOS 9 1 POLY(1) 26 32 8E-6 1 Q1 5 2 10 QX Q2 6 9 11 QX R5 10 4 96 R6 11 4 96 D12 2 9 DX D13 9 2 DX * * GAIN STAGE & DOMINANT POLE AT 0.26 HZ * R9 13 99 1.22E9 R10 13 50 1.22E9 C3 13 99 500E-12 C4 13 50 500E-12 G3 99 13 5 6 1.634E-3 G4 13 50 6 5 1.634E-3 V2 99 14 1.3 V3 15 50 1.3 D1 13 14 DX D2 15 13 DX GS 99 50 POLY(1) 99 50 0.28E-3 -3.7E-6 * * ZERO-POLE PAIR AT 150 KHZ / 285 KHZ * R17 19 20 1E6 R18 19 21 1E6 R19 20 99 0.9E6 R20 21 50 0.9E6 L3 20 99 0.503 L4 21 50 0.503 G7 99 19 13 32 1E-6 G8 19 50 32 13 1E-6 * * POLE AT 4.8 MHZ * R21 22 99 1E6 R22 22 50 1E6 C7 22 99 33.2E-15 C8 22 50 33.2E-15 G9 99 22 19 32 1E-6 G10 22 50 32 19 1E-6 * * POLE AT 8 MHZ * R23 23 99 1E6 R24 23 50 1E6 C9 23 99 19.9E-15 C10 23 50 19.9E-15 G11 99 23 22 32 1E-6 G12 23 50 32 22 1E-6 * * POLE AT 10 MHZ * R25 24 99 1E6 R26 24 50 1E6 C11 24 99 15.9E-15 C12 24 50 15.9E-15 G13 99 24 23 32 1E-6 G14 24 50 32 23 1E-6 * * POLE AT 15 MHZ * R27 25 99 1E6 R28 25 50 1E6 C13 25 99 10.6E-15 C14 25 50 10.6E-15 G15 99 25 24 32 1E-6 G16 25 99 32 24 1E-6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 50 KHZ * R29 26 27 1E6 R30 26 28 1E6 L5 27 99 3.183E3 L6 28 50 3.183E3 RS1 27 99 16E9 RS2 28 50 16E9 G17 99 26 3 32 2.51E-13 G18 26 50 32 3 2.51E-13 D3 26 99 DX D4 50 26 DX * * POLE AT 12 MHZ * R32 31 99 1E6 R33 31 50 1E6 C15 31 99 13.2E-15 C16 31 50 13.2E-15 G19 99 31 25 32 1E-6 G20 31 50 32 25 1E-6 * * OUTPUT STAGE * R34 32 99 1E6 R35 32 50 1E6 R36 33 99 600 R37 33 50 600 L7 33 38 2.65E-7 G21 36 50 31 33 1.6667E-3 G22 37 50 33 31 1.6667E-3 G23 33 99 99 31 1.6667E-3 G24 50 33 31 50 1.6667E-3 V6 34 33 3.6 V7 33 35 3.0 D5 31 34 DX D6 35 31 DX D7 99 36 DX D8 99 37 DX D9 50 36 DY D10 50 37 DY * * MODELS USED * .MODEL QX NPN(BF=2E6) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * AD645 SPICE Macro-model 4/92, Rev. B * JCB / PMI * * Revision History: * Rev. B: Converted model to include noise analysis. * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD645 1 2 99 50 30 * * INPUT STAGE & POLE AT 40 MHZ * R3 5 50 2.097 R4 6 50 2.097 CIN 1 2 1E-12 C2 5 6 9.48E-10 I1 99 4 100E-3 IOS 1 2 0.05E-12 EOS 65 1 POLY(1) 17 24 100E-6 1 J1 5 2 4 JX J2 6 7 4 JX EN 7 65 43 0 1 GN1 0 1 47 0 1E-6 GN2 0 2 61 0 1E-6 GB1 2 50 POLY(3) 4,2 5,2 50,2 0 1E-12 1E-12 1E-12 GB2 7 50 POLY(3) 4,7 6,7 50,7 0 1E-12 1E-12 1E-12 * EREF 98 0 24 0 1 * * VOLTAGE NOISE GENERATOR * VN1 41 0 DC 2 RS1 41 42 8E3 RS2 42 43 1.2E9 CS1 42 43 398E-11 RS3 43 44 1.2E9 CS2 43 44 398E-11 RS4 44 45 8E3 VN2 0 45 DC 2 * * CURRENT NOISE GENERATOR * VN3 46 0 DC 2 RN5 46 47 41.5 RN6 47 48 41.5 VN4 0 48 DC 2 * * CURRENT NOISE GENERATOR * VN5 60 0 DC 2 RN7 60 61 41.5 RN8 61 62 41.5 VN6 0 62 DC 2 * * SECOND STAGE & POLE AT 0.48 HZ * R5 9 98 6.632E6 C3 9 98 5.00E-8 G1 98 9 5 6 4.769E-1 V2 99 8 3.6 V3 10 50 3.6 D1 9 8 DX D2 10 9 DX * * NEGATIVE ZERO AT 15 MHZ * R6 11 12 1E6 C4 11 12 -10.6E-15 R7 12 98 1 E2 11 98 9 24 1E6 * * POLE AT 40 MHZ * R8 13 98 1E3 C5 13 98 3.98E-12 G2 98 13 12 24 1E-3 * * POLE AT 40 MHZ * R9 14 98 1E3 C6 14 98 3.98E-12 G3 98 14 13 24 1E-3 * * POLE AT 40 MHZ * R10 15 98 1E3 C7 15 98 3.98E-12 G4 98 15 14 24 1E-3 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 60 HZ * R11 16 17 1E6 C8 16 17 2.65E-9 R12 17 98 1 E3 16 98 POLY(2) 1 98 2 98 0 1.58 1.58 * * POLE AT 40 MHZ * R13 18 98 1E3 C9 18 98 3.98E-12 G5 98 18 15 24 1E-3 * * OUTPUT STAGE * R14 24 99 2000E3 R15 24 50 2000E3 ISY 99 50 -97E-3 R16 29 99 360 R17 29 50 360 L1 29 30 1E-8 G6 27 50 18 29 2.78E-3 G7 28 50 29 18 2.78E-3 G8 29 99 99 18 2.78E-3 G9 50 29 18 50 2.78E-3 V4 25 29 2.0 V5 29 26 2.0 D3 18 25 DX D4 26 18 DX D5 99 27 DX D6 99 28 DX D7 50 27 DY D8 50 28 DY F1 29 0 V4 1 F2 0 29 V5 1 * * MODELS USED * .MODEL JX PJF(BETA=1.137 VTO=-2.000 IS=0.35E-12 RD=0.1 + RS=0.1 CGD=1E-15 CGS=1E-15) .MODEL DX D(IS=1E-15 RS=10 CJO=1E-15) .MODEL DY D(IS=1E-15 BV=50 RS=10 CJO=1E-15) .MODEL DEN D(IS=1E-12 RS=7409.6 KF=2.051E-15 AF=1) .MODEL DIN D(IS=1E-12 RS=41.5 KF=0 AF=1) .ENDS AD645 * AD706 SPICE Macro-model 9/91, Rev. A * AAG / PMI * * Copyright 1991 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD706 1 2 99 50 28 * * INPUT STAGE & POLE AT 3 MHz * IOS 1 2 DC 15E-12 CIN 1 2 2E-12 R1 2 3 8.8415E8 R2 1 3 8.8415E8 EOS 9 1 POLY(1) 16 22 10E-6 1 D1 2 9 DX D2 9 2 DX Q1 5 2 10 QX Q2 6 9 11 QX R3 99 5 530.51 R4 99 6 530.51 C2 5 6 50E-12 R5 10 4 13.314 R6 11 4 13.314 I1 4 50 100E-6 * * GAIN STAGE & DOMINANT POLE AT 0.45 HZ * EREF 98 0 22 0 1 G1 98 12 5 6 1.885E-3 R7 12 98 530.51E6 C3 12 98 666.67E-12 V1 99 13 DC 1.3375 D3 12 13 DX V2 14 50 DC 1.3375 D4 14 12 DX * * COMMON-MODE GAIN NETWORK WITH ZERO AT 500 HZ * ECM 15 98 3 22 251.19E-3 RCM1 15 16 1E6 CCM 15 16 318.31E-12 RCM2 16 98 1 * * ZERO-POLE PAIR AT 165 kHz / 430 kHz * GZP1 98 17 12 22 1E-6 RZP1 17 18 1E6 RZP2 18 98 1.6061E6 LZP 18 98 594.45E-3 * * NEGATIVE ZERO AT -3 MHz * ENZ 19 98 17 22 1E6 RNZ1 19 20 1 CNZ 19 20 -53.052E-9 RNZ2 20 98 1E-6 * * POLE AT 10 MHz * G2 98 21 20 22 1E-6 R10 21 98 1E6 C5 21 98 15.915E-15 * * OUTPUT STAGE * IDC 99 50 DC 260E-6 RDC1 99 22 1E6 RDC2 22 50 1E6 DO1 99 23 DX GO1 23 50 27 21 2E-3 DO2 50 23 DY DO3 99 24 DX GO2 24 50 21 27 2E-3 DO4 50 24 DY VSC1 25 27 3.15 DSC1 21 25 DX VSC2 27 26 3.15 DSC2 26 21 DX GO3 27 99 99 21 2E-3 GO4 50 27 21 50 2E-3 RO1 99 27 500 RO2 27 50 500 LO 27 28 265E-9 * * MODELS USED * .MODEL QX NPN(BF=1.6667E6) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS AD706 * AD711 SPICE Macro-model 3/91, Rev. B * JLW / PMI * * Revision History: * Corrected VOS to be 0.1mV * * This version of the AD711 model simulates the typical * parameters corresponding to the device data sheet. * * Copyright 1991 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * connections: non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD711 13 15 12 16 14 * VOS 15 8 DC 0.1E-3 EC 9 0 (14,0) 1 C1 6 7 .5E-12 RP 16 12 12E3 GB 11 0 (3,0) 1.67E3 RD1 6 16 16E3 RD2 7 16 16E3 ISS 12 1 DC 100E-6 CCI 3 11 150E-12 GCM 0 3 (0,1) 1.76E-9 GA 3 0 (7,6) 2.3ME-3 RE 1 0 2.5E6 RGM 3 0 1.69E3 VC 12 2 DC 2.8 VE 10 16 DC 2.8 RO1 11 14 25 CE 1 0 2E-12 RO2 0 11 30 RS1 1 4 5.77E3 RS2 1 5 5.77E3 J1 6 13 4 FET J2 7 8 5 FET DC 14 2 DIODE DE 10 14 DIODE DP 16 12 DIODE D1 9 11 DIODE D2 11 9 DIODE IOS 15 13 5E-12 .MODEL DIODE D() .MODEL FET PJF(VTO=-1 BETA=1E-3 IS=15E-12) .ENDS * AD712 SPICE Macro-model 4/92, Rev. B * JCB/JW/PMI * * Revision History: * Rev B: Convert model into ADSpice format * Add noise generators * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD712 1 2 99 50 30 * * INPUT STAGE * R3 5 50 6.631 R4 6 50 6.631 CIN 1 2 5.5E-12 I1 99 4 100E-3 IOS 1 2 2.5E-12 EOS 60 1 POLY(1) 17 24 100E-6 1 EN 7 60 42 0 1 GN1 0 1 45 0 1E-6 GN2 0 2 48 0 1E-6 J1 5 2 4 JX J2 6 7 4 JX GB1 2 50 POLY(3) 4,2 5,2 50,2 0 1E-12 1E-12 1E-12 GB2 7 50 POLY(3) 4,7 6,7 50,7 0 1E-12 1E-12 1E-12 * EREF 98 0 24 0 1 * * VOLTAGE NOISE GENERATOR * VN1 41 0 DC 2 DN1 41 42 DEN DN2 42 43 DEN VN2 0 43 DC 2 * * CURRENT NOISE GENERATOR * VN3 44 0 DC 2 DN3 44 45 DIN DN4 45 46 DIN VN4 0 46 DC 2 * * CURRENT NOISE GENERATOR * VN5 47 0 DC 2 DN5 47 48 DIN DN6 48 49 DIN VN6 0 49 DC 2 * * SECOND STAGE & POLE AT 12 HZ * R5 9 98 2.65E6 C3 9 98 5.00E-9 G1 98 9 5 6 1.51E-1 V2 99 8 1.3 V3 10 50 1.9 D1 9 8 DX D2 10 9 DX * * COMMON-MODE GAIN NETWORK WITH ZERO AT 300 HZ * R11 16 17 1E6 C8 16 17 5.318E-10 R12 17 98 1 E3 16 98 POLY(2) 1 98 2 98 0 9.975 9.975 * * POLE AT 15 MHZ * R13 18 98 1E3 C9 18 98 10.61E-12 G5 98 18 9 24 1E-3 * * OUTPUT STAGE * R14 24 99 500E3 R15 24 50 500E3 CF 24 0 1E-6 ISY 99 50 -95E-3 R16 29 99 110 R17 29 50 110 L1 29 30 1E-8 G6 27 50 18 29 9.09E-3 G7 28 50 29 18 9.09E-3 G8 29 99 99 18 9.09E-3 G9 50 29 18 50 9.09E-3 V4 25 29 0.675 V5 29 26 0.675 D3 18 25 DX D4 26 18 DX D5 99 27 DX D6 99 28 DX D7 50 27 DY D8 50 28 DY F1 29 0 V4 1 F2 0 29 V5 1 * * MODELS USED * .MODEL JX PJF(BETA=1.14E-1 VTO=-2.000 IS=20E-12 RD=0 + RS=0 CGD=1E-12 CGS=1E-12) .MODEL DX D(IS=1E-15 RS=0 CJO=1E-12) .MODEL DY D(IS=1E-15 BV=50 RS=10 CJO=1E-12) .MODEL DEN D(IS=1E-12 RS=30909 KF=2.651E-15 AF=1) .MODEL DIN D(IS=1E-12 RS=12090 KF=0 AF=1) .ENDS AD712 * AD713 SPICE Macro-model 3/91, Rev. B * JLW / PMI * * Revision History: * Corrected VOS to be 0.2mV * * * This version of the AD713 model simulates the typical * parameters corresponding to those in the device data * sheet. * * * Copyright 1991 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * connections: non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD713 13 15 12 16 14 * VOS 15 8 DC 0.2E-3 EC 9 0 (14,0) 1 C1 6 7 .5E-12 RP 16 12 12E3 GB 11 0 (3,0) 1.67E3 RD1 6 16 16E3 RD2 7 16 16E3 ISS 12 1 DC 100E-6 CCI 3 11 150E-12 GCM 0 3 (0,1) 1.76E-9 GA 3 0 (7,6) 2.3E-3 RE 1 0 2.5E6 RGM 3 0 1.69E3 VC 12 2 DC 2.8 VE 10 16 DC 2.8 RO1 11 14 25 CE 1 0 2E-12 RO2 0 11 30 RS1 1 4 5.77E3 RS2 1 5 5.77E3 J1 6 13 4 FET J2 7 8 5 FET DC 14 2 DIODE DE 10 14 DIODE DP 16 12 DIODE D1 9 11 DIODE D2 11 9 DIODE IOS 15 13 5E-12 .MODEL DIODE D() .MODEL FET PJF(VTO=-1 BETA=1E-3 IS=40E-12) .ENDS * AD743 SPICE Macro-model 4/92, Rev. A * AAG / PMI * * Copyright 1992 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD743 1 2 99 50 37 * * INPUT STAGE & POLE AT 65 MHz * IOS 1 2 DC 12.5E-12 CIN 1 2 20E-12 EOS 9 3 POLY(1) 16 31 100E-6 1 EN 3 1 41 0 1 J1 5 2 4 PJX J2 6 9 4 PJX R3 5 51 0.9323 R4 6 51 0.9323 C2 5 6 1.3132E-9 I1 97 4 100E-3 EPOS 97 0 99 0 1 ENEG 51 0 50 0 1 GN1 0 1 44 0 1E-6 GN2 0 2 47 0 1E-6 * * INPUT NOISE VOLTAGE GENERATOR * VN1 40 0 DC 2 DN1 40 41 DEN DN2 41 42 DEN VN2 0 42 DC 2 * * INPUT NOISE CURRENT GENERATOR FOR IN+ * VN3 43 0 DC 2 DN3 43 44 DIN DN4 44 45 DIN VN4 0 45 DC 2 * * INPUT NOISE CURRENT GENERATOR FOR IN- * VN5 46 0 DC 2 DN5 46 47 DIN DN6 47 48 DIN VN6 0 48 DC 2 * * GAIN STAGE & DOMINANT POLE AT 1.195 Hz * EREF 98 0 31 0 1 G1 98 12 5 6 1.0726 R5 12 98 3.7292E6 C3 12 98 35.714E-9 V1 99 13 DC 187.5E-3 D1 12 13 DX V2 14 50 DC 1.3375 D4 14 12 DX * * CMR Network with Zero at 600 Hz * ECM 15 98 POLY(2) 1 31 2 31 (0,3.9717,3.9717) RCM1 15 16 1 CCM 15 16 265.26E-6 RCM2 16 98 1E-6 * * NEGATIVE ZERO AT -19.5 MHz * ENZ 17 98 12 31 1E6 RNZ1 17 18 1 CNZ 17 18 -8.1618E-9 RNZ2 18 98 1E-6 * * POLE-ZERO PAIR AT 330 kHz/690 kHz * GPZ 98 19 18 31 1 RPZ1 19 98 1 RPZ2 19 20 0.91667 CPZ 20 98 251.63E-9 * * POLE AT 65 MHz * G2 98 21 19 31 1 R10 21 98 1 C5 21 98 2.4485E-9 * * OUTPUT STAGE * VWIRE 21 30 * IDC 99 50 DC 7.8E-3 RDC1 99 31 50E3 CDC 31 0 1E-12 RDC2 31 50 50E3 DO1 99 32 DX GO1 32 50 36 30 5.5556E-3 DO2 50 32 DY DO3 99 33 DX GO2 33 50 30 36 5.5556E-3 DO4 50 33 DY VSC1 34 36 3.1 DSC1 30 34 DX VSC2 36 35 2.66 DSC2 35 30 DX GO3 36 99 99 30 5.5556E-3 GO4 50 36 30 50 5.5556E-3 FO1 36 0 VSC1 1 FO2 0 36 VSC2 1 RO1 99 36 180 RO2 36 50 180 LO 36 37 250E-9 * * MODELS USED * .MODEL PJX PJF(VTO=-2 BETA=5.7526 IS=150E-12) .MODEL DEN D(IS=1E-12 RS=1.237E3 AF=1 KF=1.3772E-15) .MODEL DIN D(IS=1E-12 RS=5.7483E3 AF=1 KF=7.7505E-15) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS AD743 * AD745 SPICE Macro-model 10/95, Rev. B * ARG / ADSC * * Revision History: * Rev. B * Changed the negative zero circuit to correspond to the new design * which eliminates the negative capacitor value. * * * Copyright 1992 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License * Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD745 3 2 99 50 37 * * INPUT STAGE AND POLE AT 54MHZ * I1 97 1 1 J1 5 2 1 JX J2 6 4 1 JX CIN 2 3 20E-12 IOS 3 2 15E-12 EN 7 3 9 0 1 GN1 0 2 12 0 1E-6 GN2 0 3 15 0 1E-6 EOS 4 7 POLY(1) 31 52 100E-6 1 R1 5 51 86.842E-3 R2 6 51 86.842E-3 C1 5 6 16.969E-9 EPOS 97 0 99 0 1 ENEG 51 0 50 0 1 EREF 98 0 52 0 1 * * VOLTAGE NOISE SOURCE WITH FLICKER NOISE * VN1 8 0 DC 2 VN2 0 10 DC 2 DN1 8 9 DEN DN2 9 10 DEN * * CURRENT NOISE SOURCE WITH FLICKER NOISE * VN3 11 0 DC 10 VN4 0 13 DC 10 DN3 11 12 DIN DN4 12 13 DIN * * CURRENT NOISE SOURCE WITH FLICKER NOISE * VN5 14 0 DC 10 VN6 0 16 DC 10 DN5 14 15 DIN DN6 15 16 DIN * * GAIN STAGE AND DOMINANT POLE AT 5.727HZ * R3 17 98 347.368E3 C2 17 98 80E-9 G1 98 17 5 6 11.515 V1 97 18 .027 V2 19 51 1.193 D1 17 18 DX D2 19 17 DX * * POLE AT 30MHZ * R4 23 98 1 C3 23 98 5.305E-9 G2 98 23 17 52 1 * * POLE AT 30MHZ * R5 24 98 1 C4 24 98 5.305E-9 G3 98 24 23 52 1 * * NEGATIVE ZERO AT -54MHZ * R6 25 26 1 R7 26 98 1E-6 E1 25 98 24 52 1E6 VX1 84 0 DC 0 EX1 83 0 25 26 1 FX1 25 26 VX1 -1 CX1 83 84 2.947E-9 * * POLE / ZERO AT 2MHZ / 2.25MHZ * R8 27 98 1 R9 27 28 8 C6 28 98 8.842E-9 G4 98 27 26 52 1 * * COMMON MODE GAIN STAGE WITH ZERO AT 10KHZ * E2 29 30 2 52 0.5 E3 30 98 3 52 0.5 R10 29 31 1 R11 31 98 7.943E-6 C7 29 31 15.916E-6 * * REFERENCE NODE AND OUTPUT STAGE * RMP1 97 52 1 RMP2 52 51 1 GSY 99 50 POLY(1) 99 50 7.625E-3 12.5E-6 R13 99 36 200 R14 36 50 200 L1 36 37 1E-10 G5 34 50 27 36 5E-3 G6 35 50 36 27 5E-3 G7 36 99 99 27 5E-3 G8 50 36 27 50 5E-3 V3 32 36 2.922 V4 36 33 1.460 D3 27 32 DX D4 33 27 DX D5 99 34 DX D6 99 35 DX D7 50 34 DY D8 50 35 DY F1 36 0 V3 1 F2 0 36 V4 1 * * MODELS USED * .MODEL JX PJF(BETA=66.299, VTO=-1.5 IS=150E-12) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15, BV=50) .MODEL DEN D(RS=1.015E3, KF=4.311E-15, AF=1) .MODEL DIN D(RS=5.277E3, KF=42.593E-15, AF=1) .ENDS AD745 * AD746 SPICE Macro-model 3/91, Rev. B * JLW / PMI * * Revision History: * Corrected VOS to be 0.25mV * * * This version of the AD746 model simulates the typical * parameters corresponding to those in the device data * sheet. * * * Copyright 1991 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | .subckt AD746 11 14 10 16 13 * VOS 14 7 DC 0.25E-3 EC 8 0 (13,0) 1 C1 5 6 0.33E-12 GB 12 0 (15,0) 1.67E3 RD1 5 16 16E3 RD2 6 16 16E3 ISS 10 1 DC 100E-6 GCM 0 15 (0,1) 1.76E-9 GA 15 0 (6,5) 1.75E-3 RE 1 0 2.5E6 RGM 15 0 1.76E3 VC 10 2 DC 2.8 VE 9 16 DC 2.8 RO1 12 13 25 CE 1 0 1E-12 RO2 0 12 30 RS1 1 3 5.77E3 RS2 1 4 5.77E3 CCI 15 12 40E-12 RP 16 10 8.5E3 J1 5 11 3 FET J2 6 7 4 FET DC 13 2 DIODE DE 9 13 DIODE DP 16 10 DIODE D1 8 12 DIODE D2 12 8 DIODE .MODEL DIODE D() .MODEL FET PJF(VTO=-1 BETA=1E-3 IS=110E-12) .ENDS * AD795 SPICE Macro-model 11/94, Rev. A * JOM / ADSC * * Revision History: * NONE * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD795 1 2 99 50 30 * * INPUT STAGE & POLE AT 40 MHZ * R3 5 50 .719 R4 6 50 .719 CIN 1 2 2E-12 C2 5 6 1.383E-9 I1 99 4 100E-3 IOS 1 2 0.1E-12 EOS 65 1 POLY(1) 17 24 50E-6 1 J1 5 2 4 JX J2 6 7 4 JX EN 7 65 43 0 1 GN1 0 1 47 0 1E-6 GN2 0 2 61 0 1E-6 GB1 2 50 POLY(3) 4,2 5,2 50,2 0 1E-12 1E-12 1E-12 GB2 7 50 POLY(3) 4,7 6,7 50,7 0 1E-12 1E-12 1E-12 * EREF 98 0 24 0 1 * * VOLTAGE NOISE GENERATOR * VN1 41 0 DC 2 RS1 41 42 8E3 RS2 42 43 1.2E9 CS1 42 43 398E-11 RS3 43 44 1.2E9 CS2 43 44 398E-11 RS4 44 45 8E3 VN2 0 45 DC 2 * * CURRENT NOISE GENERATOR * VN3 46 0 DC 2 RN5 46 47 41.5 RN6 47 48 41.5 VN4 0 48 DC 2 * * CURRENT NOISE GENERATOR * VN5 60 0 DC 2 RN7 60 61 41.5 RN8 61 62 41.5 VN6 0 62 DC 2 * * SECOND STAGE & POLE AT 2.213 HZ * R5 9 98 719203 C3 9 98 1.00E-7 G1 98 9 5 6 1.39 V2 99 8 3.025 V3 10 50 3.025 D1 9 8 DX D2 10 9 DX * * NEGATIVE ZERO AT 15 MHZ * R6 11 12 1E6 R7 12 98 1 E2 11 98 9 24 1E6 VX1 84 0 EX1 83 0 11 12 1 FX1 11 12 VX1 -1 CX1 83 84 10.6E-15 * * POLE AT 20 MHZ * R8 13 98 1E3 C5 13 98 7.96E-12 G2 98 13 12 24 1E-3 * * POLE AT 20 MHZ * R9 14 98 1E3 C6 14 98 7.96E-12 G3 98 14 13 24 1E-3 * * POLE AT 20 MHZ * R10 15 98 1E3 C7 15 98 7.96E-12 G4 98 15 14 24 1E-3 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 300 HZ * R11 16 17 1E6 C8 16 17 5.3E-10 R12 17 98 1 E3 16 98 POLY(2) 1 98 2 98 0 1.585 1.585 * * POLE AT 20 MHZ * R13 18 98 1E3 C9 18 98 7.96E-12 G5 98 18 15 24 1E-3 * * OUTPUT STAGE * R14 24 99 2000E3 R15 24 50 2000E3 FSY 99 50 POLY(2) V7 V8 -98.7E-3 1 1 R16 29 99 360 R17 29 50 360 L1 29 30 1E-8 G8 29 99 99 18 2.78E-3 G9 50 29 18 50 2.78E-3 V4 25 29 2.0 V5 29 26 2.0 D3 18 25 DX D4 26 18 DX F1 29 0 V4 1 F2 0 29 V5 1 G6 98 70 29 18 2.78E-3 D5 70 71 DX D6 72 70 DX V7 71 98 DC 0 V8 98 72 DC 0 * * MODELS USED * .MODEL JX PJF(BETA=9.67 VTO=-2.000 IS=0.50E-12 RD=0.1 + RS=0.1 CGD=1E-15 CGS=1E-15) .MODEL DX D(IS=1E-15 RS=10 CJO=1E-15) .ENDS AD795 *AD8002A SPICE Macro Model 11/95, Rev. A * RFD/ADS * * Copyright 1995 by Analog Devices, Inc. * * This version of the AD8002 model simulates the typical * parameters of the 'A' grade part. * * This model was developed using the +/-5V specifications. * * Refer to the "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License * Statement. * * Node assignments * Non-inverting input * | Inverting input * | | Positive supply * | | | Negative supply * | | | | Output * | | | | | .SUBCKT AD8002A 3 2 7 4 6 * ****** INPUT STAGE ****** * Q1 7 9 10 QN Q2 4 9 11 QP Q3 14 11 15 QN Q4 16 10 15 QP I1 10 4 DC 2.568e-4 I2 7 11 DC 2.568e-4 D1 17 14 DX D2 16 18 DX V2 18 4 DC -4.41135e-2 V1 7 17 DC -4.41135e-2 R1 14 7 1E3 R2 4 16 1E3 CS1 7 2 .235e-12 CS2 2 4 .235e-12 CIN 3 4 1.5E-12 LIN- 15 2 .9e-9 GB1 7 3 POLY(1) 3 100 (3e-6,0.2e-6) GB2 7 2 POLY(1) 3 100 (5e-6,0.3e-6) EOS 3 9 POLY(1) 100 23 (2E-3,1) * ****** GAIN STAGE ******** * V3 7 20 DC 2.4 V4 21 4 DC 2.4 R3 100 19 9e5 C1 19 100 6.1e-13 D3 19 20 DX D4 21 19 DX G1 100 19 POLY(1) 7 14 (0.0,1E-3) G2 19 100 POLY(1) 16 4 (0.0,1E-3) EREF 100 0 POLY(2) (7,0) (4,0) (0,0.5,0.5) * ****** CMRR STAGE ****** * CCM 22 23 4.56424e-13 RCM2 100 23 1 RCM1 23 22 1e4 ECM 22 100 POLY(1) 100 3 (0.0,31.668) * ****** POLE STAGE AT ****** * C3 100 24 2.273642e-16 R5 24 100 1e6 G4 100 24 POLY(1) 19 100 (0.0,1E-6) * ****** POLE STAGE AT ****** * C4 25 100 3.978877e-17 R6 25 100 1e6 G5 100 25 POLY(1) 24 100 (0.0,1E-6) * ****** OUTPUT STAGE ****** * RO1 33 7 21.4 RO2 4 33 21.4 VW 25 30 DC 0 VSC1 31 33 DC .58 VSC2 33 32 DC .58 LO 33 6 2e-9 DSC2 32 30 DX DSC1 30 31 DX GO1 33 7 POLY(1) 7 30 (0.0,4.6728972e-2) GO2 4 33 POLY(1) 30 4 (0.0,4.6728972e-2) * VSY1 36 100 DC 0 VSY2 100 37 DC 0 DSY1 35 36 DX DSY2 37 35 DX FSY 7 4 POLY(2) VSY1 VSY2 (4.7326E-3,1,1) GSY 100 35 33 30 4.6728972E-2 * .MODEL QN NPN(BF=100 IS=1E-15) .MODEL QP PNP(BF=100 IS=1E-15) .MODEL DX D(IS=1E-15) .ENDS AD8002A * AD812 SPICE Macro-model 12/93, Rev. A * JCB / PMI * * Copyright 1993 by Analog Devices, Inc. * * This model was developed using the +-5V specifications. * * Refer to "README.DOC" file for License Statement. * Use of this model indicates your acceptance with * the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD812 1 2 99 50 28 * * INPUT STAGE * R1 99 8 1E3 R2 10 50 1E3 V1 99 9 1.3 D1 9 8 DX V2 11 50 1.3 D2 10 11 DX I1 99 5 140E-6 I2 4 50 140E-6 Q1 5 5 3 QN Q2 4 4 3 QP Q3 8 5 2 QN Q4 10 4 2 QP * * INPUT ERROR SOURCES * GB1 99 1 POLY(1) 1 22 0.3E-6 0.07E-6 GB2 99 2 POLY(1) 1 22 7E-6 2E-6 EOS 3 1 POLY(1) 16 22 2E-3 1 CS2 50 2 1.7E-12 CIN 1 50 1.7E-12 * EREF 98 0 22 0 1 * * GAIN STAGE & DOMINANT POLE * R5 12 98 1.2E6 C3 12 98 3.8E-12 G1 98 12 99 8 1E-3 G2 12 98 10 50 1E-3 V3 99 13 1.1 V4 14 50 1.1 D3 12 13 DX D4 14 12 DX * * POLE AT 200 MHZ * R6 17 98 1E6 C4 17 98 0.795E-15 G3 98 17 12 22 1E-6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 19 KHZ * R7 15 16 1E4 R8 16 98 1 C5 15 16 30E-12 E3 98 15 1 22 7.0 * * POLE AT 150 MHZ * R9 21 98 1E6 C6 21 98 1.06E-15 G4 98 21 17 22 1E-6 * * OUTPUT STAGE * R10 22 99 8E3 R11 22 50 8E3 R12 27 99 60 R13 27 50 60 L2 27 28 1E-8 G5 27 99 99 21 16.67E-3 G6 50 27 21 50 16.67E-3 V5 23 27 1.75 V6 27 24 1.75 D5 21 23 DX D6 24 21 DX G7 98 35 (27,21) 16.67E-3 D7 35 36 DX D8 37 35 DX V7 36 98 DC 0 V8 98 37 DC 0 F1 99 50 POLY(2) V7 V8 2.604E-3 1 1 * * MODELS USED * .MODEL QN NPN(BF=1E3 IS=1E-15) .MODEL QP PNP(BF=1E3 IS=1E-15) .MODEL DX D(IS=1E-15) .ENDS * AD815 Spice Macro-model 9/96, Rev A * * Copyright 1996 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. * Use of this model indicates your acceptance with * the terms and provisions in the License Statement. * This model will give typical performance characteristics * for the following parameters; * closed loop gain and phase vs bandwidth * output current and voltage limiting * offset voltage (is static, will not vary with vcm) * ibias (again, is static, will not vary with vcm) * slew rate and step response performance * (slew rate is based on 10-90% of step response) * current on output will be reflected to the supplies * vnoise, referred to the input * inoise, referred to the input * distortion is not characterized * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD815an 1 2 99 50 61 ***** Input Stage q1 50 41 4 qp1 q2 99 41 3 qn1 i1 99 4 1e-4 i2 3 50 1e-4 fni 99 2 vn2 1 fnn 99 1 vn2 0.1 ibneg 2 99 10e-6 ibpos 1 99 2e-6 cin1 4 88 1.4pf cin2 2 88 1.4pf q3 9 4 2 qn2 q4 10 3 2 qp2 rxxa 99 4 28k rxxb 3 50 28k VT1 99 9 0 ;ammeters for monitoring VT2 50 10 0 ;current thru Q3, Q4 eos 41 1 poly(1) 43 88 5e-3 1 ***** internal vnoise source dn1 42 88 dnv rn1 42 88 5e-3 vn1 42 88 0 hn1 43 88 vn1 1 rn2 43 88 1 ***** internal inoise source dn2 72 88 dniinv rn3 72 88 50 vn2 72 88 0 hn2 73 88 vn2 1 rn4 73 88 1 ***** internal reference Eref 88 0 poly(2) 99 0 50 0 0 0.5 0.5 ***** gain stage/dominant pole/clamp circuitry f3 88 31 vt1 0.7e-4 f4 88 31 vt2 0.7e-4 dgain1 88 31 dy dgain2 31 88 dy egain1 28 88 31 88 143000 r3 28 29 5 c1 29 88 4500nf vc1 99 45 3.65 vc2 46 50 3.65 dc1 29 45 dx dc2 46 29 dx ***** pole at 100MHz egain2 32 88 88 29 1 r4 32 44 0.001 c3 44 88 1500000p ***** buffer to output stage gbuf 34 88 44 88 1e-2 re1 34 88 100 ***** output stage fo1 88 110 vcd 1 do1 110 111 dx do2 112 110 dx vi1 111 88 0 vi2 88 112 0 fsy 99 50 poly(2) vi1 vi2 5.61e-4 1 1 go3 60 99 99 34 0.385 go4 50 60 34 50 0.385 r03 60 99 2.6 r04 60 50 2.6 vcd 60 62 0 lo1 62 61 1e-10 ro2 61 88 1e9 do5 34 70 dx do6 71 34 dx vo1 70 60 0.45 vo2 60 71 0.45 .model dx d(is=1e-13 kf=1e-30 af=0) .model dy d(is=26e-9 kf=1e-30 af=0) .model dnv d(is=1e-15 kf=2e-15 af=0) .model dniinv d(is=1e-15 kf=1e-19 af=0) .model qn1 npn(bf=200 kf=1e-30 af=0) .model qn2 npn(bf=200 kf=1e-30 af=0) .model qp1 pnp(bf=200 kf=1e-30 af=0) .model qp2 pnp(bf=200 kf=1e-30 af=0) .ends ad815an * AD817 SPICE Macro-model Rev. A, 11/92 * ARG / ADI * * Copyright 1993 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of * this model indicates your acceptance of the terms and pro- * visions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD817 2 1 99 50 46 * * INPUT STAGE AND POLE AT 160MHZ * I1 8 50 1E-3 Q1 4 1 6 QN Q2 5 3 7 QN CIN 1 2 1.5PF R1 99 4 1.188K R2 99 5 1.188K C1 4 5 4.187E-13 R3 6 8 1.137K R4 7 8 1.137K IOS 1 2 12.5E-9 EOS 3 2 POLY(1) (15,98) 0.5E-3 10 * * GAIN STAGE AND DOMINANT POLE AT 8.8KHZ * EREF 98 0 POLY(2) (99,0) (50,0) 0 0.5 0.5 G1 98 9 (4,5) .8415E-3 R5 9 98 5.942E6 C2 9 98 3.045E-12 D1 9 10 DX D2 11 9 DX V1 99 10 1.83 V2 11 50 1.83 * * COMMON MODE STAGE WITH ZERO AT 3.16KHZ * ECM 14 98 POLY(2) (1,98) (2,98) 0 0.5 0.5 R7 14 15 1E6 C4 14 15 5.036E-11 R8 15 98 1 * *POLE AT 120MHZ * GP2 98 31 (9,98) 1E-6 RP2 31 98 1E6 CP2 31 98 1.326E-15 * *ZERO AT 60MHZ * EZ1 32 98 (31,98) 1E6 RZ1 32 33 1E6 RZ2 33 98 1 CZ1 32 33 2.65E-15 * *ZERO AT 100MHZ * EZ2 34 98 (33,98) 1E6 RZ3 34 35 1E6 RZ4 35 98 1 CZ2 34 35 1.59E-15 * *POLE AT 120MHZ * GP3 98 36 (35,98) 1E-6 RP3 36 98 1E6 CP3 36 98 1.326E-15 * *POLE AT 160MHZ * GP10 98 40 (36,98) 1E-6 RP10 40 98 1E6 CP10 40 98 .995E-15 * * OUTPUT STAGE * RO1 99 45 16 RO2 45 50 16 G7 45 99 (99,40) 62.5E-3 G8 50 45 (40,50) 62.5E-3 G9 98 60 (45,40) 62.5E-3 D7 60 61 DX D8 62 60 DX V7 61 98 DC 0 V8 98 62 DC 0 GSY 99 50 (99,50) 7.692E-6 FSY 99 50 POLY(2) V7 V8 5.77E-3 1 1 D9 41 45 DX D10 45 42 DX V5 40 41 0.04 V6 42 40 0.04 LO 45 46 .06E-9 * * MODELS USED * .MODEL DX D .MODEL QN NPN(BF=151.52) .ENDS * AD818 SPICE Model Rev. A, 4/93 * ARG / PMI * * Copyright 1993 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of * this model indicates your acceptance of the terms and pro- * visions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD818 2 1 99 50 45 * * INPUT STAGE AND POLE AT 400MHZ * I1 4 50 1E-3 CIN 1 2 1.5E-12 IOS 2 1 12.5E-9 Q1 5 1 7 QN Q2 6 3 8 QN R3 99 5 833 R4 99 6 833 R5 7 4 782 R6 8 4 782 C1 5 6 239E-15 EOS 3 2 POLY(1) (13,98) 500E-6 0.1 * * GAIN STAGE AND DOMINANT POLE AT 10.6KHZ * EREF 98 0 (39,0) 1 G1 98 9 (5,6) 1.2E-3 R7 9 98 7.5E6 C2 9 98 2E-12 D1 9 10 DX D2 11 9 DX V1 99 10 1.8 V2 11 50 1.8 * * COMMON MODE GAIN STAGE WITH ZERO AT 100HZ * ECM 12 98 POLY(2) (1,39) (2,39) 0 0.5 0.5 R8 12 13 1E6 R9 13 98 10 C3 12 13 1.592E-9 * * NEGATIVE ZERO AT 150MHZ * E1 14 98 (9,39) 1E6 R11 14 15 1 R12 15 98 1E-6 FNZ 14 15 VNZ -1 ENZ 16 98 (14,15) 1 VNZ 17 98 DC 0 CNZ 16 17 1.061E-9 * * ZERO/POLE AT 20MHZ/25MHZ * E2 18 98 (15,39) 1.25 R13 18 19 1 R14 19 98 4 C5 18 19 7.958E-9 * * POLE AT 400MHZ * G2 98 40 (19,39) 1E-6 R10 40 98 1E6 C4 40 98 .398E-15 * * OUTPUT STAGE * RS1 99 39 65E3 RS2 39 50 65E3 RO1 99 45 16 RO2 45 50 16 G7 45 99 (99,40) 62.5E-3 G8 50 45 (40,50) 62.5E-3 G9 98 60 (45,40) 62.5E-3 D7 60 61 DX D8 62 60 DX V7 61 98 DC 0 V8 98 62 DC 0 FSY 99 50 POLY(2) V7 V8 5.77E-3 1 1 D9 41 45 DX D10 45 42 DX V5 40 41 0.18 V6 42 40 0.18 .MODEL QN NPN(BF=151.52) .MODEL DX D() .ENDS AD818 * AD820 SPICE Macro-model 8/91, Rev. A * JCB / PMI * * Copyright 1993 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. * Use of this model indicates your acceptance with * the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD820 1 2 99 50 25 * * INPUT STAGE & POLE AT 3 MHZ * R3 5 99 2456 R4 6 99 2456 CIN 1 2 5E-12 C2 5 6 10.8E-12 I1 4 50 108E-6 IOS 1 2 1E-12 EOS 7 1 POLY(1) (12,98) 100E-6 1 J1 4 2 5 JX J2 4 7 6 JX * EREF 98 0 30 0 1 * * GAIN STAGE & POLE AT 124 HZ * R5 9 98 2.46E6 C3 9 25 35E-12 G1 98 9 6 5 4.07E-4 V1 8 98 0 V2 98 10 -1 D1 9 10 DX D2 8 9 DX * * COMMON-MODE GAIN NETWORK WITH ZERO AT 1 KHZ * R21 11 12 1E6 R22 12 98 1 C14 11 12 159E-12 E13 11 98 POLY(2) (2,98) (1,98) 0 50 50 * * POLE AT 10 MHZ * R23 18 98 1E6 C15 18 98 15.9E-15 G15 98 18 9 98 1E-6 * * OUTPUT STAGE * ES 26 51 POLY(1) (18,98) 1.72 1 RS 26 22 500 V3 23 51 1.1 V4 21 23 1.36 C16 20 25 2E-12 C17 24 25 2E-12 RG1 20 97 1E8 RG2 24 97 1E8 Q1 20 20 97 PNP Q2 20 21 22 NPN Q3 24 23 22 PNP Q4 24 24 51 NPN Q5 25 20 97 PNP 20 Q6 25 24 51 NPN 20 VP 96 97 0 VN 51 52 0 EP 96 0 POLY(1) (99,0) 0.01 1 EN 52 0 POLY(1) (50,0) -0.015 1 * R25 30 99 5E6 R26 30 50 5E6 FSY1 99 0 VP 1 FSY2 0 50 VN 1 * * MODELS USED * .MODEL JX NJF(BETA=7.67E-4 VTO=-2.000 IS=1E-12) .MODEL NPN NPN(BF=120 VAF=150 VAR=15 RB=2E3 + RE=4 RC=200 IS=1E-16) .MODEL PNP PNP(BF=80 VAF=150 VAR=15 RB=2E3 + RE=4 RC=900 IS=1E-16) .MODEL DX D(IS=1E-15) .ENDS AD820 * AD822 SPICE Macro-model 2/95, Rev. A * ARG / ADSC * * Copyright 1995 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. * Use of this model indicates your acceptance with * the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD822 1 2 99 50 25 * * INPUT STAGE & POLE AT 5 MHZ * R3 5 99 2456 R4 6 99 2456 CIN 1 2 5E-12 C2 5 6 6.48E-12 I1 4 50 108E-6 IOS 1 2 1E-12 EOS 7 1 POLY(1) (12,98) 100E-6 1 J1 5 2 4 JX J2 6 7 4 JX GB1 50 2 POLY(3) (2,4) (2,5) (2,50) 0 1E-12 1E-12 1E-12 GB2 50 7 POLY(3) (7,4) (7,5) (7,50) 0 1E-12 1E-12 1E-12 * * GAIN STAGE & POLE AT 13.4 HZ * EREF 98 0 (30,0) 1 R5 9 98 2.313E6 C3 9 25 32E-12 G1 98 9 (6,5) 4.07E-4 V1 8 98 0 V2 98 10 -1 D1 9 10 DX D2 8 9 DX * * COMMON-MODE GAIN NETWORK WITH ZERO AT 1 KHZ * R21 11 12 1E6 R22 12 98 100 C14 11 12 159E-12 E13 11 98 POLY(2) (2,98) (1,98) 0 0.5 0.5 * * POLE AT 10 MHZ * R23 18 98 1E6 C15 18 98 15.9E-15 G15 98 18 (9,98) 1E-6 * * OUTPUT STAGE * ES 26 51 POLY(1) (18,98) 1.72 1 RS 26 22 500 V3 23 51 1.03951 V4 21 23 1.36 C16 20 25 2E-12 C17 24 25 2E-12 RG1 20 97 1E8 RG2 24 97 1E8 Q1 20 20 97 PNP Q2 20 21 22 NPN Q3 24 23 22 PNP Q4 24 24 51 NPN Q5 25 20 97 PNP 20 Q6 25 24 51 NPN 20 VP 96 97 0 VN 51 52 0 EP 96 0 POLY(1) (99,0) 0.01 1 EN 52 0 POLY(1) (50,0) -0.015 1 R25 30 99 63.5E3 R26 30 50 63.5E3 FSY1 99 0 VP 1 FSY2 0 50 VN 1 * * MODELS USED * .MODEL JX NJF(BETA=7.67E-4 VTO=-2.000 IS=1E-12) .MODEL NPN NPN(BF=120 VAF=150 VAR=15 RB=2E3 RE=4 RC=200) .MODEL PNP PNP(BF=120 VAF=150 VAR=15 RB=2E3 RE=4 RC=900) .MODEL DX D(IS=1E-15) .ENDS AD822 * AD822S SPICE Macro-model 2/95, Rev. A * ARG / ADSC * * This version of the AD822 model simulates the worst-case * parameters of the 'S' grade. The worst-case parameters * used correspond to those in the data sheet. * * Copyright 1995 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. * Use of this model indicates your acceptance with * the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD822S 1 2 99 50 25 * * INPUT STAGE & POLE AT 5MHZ * R3 5 99 2456 R4 6 99 2456 CIN 1 2 5E-12 C2 5 6 6.48E-12 I1 4 50 108E-6 IOS 1 2 1E-11 EOS 7 1 POLY(1) (12,98) 800E-6 2.41 J1 5 2 4 JX J2 6 7 4 JX GB1 50 2 POLY(3) (2,4) (2,5) (2,50) 0 1E-12 1E-12 1E-12 GB2 50 7 POLY(3) (7,4) (7,5) (7,50) 0 1E-12 1E-12 1E-12 * EREF 98 0 (30,0) 1 * * GAIN STAGE & POLE AT 25 HZ * R5 9 98 1.234E6 C3 9 25 32E-12 G1 98 9 (6,5) 4.07E-4 V1 8 98 0 V2 98 10 -1 D1 9 10 DX D2 8 9 DX * * COMMON-MODE GAIN NETWORK WITH ZERO AT 5 KHZ * R21 11 12 1E6 R22 12 98 200 C14 11 12 32.25E-12 E13 11 98 POLY(2) (2,98) (1,98) 0 0.5 0.5 * * POLE AT 10 MHZ * R23 18 98 1E6 C15 18 98 15.9E-15 G15 98 18 (9,98) 1E-6 * * OUTPUT STAGE * ES 26 51 POLY(1) (18,98) 1.72 1 RS 26 22 500 V3 23 51 1.03951 V4 21 23 1.36 C16 20 25 2E-12 C17 24 25 2E-12 RG1 20 97 1E8 RG2 24 97 1E8 Q1 20 20 97 PNP Q2 20 21 22 NPN Q3 24 23 22 PNP Q4 24 24 51 NPN Q5 25 20 97 PNP 20 Q6 25 24 51 NPN 20 VP 96 97 0 VN 51 52 0 EP 96 0 POLY(1) (99,0) 0.01 1 EN 52 0 POLY(1) (50,0) -0.015 1 R25 30 99 275E3 R26 30 50 275E3 FSY1 99 0 POLY(1) VP 210.5E-6 1 FSY2 0 50 POLY(1) VN 210.5E-6 1 * * MODELS USED * .MODEL JX NJF(BETA=7.67E-4 VTO=-2.000 IS=12.5E-12) .MODEL NPN NPN(BF=120 VAF=150 VAR=15 RB=2E3 RE=4 RC=200) .MODEL PNP PNP(BF=120 VAF=150 VAR=15 RB=2E3 RE=4 RC=900) .MODEL DX D(IS=1E-15) .ENDS AD822S * AD826 SPICE Macro-model Rev. A, 11/92 * ARG / ADI * * Copyright 1993 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of * this model indicates your acceptance of the terms and pro- * visions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD826 2 1 99 50 46 * * INPUT STAGE AND POLE AT 160MHZ * I1 8 50 1E-3 Q1 4 1 6 QN Q2 5 3 7 QN CD 1 2 1.5E-12 CC1 1 0 2.4E-12 CC2 2 0 2.4E-12 R1 99 4 1.114E3 R2 99 5 1.114E3 C1 4 5 .446E-12 R3 6 8 1.062E3 R4 7 8 1.062E3 IOS 1 2 25E-9 EOS 3 2 POLY(1) (15,39) 0.5E-3 .1 * * GAIN STAGE AND DOMINANT POLE AT 8.333KHZ * EREF 98 0 (39,0) 1 G1 98 9 (4,5) .898E-3 R5 9 98 6.685E6 C2 9 98 2.857E-12 D1 9 10 DX D2 11 9 DX V1 99 10 1.83 V2 11 50 1.83 * * COMMON MODE STAGE WITH ZERO AT 316HZ * ECM 14 98 POLY(2) (1,39) (2,39) 0 0.5 0.5 R7 14 15 1E6 C4 14 15 503.3E-12 R8 15 98 10 * *POLE AT 120MHZ * GP2 98 31 (9,39) 1E-6 RP2 31 98 1E6 CP2 31 98 1.326E-15 * *ZERO AT 75MHZ * EZ1 32 98 (31,39) 1E6 RZ1 32 33 1E6 RZ2 33 98 1 CZ1 32 33 2.12E-15 * *ZERO AT 100MHZ * EZ2 34 98 (33,39) 1E6 RZ3 34 35 1E6 RZ4 35 98 1 CZ2 34 35 1.59E-15 * *POLE AT 160MHZ * GP3 98 36 (35,39) 1E-6 RP3 36 98 1E6 CP3 36 98 .995E-15 * *POLE AT 160MHZ * GP10 98 40 (36,39) 1E-6 RP10 40 98 1E6 CP10 40 98 .995E-15 * * OUTPUT STAGE * RS1 99 39 65.217E3 RS2 39 50 65.217E3 RO1 99 45 16 RO2 45 50 16 G7 45 99 (99,40) 62.5E-3 G8 50 45 (40,50) 62.5E-3 G9 98 60 (45,40) 62.5E-3 D7 60 61 DX D8 62 60 DX V7 61 98 DC 0 V8 98 62 DC 0 FSY 99 50 POLY(2) V7 V8 5.77E-3 1 1 D9 41 45 DX D10 45 42 DX V5 40 41 .4 V6 42 40 .4 LO 45 46 .06E-9 * * MODELS USED * .MODEL DX D(IS=1E-12) .MODEL QN NPN(BF=150.52) .ENDS AD826* AD828 SPICE Model Rev. A, 4/93 * ARG / PMI * * Copyright 1993 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of * this model indicates your acceptance of the terms and pro- * visions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD828 2 1 99 50 46 * * INPUT STAGE AND POLE AT 500MHZ * I1 4 50 1E-3 CIN 1 2 1.5E-12 CC1 1 0 .5E-12 CC2 2 0 .5E-12 IOS 2 1 25E-9 Q1 5 1 7 QN Q2 6 3 8 QN R3 99 5 884 R4 99 6 884 R5 7 4 832 R6 8 4 832 C1 5 6 180E-15 EOS 3 2 POLY(1) (21,98) 500E-6 0.1 * * GAIN STAGE AND DOMINANT POLE AT 10KHZ * EREF 98 0 (39,0) 1 G1 98 9 (5,6) 1.131E-3 R7 9 98 7.958E6 C2 9 98 2E-12 D1 9 10 DX D2 11 9 DX V1 99 10 1.8 V2 11 50 1.8 * * NEGATIVE ZERO AT 150MHZ * E1 14 98 (9,39) 1E6 R11 14 15 1 R12 15 98 1E-6 FNZ 14 15 VNZ -1 ENZ 16 98 (14,15) 1 VNZ 17 98 DC 0 CNZ 16 17 1.061E-9 * * ZERO/POLE AT 60MHZ/75MHZ * E2 18 98 (15,39) 1.25 R13 18 19 1 R14 19 98 4 C5 18 19 2.653E-9 * * COMMON MODE GAIN STAGE WITH ZERO AT 100HZ * ECM 20 98 POLY(2) (1,39) (2,39) 0 0.5 0.5 R8 20 21 1E6 R9 21 98 10 C3 20 21 1.592E-9 * * POLE AT 400MHZ * G2 98 40 (19,39) 1E-6 R10 40 98 1E6 C4 40 98 .398E-15 * * OUTPUT STAGE * RS1 99 39 65E3 RS2 39 50 65E3 RO1 99 45 16 RO2 45 50 16 G7 45 99 (99,40) 62.5E-3 G8 50 45 (40,50) 62.5E-3 G9 98 60 (45,40) 62.5E-3 D7 60 61 DX D8 62 60 DX V7 61 98 DC 0 V8 98 62 DC 0 FSY 99 50 POLY(2) V7 V8 5.77E-3 1 1 D9 41 45 DX D10 45 42 DX V5 40 41 0.4 V6 42 40 0.4 LO 45 46 5E-8 .MODEL QN NPN(BF=150.52) .MODEL DX D(IS=1E-12) .ENDS AD828* AD829 SPICE Macro-model 9/90, Rev. A * JCB / PMI * * Copyright 1990 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | compensation node * | | | | | | .SUBCKT AD829 1 2 99 50 30 12 * * INPUT STAGE & POLE AT 200 MHZ * R1 2 3 17.8E3 R2 1 3 17.8E3 R3 5 99 56.4 R4 6 99 56.4 CIN 1 2 5E-12 C2 5 6 7.18E-12 I1 4 50 1.2E-3 IOS 1 2 25E-9 EOS 9 1 POLY(1) 19 23 0.2E-3 1 Q1 5 2 10 QX Q2 6 9 11 QX R5 10 4 13.4 R6 11 4 13.4 * EREF 98 0 23 0 1 * * GAIN STAGE & DOMINANT POLE AT 5.4 KHZ * R7 12 98 5.64E6 C3 12 98 5.2E-12 G1 98 12 5 6 17.73E-3 V2 99 13 2.1 V3 14 50 2.1 D3 12 13 DX D4 14 12 DX * * ZERO/POLE PAIR AT 50MHz/100MHz * R8 15 16 1E6 R9 16 98 1E6 L1 16 98 1.59E-3 G2 98 15 12 23 1E-6 * * POLE AT 400 MHZ * R41 41 98 1E6 C41 41 98 398E-18 G41 98 41 15 23 1E-6 * * POLE AT 400 MHZ * R42 42 98 1E6 C42 42 98 398E-18 G42 98 42 41 23 1E-6 * * POLE AT 200 MHZ * R43 43 98 1E6 C43 43 98 796E-18 G43 98 43 42 23 1E-6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 3 kHZ * R11 18 19 1E6 C6 18 19 53.1E-12 R12 19 98 1 E2 18 98 3 23 1 * * POLE AT 400 MHZ * R15 22 98 1E6 C8 22 98 398E-18 G3 98 22 43 23 1E-6 * * OUTPUT STAGE * RF 25 60 500 CF 60 12 12.5E-12 R16 23 99 100E3 R17 23 50 100E3 ISY 99 50 3.95E-3 R18 25 99 30 R19 25 50 30 L2 25 30 1E-8 G4 28 50 22 25 33.33E-3 G5 29 50 25 22 33.33E-3 G6 25 99 99 22 33.33E-3 G7 50 25 22 50 33.33E-3 V4 26 25 -0.2 V5 25 27 -0.2 D5 22 26 DX D6 27 22 DX D7 99 28 DX D8 99 29 DX D9 50 28 DY D10 50 29 DY * * MODELS USED * .MODEL QX NPN(BF=181.8) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * AD840 SPICE Macro-model 1/91, Rev. A * AAG / PMI * * Copyright 1991 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD840 1 2 100 101 36 * * INPUT STAGE & POLE AT 120 MHz * IOS 1 2 DC 0.05E-6 CIN 1 2 2E-12 R1 1 3 15E3 R2 2 3 15E3 EOS 9 1 POLY(1) 16 11 200E-6 1 R3 100 5 223.38 R4 100 6 223.38 C2 5 6 2.9687E-12 R5 7 4 171.66 R6 8 4 171.66 Q1 5 2 7 QX Q2 6 9 8 QX I1 4 101 DC 1E-3 * * VIRTUAL NODE * RVN1 100 10 25E3 RVN2 10 101 25E3 * * GAIN STAGE & DOMINANT POLE AT 2.1923 KHz * EREF 11 0 10 0 1 G1 11 12 5 6 4.4768E-3 R7 12 11 29.039E6 C3 12 11 2.5E-12 V1 100 13 DC 2.4375 D1 12 13 DX V2 14 101 DC 2.4375 D2 14 12 DX * * COMMON-MODE GAIN NETWORK WITH ZERO AT 20 KHz * ECM 15 11 3 11 3.1623 RCM1 15 16 1E6 CCM 15 16 7.9577E-12 RCM2 16 11 1 * * NEGATIVE ZERO STAGE AT 290 MHz * EZ1 17 11 12 11 1E6 RZ1 17 18 1 CZ1 17 18 -548.81E-12 RZ2 18 11 1E-6 * * POLE STAGE AT 500 MHz * GP1 11 19 18 11 1E-6 RP1 19 11 1E6 CP1 19 11 318.31E-18 * * OUTPUT STAGE * IDC 100 101 DC 8.9E-3 VX 19 30 V3 32 35 DC 2.725 D3 30 32 DX V4 35 33 DC 2.575 D4 33 30 DX D5 100 31 DX GO1 31 101 30 35 16.667E-3 D6 101 31 DY D7 100 34 DX GO2 34 101 35 30 16.667E-3 D8 101 34 DY RO1 100 35 60 GO3 35 100 100 30 16.667E-3 RO2 35 101 60 GO4 101 35 30 101 16.667E-3 LO 35 36 0.04E-6 * * MODELS USED * .MODEL QX NPN(BF=142.86) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * AD843 SPICE Macro-model 1/92, Rev. A * JCB / PMI * * Copyright 1991 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD843 1 2 99 50 30 * * INPUT STAGE & POLE AT 150 MHZ * R1 1 3 5E11 R2 2 3 5E11 R3 5 50 1084.2 R4 6 50 1084.2 CIN 1 2 4E-12 C2 5 6 0.489E-12 I1 99 4 1.0E-3 IOS 1 2 1E-10 EOS 7 1 POLY(1) 16 24 500E-6 1 J1 5 2 4 JX J2 6 7 4 JX * EREF 98 0 24 0 1 * * GAIN STAGE & POLE AT 1.23 KHZ * R5 9 98 3.25E7 C3 9 98 4.0E-12 G1 98 9 5 6 9.22E-4 V2 99 8 3.8 V3 10 50 2.7 D1 9 8 DX D2 10 9 DX * * POLE AT 200 MHZ * R6 11 98 1E6 C4 11 98 0.796E-15 G2 98 11 9 24 1E-6 * * NEGATIVE ZERO AT 100 MHZ * R8 13 14 1E6 R9 14 98 1 C6 13 14 -1.59E-15 E2 13 98 11 24 1000001 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 19 KHZ * R10 15 16 1E6 R11 16 98 1 C7 15 16 8.368E-12 E3 98 15 3 24 158.5 * * POLE AT 200 MHZ * R12 23 98 1E6 C8 23 98 0.796E-15 G4 98 23 14 24 1E-6 * * OUTPUT STAGE * R13 24 99 50E3 R14 24 50 50E3 ISY 99 50 10.7E-3 R15 29 99 40 R16 29 50 40 L1 29 30 6E-8 G5 27 50 23 29 2.5E-2 G6 28 50 29 23 2.5E-2 G7 29 99 99 23 2.5E-2 G8 50 29 23 50 2.5E-2 V4 25 29 0.7 V5 29 26 0.7 D3 23 25 DX D4 26 23 DX D5 99 27 DX D6 99 28 DX D7 50 27 DY D8 50 28 DY * * MODELS USED * .MODEL JX PJF(BETA=4.25E-4 VTO=-2.000 IS=6E-10) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * AD845 SPICE Macro-model 12/90, Rev. A * AAG / PMI * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD845 1 2 100 101 36 * * INPUT STAGE & POLE AT 170 MHz * R1 1 3 5E10 R2 2 3 5E10 R3 100 5 820.39 R4 100 6 820.39 CIN 1 2 4E-12 C2 5 6 570.59E-15 I1 4 101 1E-3 IOS 1 2 DC 7.5E-12 EOS 7 1 POLY(1) 13 14 100E-6 1 J1 5 2 4 JX J2 6 7 4 JX * * GAIN STAGE & DOMINANT POLE AT 77.6 HZ * EREF 8 0 14 0 1 G1 8 9 5 6 1.2189E-3 R5 9 8 205.1E6 C3 9 8 10E-12 V1 100 10 DC 2.8125 D1 9 10 DX V2 11 101 DC 2.8125 D2 11 9 DX * * COMMON-MODE GAIN NETWORK WITH ZERO AT 10 KHZ * ECM 12 8 3 14 3.1623 RCM1 12 13 1E6 RCM2 13 8 1 CCM 12 13 15.915E-12 * * VIRTUAL NODE * RVN1 100 14 17.33E3 RVN2 14 101 17.33E3 * * POLE STAGE AT 170 MHz * GP1 8 15 9 14 1E-6 RP1 15 8 1E6 CP1 15 8 0.93621E-15 * * NEGATIVE ZERO STAGE AT 46 MHz * EZ1 16 8 15 14 1E6 RZ1 16 17 1 RZ2 17 8 1E-6 CZ1 16 17 -3.4599E-9 * * POLE STAGE AT 170 MHz * GP2 8 18 17 14 1E-6 RP2 18 8 1E6 CP2 18 8 0.93621E-15 * * OUTPUT STAGE * IDC 100 101 DC 8.134E-3 VX 18 30 V3 32 35 DC 0.15 D3 30 32 DX V4 35 33 DC 0.15 D4 33 30 DX D5 100 31 DX GO1 31 101 30 35 33.33E-3 D6 101 31 DY D7 100 34 DX GO2 34 101 35 30 33.33E-3 D8 101 34 DY RO1 100 35 30 GO3 35 100 100 30 33.33E-3 RO2 35 101 30 GO4 101 35 30 101 33.33E-3 LO 35 36 45E-9 * * MODELS USED * .MODEL JX NJF(VTO=-2 BETA=742.9E-6 IS=2.5E-10) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * AD847 SPICE Macro-model 12/90, Rev. A * JCB / PMI * * Copyright 1990 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | * | | | | | .SUBCKT AD847 1 2 99 50 30 * * INPUT STAGE & POLE AT 300 MHZ * R1 2 3 5E11 R2 1 3 5E11 R3 5 99 443 R4 6 99 443 CIN 1 2 1.5E-12 C2 5 6 0.599E-12 I1 4 50 2.22E-3 IOS 1 2 25E-9 EOS 9 1 POLY(1) 19 23 0.5E-3 1 Q1 5 2 10 QX Q2 6 9 11 QX R5 10 4 419.8 R6 11 4 419.8 * EREF 98 0 23 0 1 * * GAIN STAGE & DOMINANT POLE AT 8.8 KHZ * R7 12 98 2.44E6 C3 12 98 7.4E-12 G1 98 12 5 6 2.25E-3 V2 99 13 0.8 V3 14 50 0.8 D3 12 13 DX D4 14 12 DX * * ZERO/POLE PAIR AT 70MHz/200MHz * R8 15 16 1E6 R9 16 98 1.86E6 L1 16 98 1.48E-3 G2 98 15 12 23 1E-6 * * POLE AT 300 MHZ * R41 41 98 1E6 C41 41 98 531E-18 G41 98 41 15 23 1E-6 * * POLE AT 300 MHZ * R42 42 98 1E6 C42 42 98 531E-18 G42 98 42 41 23 1E-6 * * POLE AT 400 MHZ * R43 43 98 1E6 C43 43 98 398E-18 G43 98 43 42 23 1E-6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 40 kHZ * R11 18 19 1E6 C6 18 19 3.98E-12 R12 19 98 1 E2 18 98 3 23 17.8 * * POLE AT 400 MHZ * R15 22 98 1E6 C8 22 98 398E-18 G3 98 22 43 23 1E-6 * * OUTPUT STAGE * RF 30 60 500 CF 60 12 12.5E-12 R16 23 99 100E3 R17 23 50 100E3 ISY 99 50 2.95E-3 R18 25 99 90 R19 25 50 90 L2 25 30 3E-8 G4 28 50 22 25 11.11E-3 G5 29 50 25 22 11.11E-3 G6 25 99 99 22 11.11E-3 G7 50 25 22 50 11.11E-3 V4 26 25 0.8 V5 25 27 0.8 D5 22 26 DX D6 27 22 DX D7 99 28 DX D8 99 29 DX D9 50 28 DY D10 50 29 DY * * MODELS USED * .MODEL QX NPN(BF=336) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * AD848 SPICE Macro-model 3/94, Rev. B * JCB / PMI * * Revision History: * Changed Negative Zero stage to remove the * negative capacitor value. * * Copyright 1990 by Analog Devices * * Refer to "README.DOC" file for License Statement. * Use of this model indicates your acceptance with the * terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | * | | | | | .SUBCKT AD848 1 2 99 50 30 * * INPUT STAGE & POLE AT 400 MHZ * R1 2 3 5E11 R2 1 3 5E11 R3 5 99 62.5 R4 6 99 62.5 CIN 1 2 1.5E-12 C2 5 6 3.184E-12 I1 4 50 4.0E-3 IOS 1 2 25E-9 EOS 9 1 POLY(1) 20 23 0.5E-3 1 Q1 5 2 10 QX Q2 6 9 11 QX R5 10 4 49.6 R6 11 4 49.6 * EREF 98 0 23 0 1 * * GAIN STAGE & DOMINANT POLE AT 10 KHZ * R7 12 98 1.25E6 C3 12 98 12.74E-12 G1 98 12 5 6 16.0E-3 V2 99 13 1.7 V3 14 50 1.7 D3 12 13 DX D4 14 12 DX * * NEGATIVE ZERO AT 160 MHZ * R8 15 16 1E6 R9 16 98 1 FX1 15 16 VX1 -1 E1 15 98 12 23 1E6 VX1 80 0 0 EX1 81 0 15 16 1 C4 80 81 0.995E-15 * * POLE AT 400 MHZ * R10 17 98 1E6 C5 17 98 398E-18 G2 98 17 16 23 1E-6 * * POLE AT 400 MHZ * R11 18 98 1E6 C6 18 98 398E-18 G3 98 18 17 23 1E-6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 100 kHZ * R12 19 20 1E6 C7 19 20 1.59E-12 R13 20 98 1 E2 19 98 3 23 5.62 * * POLE AT 400 MHZ * R14 21 98 1E6 C8 21 98 398E-18 G4 98 21 18 23 1E-6 * * OUTPUT STAGE * RF 25 22 500 CF 22 12 12.5E-12 R16 23 99 25E3 R17 23 50 25E3 ISY 99 50 0.5E-3 R18 25 99 90 R19 25 50 90 L2 25 30 3E-8 G5 28 50 21 25 11.11E-3 G6 29 50 25 21 11.11E-3 G7 25 99 99 21 11.11E-3 G8 50 25 21 50 11.11E-3 V4 26 25 0.8 V5 25 27 0.8 D5 21 26 DX D6 27 21 DX D7 99 28 DX D8 99 29 DX D9 50 28 DY D10 50 29 DY * * MODELS USED * .MODEL QX NPN(BF=606.1) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * AD8541 SPICE Macro-model Typical Values * 6/98, Ver. 1 * TAM / ADSC * * jjt 11/9/2001: replaced pSpice sources with SPICE3 sources, changed pSpice VC switch to switch with hysteresis. * * Copyright 1998 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of this * model indicates your acceptance of the terms and provisions in * the License Statement. * * Node Assignments * noninverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | * | | | | | .SUBCKT AD8541 1 2 99 50 45 * * INPUT STAGE * M1 4 1 8 8 PIX L=0.6E-6 W=16E-6 M2 6 7 8 8 PIX L=0.6E-6 W=16E-6 M3 11 1 10 10 NIX L=0.6E-6 W=16E-6 M4 12 7 10 10 NIX L=0.6E-6 W=16E-6 RC1 4 50 20E3 RC2 6 50 20E3 RC3 99 11 20E3 RC4 99 12 20E3 C1 4 6 1.5E-12 C2 11 12 1.5E-12 I1 99 8 1E-5 I2 10 50 1E-5 V1 99 9 0.2 V2 13 50 0.2 D1 8 9 DX D2 13 10 DX *EOS 7 2 POLY(3) (22,98) (73,98) (81,0) 1E-3 1 1 1 BEOS 7 2 V = 1E-3 + V(22,98) + V(73,98) + V(81,0) IOS 1 2 2.5E-12 * * CMRR 64dB, ZERO AT 20kHz * *ECM1 21 98 POLY(2) (1,98) (2,98) 0 .5 .5 BECM1 21 98 V = 0.5*V(1,98) + 0.5*V(2,98) RCM1 21 22 79.6E3 CCM1 21 22 100E-12 RCM2 22 98 50 * * PSRR=90DB, ZERO AT 200Hz * RPS1 70 0 1E6 RPS2 71 0 1E6 CPS1 99 70 1E-5 CPS2 50 71 1E-5 *EPSY 98 72 POLY(2) (70,0) (0,71) 0 1 1 BEPSY 98 72 V = V(70,0) + V(0,71) RPS3 72 73 1.59E6 CPS3 72 73 500E-12 RPS4 73 98 25 * * VOLTAGE NOISE REFERENCE OF 35NV/RT(Hz) * VN1 80 0 0 RN1 80 0 16.45E-3 *HN 81 0 VN1 35 BHN 81 0 V = 35*I(VN1) RN2 81 0 1 * * INTERNAL VOLTAGE REFERENCE * *VFIX 90 98 DC 1 VFIX 90 98 1 S1 90 91 50 99 VSY_SWITCH *VSN1 91 92 DC 0 VSN1 91 92 0 RSY 92 98 1E3 *EREF 98 0 POLY(2) (99,0) (50,0) 0 .5 .5 BEREF 98 0 V = 0.5*V(99,0) + 0.5*V(50,0) *GSY 99 50 POLY(1) (99,50) 0 3.7E-6 BGSY 99 50 I = 3.7E-6*V(99,50) * * ADAPTIVE GAIN STAGE * AT VSY>+4.2, AVOL=45 V/MV * AT VSY<+3.8, AVOL=450 V/MV * *G1 98 30 POLY(2) (4,6) (11,12) 0 2.5E-5 2.5E-5 BG1 98 30 I = 2.5E-5*V(4,6) + 2.5E-5*V(11,12) *VR1 30 31 DC 0 VR1 30 31 0 *H1 31 98 POLY(2) VR1 VSN1 0 5.45E6 0 0 49.05E9 BH1 31 98 V = 0 + 5.45E6*I(VR1) + 49.05E9*I(VR1)*I(VSN1) CF 45 30 10E-12 D3 30 99 DX D4 50 30 DX * * OUTPUT STAGE * M5 45 46 99 99 POX L=0.6E-6 W=375E-6 M6 45 47 50 50 NOX L=0.6E-6 W=500E-6 *EG1 99 46 POLY(1) (98,30) 1.05 1 BEG1 99 46 V = 1.05 + V(98,30) *EG2 47 50 POLY(1) (30,98) 1.04 1 BEG2 47 50 V = 1.04 + V(30,98) * * MODELS * .MODEL POX PMOS (LEVEL=2,KP=20E-6,VTO=-1,LAMBDA=0.067) .MODEL NOX NMOS (LEVEL=2,KP=20E-6,VTO=1,LAMBDA=0.067) .MODEL PIX PMOS (LEVEL=2,KP=20E-6,VTO=-0.7,LAMBDA=0.01,KF=1E-31) .MODEL NIX NMOS (LEVEL=2,KP=20E-6,VTO=0.7,LAMBDA=0.01,KF=1E-31) .MODEL DX D(IS=1E-14) *.MODEL VSY_SWITCH VSWITCH(ROFF=100E3,RON=1,VOFF=-4.2,VON=-3.5) .MODEL VSY_SWITCH SW(ROFF=100E3,RON=1,VT=-3.85,VH=0.35) .ENDS AD8541* OP160 SPICE Macro-model 12/90, Rev. B * JCB / PMI * * Revision History: * REV. B * Re-ordered subcircuit call out nodes to put the * output node last. * * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP160 1 2 99 50 28 * * INPUT STAGE * R1 99 8 1E3 R2 10 50 1E3 V1 99 9 9.4 D1 9 8 DX V2 11 50 5.9 D2 10 11 DX I1 99 5 175E-6 I2 4 50 175E-6 Q1 50 3 5 QP Q2 99 3 4 QN Q3 8 6 30 QN Q4 10 7 30 QP R3 5 6 300E3 R4 4 7 300E3 C1 99 6 0.0133E-12 C2 50 7 0.0133E-12 * * INPUT ERROR SOURCES * GB1 99 1 POLY(1) 1 22 2E-7 4E-8 GB2 99 30 POLY(1) 1 22 6E-6 3E-8 VOS 3 1 1E-3 LS1 30 2 1E-6 CS1 99 2 1.5E-12 CS2 50 2 1.5E-12 * EREF 97 0 22 0 1 * * GAIN STAGE & DOMINANT POLE * R5 12 97 5E6 C3 12 97 6E-12 G1 97 12 99 8 1E-3 G2 12 97 10 50 1E-3 V3 99 13 2.2 V4 14 50 2.2 D3 12 13 DX D4 14 12 DX CF 29 28 30E-12 RF 12 29 300 * * ZERO / POLE PAIR AT 50 MHZ / 300 MHZ * R6 15 16 1E6 L1 16 97 2.65E-3 R7 16 97 5E6 G3 97 15 12 22 1E-6 * * POLE AT 300 MHZ * R8 17 97 1E6 C4 17 97 0.531E-15 G4 97 17 15 22 1E-6 * * POLE AT 300 MHZ * R9 18 97 1E6 C5 18 97 0.531E-15 G5 97 18 17 22 1E-6 * * POLE AT 500 MHZ * R10 19 97 1E6 C6 19 97 0.318E-15 G6 97 19 18 22 1E-6 * * POLE AT 500 MHZ * R11 20 97 1E6 C7 20 97 0.318E-15 G7 97 20 19 22 1E-6 * * POLE AT 500 MHZ * R12 21 97 1E6 C8 21 97 0.318E-15 G8 97 21 20 22 1E-6 * * OUTPUT STAGE * ISY 99 50 1.65E-3 R13 22 99 3.333E3 R14 22 50 3.333E3 R15 27 99 40 R16 27 50 40 L2 27 28 4E-8 G9 25 50 21 27 25E-3 G10 26 50 27 21 25E-3 G11 27 99 99 21 25E-3 G12 50 27 21 50 25E-3 V5 23 27 0.5 V6 27 24 0.2 D5 21 23 DX D6 24 21 DX D7 99 25 DX D8 99 26 DX D9 50 25 DY D10 50 26 DY * * MODELS USED * .MODEL QN NPN(BF=1E9 IS=1E-15 VAF=92) .MODEL QP PNP(BF=1E9 IS=1E-15 VAF=92) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP176 SPICE Macro-model 11/93, Rev. A * ARG / PMI * * Copyright 1992 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License * Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | * | | | | | .SUBCKT OP176 1 2 99 50 34 * * INPUT STAGE & POLE AT 100MHZ * R3 5 51 2.487 R4 6 51 2.487 CIN 1 2 3.7E-12 CM1 1 98 7.5E-12 CM2 2 98 7.5E-12 C2 5 6 320E-12 I1 97 4 100E-3 IOS 1 2 1E-9 EOS 9 3 POLY(1) (26,28) 0.2E-3 1 Q1 5 2 7 QX Q2 6 9 8 QX R5 7 4 1.970 R6 8 4 1.970 D1 2 36 DZ D2 1 36 DZ EN 3 1 (10,0) 1 GN1 0 2 (13,0) 1E-3 GN2 0 1 (16,0) 1E-3 * EREF 98 0 (28,0) 1 EP 97 0 (99,0) 1 EM 51 0 (50,0) 1 * * VOLTAGE NOISE SOURCE * DN1 35 10 DEN DN2 10 11 DEN VN1 35 0 DC 2 VN2 0 11 DC 2 * * CURRENT NOISE SOURCE * DN3 12 13 DIN DN4 13 14 DIN VN3 12 0 DC 2 VN4 0 14 DC 2 * * CURRENT NOISE SOURCE * DN5 15 16 DIN DN6 16 17 DIN VN5 15 0 DC 2 VN6 0 17 DC 2 * * GAIN STAGE & DOMINANT POLE AT 32HZ * R7 18 98 1.243E6 C3 18 98 4E-9 G1 98 18 (5,6) 4.021E-1 V2 97 19 1.35 V3 20 51 1.35 D3 18 19 DX D4 20 18 DX * * POLE/ZERO PAIR AT 1.5MHZ/2.7MHZ * R8 21 98 1E3 R9 21 22 1.25E3 C4 22 98 47.2E-12 G2 98 21 (18,28) 1E-3 * * POLE AT 100MHZ * R10 23 98 1 C5 23 98 1.59E-9 G3 98 23 (21,28) 1 * * POLE AT 100MHZ * R11 24 98 1 C6 24 98 1.59E-9 G4 98 24 (23,28) 1 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 1KHZ * R12 25 26 1E6 C7 25 26 60E-12 R13 26 98 1 E2 25 98 POLY(2) (1,98) (2,98) 0 2.50 2.50 * * POLE AT 100MHZ * R14 27 98 1 C8 27 98 1.59E-9 G5 98 27 (24,28) 1 * * OUTPUT STAGE * R15 28 99 58.333E3 R16 28 50 58.333E3 C9 28 50 1E-6 ISY 99 50 1.743E-3 R17 29 99 100 R18 29 50 100 L2 29 34 1E-9 G6 32 50 (27,29) 10E-3 G7 33 50 (29,27) 10E-3 G8 29 99 (99,27) 10E-3 G9 50 29 (27,50) 10E-3 V4 30 29 1.74 V5 29 31 1.74 F1 29 0 V4 1 F2 0 29 V5 1 D5 27 30 DX D6 31 27 DX D7 99 32 DX D8 99 33 DX D9 50 32 DY D10 50 33 DY * * MODELS USED * .MODEL QX PNP(BF=5E5) .MODEL DX D(IS=1E-12) .MODEL DY D(IS=1E-15 BV=50) .MODEL DZ D(IS=1E-15 BV=7.0) .MODEL DEN D(IS=1E-12 RS=4.35K KF=1.95E-15 AF=1) .MODEL DIN D(IS=1E-12 RS=268 KF=1.08E-15 AF=1) .ENDS * OP177 SPICE Macro-model 12/90, Rev. B * JCB / PMI * * Revision History: * REV. B * Re-ordered subcircuit call out nodes to put the * output node last. * Changed Ios from 0.3E-9 to 0.15E-9 * Added F1 and F2 to fix short circuit current limit. * * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP177 1 2 99 50 39 * * INPUT STAGE & POLE AT 6 MHZ * R1 2 3 5E11 R2 1 3 5E11 R3 5 97 0.0606 R4 6 97 0.0606 CIN 1 2 4E-12 C2 5 6 218.9E-9 I1 4 51 1 IOS 1 2 0.15E-9 EOS 9 10 POLY(1) 30 33 4E-6 1 Q1 5 2 7 QX Q2 6 9 8 QX R5 7 4 0.009 R6 8 4 0.009 D1 2 1 DX D2 1 2 DX EN 10 1 12 0 1 GN1 0 2 15 0 1 GN2 0 1 18 0 1 * EREF 98 0 33 0 1 EPLUS 97 0 99 0 1 ENEG 51 0 50 0 1 * * VOLTAGE NOISE SOURCE WITH FLICKER NOISE * DN1 11 12 DEN DN2 12 13 DEN VN1 11 0 DC 2 VN2 0 13 DC 2 * * CURRENT NOISE SOURCE WITH FLICKER NOISE * DN3 14 15 DIN DN4 15 16 DIN VN3 14 0 DC 2 VN4 0 16 DC 2 * * SECOND CURRENT NOISE SOURCE * DN5 17 18 DIN DN6 18 19 DIN VN5 17 0 DC 2 VN6 0 19 DC 2 * * FIRST GAIN STAGE * R7 20 98 1 G1 98 20 5 6 59.91 D3 20 21 DX D4 22 20 DX E1 97 21 POLY(1) 97 33 -2.4 1 E2 22 51 POLY(1) 33 51 -2.4 1 * * GAIN STAGE & DOMINANT POLE AT 0.053 HZ * R8 23 98 6.01E9 C3 23 98 500E-12 G2 98 23 20 33 33.3E-6 V1 97 24 1.3 V2 25 51 1.3 D5 23 24 DX D6 25 23 DX * * NEGATIVE ZERO AT -4MHZ * R9 26 27 1 C4 26 27 -39.75E-9 R10 27 98 1E-6 E3 26 98 23 33 1E6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 20 HZ * R13 30 31 1 L2 31 98 7.96E-3 G4 98 30 3 33 1.0E-7 D7 30 97 DX D8 51 30 DX * * POLE AT 2 MHZ * R14 32 98 1 C5 32 98 79.5E-9 G5 98 32 27 33 1 * * OUTPUT STAGE * R15 33 97 1 R16 33 51 1 GSY 99 50 POLY(1) 99 50 0.325E-3 0.0425E-3 F1 34 0 V3 1 F2 0 34 V4 1 R17 34 99 400 R18 34 50 400 L3 34 39 2E-7 G6 37 50 32 34 2.5E-3 G7 38 50 34 32 2.5E-3 G8 34 99 99 32 2.5E-3 G9 50 34 32 50 2.5E-3 V3 35 34 6.8 V4 34 36 4.4 D9 32 35 DX D10 36 32 DX D11 99 37 DX D12 99 38 DX D13 50 37 DY D14 50 38 DY * * MODELS USED * .MODEL QX NPN(BF=500E6) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .MODEL DEN D(IS=1E-12, RS=12.08K, KF=1E-17, AF=1) .MODEL DIN D(IS=1E-12, RS=7.55E-6, KF=1.55E-15, AF=1) .ENDS * OP283 SPICE Macro-model Rev. A, 9/93 * JCB / ADI * * Copyright 1993 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of * this model indicates your acceptance of the terms and pro- * visions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP283 2 1 99 50 45 * * INPUT STAGE AND POLE AT 600KHZ * I1 99 8 1E-4 Q1 4 1 6 QP Q2 5 3 7 QP CIN 1 2 1.5PF R1 50 4 1591 R2 50 5 1591 C1 4 5 83.4E-12 R3 6 8 1075 R4 7 8 1075 IOS 1 2 12.5E-9 EOS 3 2 POLY(1) (15,98) 25E-6 1 DC1 2 36 DZ DC2 1 36 DZ * * GAIN STAGE AND DOMINANT POLE AT 10HZ * EREF 98 0 POLY(2) (99,0) (50,0) 0 0.5 0.5 G1 98 9 (4,5) 6.28E-4 R5 9 98 1.59E9 C2 9 98 10E-12 D1 9 10 DX D2 11 9 DX E1 10 98 POLY(1) 99 98 -1.35 1.03 V2 50 11 -0.63 * * COMMON MODE STAGE WITH ZERO AT 353HZ * ECM 14 98 POLY(2) (1,98) (2,98) 0 3.5 3.5 R7 14 15 1E6 C4 14 15 3.75E-11 R8 15 98 1 * *POLE AT 20MHZ * GP2 98 31 (9,98) 1E-6 RP2 31 98 1E6 CP2 31 98 7.96E-15 * *ZERO AT 1.5MHZ * EZ1 32 98 (31,98) 1E6 RZ1 32 33 1E6 RZ2 33 98 1 CZ1 32 33 106E-15 * *POLE AT 10MHZ * GP10 98 40 (33,98) 1E-6 RP10 40 98 1E6 CP10 40 98 15.9E-15 * * OUTPUT STAGE * RO1 99 45 140 RO2 45 50 140 G7 45 99 (99,40) 7.14E-3 G8 50 45 (40,50) 7.14E-3 G9 98 60 (45,40) 7.14E-3 D7 60 61 DX D8 62 60 DX V7 61 98 DC 0 V8 98 62 DC 0 GSY 99 50 (99,50) 5E-6 FSY 99 50 POLY(2) V7 V8 1.075E-3 1 1 D9 40 41 DX D10 42 40 DX V5 41 45 1.2 V6 45 42 1.5 * * MODELS USED * .MODEL DX D .MODEL DZ D(IS=1E-15 BV=7.0) .MODEL QP PNP(BF=143) .ENDS * OP191 SPICE Macro-model Rev. A, 12/94 * ARG / PMI * * Copyright 1994 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of * this model indicates your acceptance of the terms and pro- * visions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP191 1 2 99 50 45 * * INPUT STAGE * I1 99 7 8.06E-6 Q1 6 4 7 QP Q2 5 3 7 QP D1 3 99 DX D2 4 99 DX D3 3 4 DX D4 4 3 DX R1 3 8 5E3 R2 4 2 5E3 R3 5 50 6.4654E3 R4 6 50 6.4654E3 EOS 8 1 POLY(1) (16,39) -80E-6 1 IOS 3 4 50E-12 GB1 3 98 (21,98) 50E-9 GB2 4 98 (21,98) 50E-9 CIN 1 2 1E-12 * * 1ST GAIN STAGE * EREF 98 0 (39,0) 1 G1 98 9 (6,5) 31.667E-6 R7 9 98 1E6 EC1 99 10 POLY(1) (99,39) -0.52 1 EC2 11 50 POLY(1) (39,50) -0.52 1 D5 9 10 DX D6 11 9 DX * * 2ND GAIN STAGE AND DOMINANT POLE AT 36HZ * G2 98 12 (9,39) 8E-6 R8 12 98 276.311E6 C2 12 98 16E-12 D7 12 13 DX D8 14 12 DX V1 99 13 0.58 V2 14 50 0.58 * * COMMON MODE STAGE * ECM 15 98 POLY(2) (1,39) (2,39) 0 0.5 0.5 R9 15 16 1E6 R10 16 98 10 * * POLE AT 2.5MHZ * G3 98 18 (12,39) 1E-6 R11 18 98 1E6 C4 18 98 63.662E-15 * * BIAS CURRENT-VS-COMMON MODE VOLTAGE * EP 97 0 (99,0) 1 VB 99 17 1.3 RB 17 50 1E9 E3 19 0 (15,17) 16 D13 19 20 DX R12 20 0 1E6 G4 98 21 (20,0) 1E-3 R13 21 98 5E3 D14 21 22 DY E4 97 22 (POLY(1) (99,98) -0.765 1 * * POLE AT 100MHZ * G6 98 40 (18,39) 1E-6 R20 40 98 1E6 C10 40 98 1.592E-15 * * OUTPUT STAGE * RS1 99 39 109.375E3 RS2 39 50 109.375E3 RO1 99 45 41.667 RO2 45 50 41.667 G7 45 99 (99,40) 24E-3 G8 50 45 (40,50) 24E-3 G9 98 60 (45,40) 24E-3 D9 60 61 DX D10 62 60 DX V7 61 98 DC 0 V8 98 62 DC 0 FSY 99 50 POLY(2) V7 V8 0.207E-3 1 1 D11 41 45 DZ D12 45 42 DZ V5 40 41 0.131 V6 42 40 0.131 .MODEL DX D() .MODEL DY D(IS=1E-9) .MODEL DZ D(IS=1E-6) .MODEL QP PNP(BF=133.333) .ENDS * OP193 SPICE Macro-model 1/95, Rev. A * ARG / ADI * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License * Statement. This model has been optimized for a total supply voltage of * 5V. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP193 51 52 99 50 32 * * INPUT STAGE & POLE AT 16KHZ * R3 5 50 53.827E3 R4 6 50 53.827E3 R5 4 7 2.104E3 R6 4 8 2.104E3 CIN 1 2 4E-12 C2 5 6 92.4E-12 I1 99 4 1.006E-6 IOS 1 2 0.05E-9 EOS 9 1 POLY(2) (24,27) (102,0) 25E-6 15.851E-3 1 Q1 5 2 7 QX Q2 6 9 8 QX EREF 98 0 POLY(2) (99,0) (50,0) 0 0.5 0.5 R24 1 51 2E3 R25 2 52 2E3 VN1 101 0 DC 2 VN2 0 103 DC 2 DN1 101 102 DEN DN2 102 103 DEN * * GAIN STAGE & DOMINANT POLE AT 0.21 HZ * R7 10 98 9.151E9 G1 98 10 (5,6) 18.578E-6 C3 10 98 83.333E-12 V1 99 11 0.65 D1 10 11 DX D2 50 10 DX * * NEGATIVE ZERO AT 50KHZ * R9 13 14 1E6 R10 14 98 1 FNZ 13 14 VNZ -1 E2 13 98 (10,27) 1 CNZ 15 16 3.183E-12 ENZ 15 98 (13,14) 1 VNZ 16 98 DC 0 * * ZERO-POLE PAIR AT 28KHZ / 84KHZ * R18 17 18 2E6 C4 17 18 2.842E-12 R19 18 98 1E6 E3 17 98 (14,27) 3E6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 0.5HZ * R1 23 24 1E6 R2 24 98 100 C5 23 24 318E-9 E4 23 98 POLY(2) (1,27) (2,27) 0 0.5 0.5 * * ZERO-POLE PAIR AT 40KHZ / 160KHZ * R20 25 26 3E6 C6 25 26 1.326E-12 R21 26 98 1E6 E5 25 98 (18,27) 4 * * OUTPUT STAGE * ISY 99 50 9.637E-6 R16 27 99 4.5E6 R17 27 50 4.5E6 EIN 28 98 POLY(1) (26,27) 0.52255 1.05 RIN 28 31 15E3 Q11 45 31 32 QN 6 Q12 32 33 44 QN 6 Q13 41 34 33 QN 1 Q14 34 35 36 QP 1 Q15 36 38 39 QN 8 Q16 35 35 37 QP 1 Q17 99 99 37 QN 1 Q18 99 99 36 QN 1 Q19 50 42 34 QP 1 Q20 42 42 34 QP 1 Q21 32 33 42 QN 1 Q22 99 40 41 QN 1 Q23 43 43 50 QN 1 Q24 34 43 50 QN 2 Q25 33 43 50 QN 2 Q26 34 44 50 QC 1 Q27 31 46 50 QC 1 EC 47 50 (99,45) 0.96 RC 46 47 1E3 IREF 99 43 4.5E-7 I13 35 50 4.5E-7 R11 99 40 75E3 R12 99 36 40E3 R13 31 38 20E3 R14 32 39 5E3 R15 40 37 75E3 R22 44 50 30 R23 99 45 50 * * MODELS USED * .MODEL QN NPN(BF=200 IS=1E-16 VA=150) .MODEL QP PNP(BF=100 IS=5E-17 VA=50) .MODEL QX PNP(BF=166.667 KF=2E-17) .MODEL QC NPN(BF=200 IS=2E-11) .MODEL DX D(IS=1E-15) .MODEL DEN D(RS=2.45E3 KF=33E-15) .ENDS * OP196 SPICE Macro-model Rev. A, 5/95 * ARG / ADSC * * Copyright 1995 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of * this model indicates your acceptance of the terms and pro- * visions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP196 1 2 99 50 49 * * INPUT STAGE * IREF 21 50 1U QB1 21 21 99 99 QP 1 QB2 22 21 99 99 QP 1 QB3 4 21 99 99 QP 1.5 QB4 22 22 50 50 QN 2 QB5 11 22 50 50 QN 3 Q1 5 4 7 50 QN 2 Q2 6 4 8 50 QN 2 Q3 4 4 7 50 QN 1 Q4 4 4 8 50 QN 1 Q5 50 1 7 99 QP 2 Q6 50 3 8 99 QP 2 EOS 3 2 POLY(1) (17,98) 35U 1 Q7 99 1 9 50 QN 2 Q8 99 3 10 50 QN 2 Q9 12 11 9 99 QP 2 Q10 13 11 10 99 QP 2 Q11 11 11 9 99 QP 1 Q12 11 11 10 99 QP 1 R1 99 5 50K R2 99 6 50K R3 12 50 50K R4 13 50 50K IOS 1 2 0.75N C10 5 6 3.183P C11 12 13 3.183P CIN 1 2 1P * * GAIN STAGE * EREF 98 0 POLY(2) (99,0) (50,0) 0 0.5 0.5 G1 98 15 POLY(2) (6,5) (13,12) 0 10U 10U R10 15 98 251.641MEG CC 15 49 8P D1 15 99 DX D2 50 15 DX * * COMMON MODE STAGE * ECM 16 98 POLY(2) (1,98) (2,98) 0 0.5 0.5 R11 16 17 1E6 R12 17 98 10 * * OUTPUT STAGE * ISY 99 50 20E-6 EIN 35 50 POLY(1) (15,98) 1.42735 1 Q24 37 35 36 50 QN 1 QD4 37 37 38 99 QP 1 Q27 40 37 38 99 QP 1 R5 36 39 150K R6 99 38 45K Q26 39 42 50 50 QN 3 QD5 40 40 39 50 QN 1 Q28 41 40 44 50 QN 1 QL1 37 41 99 99 QP 1 R7 99 41 10.7K I4 99 43 2U QD7 42 42 50 50 QN 2 QD6 43 43 42 50 QN 2 Q29 47 43 44 50 QN 1 Q30 44 45 50 50 QN 1.5 QD10 45 46 50 50 QN 1 R9 45 46 175 Q31 46 47 48 99 QP 1 QD8 47 47 48 99 QP 1 QD9 48 48 51 99 QP 5 R8 99 51 2.9K I5 99 46 1U Q32 49 48 99 99 QP 10 Q33 49 44 50 50 QN 4 .MODEL DX D() .MODEL QN NPN(BF=120 VAF=100) .MODEL QP PNP(BF=80 VAF=60) .ENDS * OP200 SPICE Macro-model 12/90, Rev. B * AAG / PMI * Revision History: * Re-ordered subcircuit call out nodes to put the * output node last. * Changed Ios from 50E-12 to 25E-12 * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP200 1 2 99 50 25 * * INPUT STAGE & POLE AT 4.5 MHZ * RI1 2 31 1E3 RI2 1 32 1E3 R1 31 3 5E5 R2 32 3 5E5 R3 5 99 516 R4 6 99 516 CIN 32 31 3.2E-12 C2 5 6 34.271E-12 I1 4 50 0.1E-3 IOS 32 31 25E-12 EOS 7 32 POLY(1) 13 19 25E-6 1 Q1 5 31 4 QX Q2 6 7 4 QX D21 31 7 DX D22 7 31 DX * * FIRST GAIN STAGE & DOMINANT POLE AT 0.125 HZ * R5 8 99 1.9098E9 R6 8 50 1.9098E9 C3 8 99 666.67E-12 C4 8 50 666.67E-12 G1 99 8 POLY(1) 5 6 200E-6 1.938E-3 G2 8 50 POLY(1) 6 5 200E-6 1.938E-3 D1 8 99 DX D2 50 8 DX * * SECOND GAIN STAGE & POLE AT 4.5 MHZ * R7 10 99 1E6 R8 10 50 1E6 C5 10 99 35.368E-15 C6 10 50 35.368E-15 G3 99 10 8 19 1.3509E-6 G4 10 50 19 8 1.3509E-6 V2 99 9 2.7 V3 11 50 2.7 D3 10 9 DX D4 11 10 DX * * POLE AT 4.5 MHZ * R9 12 99 1E6 R10 12 50 1E6 C7 12 99 35.368E-15 C8 12 50 35.368E-15 G5 99 12 10 19 1E-6 G6 12 50 19 10 1E-6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 20 HZ * R11 13 14 1E6 R12 13 15 1E6 L1 14 99 7.9578E3 L2 15 50 7.9578E3 G7 99 13 3 19 1.778E-13 G8 13 50 19 3 1.778E-13 D5 13 99 DX D6 50 13 DX * * POLE AT 4.5 MHZ * R14 18 99 1E6 R15 18 50 1E6 C9 18 99 35.368E-15 C10 18 50 35.368E-15 G9 99 18 12 19 1E-6 G10 18 50 19 12 1E-6 * * OUTPUT STAGE * R16 19 99 62.22E3 R17 19 50 62.22E3 R18 24 99 250 R19 24 50 250 L3 24 25 7E-7 G11 22 50 18 24 4E-3 G12 23 50 24 18 4E-3 G13 24 99 99 18 4E-3 G14 50 24 18 50 4E-3 V6 20 24 3 V7 24 21 3 D7 18 20 DX D8 21 18 DX D9 99 22 DX D10 99 23 DX D11 50 22 DY D12 50 23 DY * * MODELS USED * .MODEL QX NPN(BF=500000) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP215 SPICE Macro-model 10/90, Rev. A * AN / PMI * * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP215 1 2 99 50 26 * * INPUT STAGE & POLE AT 150 MHZ * R1 1 3 5E11 R2 2 3 5E11 R3 5 50 568.5 R4 6 50 568.5 CIN 1 2 3E-12 C2 5 6 9.332E-13 I1 99 4 1E-3 IOS 1 2 1.5E-12 EOS 7 1 POLY(1) 18 20 200E-6 1 J1 5 2 4 JX J2 6 7 4 JX * EREF 98 0 20 0 1 * * SECOND STAGE & POLE AT 10.0 HZ * R5 9 98 284.2E6 C3 9 98 56E-12 G1 98 9 5 6 1.759E-3 V2 99 8 2.35 V3 10 50 2.35 D1 9 8 DX D2 10 9 DX * * NEGATIVE ZERO AT 30 MHZ * R6 11 12 1E6 R7 12 98 1 E1 11 98 9 98 1E6 C4 11 12 -5.305E-15 * * POLE AT 200 MHZ * R8 13 98 1E6 C5 13 98 7.95E-16 G2 98 13 12 20 1E-6 * * POLE AT 100 MHZ * R9 14 98 1E6 C6 14 98 1.59E-15 G3 98 14 13 20 1E-6 * * POLE AT 150 MHZ * R10 15 98 1E6 C7 15 98 1.061E-15 G4 98 15 14 20 1E-6 * * POLE AT 100 MHZ * R11 16 98 1E6 C8 16 98 1.59E-15 G5 98 16 15 20 1E-6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 400 HZ * R12 17 18 1E6 R13 18 98 1 C9 17 18 397.9E-12 E2 17 98 3 20 10 * * POLE AT 100 MHZ * R14 19 98 1E6 C10 19 98 1.59E-15 G6 98 19 16 20 1E-6 * * OUTPUT STAGE * R15 20 99 135E3 R16 20 50 135E3 ISY 99 50 4.9E-3 R17 25 99 172.78 R18 25 50 172.78 L2 25 26 4E-11 G7 23 50 19 25 5.79E-3 G8 24 50 25 19 5.79E-3 G9 25 99 99 19 5.79E-3 G10 50 25 19 50 5.79E-3 V4 21 25 2.0 V5 25 22 2.0 D3 19 21 DX D4 22 19 DX D5 99 23 DX D6 99 24 DX D7 50 23 DY D8 50 24 DY * * MODELS USED * .MODEL JX PJF(BETA=1.547E-3 VTO=-2.000 IS=15E-12) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP220 SPICE Macro-model 9/91, Rev. A * JCB / PMI * * Copyright 1991 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP220 1 2 99 50 30 * * INPUT STAGE & POLE AT 1.5 MEGHZ * R1 2 3 5E11 R2 1 3 5E11 R3 5 50 5.16K R4 6 50 5.16K CIN 1 2 4E-12 C2 5 6 15.42E-12 I1 99 4 10UA IOS 1 2 0.075E-9 EOS 9 1 POLY(1) 24 27 120E-6 1 Q1 5 2 4 QX Q2 6 9 4 QX * EREF 98 0 27 0 1 * * FIRST GAIN STAGE * R5 10 98 1E6 G1 98 10 5 6 50.27E-6 D1 10 11 DX D2 12 10 DX E1 99 11 POLY(1) 99 27 -1.475 1 E2 12 50 POLY(1) 27 50 -1.475 1 * * GAIN STAGE & DOMINANT POLE AT 0.1 HZ * R6 13 98 7.96E9 C3 13 98 200E-12 G2 98 13 10 27 5E-6 V1 99 14 0.73 V2 15 50 0.73 D3 13 14 DX D4 15 13 DX * * COMMON-MODE GAIN NETWORK WITH ZERO AT 200 HZ * R7 24 98 1 R8 23 24 1E6 C4 23 24 0.796E-9 E4 98 23 3 27 10 * * POLE AT 600 KHZ * R9 25 98 1E6 C5 25 98 265E-15 G3 98 25 13 27 1E-6 * * OUTPUT STAGE * ISY 99 50 33.6E-6 R10 27 99 568E3 R11 27 50 568E3 R12 30 99 2000 R13 30 50 2000 G4 28 50 25 30 0.5E-3 G5 29 50 30 25 0.5E-3 G6 30 99 99 25 0.5E-3 G7 50 30 25 50 0.5E-3 D5 99 28 DX D6 99 29 DX D7 50 28 DY D8 50 29 DY D9 25 31 DX V3 31 30 1.9 D10 32 25 DX V4 30 32 0.8 * * MODELS USED * .MODEL QX PNP(BF=416.667) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP221 SPICE Macro-model 9/91, Rev. A * JCB / PMI * * * Copyright 1991 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP221 1 2 99 50 31 * * INPUT STAGE & POLE AT 1.9 MEGHZ * R1 2 3 5E11 R2 1 3 5E11 R3 5 50 7701 R4 6 50 7701 CIN 1 2 2E-12 C2 5 6 5.51E-12 I1 99 4 10E-6 IOS 1 2 0.25E-9 EOS 9 1 POLY(1) 24 27 75E-6 1 Q1 5 2 10 QX Q2 6 9 11 QX R5 10 4 2541 R6 11 4 2541 * EREF 98 0 27 0 1 * * GAIN STAGE & DOMINANT POLE AT 0.20 HZ * R7 13 98 2.44E10 C3 13 98 33.3E-12 G2 98 13 5 6 1.3E-4 V1 99 14 1.25 V2 15 50 0.9 D3 13 14 DX D4 15 13 DX * * POLE AT 3.0 MEGHZ * R8 16 98 1E6 C5 16 98 53.1E-15 G3 98 16 13 27 1E-6 * * POLE AT 3.0 MEGHZ * R9 17 98 1E6 C7 17 98 53.1E-15 G10 98 17 16 27 1E-6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 10 HZ * R10 24 98 1 R11 23 24 1E6 C4 23 24 1.592E-8 E4 98 23 3 27 10 * * POLE AT 3.0 MEGHZ * R12 25 98 1E6 C6 25 98 53.1E-15 G9 98 25 17 27 1E-6 * * OUTPUT STAGE * ISY 99 50 190E-6 R13 27 99 150E3 R14 27 50 150E3 R15 30 99 450 R16 30 50 450 L1 30 31 1E-8 G4 28 50 25 30 2.22E-3 G5 29 50 30 25 2.22E-3 G6 30 99 99 25 2.22E-3 G7 50 30 25 50 2.22E-3 D5 99 28 DX D6 99 29 DX D7 50 28 DY D8 50 29 DY D9 25 33 DX V3 33 30 1.6 D10 32 25 DX V4 30 32 1.6 * * MODELS USED * .MODEL QX PNP(BF=100) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP249 SPICE Macro-model 10/91, Rev. C * JCB / PMI * * Revision History: * REV. C * Corrected the supply current in G1 and G2 * REV. B * Re-ordered subcircuit call out nodes to put the * output node last. * Changed Ios from 6E-12 to 3E-12 * * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP249 1 2 99 50 30 * * INPUT STAGE & POLE AT 100 MHZ * R1 1 3 5E11 R2 2 3 5E11 R3 5 50 652.3 R4 6 50 652.3 CIN 1 2 5E-12 C2 5 6 1.22E-12 I1 99 4 1E-3 IOS 1 2 3E-12 EOS 7 1 POLY(1) 20 24 200E-6 1 J1 5 2 4 JX J2 6 7 4 JX * * SECOND STAGE & POLE AT 4.37 HZ * R5 9 99 913.4E6 R6 9 50 913.4E6 C3 9 99 40E-12 C4 9 50 40E-12 G1 99 9 POLY(1) 5 6 1.7E-3 1.533E-3 G2 9 50 POLY(1) 6 5 1.7E-3 1.533E-3 V2 99 8 2.9 V3 10 50 2.9 D1 9 8 DX D2 10 9 DX * * POLE-ZERO PAIR AT 2 MHZ / 4.0 MHZ * R7 11 99 1E6 R8 11 50 1E6 R9 11 12 1E6 R10 11 13 1E6 C5 12 99 39.79E-15 C6 13 50 39.79E-15 G3 99 11 9 24 1E-6 G4 11 50 24 9 1E-6 * * ZERO-POLE PAIR AT 4 MHZ / 8 MHZ * R11 99 15 1E6 R12 14 15 1E6 R13 14 16 1E6 R14 50 16 1E6 L1 99 15 19.89E-3 L2 50 16 19.89E-3 G5 99 14 11 24 1E-6 G6 14 50 24 11 1E-6 * * POLE AT 20 MHZ * R15 17 99 1E6 R16 17 50 1E6 C9 17 99 7.96E-15 C10 17 50 7.96E-15 G7 99 17 14 24 1E-6 G8 17 50 24 14 1E-6 * * POLE AT 50 MHZ * R17 18 99 1E6 R18 18 50 1E6 C11 18 99 3.18E-15 C12 18 50 3.18E-15 G9 99 18 17 24 1E-6 G10 18 50 24 17 1E-6 * * POLE AT 50 MHZ * R19 19 99 1E6 R20 19 50 1E6 C13 19 99 3.18E-15 C14 19 50 3.18E-15 G11 99 19 18 24 1E-6 G12 19 50 24 18 1E-6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 60 KHZ * R21 20 21 1E6 R22 20 22 1E6 L3 21 99 2.65 L4 22 50 2.65 G13 99 20 3 24 31.6E-12 G14 20 50 24 3 31.6E-12 * * POLE AT 50 MHZ * R23 23 99 1E6 R24 23 50 1E6 C15 23 99 3.18E-15 C16 23 50 3.18E-15 G15 99 23 19 24 1E-6 G16 23 50 24 19 1E-6 * * OUTPUT STAGE * R25 24 99 10E6 R26 24 50 10E6 R27 29 99 70 R28 29 50 70 L5 29 30 4E-7 G17 27 50 23 29 14.3E-3 G18 28 50 29 23 14.3E-3 G19 29 99 99 23 14.3E-3 G20 50 29 23 50 14.3E-3 V4 25 29 .4 V5 29 26 .4 D3 23 25 DX D4 26 23 DX D5 99 27 DX D6 99 28 DX D7 50 27 DY D8 50 28 DY * * MODELS USED * .MODEL JX PJF(BETA=1.175E-3 VTO=-2.000 IS=30E-12) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP27 SPICE Macro-model 12/90, Rev. B * JCB / PMI * * Revision History: * REV. B * Re-ordered subcircuit call out nodes to put the * output node last. * Changed Ios from 7E-9 to 3.5E-9 * Added F1 and F2 to fix short circuit current limit. * * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP27 1 2 99 50 39 * * INPUT STAGE & POLE AT 80 MHZ * R3 5 97 0.0619 R4 6 97 0.0619 CIN 1 2 4E-12 C2 5 6 16.07E-9 I1 4 51 1 IOS 1 2 3.5E-9 EOS 9 10 POLY(1) 30 33 10E-6 1 Q1 5 2 7 QX Q2 6 9 8 QX R5 7 4 0.0107 R6 8 4 0.0107 D1 2 1 DX D2 1 2 DX EN 10 1 12 0 1 GN1 0 2 15 0 1 GN2 0 1 18 0 1 * EREF 98 0 33 0 1 EPLUS 97 0 99 0 1 ENEG 51 0 50 0 1 * * VOLTAGE NOISE SOURCE WITH FLICKER NOISE * DN1 11 12 DEN DN2 12 13 DEN VN1 11 0 DC 2 VN2 0 13 DC 2 * * CURRENT NOISE SOURCE WITH FLICKER NOISE * DN3 14 15 DIN DN4 15 16 DIN VN3 14 0 DC 2 VN4 0 16 DC 2 * * SECOND CURRENT NOISE SOURCE * DN5 17 18 DIN DN6 18 19 DIN VN5 17 0 DC 2 VN6 0 19 DC 2 * * GAIN STAGE & DOMINANT POLE AT 4.0 HZ * R7 20 98 111.5E3 C3 20 98 357E-9 G1 98 20 5 6 16.15 V1 97 21 1.2 V2 22 51 1.2 D5 20 21 DX D6 22 20 DX * * POLE - ZERO AT 2.9MHZ / 6MHZ * R8 23 98 1 R9 23 24 0.935 C4 24 98 28.4E-9 G2 98 23 20 33 1 * * ZERO - POLE AT 6.8MHZ / 40MHZ * R10 25 26 1 R11 26 98 4.88 L1 26 98 19.4E-9 G3 98 25 23 33 1 * * POLE AT 60 MHZ * R12 27 98 1 C5 27 98 2.65E-9 G4 98 27 25 33 1 * * ZERO AT 28 MHZ * R13 28 29 1 C6 28 29 -5.68E-9 R14 29 98 1E-6 E1 28 98 27 33 1E6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 3 KHZ * R15 30 31 1 L2 31 98 53.1E-6 G5 98 30 POLY(2) 2 33 1 33 0 250.5E-9 250.5E-9 D7 30 97 DX D8 51 30 DX * * POLE AT 80 MHZ * R16 32 98 1 C7 32 98 1.99E-9 G6 98 32 29 33 1 * * OUTPUT STAGE * R17 33 97 1 R18 33 51 1 GSY 99 50 POLY(1) 99 50 1.8E-3 40E-6 F1 34 0 V3 1 F2 0 34 V4 1 R19 34 99 180 R20 34 50 180 L3 34 39 1E-7 G7 37 50 32 34 5.56E-3 G8 38 50 34 32 5.56E-3 G9 34 99 99 32 5.56E-3 G10 50 34 32 50 5.56E-3 V3 35 34 2.5 V4 34 36 3.1 D9 32 35 DX D10 36 32 DX D11 99 37 DX D12 99 38 DX D13 50 37 DY D14 50 38 DY * * MODELS USED * .MODEL QX NPN(BF=50E6) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .MODEL DEN D(IS=1E-12, RS=1.09K, KF=1.08E-16, AF=1) .MODEL DIN D(IS=1E-12, RS=19.3E-6, KF=4.28E-15, AF=1) .ENDS * OP275 SPICE Macro-model 3/95, Rev. C * JCB / PMI * Revision History: * Added common-mode input capacitance. * Corrected output short circuit current. * Corrected common-mode zero location (rev C). * * Copyright 1995 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | * | | | | | .SUBCKT OP275 1 2 99 50 34 * * INPUT STAGE & POLE AT 100 MHZ * R3 5 51 2.188 R4 6 51 2.188 CIN 1 2 3.7E-12 CM1 1 98 7.5E-12 CM2 2 98 7.5E-12 C2 5 6 364E-12 I1 97 4 100E-3 IOS 1 2 1E-9 EOS 9 3 POLY(1) 26 28 0.5E-3 1 Q1 5 2 7 QX Q2 6 9 8 QX R5 7 4 1.672 R6 8 4 1.672 D1 2 36 DZ D2 1 36 DZ EN 3 1 10 0 1 GN1 0 2 13 0 1E-3 GN2 0 1 16 0 1E-3 * EREF 98 0 28 0 1 EP 97 0 99 0 1 EM 51 0 50 0 1 * * VOLTAGE NOISE SOURCE * DN1 35 10 DEN DN2 10 11 DEN VN1 35 0 DC 2 VN2 0 11 DC 2 * * CURRENT NOISE SOURCE * DN3 12 13 DIN DN4 13 14 DIN VN3 12 0 DC 2 VN4 0 14 DC 2 * * CURRENT NOISE SOURCE * DN5 15 16 DIN DN6 16 17 DIN VN5 15 0 DC 2 VN6 0 17 DC 2 * * GAIN STAGE & DOMINANT POLE AT 32 HZ * R7 18 98 1.09E6 C3 18 98 4.55E-9 G1 98 18 5 6 4.57E-1 V2 97 19 1.35 V3 20 51 1.35 D3 18 19 DX D4 20 18 DX * * POLE/ZERO PAIR AT 1.5MHz/2.7MHz * R8 21 98 1E3 R9 21 22 1.25E3 C4 22 98 47.2E-12 G2 98 21 18 28 1E-3 * * POLE AT 100 MHZ * R10 23 98 1 C5 23 98 1.59E-9 G3 98 23 21 28 1 * * POLE AT 100 MHZ * R11 24 98 1 C6 24 98 1.59E-9 G4 98 24 23 28 1 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 1 kHZ * R12 25 26 1E6 C7 25 26 159.15E-12 R13 26 98 1 E2 25 98 POLY(2) 1 98 2 98 0 2.50 2.50 * * POLE AT 100 MHZ * R14 27 98 1 C8 27 98 1.59E-9 G5 98 27 24 28 1 * * OUTPUT STAGE * R15 28 99 100E3 R16 28 50 100E3 C9 28 50 1E-6 ISY 99 50 1.85E-3 R17 29 99 100 R18 29 50 100 L2 29 34 1E-9 G6 32 50 27 29 10E-3 G7 33 50 29 27 10E-3 G8 29 99 99 27 10E-3 G9 50 29 27 50 10E-3 V4 30 29 1.3 V5 29 31 3.8 F1 29 0 V4 1 F2 0 29 V5 1 D5 27 30 DX D6 31 27 DX D7 99 32 DX D8 99 33 DX D9 50 32 DY D10 50 33 DY * * MODELS USED * .MODEL QX PNP(BF=5E5) .MODEL DX D(IS=1E-12) .MODEL DY D(IS=1E-15 BV=50) .MODEL DZ D(IS=1E-15 BV=7.0) .MODEL DEN D(IS=1E-12 RS=4.35K KF=1.95E-15 AF=1) .MODEL DIN D(IS=1E-12 RS=268 KF=1.08E-15 AF=1) .ENDS * OP279 SPICE Macro-model Rev. A, 7/94 * ARG / PMI * * Copyright 1994 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of * this model indicates your acceptance of the terms and pro- * visions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP279 3 2 99 50 45 * * INPUT STAGE AND POLE AT 6MHZ * I1 1 50 60.2E-6 Q1 5 2 7 QN Q2 6 4 8 QN D1 4 2 DX D2 2 4 DX R1 1 7 1.628E3 R2 1 8 1.628E3 R3 5 99 2.487E3 R4 6 99 2.487E3 C1 5 6 5.333E-12 EOS 4 3 POLY(1) (16,39) 0.25E-3 50.118 IOS 2 3 5E-9 GB1 2 98 (24,98) 100E-9 GB2 4 98 (24,98) 100E-9 CIN 2 3 1E-12 * * GAIN STAGE AND DOMINANT POLE AT 16HZ * EREF 98 0 (39,0) 1 G1 98 9 (5,6) 402.124E-6 R7 9 98 497.359E6 C2 9 98 20E-12 V1 99 10 0.58 V2 11 50 0.47 D5 9 10 DX D6 11 9 DX * * COMMON MODE STAGE WITH ZERO AT 10KHZ * ECM 15 98 POLY(2) (3,39) (2,39) 0 0.5 0.5 R9 15 16 1E6 R10 16 98 10 C3 15 16 15.915E-12 * * ZERO AT 1.5MHZ * E1 14 98 (9,39) 1E6 R5 14 18 1E6 R6 18 98 1 C4 14 18 106.103E-15 * * BIAS CURRENT-VS-COMMON MODE VOLTAGE * EP 97 0 (99,0) 1 EN 51 0 (50,0) 1 V3 20 21 1.6 V4 22 23 2.8 R12 97 20 530 R13 23 51 1E3 D13 15 21 DX D14 22 15 DX FIB 98 24 POLY(2) V3 V4 0 -1 1 RIB 24 98 10E3 E3 97 25 POLY(1) (99,39) -1.63 1 E4 26 51 POLY(1) (39,50) -2.73 1 D15 24 25 DX D16 26 24 DX * * POLE AT 6MHZ * G6 98 40 (18,39) 1E-6 R20 40 98 1E6 C10 40 98 26.526E-15 * * OUTPUT STAGE * RS1 99 39 6.0345E3 RS2 39 50 6.0345E3 RO1 99 45 40 RO2 45 50 40 G7 45 99 (99,40) 25E-3 G8 50 45 (40,50) 25E-3 G9 98 60 (45,40) 25E-3 D9 60 61 DX D10 62 60 DX V7 61 98 DC 0 V8 98 62 DC 0 FSY 99 50 POLY(2) V7 V8 1.711E-3 1 1 D11 41 45 DZ D12 45 42 DZ V5 40 41 1.54 V6 42 40 1.54 .MODEL DX D() .MODEL DZ D(IS=1E-6) .MODEL QN NPN(BF=300) .ENDS * OP283 SPICE Macro-model Rev. A, 9/93 * JCB / ADI * * Copyright 1993 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of * this model indicates your acceptance of the terms and pro- * visions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP283 2 1 99 50 45 * * INPUT STAGE AND POLE AT 600KHZ * I1 99 8 1E-4 Q1 4 1 6 QP Q2 5 3 7 QP CIN 1 2 1.5PF R1 50 4 1591 R2 50 5 1591 C1 4 5 83.4E-12 R3 6 8 1075 R4 7 8 1075 IOS 1 2 12.5E-9 EOS 3 2 POLY(1) (15,98) 25E-6 1 DC1 2 36 DZ DC2 1 36 DZ * * GAIN STAGE AND DOMINANT POLE AT 10HZ * EREF 98 0 POLY(2) (99,0) (50,0) 0 0.5 0.5 G1 98 9 (4,5) 6.28E-4 R5 9 98 1.59E9 C2 9 98 10E-12 D1 9 10 DX D2 11 9 DX E1 10 98 POLY(1) 99 98 -1.35 1.03 V2 50 11 -0.63 * * COMMON MODE STAGE WITH ZERO AT 353HZ * ECM 14 98 POLY(2) (1,98) (2,98) 0 3.5 3.5 R7 14 15 1E6 C4 14 15 3.75E-11 R8 15 98 1 * *POLE AT 20MHZ * GP2 98 31 (9,98) 1E-6 RP2 31 98 1E6 CP2 31 98 7.96E-15 * *ZERO AT 1.5MHZ * EZ1 32 98 (31,98) 1E6 RZ1 32 33 1E6 RZ2 33 98 1 CZ1 32 33 106E-15 * *POLE AT 10MHZ * GP10 98 40 (33,98) 1E-6 RP10 40 98 1E6 CP10 40 98 15.9E-15 * * OUTPUT STAGE * RO1 99 45 140 RO2 45 50 140 G7 45 99 (99,40) 7.14E-3 G8 50 45 (40,50) 7.14E-3 G9 98 60 (45,40) 7.14E-3 D7 60 61 DX D8 62 60 DX V7 61 98 DC 0 V8 98 62 DC 0 GSY 99 50 (99,50) 5E-6 FSY 99 50 POLY(2) V7 V8 1.075E-3 1 1 D9 40 41 DX D10 42 40 DX V5 41 45 1.2 V6 45 42 1.5 * * MODELS USED * .MODEL DX D .MODEL DZ D(IS=1E-15 BV=7.0) .MODEL QP PNP(BF=143) .ENDS * OP284 SPICE Macro-model 11/95 / Rev. B * ARG / ADSC * * Revision History: * * Rev. B * Changed input transistor betas to conform to final data sheet * Ios typical spec of 60nA. * * * Copyright 1993 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance of the terms and provisions in the License * Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP284 1 2 99 50 45 * * INPUT STAGE * Q1 5 2 3 QIN 1 Q2 6 11 3 QIN 1 Q3 7 2 4 QIP 1 Q4 8 11 4 QIP 1 DC1 2 11 DC DC2 11 2 DC Q5 4 9 99 QIP 1 Q6 9 9 99 QIP 1 Q7 3 10 50 QIN 1 Q8 10 10 50 QIN 1 R1 99 5 4E3 R2 99 6 4E3 R3 7 50 4E3 R4 8 50 4E3 IREF 9 10 50.5E-6 EOS 1 11 POLY(2) (22,98) (14,98) -25E-6 1E-2 1 IOS 2 1 5E-9 CIN 1 2 2E-12 GN1 98 1 (17,98) 1E-3 GN2 98 2 (23,98) 1E-3 * * VOLTAGE NOISE SOURCE WITH FLICKER NOISE * VN1 13 98 DC 2 VN2 98 15 DC 2 DN1 13 14 DEN DN2 14 15 DEN * * CURRENT NOISE SOURCE WITH FLICKER NOISE * VN3 16 98 DC 2 VN4 98 18 DC 2 DN3 16 17 DIN DN4 17 18 DIN * * 2ND CURRENT NOISE SOURCE WITH FLICKER NOISE * VN5 19 98 DC 2 VN6 98 24 DC 2 DN5 19 23 DIN DN6 23 24 DIN * * GAIN STAGE * EREF 98 0 POLY(2) (99,0) (50,0) 0 0.5 0.5 G1 98 20 POLY(2) (6,5) (8,7) 0 0.5E-3 0.5E-3 R9 20 98 1E3 * * COMMON MODE STAGE WITH ZERO AT 100HZ * ECM 98 21 POLY(2) (1,98) (2,98) 0 0.5 0.5 R10 21 22 1 R11 22 98 100E-6 C4 21 22 1.592E-3 * * NEGATIVE ZERO AT 20MHZ * E1 27 98 (20,98) 1E6 R17 27 28 1 R18 28 98 1E-6 C8 25 26 7.958E-9 ENZ 25 98 (27,28) 1 VNZ 26 98 DC 0 FNZ 27 28 VNZ -1 * * POLE AT 40MHZ * G4 98 29 (28,98) 1 R19 29 98 1 C9 29 98 3.979E-9 * * POLE AT 40MHZ * G5 98 30 (29,98) 1 R20 30 98 1 C10 30 98 3.979E-9 * * OUTUT STAGE * ISY 99 50 0.276E-3 GIN 50 31 POLY(1) (30,98) .862574E-6 505.879E-6 RIN 31 50 2.75E6 VB 99 32 0.7 Q11 32 31 33 QON 1 R21 33 34 4.5E3 I1 34 50 50E-6 R22 99 35 6E3 Q12 36 36 35 QOP 1 I2 36 50 50E-6 R23 99 37 2.6E3 R24 34 38 5E3 Q13 39 36 37 QOP 1 Q14 39 38 40 QON 1.5 R25 40 50 40 Q15 39 39 41 QON 1 R26 41 42 1E3 R27 99 43 220 Q16 44 44 43 QOP 1.5 Q17 44 39 42 QON 1 R28 42 50 2E3 VSCP 99 97 DC 0 FSCP 46 99 VSCP 1 RSCP 46 99 40 Q20 44 46 99 QOP 1 Q18 45 44 97 QOP 4.5 Q19 45 34 51 QON 4.5 VSCN 51 50 DC 0 FSCN 50 47 VSCN 1 RSCN 47 50 40 Q21 34 47 50 QON 1 CC2 31 45 20E-12 CF1 31 34 15E-12 CF2 31 42 15E-12 CO1 34 45 15E-12 CO2 42 45 5E-12 D3 45 99 DX D4 50 45 DX .MODEL DC D(IS=130E-21) .MODEL DX D() .MODEL DEN D(RS=100 KF=12E-15 AF=1) .MODEL DIN D(RS=5.358 KF=56E-15 AF=1) .MODEL QIN NPN(BF=120 VA=200 IS=0.5E-16) .MODEL QIP PNP(BF=90 VA=60 IS=0.5E-16) .MODEL QON NPN(BF=200 VA=200 IS=0.5E-16 RC=50) .MODEL QOP PNP(BF=200 VA=200 IS=0.5E-16 RC=160) .ENDS * OP290 SPICE Macro-model 10/92, Rev. C * JCB / PMI * * Revision History: * REV. C * Altered gain stage for proper open-loop gain. * REV. B * Re-ordered subcircuit call out nodes to put the * output node last. * Changed Ios from 0.1E-9 to 0.05E-9 * * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP290 1 2 99 50 31 * * INPUT STAGE & POLE AT 10 KHZ * R1 2 3 5E11 R2 1 3 5E11 R3 5 51 61.6E3 R4 6 51 61.6E3 CIN 1 2 4E-12 C2 5 6 129.2E-12 I1 97 4 1UA IOS 1 2 0.05E-9 EOS 9 1 POLY(1) 23 27 50E-6 1 Q1 5 2 7 QX Q2 6 9 8 QX R5 7 4 10E3 R6 8 4 10E3 * EREF 98 0 27 0 1 EPLUS 97 0 99 0 1 ENEG 51 0 50 0 1 * * FIRST GAIN STAGE * R7 10 98 1E6 G1 98 10 5 6 42.23E-6 D1 10 11 DX D2 12 10 DX E1 97 11 POLY(1) 97 27 -1.4 1 E2 12 51 POLY(1) 27 51 -1.4 1 * * GAIN STAGE & DOMINANT POLE AT 0.035 HZ * R8 13 98 5.457E6 C3 13 98 83.333E-8 G2 98 13 10 27 5E-3 H2 97 14 POLY(1) VS2 1.6 -3E3 E5 15 51 POLY(2) (17,51) (97,27) 1.4 1.5 -0.4 D3 13 14 DX D4 15 13 DX * * ZERO-IN ZERO-OUT CLAMP * F1 51 17 VS2 -1000 RS1 17 51 1E9 D5 17 51 DX D6 51 17 DX * * NEGATIVE ZERO AT -100 KHZ * R9 19 20 1E6 C4 19 20 -1.59E-12 R10 20 98 1 E3 19 98 13 27 1E6 * * ZERO - POLE PAIR AT 28 KHZ / 100 KHZ * R11 21 22 1E6 L1 22 98 4.09 R12 22 98 2.57E6 G3 98 21 20 27 1E-6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 4 HZ * R13 23 24 1E6 L2 24 98 39.79E3 G4 98 23 3 27 3.16E-13 D8 23 97 DX D9 51 23 DX * * ZERO - POLE PAIR AT 40 KHZ / 160 KHZ * R14 25 26 1E6 L3 26 98 2.98 R15 26 98 3E6 G5 98 25 21 27 1E-6 * * OUTPUT STAGE * ISY 99 50 9.167E-6 R16 27 99 4.5E6 R17 27 50 4.5E6 R18 30 99 6000 R19 30 50 6000 VS2 30 31 DC 0 G6 28 50 25 30 166.7E-6 G7 29 50 30 25 166.7E-6 G8 30 99 99 25 166.7E-6 G9 50 30 25 50 166.7E-6 D10 99 28 DX D11 99 29 DX D12 50 28 DY D13 50 29 DY * * MODELS USED * .MODEL QX PNP(BF=125) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP291 SPICE Macro-model Rev. A, 5/94 * ARG / PMI * * Copyright 1994 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of * this model indicates your acceptance of the terms and pro- * visions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP291 1 2 99 50 45 * * INPUT STAGE * I1 99 7 8.06E-6 Q1 6 4 7 QP Q2 5 3 7 QP D1 3 99 DX D2 4 99 DX D3 3 4 DX D4 4 3 DX R1 3 8 5E3 R2 4 2 5E3 R3 5 50 6.4654E3 R4 6 50 6.4654E3 EOS 8 1 POLY(1) (16,39) -80E-6 1 IOS 3 4 50E-12 GB1 3 98 (21,98) 50E-9 GB2 4 98 (21,98) 50E-9 CIN 1 2 1E-12 * * 1ST GAIN STAGE * EREF 98 0 (39,0) 1 G1 98 9 (6,5) 31.667E-6 R7 9 98 1E6 EC1 99 10 POLY(1) (99,39) -0.52 1 EC2 11 50 POLY(1) (39,50) -0.52 1 D5 9 10 DX D6 11 9 DX * * 2ND GAIN STAGE AND DOMINANT POLE AT 36HZ * G2 98 12 (9,39) 8E-6 R8 12 98 276.311E6 C2 12 98 16E-12 D7 12 13 DX D8 14 12 DX V1 99 13 0.58 V2 14 50 0.58 * * COMMON MODE STAGE * ECM 15 98 POLY(2) (1,39) (2,39) 0 0.5 0.5 R9 15 16 1E6 R10 16 98 10 * * POLE AT 2.5MHZ * G3 98 18 (12,39) 1E-6 R11 18 98 1E6 C4 18 98 63.662E-15 * * BIAS CURRENT-VS-COMMON MODE VOLTAGE * EP 97 0 (99,0) 1 VB 99 17 1.3 RB 17 50 1E9 E3 19 0 (15,17) 16 D13 19 20 DX R12 20 0 1E6 G4 98 21 (20,0) 1E-3 R13 21 98 5E3 D14 21 22 DY E4 97 22 (POLY(1) (99,98) -0.765 1 * * POLE AT 100MHZ * G6 98 40 (18,39) 1E-6 R20 40 98 1E6 C10 40 98 1.592E-15 * * OUTPUT STAGE * RS1 99 39 109.375E3 RS2 39 50 109.375E3 RO1 99 45 41.667 RO2 45 50 41.667 G7 45 99 (99,40) 24E-3 G8 50 45 (40,50) 24E-3 G9 98 60 (45,40) 24E-3 D9 60 61 DX D10 62 60 DX V7 61 98 DC 0 V8 98 62 DC 0 FSY 99 50 POLY(2) V7 V8 0.207E-3 1 1 D11 41 45 DZ D12 45 42 DZ V5 40 41 0.131 V6 42 40 0.131 .MODEL DX D() .MODEL DY D(IS=1E-9) .MODEL DZ D(IS=1E-6) .MODEL QP PNP(BF=133.333) .ENDS * OP292 SPICE Macro-model Rev. B, 3/95 * ARG / ADSC * * Copyright 1993 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of * this model indicates your acceptance of the terms and pro- * visions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP292 2 1 99 50 34 * * INPUT STAGE AND POLE AT 40MHZ * I1 99 4 50E-6 IOS 2 1 10E-9 EOS 2 3 POLY(1) (21,30) 1.5E-3 75 CIN 1 2 3E-12 Q1 5 1 7 QP Q2 6 3 8 QP R3 5 50 2E3 R4 6 50 2E3 R5 4 7 966 R6 4 8 966 C1 5 6 .995E-12 * * GAIN STAGE * EREF 98 0 (30,0) 1 G1 98 9 (5,6) 500E-6 R7 9 98 210.819E3 D1 9 10 DX D2 11 9 DX V1 99 10 .6 V2 11 50 .6 * * ZERO/POLE AT 6MHZ/12MHZ * E1 12 98 (9,30) 2 R8 12 13 1 R9 13 98 1 C3 12 13 26.526E-9 * * ZERO AT 15MHZ * E2 14 98 (13,30) 1E6 R10 14 15 1E6 R11 15 98 1 C4 14 15 10.610E-15 * * COMMON MODE STAGE WITH ZERO AT 40KHZ * ECM 20 98 POLY(2) (1,30) (2,30) 0 0.5 0.5 R20 20 21 1E6 R21 21 98 1 C5 20 21 3.979E-12 * * POLE AT 100MHZ * G2 98 16 (15,30) 1 R12 16 98 1 C6 16 98 1.592E-9 * * OUTPUT STAGE * RS1 99 30 1E6 RS2 30 50 1E6 ISY 99 50 .44E-3 G3 31 50 POLY(1) (16,30) -1.635E-6 4E-6 R16 31 50 1E6 DCL 50 31 DZ I2 99 32 250E-6 RCL 33 50 56 M1 32 31 50 50 MN L=9E-6 W=1000E-6 AD=15E-9 AS=15E-9 M2 34 31 50 50 MN L=9E-6 W=1000E-6 AD=15E-9 AS=15E-9 CC 31 32 14E-12 Q3 99 32 34 QNA Q4 33 32 34 QPA Q5 31 33 50 QNA .MODEL QNA NPN(IS=1.19E-16 BF=253 NF=0.99 VAF=193 IKF=2.76E-3 + ISE=2.57E-13 NE=5 BR=0.4 NR=0.988 VAR=15 IKR=1.465E-4 + ISC=6.9E-16 NC=0.99 RB=2.0E3 IRB=7.73E-6 RBM=132.8 RE=4 RC=209 + CJE=2.1E-13 VJE=0.573 MJE=0.364 FC=0.5 CJC=1.64E-13 VJC=0.534 MJC=0.5 + CJS=1.37E-12 VJS=0.59 MJS=0.5 TF=0.43E-9 PTF=30) .MODEL QPA PNP(IS=5.21E-17 BF=131 NF=0.99 VAF=62 IKF=8.35E-4 + ISE=1.09E-14 NE=2.61 BR=0.5 NR=0.984 VAR=15 IKR=3.96E-5 + ISC=7.58E-16 NC=0.985 RB=1.52E3 IRB=1.67E-5 RBM=368.5 RE=6.31 RC=354.4 + CJE=1.1E-13 VJE=0.745 MJE=0.33 FC=0.5 CJC=2.37E-13 VJC=0.762 MJC=0.4 + CJS=7.11E-13 VJS=0.45 MJS=0.412 TF=1.0E-9 PTF=30) .MODEL MN NMOS(LEVEL=3 VTO=1.3 RS=0.3 RD=0.3 + TOX=8.5E-8 LD=1.48E-6 WD=1E-6 NSUB=1.53E16 UO=650 DELTA=10 VMAX=2E5 + XJ=1.75E-6 KAPPA=0.8 ETA=0.066 THETA=0.01 TPG=1 CJ=2.9E-4 PB=0.837 + MJ=0.407 CJSW=0.5E-9 MJSW=0.33) .MODEL QP PNP(BF=61.5) .MODEL DX D .MODEL DZ D(BV=3.6) .ENDS * OP293 SPICE Macro-model 1/95, Rev. A * ARG / ADI * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License * Statement. This model has been optimized for a total supply voltage of * 5V. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP293 51 52 99 50 32 * * INPUT STAGE & POLE AT 16KHZ * R3 5 50 53.827E3 R4 6 50 53.827E3 R5 4 7 2.104E3 R6 4 8 2.104E3 CIN 1 2 4E-12 C2 5 6 92.4E-12 I1 99 4 1.006E-6 IOS 1 2 0.05E-9 EOS 9 1 POLY(2) (24,27) (102,0) 25E-6 15.851E-3 1 Q1 5 2 7 QX Q2 6 9 8 QX EREF 98 0 POLY(2) (99,0) (50,0) 0 0.5 0.5 R24 1 51 2E3 R25 2 52 2E3 VN1 101 0 DC 2 VN2 0 103 DC 2 DN1 101 102 DEN DN2 102 103 DEN * * GAIN STAGE & DOMINANT POLE AT 0.21 HZ * R7 10 98 9.151E9 G1 98 10 (5,6) 18.578E-6 C3 10 98 83.333E-12 V1 99 11 0.65 D1 10 11 DX D2 50 10 DX * * NEGATIVE ZERO AT 50KHZ * R9 13 14 1E6 R10 14 98 1 FNZ 13 14 VNZ -1 E2 13 98 (10,27) 1 CNZ 15 16 3.183E-12 ENZ 15 98 (13,14) 1 VNZ 16 98 DC 0 * * ZERO-POLE PAIR AT 28KHZ / 84KHZ * R18 17 18 2E6 C4 17 18 2.842E-12 R19 18 98 1E6 E3 17 98 (14,27) 3E6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 0.5HZ * R1 23 24 1E6 R2 24 98 100 C5 23 24 318E-9 E4 23 98 POLY(2) (1,27) (2,27) 0 0.5 0.5 * * ZERO-POLE PAIR AT 40KHZ / 160KHZ * R20 25 26 3E6 C6 25 26 1.326E-12 R21 26 98 1E6 E5 25 98 (18,27) 4 * * OUTPUT STAGE * ISY 99 50 9.637E-6 R16 27 99 4.5E6 R17 27 50 4.5E6 EIN 28 98 POLY(1) (26,27) 0.52255 1.05 RIN 28 31 15E3 Q11 45 31 32 QN 6 Q12 32 33 44 QN 6 Q13 41 34 33 QN 1 Q14 34 35 36 QP 1 Q15 36 38 39 QN 8 Q16 35 35 37 QP 1 Q17 99 99 37 QN 1 Q18 99 99 36 QN 1 Q19 50 42 34 QP 1 Q20 42 42 34 QP 1 Q21 32 33 42 QN 1 Q22 99 40 41 QN 1 Q23 43 43 50 QN 1 Q24 34 43 50 QN 2 Q25 33 43 50 QN 2 Q26 34 44 50 QC 1 Q27 31 46 50 QC 1 EC 47 50 (99,45) 0.96 RC 46 47 1E3 IREF 99 43 4.5E-7 I13 35 50 4.5E-7 R11 99 40 75E3 R12 99 36 40E3 R13 31 38 20E3 R14 32 39 5E3 R15 40 37 75E3 R22 44 50 30 R23 99 45 50 * * MODELS USED * .MODEL QN NPN(BF=200 IS=1E-16 VA=150) .MODEL QP PNP(BF=100 IS=5E-17 VA=50) .MODEL QX PNP(BF=166.667 KF=2E-17) .MODEL QC NPN(BF=200 IS=2E-11) .MODEL DX D(IS=1E-15) .MODEL DEN D(RS=2.45E3 KF=33E-15) .ENDS * OP295 SPICE Macro-model 2/95, Rev. B * ARG / ADSC * * Revision History: * * Rev. B * Added common mode stage to base model. * Changed G1 to a polynomial source to correct output stage offset. * * * Copyright 1995 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License * Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP295 1 2 99 50 20 * * INPUT STAGE * I1 99 4 2E-6 R1 1 6 5E3 R2 2 5 5E3 CIN 1 2 2E-12 IOS 1 2 0.5E-9 D1 5 3 DZ D2 6 3 DZ EOS 7 6 POLY(1) (31,39) 30E-6 0.024 Q1 8 5 4 QP Q2 9 7 4 QP R3 8 50 25.8E3 R4 9 50 25.8E3 * * GAIN STAGE * R7 10 98 270E6 G1 98 10 POLY(1) (9,8) -4.26712E-9 27.8E-6 EREF 98 0 (39,0) 1 R5 99 39 100E3 R6 39 50 100E3 * * COMMON MODE STAGE * ECM 30 98 POLY(2) (1,39) (2,39) 0 0.5 0.5 R12 30 31 1E6 R13 31 98 100 * * OUTPUT STAGE * I2 18 50 1.59E-6 V2 99 12 DC 2.2763 Q4 10 14 50 QNA 1.0 R11 14 50 33 M3 15 10 13 13 MN L=9E-6 W=102E-6 AD=15E-10 AS=15E-10 M4 13 10 50 50 MN L=9E-6 W=50E-6 AD=75E-11 AS=75E-11 D8 10 22 DX V3 22 50 DC 6 M2 20 10 14 14 MN L=9E-6 W=2000E-6 AD=30E-9 AS=30E-9 Q5 17 17 99 QPA 1.0 Q6 18 17 99 QPA 4.0 R8 18 99 2.2E6 Q7 18 19 99 QPA 1.0 R9 99 19 8 C2 18 99 20E-12 M6 15 12 17 99 MP L=9E-6 W=27E-6 AD=405E-12 AS=405E-12 M1 20 18 19 99 MP L=9E-6 W=2000E-6 AD=30E-9 AS=30E-9 D4 21 18 DX V4 99 21 DC 6 R10 10 11 6E3 C3 11 20 50E-12 .MODEL QNA NPN(IS=1.19E-16 BF=253 NF=0.99 VAF=193 IKF=2.76E-3 + ISE=2.57E-13 NE=5 BR=0.4 NR=0.988 VAR=15 IKR=1.465E-4 + ISC=6.9E-16 NC=0.99 RB=2.0E3 IRB=7.73E-6 RBM=132.8 RE=4 RC=209 + CJE=2.1E-13 VJE=0.573 MJE=0.364 FC=0.5 CJC=1.64E-13 VJC=0.534 MJC=0.5 + CJS=1.37E-12 VJS=0.59 MJS=0.5 TF=0.43E-9 PTF=30) .MODEL QPA PNP(IS=5.21E-17 BF=131 NF=0.99 VAF=62 IKF=8.35E-4 + ISE=1.09E-14 NE=2.61 BR=0.5 NR=0.984 VAR=15 IKR=3.96E-5 + ISC=7.58E-16 NC=0.985 RB=1.52E3 IRB=1.67E-5 RBM=368.5 RE=6.31 RC=354.4 + CJE=1.1E-13 VJE=0.745 MJE=0.33 FC=0.5 CJC=2.37E-13 VJC=0.762 MJC=0.4 + CJS=7.11E-13 VJS=0.45 MJS=0.412 TF=1.0E-9 PTF=30) .MODEL MN NMOS(LEVEL=3 VTO=1.3 RS=0.3 RD=0.3 + TOX=8.5E-8 LD=1.48E-6 NSUB=1.53E16 UO=650 DELTA=10 VMAX=2E5 + XJ=1.75E-6 KAPPA=0.8 ETA=0.066 THETA=0.01 TPG=1 CJ=2.9E-4 PB=0.837 + MJ=0.407 CJSW=0.5E-9 MJSW=0.33) .MODEL MP PMOS(LEVEL=3 VTO=-1.1 RS=0.7 RD=0.7 + TOX=9.5E-8 LD=1.4E-6 NSUB=2.4E15 UO=650 DELTA=5.6 VMAX=1E5 + XJ=1.75E-6 KAPPA=1.7 ETA=0.71 THETA=5.9E-3 TPG=-1 CJ=1.55E-4 PB=0.56 + MJ=0.442 CJSW=0.4E-9 MJSW=0.33) .MODEL DX D(IS=1E-15) .MODEL DZ D(IS=1E-15, BV=7) .MODEL QP PNP(BF=125) .ENDS * OP297 SPICE Macro-model 10/91, Rev. C * JCB / PMI * * Revision History: * REV. C * Changed V1 and V2 for output voltage swing * Changed ISY to correct the supply current * Altered V5 for short circuit current limit * REV. B * Re-ordered subcircuit call out nodes to put the * output node last. * Changed Ios from 20E-12 to 10E-12 * * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP297 1 2 99 50 30 * * INPUT STAGE & POLE AT 6 MHZ * RIN1 1 7 2500 RIN2 2 8 2500 R1 8 3 5E11 R2 7 3 5E11 R3 5 99 612 R4 6 99 612 CIN 7 8 3E-12 C2 5 6 21.67E-12 I1 4 50 0.1E-3 IOS 7 8 10E-12 EOS 9 7 POLY(1) 19 23 25E-6 1 Q1 5 8 10 QX Q2 6 9 11 QX R5 10 4 96 R6 11 4 96 D1 8 9 DX D2 9 8 DX * EREF 98 0 23 0 1 * * GAIN STAGE & DOMINANT POLE AT 0.13 HZ * R7 12 98 2.45E9 C3 12 98 500E-12 G1 98 12 5 6 1.634E-3 V2 99 13 1.2 V3 14 50 1.2 D3 12 13 DX D4 14 12 DX * * NEGATIVE ZERO AT -1.8 MHZ * R8 15 16 1E6 C4 15 16 -88.4E-15 R9 16 98 1 E1 15 98 12 23 1E6 * * POLE AT 1.8 MHZ * R10 17 98 1E6 C5 17 98 88.4E-15 G2 98 17 16 23 1E-6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 50 HZ * R11 18 19 1E6 C6 18 19 3.183E-9 R12 19 98 1 E2 18 98 3 23 100E-3 * * POLE AT 6 MHZ * R15 22 98 1E6 C8 22 98 26.53E-15 G3 98 22 17 23 1E-6 * * OUTPUT STAGE * R16 23 99 500K R17 23 50 500K ISY 99 50 133E-6 R18 25 99 200 R19 25 50 200 L1 25 30 1E-7 G4 28 50 22 25 5E-3 G5 29 50 25 22 5E-3 G6 25 99 99 22 5E-3 G7 50 25 22 50 5E-3 V4 26 25 1.8 V5 25 27 1.8 D5 22 26 DX D6 27 22 DX D7 99 28 DX D8 99 29 DX D9 50 28 DY D10 50 29 DY * * MODELS USED * .MODEL QX NPN(BF=2.5E6) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP400 SPICE Macro-model 12/90, Rev. B * AAG / PMI * * Revision History: * Re-ordered subcircuit call out nodes to put the * output node last. * Changed Ios from 100E-12 to 50E-12 * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP400 1 2 99 50 25 * * INPUT STAGE & POLE AT 4.5 MHZ * RI1 2 31 1E3 RI2 1 32 1E3 R1 31 3 5E5 R2 32 3 5E5 R3 5 99 516 R4 6 99 516 CIN 32 31 3.2E-12 C2 5 6 34.271E-12 I1 4 50 0.1E-3 IOS 32 31 50E-12 EOS 7 32 POLY(1) 13 19 4E-5 1 Q1 5 31 4 QX Q2 6 7 4 QX D21 31 7 DX D22 7 31 DX * * FIRST GAIN STAGE & DOMINANT POLE AT 0.125 HZ * R5 8 99 1.9098E9 R6 8 50 1.9098E9 C3 8 99 666.67E-12 C4 8 50 666.67E-12 G1 99 8 POLY(1) 5 6 200E-6 1.938E-3 G2 8 50 POLY(1) 6 5 200E-6 1.938E-3 D1 8 99 DX D2 50 8 DX * * SECOND GAIN STAGE & POLE AT 4.5 MHZ * R7 10 99 1E6 R8 10 50 1E6 C5 10 99 35.368E-15 C6 10 50 35.368E-15 G3 99 10 8 19 1.3509E-6 G4 10 50 19 8 1.3509E-6 V2 99 9 2.7 V3 11 50 2.7 D3 10 9 DX D4 11 10 DX * * POLE AT 4.5 MHZ * R9 12 99 1E6 R10 12 50 1E6 C7 12 99 35.368E-15 C8 12 50 35.368E-15 G5 99 12 10 19 1E-6 G6 12 50 19 10 1E-6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 20 HZ * R11 13 14 1E6 R12 13 15 1E6 L1 14 99 7.9578E3 L2 15 50 7.9578E3 G7 99 13 3 19 1E-13 G8 13 50 19 3 1E-13 D5 13 99 DX D6 50 13 DX * * POLE AT 4.5 MHZ * R14 18 99 1E6 R15 18 50 1E6 C9 18 99 35.368E-15 C10 18 50 35.368E-15 G9 99 18 12 19 1E-6 G10 18 50 19 12 1E-6 * * OUTPUT STAGE * R16 19 99 62.22E3 R17 19 50 62.22E3 R18 24 99 250 R19 24 50 250 L3 24 25 7E-7 G11 22 50 18 24 4E-3 G12 23 50 24 18 4E-3 G13 24 99 99 18 4E-3 G14 50 24 18 50 4E-3 V6 20 24 3 V7 24 21 3 D7 18 20 DX D8 21 18 DX D9 99 22 DX D10 99 23 DX D11 50 22 DY D12 50 23 DY * * MODELS USED * .MODEL QX NPN(BF=66667) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP41 SPICE Macro-model 12/90, Rev. A * * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP41 1 2 99 50 20 * * INPUT STAGE * R1 1 3 5E12 R2 2 3 5E12 R3 5 50 3.45K R4 6 50 3.45K CIN 1 2 5E-12 I1 99 4 1E-4 IOS 1 2 0.02E-12 EOS 7 1 POLY(1) 12 14 0.2E-3 1 J1 5 2 4 JX J2 6 7 4 JX GB1 2 50 POLY(3) 4,2 5,2 50,2 0 1E-12 1E-12 1E-12 GB2 7 50 POLY(3) 4,7 6,7 50,7 0 1E-12 1E-12 1E-12 * EREF 98 0 14 0 1 * * GAIN STAGE & DOMINANT POLE AT 0.12 HZ * R5 8 98 17.3E9 C2 8 98 76.9E-12 G1 98 8 5 6 290E-6 V2 99 9 2.4 V3 10 50 2.4 D1 8 9 DX D2 10 8 DX * * COMMON-MODE GAIN NETWORK WITH ZERO AT 200 HZ * R6 11 12 1E6 C3 11 12 798E-12 R7 12 98 1 E2 11 98 3 14 1.78 * * POLE AT 2 MHZ * R8 13 98 1E6 C4 13 98 79.6E-15 G2 98 13 8 14 1E-6 * * OUTPUT STAGE * R9 14 99 400E3 R10 14 50 400E3 ISY 99 50 612.5E-6 R11 15 99 200 R12 15 50 200 L3 15 20 2.5E-8 G3 18 50 13 15 5E-3 G4 19 50 15 13 5E-3 G5 15 99 99 13 5E-3 G6 50 15 13 50 5E-3 V4 16 15 1.3 V5 15 17 1.1 D3 13 16 DX D4 17 13 DX D5 99 18 DX D6 99 19 DX D7 50 18 DY D8 50 19 DY * * MODELS USED * .MODEL JX PJF(BETA=421E-6 VTO=-2.000 IS=1.5E-12) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP42 SPICE Macro-model 12/90, Rev. D * JCB / PMI * * Revision History: * REV. D * Re-ordered subcircuit call out nodes to put the * output node last. * Changed Ios from 4E-12 to 2E-12 * * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP42 1 2 99 50 32 * * INPUT STAGE & POLE AT 15.9 MHZ * R1 1 3 5E11 R2 2 3 5E11 R3 5 50 707.36 R4 6 50 707.36 CIN 1 2 5E-12 C2 5 6 7.08E-12 I1 99 4 1E-3 IOS 1 2 2E-12 EOS 7 1 POLY(1) 20 26 0.3E-3 1 J1 5 2 4 JX J2 6 7 4 JX * * SECOND STAGE & POLE AT 45 HZ * R5 9 99 176.84E6 R6 9 50 176.84E6 C3 9 99 20E-12 C4 9 50 20E-12 G1 99 9 POLY(1) 5 6 3.96E-3 1.4137E-3 G2 9 50 POLY(1) 6 5 3.96E-3 1.4137E-3 V2 99 8 2.5 V3 10 50 3.1 D1 9 8 DX D2 10 9 DX * * POLE-ZERO PAIR AT 1.80 MHZ / 2.20 MHZ * R7 11 99 1E6 R8 11 50 1E6 R9 11 12 4.5E6 R10 11 13 4.5E6 C5 12 99 16.1E-15 C6 13 50 16.1E-15 G3 99 11 9 26 1E-6 G4 11 50 26 9 1E-6 * * POLE-ZERO PAIR AT 1.80 MHZ / 2.20 MHZ * R11 14 99 1E6 R12 14 50 1E6 R13 14 15 4.5E6 R14 14 16 4.5E6 C7 15 99 16.1E-15 C8 16 50 16.1E-15 G5 99 14 11 26 1E-6 G6 14 50 26 11 1E-6 * * POLE AT 53 MHZ * R15 17 99 1E6 R16 17 50 1E6 C9 17 99 3E-15 C10 17 50 3E-15 G7 99 17 14 26 1E-6 G8 17 50 26 14 1E-6 * * POLE AT 53 MHZ * R17 18 99 1E6 R18 18 50 1E6 C11 18 99 3E-15 C12 18 50 3E-15 G9 99 18 17 26 1E-6 G10 18 50 26 17 1E-6 * * POLE AT 53 MHZ * R19 19 99 1E6 R20 19 50 1E6 C13 19 99 3E-15 C14 19 50 3E-15 G11 99 19 18 26 1E-6 G12 19 50 26 18 1E-6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 100 KHZ * R21 20 21 1E6 R22 20 23 1E6 L1 21 99 1.5915 L2 23 50 1.5915 G13 99 20 3 26 1.58E-11 G14 20 50 26 3 1.58E-11 * * POLE AT 79.6 MHZ * R24 25 99 1E6 R25 25 50 1E6 C15 25 99 2E-15 C16 25 50 2E-15 G15 99 25 19 26 1E-6 G16 25 50 26 19 1E-6 * * OUTPUT STAGE * R26 26 99 111.1E3 R27 26 50 111.1E3 R28 27 99 90 R29 27 50 90 L3 27 32 2.5E-7 G17 30 50 25 27 11.1111E-3 G18 31 50 27 25 11.1111E-3 G19 27 99 99 25 11.1111E-3 G20 50 27 25 50 11.1111E-3 V6 28 27 0.7 V7 27 29 0.7 D5 25 28 DX D6 29 25 DX D7 99 30 DX D8 99 31 DX D9 50 30 DY D10 50 31 DY * * MODELS USED * .MODEL JX PJF(BETA=999.3E-6 VTO=-2.000 IS=4E-11) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP420 SPICE Macro-model 9/91, Rev. A * JCB / PMI * * Copyright 1991 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP420 1 2 99 50 30 * * INPUT STAGE & POLE AT 1.5 MEGHZ * R1 2 3 5E11 R2 1 3 5E11 R3 5 50 5.16K R4 6 50 5.16K CIN 1 2 4E-12 C2 5 6 15.42E-12 I1 99 4 10UA IOS 1 2 0.25E-9 EOS 9 1 POLY(1) 24 27 500E-6 1 Q1 5 2 4 QX Q2 6 9 4 QX * EREF 98 0 27 0 1 * * FIRST GAIN STAGE * R5 10 98 1E6 G1 98 10 5 6 41.47E-6 D1 10 11 DX D2 12 10 DX E1 99 11 POLY(1) 99 27 -1.475 1 E2 12 50 POLY(1) 27 50 -1.475 1 * * GAIN STAGE & DOMINANT POLE AT 0.15 HZ * R6 13 98 5.31E9 C3 13 98 200E-12 G2 98 13 10 27 5E-6 V1 99 14 1.04 V2 15 50 1.04 D3 13 14 DX D4 15 13 DX * * COMMON-MODE GAIN NETWORK WITH ZERO AT 200 HZ * R7 24 98 1 R8 23 24 1E6 C4 23 24 0.796E-9 E4 98 23 3 27 10 * * POLE AT 600 KHZ * R9 25 98 1E6 C5 25 98 265E-15 G3 98 25 13 27 1E-6 * * OUTPUT STAGE * ISY 99 50 15.5E-6 R10 27 99 263E3 R11 27 50 263E3 R12 30 99 2000 R13 30 50 2000 G4 28 50 25 30 0.5E-3 G5 29 50 30 25 0.5E-3 G6 30 99 99 25 0.5E-3 G7 50 30 25 50 0.5E-3 D5 99 28 DX D6 99 29 DX D7 50 28 DY D8 50 29 DY D9 25 31 DX V3 31 30 5.3 D10 32 25 DX V4 30 32 0.9 * * MODELS USED * .MODEL QX PNP(BF=555.6) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP421 SPICE Macro-model 5/91, Rev. A * JCB / PMI * * * Copyright 1991 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP421 1 2 99 50 31 * * INPUT STAGE & POLE AT 2.8 MEGHZ * R1 2 3 5E11 R2 1 3 5E11 R3 5 50 5.16K R4 6 50 5.16K CIN 1 2 2E-12 C2 5 6 5.51E-12 I1 99 4 10UA IOS 1 2 0.6E-9 EOS 9 1 POLY(1) 24 27 500E-6 1 Q1 5 2 4 QX Q2 6 9 4 QX * EREF 98 0 27 0 1 * * FIRST GAIN STAGE * R5 10 98 1E6 G1 98 10 5 6 23.1E-6 D1 10 11 DX D2 12 10 DX E1 99 11 POLY(1) 99 27 -1.4 1 E2 12 50 POLY(1) 27 50 -1.4 1 * * GAIN STAGE & DOMINANT POLE AT 2.3 HZ * R6 13 98 3.46E9 C3 13 98 20E-12 G2 98 13 10 27 5E-6 V1 99 14 1.3 V2 15 50 0.9 D3 13 14 DX D4 15 13 DX * * POLE AT 3.0 MEGHZ * R9 16 98 1E6 C5 16 98 53.1E-15 G3 98 16 13 27 1E-6 * * POLE AT 3.0 MEGHZ * R15 17 98 1E6 C7 17 98 53.1E-15 G10 98 17 16 27 1E-6 ** * COMMON-MODE GAIN NETWORK WITH ZERO AT 3 KHZ * R7 24 98 1 R8 23 24 1E6 C4 23 24 53.1E-12 E4 98 23 3 27 10 * * POLE AT 3.0 MEGHZ * R14 25 98 1E6 C6 25 98 53.1E-15 G9 98 25 17 27 1E-6 * * OUTPUT STAGE * ISY 99 50 140E-6 R10 27 99 33.3E3 R11 27 50 33.3E3 R12 30 99 450 R13 30 50 450 L1 30 31 1E-8 G4 28 50 25 30 2.22E-3 G5 29 50 30 25 2.22E-3 G6 30 99 99 25 2.22E-3 G7 50 30 25 50 2.22E-3 D5 99 28 DX D6 99 29 DX D7 50 28 DY D8 50 29 DY D9 25 33 DX V3 33 30 1.7 D10 32 25 DX V4 30 32 1.7 * * MODELS USED * .MODEL QX PNP(BF=250) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP484 SPICE Macro-model 11/95 / Rev. A * ARG / ADSC * * Copyright 1993 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance of the terms and provisions in the License * Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP484 1 2 99 50 45 * * INPUT STAGE * Q1 5 2 3 QIN 1 Q2 6 11 3 QIN 1 Q3 7 2 4 QIP 1 Q4 8 11 4 QIP 1 DC1 2 11 DC DC2 11 2 DC Q5 4 9 99 QIP 1 Q6 9 9 99 QIP 1 Q7 3 10 50 QIN 1 Q8 10 10 50 QIN 1 R1 99 5 4E3 R2 99 6 4E3 R3 7 50 4E3 R4 8 50 4E3 IREF 9 10 50.5E-6 EOS 1 11 POLY(2) (22,98) (14,98) -25E-6 1E-2 1 IOS 2 1 1E-9 CIN 1 2 2E-12 GN1 98 1 (17,98) 1E-3 GN2 98 2 (23,98) 1E-3 * * VOLTAGE NOISE SOURCE WITH FLICKER NOISE * VN1 13 98 DC 2 VN2 98 15 DC 2 DN1 13 14 DEN DN2 14 15 DEN * * CURRENT NOISE SOURCE WITH FLICKER NOISE * VN3 16 98 DC 2 VN4 98 18 DC 2 DN3 16 17 DIN DN4 17 18 DIN * * 2ND CURRENT NOISE SOURCE WITH FLICKER NOISE * VN5 19 98 DC 2 VN6 98 24 DC 2 DN5 19 23 DIN DN6 23 24 DIN * * GAIN STAGE * EREF 98 0 POLY(2) (99,0) (50,0) 0 0.5 0.5 G1 98 20 POLY(2) (6,5) (8,7) 0 0.5E-3 0.5E-3 R9 20 98 1E3 * * COMMON MODE STAGE WITH ZERO AT 100HZ * ECM 98 21 POLY(2) (1,98) (2,98) 0 0.5 0.5 R10 21 22 1 R11 22 98 100E-6 C4 21 22 1.592E-3 * * NEGATIVE ZERO AT 20MHZ * E1 27 98 (20,98) 1E6 R17 27 28 1 R18 28 98 1E-6 C8 25 26 7.958E-9 ENZ 25 98 (27,28) 1 VNZ 26 98 DC 0 FNZ 27 28 VNZ -1 * * POLE AT 40MHZ * G4 98 29 (28,98) 1 R19 29 98 1 C9 29 98 3.979E-9 * * POLE AT 40MHZ * G5 98 30 (29,98) 1 R20 30 98 1 C10 30 98 3.979E-9 * * OUTUT STAGE * ISY 99 50 0.276E-3 GIN 50 31 POLY(1) (30,98) .862574E-6 505.879E-6 RIN 31 50 2.75E6 VB 99 32 0.7 Q11 32 31 33 QON 1 R21 33 34 4.5E3 I1 34 50 50E-6 R22 99 35 6E3 Q12 36 36 35 QOP 1 I2 36 50 50E-6 R23 99 37 2.6E3 R24 34 38 5E3 Q13 39 36 37 QOP 1 Q14 39 38 40 QON 1.5 R25 40 50 40 Q15 39 39 41 QON 1 R26 41 42 1E3 R27 99 43 220 Q16 44 44 43 QOP 1.5 Q17 44 39 42 QON 1 R28 42 50 2E3 VSCP 99 97 DC 0.088 FSCP 46 99 VSCP 1 RSCP 46 99 40 Q20 44 46 99 QOP 1 Q18 45 44 97 QOP 4.5 Q19 45 34 51 QON 4.5 VSCN 51 50 DC 0.081 FSCN 50 47 VSCN 1 RSCN 47 50 40 Q21 34 47 50 QON 1 CC2 31 45 20E-12 CF1 31 34 15E-12 CF2 31 42 15E-12 CO1 34 45 15E-12 CO2 42 45 5E-12 D3 45 99 DX D4 50 45 DX .MODEL DC D(IS=130E-21) .MODEL DX D() .MODEL DEN D(RS=100 KF=12E-15 AF=1) .MODEL DIN D(RS=5.358 KF=56E-15 AF=1) .MODEL QIN NPN(BF=120 VA=200 IS=0.5E-16) .MODEL QIP PNP(BF=90 VA=60 IS=0.5E-16) .MODEL QON NPN(BF=200 VA=200 IS=0.5E-16 RC=50) .MODEL QOP PNP(BF=200 VA=200 IS=0.5E-16 RC=160) .ENDS * OP490 SPICE Macro-modeL 10/92, Rev. C * JCB / PMI * * Revision History: * REV. C * Altered gain stage for proper open-loop gain. * REV. B * Re-ordered subcircuit call out nodes to put the * output node last. * Changed Ios from 0.4E-9 to 0.2E-9 * * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP490 1 2 99 50 31 * * INPUT STAGE & POLE AT 10 KHZ * R1 2 3 5E11 R2 1 3 5E11 R3 5 51 61.6E3 R4 6 51 61.6E3 CIN 1 2 4E-12 C2 5 6 129.2E-12 I1 97 4 1UA IOS 1 2 0.2E-9 EOS 9 1 POLY(1) 23 27 2E-4 1 Q1 5 2 7 QX Q2 6 9 8 QX R5 7 4 10E3 R6 8 4 10E3 * EREF 98 0 27 0 1 EPLUS 97 0 99 0 1 ENEG 51 0 50 0 1 * * FIRST GAIN STAGE * R7 10 98 1E6 G1 98 10 5 6 42.23E-6 D1 10 11 DX D2 12 10 DX E1 97 11 POLY(1) 97 27 -1.4 1 E2 12 51 POLY(1) 27 51 -1.4 1 * * GAIN STAGE & DOMINANT POLE AT 0.035 HZ * R8 13 98 5.457E6 C3 13 98 83.333E-8 G2 98 13 10 27 5E-3 H2 97 14 POLY(1) VS2 1.6 -3E3 E5 15 51 POLY(2) (17,51) (97,27) 1.4 1.5 -0.4 D3 13 14 DX D4 15 13 DX * * ZERO-IN ZERO-OUT CLAMP * F1 51 17 VS2 -1000 RS1 17 51 1E9 D5 17 51 DX D6 51 17 DX * * NEGATIVE ZERO AT -100 KHZ * R9 19 20 1E6 C4 19 20 -1.59E-12 R10 20 98 1 E3 19 98 13 27 1E6 * * ZERO - POLE PAIR AT 28 KHZ / 100 KHZ * R11 21 22 1E6 L1 22 98 4.09 R12 22 98 2.57E6 G3 98 21 20 27 1E-6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 4 HZ * R13 23 24 1E6 L2 24 98 39.79E3 G4 98 23 3 27 3.16E-13 D8 23 97 DX D9 51 23 DX * * ZERO - POLE PAIR AT 40 KHZ / 160 KHZ * R14 25 26 1E6 L3 26 98 2.98 R15 26 98 3E6 G5 98 25 21 27 1E-6 * * OUTPUT STAGE * ISY 99 50 9.444E-6 R16 27 99 2.7E6 R17 27 50 2.7E6 R18 30 99 6000 R19 30 50 6000 VS2 30 31 DC 0 G6 28 50 25 30 166.7E-6 G7 29 50 30 25 166.7E-6 G8 30 99 99 25 166.7E-6 G9 50 30 25 50 166.7E-6 D10 99 28 DX D11 99 29 DX D12 50 28 DY D13 50 29 DY * * MODELS USED * .MODEL QX PNP(BF=119) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP491 SPICE Macro-model Rev. A, 5/94 * ARG / PMI * * Copyright 1994 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of * this model indicates your acceptance of the terms and pro- * visions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP491 1 2 99 50 45 * * INPUT STAGE * I1 99 7 8.06E-6 Q1 6 4 7 QP Q2 5 3 7 QP D1 3 99 DX D2 4 99 DX D3 3 4 DX D4 4 3 DX R1 3 8 5E3 R2 4 2 5E3 R3 5 50 6.4654E3 R4 6 50 6.4654E3 EOS 8 1 POLY(1) (16,39) -80E-6 1 IOS 3 4 50E-12 GB1 3 98 (21,98) 50E-9 GB2 4 98 (21,98) 50E-9 CIN 1 2 1E-12 * * 1ST GAIN STAGE * EREF 98 0 (39,0) 1 G1 98 9 (6,5) 31.667E-6 R7 9 98 1E6 EC1 99 10 POLY(1) (99,39) -0.52 1 EC2 11 50 POLY(1) (39,50) -0.52 1 D5 9 10 DX D6 11 9 DX * * 2ND GAIN STAGE AND DOMINANT POLE AT 36HZ * G2 98 12 (9,39) 8E-6 R8 12 98 276.311E6 C2 12 98 16E-12 D7 12 13 DX D8 14 12 DX V1 99 13 0.58 V2 14 50 0.58 * * COMMON MODE STAGE * ECM 15 98 POLY(2) (1,39) (2,39) 0 0.5 0.5 R9 15 16 1E6 R10 16 98 10 * * POLE AT 2.5MHZ * G3 98 18 (12,39) 1E-6 R11 18 98 1E6 C4 18 98 63.662E-15 * * BIAS CURRENT-VS-COMMON MODE VOLTAGE * EP 97 0 (99,0) 1 VB 99 17 1.3 RB 17 50 1E9 E3 19 0 (15,17) 16 D13 19 20 DX R12 20 0 1E6 G4 98 21 (20,0) 1E-3 R13 21 98 5E3 D14 21 22 DY E4 97 22 POLY(1) (99,98) -0.765 1 * * POLE AT 100MHZ * G6 98 40 (18,39) 1E-6 R20 40 98 1E6 C10 40 98 1.592E-15 * * OUTPUT STAGE * RS1 99 39 109.375E3 RS2 39 50 109.375E3 RO1 99 45 41.667 RO2 45 50 41.667 G7 45 99 (99,40) 24E-3 G8 50 45 (40,50) 24E-3 G9 98 60 (45,40) 24E-3 D9 60 61 DX D10 62 60 DX V7 61 98 DC 0 V8 98 62 DC 0 FSY 99 50 POLY(2) V7 V8 0.207E-3 1 1 D11 41 45 DZ D12 45 42 DZ V5 40 41 0.131 V6 42 40 0.131 .MODEL DX D() .MODEL DY D(IS=1E-9) .MODEL DZ D(IS=1E-6) .MODEL QP PNP(BF=133.333) .ENDS * OP492 SPICE Macro-model Rev. B, 3/95 * ARG / ADSC * * Copyright 1993 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of * this model indicates your acceptance of the terms and pro- * visions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP492 2 1 99 50 34 * * INPUT STAGE AND POLE AT 40MHZ * I1 99 4 50E-6 IOS 2 1 10E-9 EOS 2 3 POLY(1) (21,30) 1.5E-3 75 CIN 1 2 3E-12 Q1 5 1 7 QP Q2 6 3 8 QP R3 5 50 2E3 R4 6 50 2E3 R5 4 7 966 R6 4 8 966 C1 5 6 .995E-12 * * GAIN STAGE * EREF 98 0 (30,0) 1 G1 98 9 (5,6) 500E-6 R7 9 98 210.819E3 D1 9 10 DX D2 11 9 DX V1 99 10 .6 V2 11 50 .6 * * ZERO/POLE AT 6MHZ/12MHZ * E1 12 98 (9,30) 2 R8 12 13 1 R9 13 98 1 C3 12 13 26.526E-9 * * ZERO AT 15MHZ * E2 14 98 (13,30) 1E6 R10 14 15 1E6 R11 15 98 1 C4 14 15 10.610E-15 * * COMMON MODE STAGE WITH ZERO AT 40KHZ * ECM 20 98 POLY(2) (1,30) (2,30) 0 0.5 0.5 R20 20 21 1E6 R21 21 98 1 C5 20 21 3.979E-12 * * POLE AT 100MHZ * G2 98 16 (15,30) 1 R12 16 98 1 C6 16 98 1.592E-9 * * OUTPUT STAGE * RS1 99 30 1E6 RS2 30 50 1E6 ISY 99 50 .44E-3 G3 31 50 POLY(1) (16,30) -1.635E-6 4E-6 R16 31 50 1E6 DCL 50 31 DZ I2 99 32 250E-6 RCL 33 50 56 M1 32 31 50 50 MN L=9E-6 W=1000E-6 AD=15E-9 AS=15E-9 M2 34 31 50 50 MN L=9E-6 W=1000E-6 AD=15E-9 AS=15E-9 CC 31 32 14E-12 Q3 99 32 34 QNA Q4 33 32 34 QPA Q5 31 33 50 QNA .MODEL QNA NPN(IS=1.19E-16 BF=253 NF=0.99 VAF=193 IKF=2.76E-3 + ISE=2.57E-13 NE=5 BR=0.4 NR=0.988 VAR=15 IKR=1.465E-4 + ISC=6.9E-16 NC=0.99 RB=2.0E3 IRB=7.73E-6 RBM=132.8 RE=4 RC=209 + CJE=2.1E-13 VJE=0.573 MJE=0.364 FC=0.5 CJC=1.64E-13 VJC=0.534 MJC=0.5 + CJS=1.37E-12 VJS=0.59 MJS=0.5 TF=0.43E-9 PTF=30) .MODEL QPA PNP(IS=5.21E-17 BF=131 NF=0.99 VAF=62 IKF=8.35E-4 + ISE=1.09E-14 NE=2.61 BR=0.5 NR=0.984 VAR=15 IKR=3.96E-5 + ISC=7.58E-16 NC=0.985 RB=1.52E3 IRB=1.67E-5 RBM=368.5 RE=6.31 RC=354.4 + CJE=1.1E-13 VJE=0.745 MJE=0.33 FC=0.5 CJC=2.37E-13 VJC=0.762 MJC=0.4 + CJS=7.11E-13 VJS=0.45 MJS=0.412 TF=1.0E-9 PTF=30) .MODEL MN NMOS(LEVEL=3 VTO=1.3 RS=0.3 RD=0.3 + TOX=8.5E-8 LD=1.48E-6 WD=1E-6 NSUB=1.53E16 UO=650 DELTA=10 VMAX=2E5 + XJ=1.75E-6 KAPPA=0.8 ETA=0.066 THETA=0.01 TPG=1 CJ=2.9E-4 PB=0.837 + MJ=0.407 CJSW=0.5E-9 MJSW=0.33) .MODEL QP PNP(BF=61.5) .MODEL DX D .MODEL DZ D(BV=3.6) .ENDS * OP493 SPICE Macro-model 1/95, Rev. A * ARG / ADI * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License * Statement. This model has been optimized for a total supply voltage of * 5V. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP493 51 52 99 50 32 * * INPUT STAGE & POLE AT 16KHZ * R3 5 50 53.827E3 R4 6 50 53.827E3 R5 4 7 2.104E3 R6 4 8 2.104E3 CIN 1 2 4E-12 C2 5 6 92.4E-12 I1 99 4 1.006E-6 IOS 1 2 0.05E-9 EOS 9 1 POLY(2) (24,27) (102,0) 25E-6 15.851E-3 1 Q1 5 2 7 QX Q2 6 9 8 QX EREF 98 0 POLY(2) (99,0) (50,0) 0 0.5 0.5 R24 1 51 2E3 R25 2 52 2E3 VN1 101 0 DC 2 VN2 0 103 DC 2 DN1 101 102 DEN DN2 102 103 DEN * * GAIN STAGE & DOMINANT POLE AT 0.21 HZ * R7 10 98 9.151E9 G1 98 10 (5,6) 18.578E-6 C3 10 98 83.333E-12 V1 99 11 0.65 D1 10 11 DX D2 50 10 DX * * NEGATIVE ZERO AT 50KHZ * R9 13 14 1E6 R10 14 98 1 FNZ 13 14 VNZ -1 E2 13 98 (10,27) 1 CNZ 15 16 3.183E-12 ENZ 15 98 (13,14) 1 VNZ 16 98 DC 0 * * ZERO-POLE PAIR AT 28KHZ / 84KHZ * R18 17 18 2E6 C4 17 18 2.842E-12 R19 18 98 1E6 E3 17 98 (14,27) 3E6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 0.5HZ * R1 23 24 1E6 R2 24 98 100 C5 23 24 318E-9 E4 23 98 POLY(2) (1,27) (2,27) 0 0.5 0.5 * * ZERO-POLE PAIR AT 40KHZ / 160KHZ * R20 25 26 3E6 C6 25 26 1.326E-12 R21 26 98 1E6 E5 25 98 (18,27) 4 * * OUTPUT STAGE * ISY 99 50 9.637E-6 R16 27 99 4.5E6 R17 27 50 4.5E6 EIN 28 98 POLY(1) (26,27) 0.52255 1.05 RIN 28 31 15E3 Q11 45 31 32 QN 6 Q12 32 33 44 QN 6 Q13 41 34 33 QN 1 Q14 34 35 36 QP 1 Q15 36 38 39 QN 8 Q16 35 35 37 QP 1 Q17 99 99 37 QN 1 Q18 99 99 36 QN 1 Q19 50 42 34 QP 1 Q20 42 42 34 QP 1 Q21 32 33 42 QN 1 Q22 99 40 41 QN 1 Q23 43 43 50 QN 1 Q24 34 43 50 QN 2 Q25 33 43 50 QN 2 Q26 34 44 50 QC 1 Q27 31 46 50 QC 1 EC 47 50 (99,45) 0.96 RC 46 47 1E3 IREF 99 43 4.5E-7 I13 35 50 4.5E-7 R11 99 40 75E3 R12 99 36 40E3 R13 31 38 20E3 R14 32 39 5E3 R15 40 37 75E3 R22 44 50 30 R23 99 45 50 * * MODELS USED * .MODEL QN NPN(BF=200 IS=1E-16 VA=150) .MODEL QP PNP(BF=100 IS=5E-17 VA=50) .MODEL QX PNP(BF=166.667 KF=2E-17) .MODEL QC NPN(BF=200 IS=2E-11) .MODEL DX D(IS=1E-15) .MODEL DEN D(RS=2.45E3 KF=33E-15) .ENDS * OP495 SPICE Macro-model 2/95, Rev. A * ARG / ADSC * * Copyright 1995 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License * Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP495 1 2 99 50 20 * * INPUT STAGE * I1 99 4 2.016E-6 R1 1 6 5E3 R2 2 5 5E3 CIN 1 2 2E-12 IOS 1 2 0.5E-9 D1 5 3 DZ D2 6 3 DZ EOS 7 6 POLY(1) (31,39) 30E-6 0.024 Q1 8 5 4 QP Q2 9 7 4 QP R3 8 50 25.861E3 R4 9 50 25.861E3 * * GAIN STAGE * R7 10 98 270E6 G1 98 10 POLY(1) (9,8) -4.26712E-9 27.8E-6 EREF 98 0 (39,0) 1 R5 99 39 417E3 R6 39 50 417E3 * * COMMON MODE STAGE * ECM 30 98 POLY(2) (1,39) (2,39) 0 0.5 0.5 R12 30 31 1E6 R13 31 98 100 * * OUTPUT STAGE * ISY 99 50 49E-6 I2 18 50 1.59E-6 V2 99 12 DC 2.2763 Q4 10 14 50 QNA 1.0 R11 14 50 33 M3 15 10 13 13 MN L=9E-6 W=102E-6 AD=15E-10 AS=15E-10 M4 13 10 50 50 MN L=9E-6 W=50E-6 AD=75E-11 AS=75E-11 D8 10 22 DX V3 22 50 DC 6 M2 20 10 14 14 MN L=9E-6 W=2000E-6 AD=30E-9 AS=30E-9 Q5 17 17 99 QPA 1.0 Q6 18 17 99 QPA 4.0 R8 18 99 2.2E6 Q7 18 19 99 QPA 1.0 R9 99 19 8 C2 18 99 20E-12 M6 15 12 17 99 MP L=9E-6 W=27E-6 AD=405E-12 AS=405E-12 M1 20 18 19 99 MP L=9E-6 W=2000E-6 AD=30E-9 AS=30E-9 D4 21 18 DX V4 99 21 DC 6 R10 10 11 6E3 C3 11 20 54E-12 .MODEL QNA NPN(IS=1.19E-16 BF=253 NF=0.99 VAF=193 IKF=2.76E-3 + ISE=2.57E-13 NE=5 BR=0.4 NR=0.988 VAR=15 IKR=1.465E-4 + ISC=6.9E-16 NC=0.99 RB=2.0E3 IRB=7.73E-6 RBM=132.8 RE=4 RC=209 + CJE=2.1E-13 VJE=0.573 MJE=0.364 FC=0.5 CJC=1.64E-13 VJC=0.534 MJC=0.5 + CJS=1.37E-12 VJS=0.59 MJS=0.5 TF=0.43E-9 PTF=30) .MODEL QPA PNP(IS=5.21E-17 BF=131 NF=0.99 VAF=62 IKF=8.35E-4 + ISE=1.09E-14 NE=2.61 BR=0.5 NR=0.984 VAR=15 IKR=3.96E-5 + ISC=7.58E-16 NC=0.985 RB=1.52E3 IRB=1.67E-5 RBM=368.5 RE=6.31 RC=354.4 + CJE=1.1E-13 VJE=0.745 MJE=0.33 FC=0.5 CJC=2.37E-13 VJC=0.762 MJC=0.4 + CJS=7.11E-13 VJS=0.45 MJS=0.412 TF=1.0E-9 PTF=30) .MODEL MN NMOS(LEVEL=3 VTO=1.3 RS=0.3 RD=0.3 + TOX=8.5E-8 LD=1.48E-6 NSUB=1.53E16 UO=650 DELTA=10 VMAX=2E5 + XJ=1.75E-6 KAPPA=0.8 ETA=0.066 THETA=0.01 TPG=1 CJ=2.9E-4 PB=0.837 + MJ=0.407 CJSW=0.5E-9 MJSW=0.33) .MODEL MP PMOS(LEVEL=3 VTO=-1.1 RS=0.7 RD=0.7 + TOX=9.5E-8 LD=1.4E-6 NSUB=2.4E15 UO=650 DELTA=5.6 VMAX=1E5 + XJ=1.75E-6 KAPPA=1.7 ETA=0.71 THETA=5.9E-3 TPG=-1 CJ=1.55E-4 PB=0.56 + MJ=0.442 CJSW=0.4E-9 MJSW=0.33) .MODEL DX D(IS=1E-15) .MODEL DZ D(IS=1E-15, BV=7) .MODEL QP PNP(BF=125) .ENDS * OP495A SPICE Macro-model 2/95, Rev. A * ARG / ADSC * * This version of the OP495 model simulates the worst-case * parameters of the 'A' grade. The worst-case parameters * used correspond to those in the data sheet. * * Copyright 1995 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License * Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP495A 1 2 99 50 20 * * INPUT STAGE * I1 99 4 2.04E-6 R1 1 6 5E3 R2 2 5 5E3 CIN 1 2 2E-12 IOS 1 2 1.5E-9 D1 5 3 DZ D2 6 3 DZ EOS 7 6 POLY(1) (31,39) 300E-6 0.316 Q1 8 5 4 QP Q2 9 7 4 QP R3 8 50 25.861E3 R4 9 50 25.861E3 * * GAIN STAGE * R7 10 98 72.8725E6 G1 98 10 POLY(1) (9,8) -15.8072E-9 27.8E-6 EREF 98 0 (39,0) 1 R5 99 39 417E3 R6 39 50 417E3 * * COMMON MODE STAGE * ECM 30 98 POLY(2) (1,39) (2,39) 0 0.5 0.5 R12 30 31 1E6 R13 31 98 100 * * OUTPUT STAGE * ISY 99 50 99E-6 I2 18 50 1.59E-6 V2 99 12 DC 2.2763 Q4 10 14 50 QNA 1.0 R11 14 50 54 M3 15 10 13 13 MN L=9E-6 W=102E-6 AD=15E-10 AS=15E-10 M4 13 10 50 50 MN L=9E-6 W=50E-6 AD=75E-11 AS=75E-11 D8 10 22 DX V3 22 50 DC 6 M2 20 10 14 14 MN L=9E-6 W=2000E-6 AD=30E-9 AS=30E-9 Q5 17 17 99 QPA 1.0 Q6 18 17 99 QPA 4.0 R8 18 99 2.2E6 Q7 18 19 99 QPA 1.0 R9 99 19 48 C2 18 99 20E-12 M6 15 12 17 99 MP L=9E-6 W=27E-6 AD=405E-12 AS=405E-12 M1 20 18 19 99 MP L=9E-6 W=2000E-6 AD=30E-9 AS=30E-9 D4 21 18 DX V4 99 21 DC 6 R10 10 11 6E3 C3 11 20 54E-12 .MODEL QNA NPN(IS=1.19E-16 BF=253 NF=0.99 VAF=193 IKF=2.76E-3 + ISE=2.57E-13 NE=5 BR=0.4 NR=0.988 VAR=15 IKR=1.465E-4 + ISC=6.9E-16 NC=0.99 RB=2.0E3 IRB=7.73E-6 RBM=132.8 RE=4 RC=209 + CJE=2.1E-13 VJE=0.573 MJE=0.364 FC=0.5 CJC=1.64E-13 VJC=0.534 MJC=0.5 + CJS=1.37E-12 VJS=0.59 MJS=0.5 TF=0.43E-9 PTF=30) .MODEL QPA PNP(IS=5.21E-17 BF=131 NF=0.99 VAF=62 IKF=8.35E-4 + ISE=1.09E-14 NE=2.61 BR=0.5 NR=0.984 VAR=15 IKR=3.96E-5 + ISC=7.58E-16 NC=0.985 RB=1.52E3 IRB=1.67E-5 RBM=368.5 RE=6.31 RC=354.4 + CJE=1.1E-13 VJE=0.745 MJE=0.33 FC=0.5 CJC=2.37E-13 VJC=0.762 MJC=0.4 + CJS=7.11E-13 VJS=0.45 MJS=0.412 TF=1.0E-9 PTF=30) .MODEL MN NMOS(LEVEL=3 VTO=1.3 RS=0.3 RD=0.3 + TOX=8.5E-8 LD=1.48E-6 NSUB=1.53E16 UO=650 DELTA=10 VMAX=2E5 + XJ=1.75E-6 KAPPA=0.8 ETA=0.066 THETA=0.01 TPG=1 CJ=2.9E-4 PB=0.837 + MJ=0.407 CJSW=0.5E-9 MJSW=0.33) .MODEL MP PMOS(LEVEL=3 VTO=-1.1 RS=0.7 RD=0.7 + TOX=9.5E-8 LD=1.4E-6 NSUB=2.4E15 UO=650 DELTA=5.6 VMAX=1E5 + XJ=1.75E-6 KAPPA=1.7 ETA=0.71 THETA=5.9E-3 TPG=-1 CJ=1.55E-4 PB=0.56 + MJ=0.442 CJSW=0.4E-9 MJSW=0.33) .MODEL DX D(IS=1E-15) .MODEL DZ D(IS=1E-15, BV=7) .MODEL QP PNP(BF=50) .ENDS * OP497 SPICE Macro-model 4/91, Rev. B * AAG / PMI * * Copyright 1991 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP497 1 2 99 50 27 * * INPUT STAGE & POLE AT 6 MHZ * RIN1 1 7 2500 RIN2 2 8 2500 R1 8 3 6.782E8 R2 7 3 6.782E8 R3 5 99 542.57 R4 6 99 542.57 CIN 7 8 3E-12 C2 5 6 24.445E-12 I1 4 50 0.1E-3 IOS 7 8 15E-12 EOS 9 7 POLY(1) 16 21 40E-6 1 Q1 5 8 10 QX Q2 6 9 11 QX R5 10 4 25.374 R6 11 4 25.374 D1 8 9 DX D2 9 8 DX * EREF 98 0 21 0 1 * * GAIN STAGE & DOMINANT POLE AT 0.11 HZ * R7 12 98 2.1703E9 C3 12 98 666.67E-12 G1 98 12 5 6 1.8431E-3 V1 99 13 1.275 V2 14 50 1.275 D3 12 13 DX D4 14 12 DX * * COMMON-MODE GAIN NETWORK WITH ZERO AT 50 HZ * RCM1 15 16 1E6 CCM 15 16 3.183E-9 RCM2 16 98 1 ECM 15 98 3 21 177.83E-3 * * NEGATIVE ZERO AT 1.8 MHz * E1 17 98 12 21 1E6 R8 17 18 1E6 C4 17 18 -88.419E-15 R9 18 98 1 * * POLE AT 6 MHZ * G2 98 19 18 21 1E-6 R10 19 98 1E6 C5 19 98 26.526E-15 * * POLE AT 1.8 MHZ * G3 98 20 19 21 1E-6 R15 20 98 1E6 C8 20 98 88.419E-15 * * OUTPUT STAGE * R16 99 21 160K R17 21 50 160K ISY 99 50 331E-6 V3 23 22 1.9 D5 20 23 DX V4 22 24 1.9 D6 24 20 DX D7 99 25 DX G4 25 50 20 22 5E-3 D9 50 25 DY D8 99 26 DX G5 26 50 22 20 5E-3 D10 50 26 DY G6 22 99 99 20 5E-3 R18 99 22 200 G7 50 22 20 50 5E-3 R19 22 50 200 L1 22 27 0.1E-6 * * MODELS USED * .MODEL QX NPN(BF=1.25E6) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS * OP80 SPICE Macro-model 9/93, Rev. A * ARG / PMI * * Copyright 1993 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of * this model indicates your acceptance of the terms and pro- * visions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP80 1 2 99 50 45 * * INPUT STAGE AND POLE AT 500KHZ * I1 99 4 50E-6 M1 5 2 4 99 PNOM L=15U W=1500U M2 6 3 4 99 PNOM L=15U W=1500U EOS 3 1 POLY(1) (13,39) .2E-3 316.228 R1 5 50 3.125E3 R2 6 50 3.125E3 IB1 1 50 125E-15 IB2 2 50 175E-15 CIN 1 2 2E-12 C1 5 6 50.923E-12 * * GAIN STAGE AND DOMINANT POLE AT 1.018HZ * EREF 98 0 (39,0) 1 C2 9 98 125E-12 R7 9 98 1.250E9 G1 98 9 (5,6) 319.956E-6 D1 9 10 DX D2 11 9 DX V1 99 10 1.88 V2 11 50 0 * * COMMON MODE STAGE WITH ZERO AT 10KHZ * ECM 12 98 POLY(2) (1,39) (2,39) 0 0.5 0.5 R9 12 13 1E6 R10 13 98 1 C3 12 13 15.916E-12 * * POLE AT 100KHZ * G2 98 14 (9,39) 1E-6 R11 14 98 1E6 C4 14 98 1.592E-12 * * ZERO AT 185KHZ * E1 15 98 (14,39) 1E6 R12 15 16 1E6 R13 16 98 1 C5 15 16 .860E-12 * * OUTPUT STAGE * G3 98 40 (16,39) 1E-6 R14 40 98 1E6 RS1 99 39 56.818E3 RS2 39 50 56.818E3 R15 99 45 50 R16 45 50 50 G7 45 99 (99,40) 20E-3 G8 50 45 (40,50) 20E-3 G9 98 60 (45,40) 20E-3 D7 60 61 DX D8 62 60 DX V7 61 98 DC 0 V8 98 62 DC 0 FSY 99 50 POLY(2) V7 V8 62E-6 1 1 D9 41 45 DX D10 45 42 DX V5 40 41 .625 V6 42 40 .125 .MODEL DX D() .MODEL PNOM PMOS(VTO=-0.9 KP=20.474U) .ENDS * OP-90 SPICE Macro-model 10/92, Rev. C * JCB / PMI * * Revision History: * REV. C * Altered gain stage for proper open-loop gain. * REV. B * Re-ordered subcircuit call out nodes to put the * output node last. * Changed Ios from 0.4E-9 to 0.2E-9 * * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP-90 1 2 99 50 31 * * INPUT STAGE & POLE AT 10 KHZ * R1 2 3 5E11 R2 1 3 5E11 R3 5 51 61.6E3 R4 6 51 61.6E3 CIN 1 2 4E-12 C2 5 6 129.2E-12 I1 97 4 1UA IOS 1 2 0.2E-9 EOS 9 1 POLY(1) 23 27 50E-6 1 Q1 5 2 7 QX Q2 6 9 8 QX R5 7 4 10E3 R6 8 4 10E3 * EREF 98 0 27 0 1 EPLUS 97 0 99 0 1 ENEG 51 0 50 0 1 * * FIRST GAIN STAGE * R7 10 98 1E6 G1 98 10 5 6 42.23E-6 D1 10 11 DX D2 12 10 DX E1 97 11 POLY(1) 97 27 -1.4 1 E2 12 51 POLY(1) 27 51 -1.4 1 * * GAIN STAGE & DOMINANT POLE AT 0.035 HZ * R8 13 98 5.457E6 C3 13 98 83.333E-8 G2 98 13 10 27 5E-3 H2 97 14 POLY(1) VS2 1.6 -3E3 E5 15 51 POLY(2) (17,51) (97,27) 1.4 1.5 -0.4 D3 13 14 DX D4 15 13 DX * * ZERO-IN ZERO-OUT CLAMP * F1 51 17 VS2 -1000 RS1 17 51 1E9 D5 17 51 DX D6 51 17 DX * * NEGATIVE ZERO AT -100 KHZ * R9 19 20 1E6 C4 19 20 -1.59E-12 R10 20 98 1 E3 19 98 13 27 1E6 * * ZERO - POLE PAIR AT 28 KHZ / 100 KHZ * R11 21 22 1E6 L1 22 98 4.09 R12 22 98 2.57E6 G3 98 21 20 27 1E-6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 4 HZ * R13 23 24 1E6 L2 24 98 39.79E3 G4 98 23 3 27 3.16E-13 D8 23 97 DX D9 51 23 DX * * ZERO - POLE PAIR AT 40 KHZ / 160 KHZ * R14 25 26 1E6 L3 26 98 2.98 R15 26 98 3E6 G5 98 25 21 27 1E-6 * * OUTPUT STAGE * ISY 99 50 8.444E-6 R16 27 99 2.7E6 R17 27 50 2.7E6 R18 30 99 6000 R19 30 50 6000 VS2 30 31 DC 0 G6 28 50 25 30 166.7E-6 G7 29 50 30 25 166.7E-6 G8 30 99 99 25 166.7E-6 G9 50 30 25 50 166.7E-6 D10 99 28 DX D11 99 29 DX D12 50 28 DY D13 50 29 DY * * MODELS USED * .MODEL QX PNP(BF=125) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS OP-90 * OP97 SPICE Macro-model 12/90, Rev. B * JCB / PMI * * Revision History: * REV. B * Re-ordered subcircuit call out nodes to put the * output node last. * Changed Ios from 30E-12 to 15E-12 * * * Copyright 1990 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP97 1 2 99 50 38 * * INPUT STAGE & POLE AT 15 MHZ * R1 2 3 5E11 R2 1 3 5E11 R3 5 99 612 R4 6 99 612 CIN 1 2 4E-12 C2 5 6 8.67E-12 I1 4 50 0.1E-3 IOS 1 2 15E-12 EOS 9 1 POLY(1) 26 32 10E-6 1 Q1 5 2 10 QX Q2 6 9 11 QX R5 10 4 96 R6 11 4 96 D12 2 9 DX D13 9 2 DX * * GAIN STAGE & DOMINANT POLE AT 0.26 HZ * R9 13 99 1.22E9 R10 13 50 1.22E9 C3 13 99 500E-12 C4 13 50 500E-12 G3 99 13 5 6 1.634E-3 G4 13 50 6 5 1.634E-3 V2 99 14 1.3 V3 15 50 1.3 D1 13 14 DX D2 15 13 DX GS 99 50 POLY(1) 99 50 0.28E-3 -3.7E-6 * * ZERO-POLE PAIR AT 150 KHZ / 285 KHZ * R17 19 20 1E6 R18 19 21 1E6 R19 20 99 0.9E6 R20 21 50 0.9E6 L3 20 99 0.503 L4 21 50 0.503 G7 99 19 13 32 1E-6 G8 19 50 32 13 1E-6 * * POLE AT 4.8 MHZ * R21 22 99 1E6 R22 22 50 1E6 C7 22 99 33.2E-15 C8 22 50 33.2E-15 G9 99 22 19 32 1E-6 G10 22 50 32 19 1E-6 * * POLE AT 8 MHZ * R23 23 99 1E6 R24 23 50 1E6 C9 23 99 19.9E-15 C10 23 50 19.9E-15 G11 99 23 22 32 1E-6 G12 23 50 32 22 1E-6 * * POLE AT 10 MHZ * R25 24 99 1E6 R26 24 50 1E6 C11 24 99 15.9E-15 C12 24 50 15.9E-15 G13 99 24 23 32 1E-6 G14 24 50 32 23 1E-6 * * POLE AT 15 MHZ * R27 25 99 1E6 R28 25 50 1E6 C13 25 99 10.6E-15 C14 25 50 10.6E-15 G15 99 25 24 32 1E-6 G16 25 99 32 24 1E-6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 50 KHZ * R29 26 27 1E6 R30 26 28 1E6 L5 27 99 3.183E3 L6 28 50 3.183E3 RS1 27 99 16E9 RS2 28 50 16E9 G17 99 26 3 32 2.51E-13 G18 26 50 32 3 2.51E-13 D3 26 99 DX D4 50 26 DX * * POLE AT 12 MHZ * R32 31 99 1E6 R33 31 50 1E6 C15 31 99 13.2E-15 C16 31 50 13.2E-15 G19 99 31 25 32 1E-6 G20 31 50 32 25 1E-6 * * OUTPUT STAGE * R34 32 99 1E6 R35 32 50 1E6 R36 33 99 600 R37 33 50 600 L7 33 38 2.65E-7 G21 36 50 31 33 1.6667E-3 G22 37 50 33 31 1.6667E-3 G23 33 99 99 31 1.6667E-3 G24 50 33 31 50 1.6667E-3 V6 34 33 3.6 V7 33 35 3.0 D5 31 34 DX D6 35 31 DX D7 99 36 DX D8 99 37 DX D9 50 36 DY D10 50 37 DY * * MODELS USED * .MODEL QX NPN(BF=1.67E6) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-15 BV=50) .ENDS