# VDMOS model for modeling the capacitance for negative Vgd

The best way to measure capacitance as a function of voltage is in an .ac analysis performed at a single frequency with voltage stepped as a parameter. The .ac and .step commands might be:

.ac list {.5/pi} ; single frequency .ac analysis .step dec param x 1 100 10 ; step x logarithmically from 1 to 100 V1 1 0 {x} ac=1 ; ac voltage source with its dc value stepped as x C1 1 0 Q=1n*x ; here x is the voltage across C1

In the waveform viewer, with trace math, capacitance can be plotted with the expression:

im(I(C1))*2*Pi*f, where f is the .ac analysis frequency.

By selecting f=1/(2*Pi) in the single frequency .ac analysis capacitance may simply be directly plotted as im(I(C1)).

Note that for a voltage dependent capacitance, charge must be solved for the integral of capacitance with respect to voltage:

Q = int C(v)*dv

which will agree with Q = C*V only when C is independent of voltage.

For example, Cgd in LTspice's VDMOS is expressed as a function of the model parameters Cgdmax, Cgdmin and "a".

Cgd=s*atan(-a*x)+y, where s=(Cgdmax-Cgdmin)/(1+Pi/2) and y=Cgdmax-s

Note that here x is the voltage across Cgd.

To express this as a function of Q (charge) in LTspice's behavioral capacitor, the integral of this expression must be solved with respect to the Cgd voltage, x. Fortunately, the Internet has lots of tables of integrals online, making it easier to find the solution, which is:

Q=s*(x*atan(-a*x)-ln(1+(-a*x)**2)/(-a*2))+y*x

If this is plugged into the behavioral capacitor,

C1 1 0 Q=s*(x*atan(-a*x)-ln(1+(-a*x)**2)/(-a*2))+y*x

it will have the same voltage dependency a Cgd in LTspice's VDMOS model (assuming the same values for the parameters Cgdmax, Cgdmin and a).

You may replace the built-in VDMOS capacitances with your own behavioral capacitance creations by copying the VDMOS model of interest and setting its native capacitances to zero. Then simply place your own behavioral capacitors across the appropriate terminals of the VDMOS. If you like, this could easily be encapsulated within a subcircuit that uses LTspice's own VDMOS symbol. If the charge equation is continuous with a continuous derivative across the seams, there should be no glitches or run-time problems.